diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml new file mode 100644 index 000000000000..fc19b1a6f37b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/airoha.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/airoha.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha SoC based Platforms Device Tree Bindings + +maintainers: + - Felix Fietkau + - John Crispin + +description: + Boards with an Airoha SoC shall have the following properties. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - airoha,en7523-evb + - const: airoha,en7523 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index c15c92fdf2ed..5e2017c0a051 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -13,12 +13,46 @@ properties: $nodename: const: "/" compatible: - items: - - enum: - - altr,socfpga-cyclone5 - - altr,socfpga-arria5 - - altr,socfpga-arria10 - - const: altr,socfpga + oneOf: + - description: Arria 5 boards + items: + - enum: + - altr,socfpga-arria5-socdk + - const: altr,socfpga-arria5 + - const: altr,socfpga + + - description: Arria 10 boards + items: + - enum: + - altr,socfpga-arria10-socdk + - enclustra,mercury-aa1 + - const: altr,socfpga-arria10 + - const: altr,socfpga + + - description: Cyclone 5 boards + items: + - enum: + - altr,socfpga-cyclone5-socdk + - denx,mcvevk + - ebv,socrates + - macnica,sodia + - novtech,chameleon96 + - samtec,vining + - terasic,de0-atlas + - terasic,socfpga-cyclone5-sockit + - const: altr,socfpga-cyclone5 + - const: altr,socfpga + + - description: Stratix 10 boards + items: + - enum: + - altr,socfpga-stratix10-socdk + - const: altr,socfpga-stratix10 + + - description: SoCFPGA VT + items: + - const: altr,socfpga-vt + - const: altr,socfpga additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 36081734f720..61a6cabb375b 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -108,6 +108,7 @@ properties: - amlogic,p230 - amlogic,p231 - libretech,aml-s905d-pc + - osmc,vero4k-plus - phicomm,n1 - smartlabs,sml5442tw - videostrong,gxl-kii-pro @@ -170,9 +171,14 @@ properties: - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC items: - enum: + - amediatech,x96-air + - amediatech,x96-air-gbit - bananapi,bpi-m5 + - cyx,a95xf3-air + - cyx,a95xf3-air-gbit - hardkernel,odroid-c4 - hardkernel,odroid-hc4 + - haochuangyi,h96-max - khadas,vim3l - seirobotics,sei610 - const: amlogic,sm1 @@ -183,6 +189,12 @@ properties: - amlogic,ad401 - const: amlogic,a1 + - description: Boards with the Amlogic Meson S4 S805X2 SoC + items: + - enum: + - amlogic,aq222 + - const: amlogic,s4 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index ff91df04f9f4..4e495e03264b 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -175,6 +175,15 @@ properties: - const: microchip,lan9668 - const: microchip,lan966 + - description: Kontron KSwitch D10 MMT series + items: + - enum: + - kontron,kswitch-d10-mmt-8g + - kontron,kswitch-d10-mmt-6g-2gs + - const: kontron,s1921 + - const: microchip,lan9668 + - const: microchip,lan966 + - items: - enum: - atmel,sams70j19 diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml index 5dc48241efb3..8051a75c2c79 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -51,6 +51,7 @@ properties: - raspberrypi,3-model-b-plus - raspberrypi,3-compute-module - raspberrypi,3-compute-module-lite + - raspberrypi,model-zero-2-w - const: brcm,bcm2837 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 0dcebc48ea22..3aad1b93742c 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -173,6 +173,7 @@ properties: - nvidia,tegra194-carmel - qcom,krait - qcom,kryo + - qcom,kryo250 - qcom,kryo260 - qcom,kryo280 - qcom,kryo385 diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 97f6eebad76a..08bdd30e511c 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -762,6 +762,7 @@ properties: - enum: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board + - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit @@ -769,8 +770,13 @@ properties: - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw7901 # i.MX8MM Gateworks Board - gw,imx8mm-gw7902 # i.MX8MM Gateworks Board + - gw,imx8mm-gw7903 # i.MX8MM Gateworks Board - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM + - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules + - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT + - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module + - prt,prt8mm # i.MX8MM Protonic PRT8MM Board - const: fsl,imx8mm - description: Engicam i.Core MX8M Mini SoM based boards @@ -787,6 +793,24 @@ properties: - const: kontron,imx8mm-n801x-som - const: fsl,imx8mm + - description: Toradex Boards with Verdin iMX8M Mini Modules + items: + - enum: + - toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia + - toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board + - const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT + - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module + - const: fsl,imx8mm + + - description: Toradex Boards with Verdin iMX8M Mini Wi-Fi / BT Modules + items: + - enum: + - toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia + - toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B. + - const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module + - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module + - const: fsl,imx8mm + - description: Variscite VAR-SOM-MX8MM based boards items: - const: variscite,var-som-mx8mm-symphony diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml new file mode 100644 index 000000000000..6e043459fcd5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA platform device tree bindings + +maintainers: + - Dinh Nguyen + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - description: AgileX boards + items: + - enum: + - intel,n5x-socdk + - intel,socfpga-agilex-socdk + - const: intel,socfpga-agilex + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 0ffe1acf1344..ab0593c77321 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -30,6 +30,10 @@ properties: - enum: - mediatek,mt6580-evbp1 - const: mediatek,mt6580 + - items: + - enum: + - prestigio,pmt5008-3g + - const: mediatek,mt6582 - items: - enum: - fairphone,fp1 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml index 763c62323a74..b31d90dc9eb4 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml @@ -29,6 +29,7 @@ properties: - mediatek,mt8167-mmsys - mediatek,mt8173-mmsys - mediatek,mt8183-mmsys + - mediatek,mt8186-mmsys - mediatek,mt8192-mmsys - mediatek,mt8365-mmsys - const: syscon diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 03882aac8d2d..30fcbe2ad8a3 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -27,6 +27,8 @@ properties: - qcom,sm6350-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc reg: items: diff --git a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml index a316eef1b728..8892eb6bd3ef 100644 --- a/Documentation/devicetree/bindings/arm/mstar/mstar.yaml +++ b/Documentation/devicetree/bindings/arm/mstar/mstar.yaml @@ -23,8 +23,12 @@ properties: - description: infinity2m boards items: - enum: + - 100ask,dongshanpione # 100ask DongShanPiOne - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit - m5stack,unitv2 # M5Stack UnitV2 + - miyoo,miyoo-mini # Miyoo Mini + - wirelesstag,ido-som2d01 # Wireless Tag IDO-SOM2D01 + - wirelesstag,ido-sbc2d06-v1b-22w # Wireless Tag IDO-SBC2D06-1VB-22W - const: mstar,infinity2m - description: infinity3 boards diff --git a/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml new file mode 100644 index 000000000000..fcb211add7d3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Global Control Registers block in Nuvoton SoCs + +maintainers: + - Jonathan Neuschäfer + +description: + The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs + that expose misc functionality such as chip model and version information or + pinmux settings. + +properties: + compatible: + items: + - enum: + - nuvoton,wpcm450-gcr + - nuvoton,npcm750-gcr + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + gcr: syscon@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd"; + reg = <0x800000 0x1000>; + + mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x38 0x07>; + idle-states = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 04ff0b55bb85..129cdd246223 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -42,6 +42,7 @@ description: | sc7180 sc7280 sdm630 + sdm632 sdm660 sdm845 sdx55 @@ -172,7 +173,21 @@ properties: - const: qcom,apq8094 - items: - - const: qcom,msm8996-mtp + - enum: + - arrow,apq8096-db820c + - inforce,ifc6640 + - const: qcom,apq8096-sbc + - const: qcom,apq8096 + + - items: + - enum: + - qcom,msm8996-mtp + - sony,dora-row + - sony,kagura-row + - sony,keyaki-row + - xiaomi,gemini + - xiaomi,scorpio + - const: qcom,msm8996 - items: - enum: @@ -210,6 +225,11 @@ properties: - google,senor - const: qcom,sc7280 + - items: + - enum: + - fairphone,fp3 + - const: qcom,sdm632 + - items: - enum: - xiaomi,lavender @@ -262,6 +282,7 @@ properties: - items: - enum: + - qcom,sm8450-hdk - qcom,sm8450-qrd - const: qcom,sm8450 diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/arm/renesas.yaml index 6a9350ee690b..fa435d6fda77 100644 --- a/Documentation/devicetree/bindings/arm/renesas.yaml +++ b/Documentation/devicetree/bindings/arm/renesas.yaml @@ -421,6 +421,15 @@ properties: - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L - const: renesas,r9a07g044 + - description: RZ/V2L (R9A07G054) + items: + - enum: + - renesas,smarc-evk # SMARC EVK + - enum: + - renesas,r9a07g054l1 # Single Cortex-A55 RZ/V2L + - renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L + - const: renesas,r9a07g054 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 4aed16176434..eece92f83a2d 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -481,6 +481,14 @@ properties: - const: pine64,pinebook-pro - const: rockchip,rk3399 + - description: Pine64 PineNote + items: + - enum: + - pine64,pinenote-v1.1 + - pine64,pinenote-v1.2 + - const: pine64,pinenote + - const: rockchip,rk3566 + - description: Pine64 Rock64 items: - const: pine64,rock64 @@ -651,6 +659,11 @@ properties: - const: rockchip,rk3568-evb1-v10 - const: rockchip,rk3568 + - description: Rockchip RK3568 Banana Pi R2 Pro + items: + - const: rockchip,rk3568-bpi-r2pro + - const: rockchip,rk3568 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index 052cd94113d4..faea33e4f731 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -140,6 +140,8 @@ properties: items: - enum: - insignal,arndale-octa # Insignal Arndale Octa + - samsung,chagall-wifi # Samsung SM-T800 + - samsung,klimt-wifi # Samsung SM-T700 - samsung,smdk5420 # Samsung SMDK5420 eval - const: samsung,exynos5420 - const: samsung,exynos5 diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index b07720ea9611..fa0a1b84122e 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -28,6 +28,12 @@ properties: - enum: - st,stm32mp153 - st,stm32mp157 + + - description: emtrion STM32MP1 Argon based Boards + items: + - const: emtrion,stm32mp157c-emsbc-argon + - const: emtrion,stm32mp157c-emstamp-argon + - const: st,stm32mp157 - items: - enum: - st,stm32f429i-disco diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index c8a3102c0fde..086c68771d2b 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -444,6 +444,11 @@ properties: - const: haoyu,a10-marsboard - const: allwinner,sun4i-a10 + - description: HAOYU Electronics Marsboard A20 + items: + - const: haoyu,a20-marsboard + - const: allwinner,sun7i-a20 + - description: MapleBoard MP130 items: - const: mapleboard,mp130 diff --git a/Documentation/devicetree/bindings/arm/tesla.yaml b/Documentation/devicetree/bindings/arm/tesla.yaml new file mode 100644 index 000000000000..09856da657dc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tesla.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/tesla.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla Full Self Driving(FSD) platforms device tree bindings + +maintainers: + - Alim Akhtar + - linux-fsd@tesla.com + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: FSD SoC board + items: + - enum: + - tesla,fsd-evb # Tesla FSD Evaluation + - const: tesla,fsd + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index b03c10fa2e7a..61c6ab4f52e2 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -46,6 +46,12 @@ properties: - ti,j7200-evm - const: ti,j7200 + - description: K3 AM625 SoC + items: + - enum: + - ti,am625-sk + - const: ti,am625 + - description: K3 AM642 SoC items: - enum: diff --git a/Documentation/devicetree/bindings/clock/intc_stratix10.txt b/Documentation/devicetree/bindings/clock/intc_stratix10.txt deleted file mode 100644 index 9f4ec5cb5c6b..000000000000 --- a/Documentation/devicetree/bindings/clock/intc_stratix10.txt +++ /dev/null @@ -1,20 +0,0 @@ -Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be - "intel,stratix10-clkmgr" - -- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. - -- #clock-cells : from common clock binding, shall be set to 1. - -Example: - clkmgr: clock-controller@ffd10000 { - compatible = "intel,stratix10-clkmgr"; - reg = <0xffd10000 0x1000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/clock/intel,stratix10.yaml b/Documentation/devicetree/bindings/clock/intel,stratix10.yaml new file mode 100644 index 000000000000..f506e3db9782 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,stratix10.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Stratix10 platform clock controller binding + +maintainers: + - Dinh Nguyen + +properties: + compatible: + const: intel,stratix10-clkmgr + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@ffd10000 { + compatible = "intel,stratix10-clkmgr"; + reg = <0xffd10000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml new file mode 100644 index 000000000000..a9ad7ab5230c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar/Sigmastar MSC313 CPU PLL + +maintainers: + - Daniel Palmer + +description: | + The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable + PLL that can be used as the clock source for the CPU(s). + +properties: + compatible: + const: mstar,msc313-cpupll + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + #include + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <1>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; diff --git a/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml new file mode 100644 index 000000000000..dc808e2f8327 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml @@ -0,0 +1,198 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tesla FSD (Full Self-Driving) SoC clock controller + +maintainers: + - Alim Akhtar + - linux-fsd@tesla.com + +description: | + FSD clock controller consist of several clock management unit + (CMU), which generates clocks for various inteernal SoC blocks. + The root clock comes from external OSC clock (24 MHz). + + All available clocks are defined as preprocessor macros in + 'dt-bindings/clock/fsd-clk.h' header. + +properties: + compatible: + enum: + - tesla,fsd-clock-cmu + - tesla,fsd-clock-imem + - tesla,fsd-clock-peric + - tesla,fsd-clock-fsys0 + - tesla,fsd-clock-fsys1 + - tesla,fsd-clock-mfc + - tesla,fsd-clock-cam_csi + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + maxItems: 6 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-cmu + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-imem + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: IMEM TCU clock (from CMU_CMU) + - description: IMEM bus clock (from CMU_CMU) + - description: IMEM DMA clock (from CMU_CMU) + clock-names: + items: + - const: fin_pll + - const: dout_cmu_imem_tcuclk + - const: dout_cmu_imem_aclk + - const: dout_cmu_imem_dmaclk + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-peric + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: Shared0 PLL div4 clock (from CMU_CMU) + - description: PERIC shared1 div36 clock (from CMU_CMU) + - description: PERIC shared0 div3 TBU clock (from CMU_CMU) + - description: PERIC shared0 div20 clock (from CMU_CMU) + - description: PERIC shared1 div4 DMAclock (from CMU_CMU) + clock-names: + items: + - const: fin_pll + - const: dout_cmu_pll_shared0_div4 + - const: dout_cmu_peric_shared1div36 + - const: dout_cmu_peric_shared0div3_tbuclk + - const: dout_cmu_peric_shared0div20 + - const: dout_cmu_peric_shared1div4_dmaclk + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-fsys0 + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: Shared0 PLL div6 clock (from CMU_CMU) + - description: FSYS0 shared1 div4 clock (from CMU_CMU) + - description: FSYS0 shared0 div4 clock (from CMU_CMU) + clock-names: + items: + - const: fin_pll + - const: dout_cmu_pll_shared0_div6 + - const: dout_cmu_fsys0_shared1div4 + - const: dout_cmu_fsys0_shared0div4 + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-fsys1 + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + - description: FSYS1 shared0 div8 clock (from CMU_CMU) + - description: FSYS1 shared0 div4 clock (from CMU_CMU) + clock-names: + items: + - const: fin_pll + - const: dout_cmu_fsys1_shared0div8 + - const: dout_cmu_fsys1_shared0div4 + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-mfc + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + contains: + const: tesla,fsd-clock-cam_csi + then: + properties: + clocks: + items: + - description: External reference clock (24 MHz) + clock-names: + items: + - const: fin_pll + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS1 + - | + #include + + clock_fsys1: clock-controller@16810000 { + compatible = "tesla,fsd-clock-fsys1"; + reg = <0x16810000 0x3000>; + #clock-cells = <1>; + + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; + clock-names = "fin_pll", + "dout_cmu_fsys1_shared0div8", + "dout_cmu_fsys1_shared0div4"; + }; + +... diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 5c4c6782e052..590743883802 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -38,6 +38,9 @@ properties: The virtio transport only supports a single device. items: - const: arm,scmi-virtio + - description: SCMI compliant firmware with OP-TEE transport + items: + - const: linaro,scmi-optee interrupts: description: @@ -78,11 +81,24 @@ properties: '#size-cells': const: 0 + atomic-threshold-us: + description: + An optional time value, expressed in microseconds, representing, on this + platform, the threshold above which any SCMI command, advertised to have + an higher-than-threshold execution latency, should not be considered for + atomic mode of operation, even if requested. + default: 0 + arm,smc-id: $ref: /schemas/types.yaml#/definitions/uint32 description: SMC id required when using smc or hvc transports + linaro,optee-channel-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Channel specifier required when using OP-TEE transport. + protocol@11: type: object properties: @@ -195,6 +211,12 @@ patternProperties: minItems: 1 maxItems: 2 + linaro,optee-channel-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Channel specifier required when using OP-TEE transport and + protocol has a dedicated communication channel. + required: - reg @@ -226,6 +248,16 @@ else: - arm,smc-id - shmem + else: + if: + properties: + compatible: + contains: + const: linaro,scmi-optee + then: + required: + - linaro,optee-channel-id + examples: - | firmware { @@ -240,6 +272,8 @@ examples: #address-cells = <1>; #size-cells = <0>; + atomic-threshold-us = <10000>; + scmi_devpd: protocol@11 { reg = <0x11>; #power-domain-cells = <1>; @@ -340,7 +374,48 @@ examples: reg = <0x11>; #power-domain-cells = <1>; }; + }; + }; + - | + firmware { + scmi { + compatible = "linaro,scmi-optee"; + linaro,optee-channel-id = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + scmi_dvfs1: protocol@13 { + reg = <0x13>; + linaro,optee-channel-id = <1>; + shmem = <&cpu_optee_lpri0>; + #clock-cells = <1>; + }; + + scmi_clk0: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + + sram@51000000 { + compatible = "mmio-sram"; + reg = <0x0 0x51000000 0x0 0x10000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x51000000 0x10000>; + + cpu_optee_lpri0: optee-sram-section@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; }; }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt deleted file mode 100644 index f4b4193d830e..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Andestech Internal Vector Interrupt Controller - -The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller -suitable for a simpler SoC platform not requiring a more sophisticated and -bigger External Vector Interrupt Controller. - - -Main node required properties: - -- compatible : should at least contain "andestech,ativic32". -- interrupt-controller : Identifies the node as an interrupt controller -- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts - -Examples: - intc: interrupt-controller { - compatible = "andestech,ativic32"; - #interrupt-cells = <1>; - interrupt-controller; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml new file mode 100644 index 000000000000..f3e62ee07126 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR2 SDRAM AC timing parameters for a given speed-bin + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: jedec,lpddr2-timings + + max-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum DDR clock frequency for the speed-bin, in Hz. + + min-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Minimum DDR clock frequency for the speed-bin, in Hz. + + tCKESR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in pico seconds. + + tDQSCK-max: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + DQS output data access time from CK_t/CK_c in pico seconds. + + tDQSCK-max-derated: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + DQS output data access time from CK_t/CK_c, temperature de-rated, in pico + seconds. + + tFAW: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Four-bank activate window in pico seconds. + + tRAS-max-ns: + description: | + Row active time in nano seconds. + + tRAS-min: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row active time in pico seconds. + + tRCD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + RAS-to-CAS delay in pico seconds. + + tRPab: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (all banks) in pico seconds. + + tRRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Active bank A to active bank B in pico seconds. + + tRTP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal READ to PRECHARGE command delay in pico seconds. + + tWR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WRITE recovery time in pico seconds. + + tWTR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal WRITE-to-READ command delay in pico seconds. + + tXP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Exit power-down to next valid command delay in pico seconds. + + tZQCL: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Long calibration time in pico seconds. + + tZQCS: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Short calibration time in pico seconds. + + tZQinit: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Initialization calibration time in pico seconds. + +required: + - compatible + - min-freq + - max-freq + +additionalProperties: false + +examples: + - | + timings { + compatible = "jedec,lpddr2-timings"; + min-freq = <10000000>; + max-freq = <400000000>; + tCKESR = <15000>; + tDQSCK-max = <5500>; + tFAW = <50000>; + tRAS-max-ns = <70000>; + tRAS-min = <42000>; + tRPab = <21000>; + tRCD = <18000>; + tRRD = <10000>; + tRTP = <7500>; + tWR = <15000>; + tWTR = <7500>; + tXP = <7500>; + tZQCL = <360000>; + tZQCS = <90000>; + tZQinit = <1000000>; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml index 25ed0266f6dd..dd2141cad866 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml @@ -30,12 +30,26 @@ properties: maximum: 255 description: | Revision 1 value of SDRAM chip. Obtained from device datasheet. + Property is deprecated, use revision-id instead. + deprecated: true revision-id2: $ref: /schemas/types.yaml#/definitions/uint32 maximum: 255 description: | Revision 2 value of SDRAM chip. Obtained from device datasheet. + Property is deprecated, use revision-id instead. + deprecated: true + + revision-id: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. ). + minItems: 2 + maxItems: 2 + items: + minimum: 0 + maximum: 255 density: $ref: /schemas/types.yaml#/definitions/uint32 @@ -142,14 +156,12 @@ properties: patternProperties: "^lpddr2-timings": - type: object + $ref: jedec,lpddr2-timings.yaml description: | The lpddr2 node may have one or more child nodes of type "lpddr2-timings". "lpddr2-timings" provides AC timing parameters of the device for a given speed-bin. The user may provide the timings for as many - speed-bins as is required. Please see Documentation/devicetree/ - bindings/memory-controllers/ddr/lpddr2-timings.txt for more information - on "lpddr2-timings". + speed-bins as is required. required: - compatible @@ -164,8 +176,7 @@ examples: compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4"; density = <2048>; io-width = <32>; - revision-id1 = <1>; - revision-id2 = <0>; + revision-id = <1 0>; tRPab-min-tck = <3>; tRCD-min-tck = <3>; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml new file mode 100644 index 000000000000..97c3e988af5f --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR3 SDRAM AC timing parameters for a given speed-bin + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + const: jedec,lpddr3-timings + + reg: + maxItems: 1 + description: | + Maximum DDR clock frequency for the speed-bin, in Hz. + Property is deprecated, use max-freq. + deprecated: true + + max-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum DDR clock frequency for the speed-bin, in Hz. + + min-freq: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Minimum DDR clock frequency for the speed-bin, in Hz. + + tCKE: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds. + + tCKESR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in pico seconds. + + tFAW: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Four-bank activate window in pico seconds. + + tMRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Mode register set command delay in pico seconds. + + tR2R-C2C: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Additional READ-to-READ delay in chip-to-chip cases in pico seconds. + + tRAS: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row active time in pico seconds. + + tRC: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + ACTIVATE-to-ACTIVATE command period in pico seconds. + + tRCD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + RAS-to-CAS delay in pico seconds. + + tRFC: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Refresh Cycle time in pico seconds. + + tRPab: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (all banks) in pico seconds. + + tRPpb: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Row precharge time (single banks) in pico seconds. + + tRRD: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Active bank A to active bank B in pico seconds. + + tRTP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal READ to PRECHARGE command delay in pico seconds. + + tW2W-C2C: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds. + + tWR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + WRITE recovery time in pico seconds. + + tWTR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Internal WRITE-to-READ command delay in pico seconds. + + tXP: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Exit power-down to next valid command delay in pico seconds. + + tXSR: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + SELF REFRESH exit to next valid command delay in pico seconds. + +required: + - compatible + - min-freq + - max-freq + +additionalProperties: false + +examples: + - | + lpddr3 { + timings { + compatible = "jedec,lpddr3-timings"; + max-freq = <800000000>; + min-freq = <100000000>; + tCKE = <3750>; + tCKESR = <3750>; + tFAW = <25000>; + tMRD = <7000>; + tR2R-C2C = <0>; + tRAS = <23000>; + tRC = <33750>; + tRCD = <10000>; + tRFC = <65000>; + tRPab = <12000>; + tRPpb = <12000>; + tRRD = <6000>; + tRTP = <3750>; + tW2W-C2C = <0>; + tWR = <7500>; + tWTR = <3750>; + tXP = <3750>; + tXSR = <70000>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml new file mode 100644 index 000000000000..c542f32c39fa --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml @@ -0,0 +1,263 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LPDDR3 SDRAM compliant to JEDEC JESD209-3 + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + items: + - enum: + - samsung,K3QF2F20DB + - const: jedec,lpddr3 + + '#address-cells': + const: 1 + deprecated: true + + density: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Density in megabits of SDRAM chip. + enum: + - 4096 + - 8192 + - 16384 + - 32768 + + io-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + IO bus width in bits of SDRAM chip. + enum: + - 32 + - 16 + + manufacturer-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Manufacturer ID value read from Mode Register 5. The property is + deprecated, manufacturer should be derived from the compatible. + deprecated: true + + revision-id: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + maximum: 255 + description: | + Revision value of SDRAM chip read from Mode Registers 6 and 7. + + '#size-cells': + const: 0 + deprecated: true + + tCKE-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + CKE minimum pulse width (HIGH and LOW pulse width) in terms of number + of clock cycles. + + tCKESR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + CKE minimum pulse width during SELF REFRESH (low pulse width during + SELF REFRESH) in terms of number of clock cycles. + + tDQSCK-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + DQS output data access time from CK_t/CK_c in terms of number of clock + cycles. + + tFAW-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + Four-bank activate window in terms of number of clock cycles. + + tMRD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Mode register set command delay in terms of number of clock cycles. + + tR2R-C2C-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Additional READ-to-READ delay in chip-to-chip cases in terms of number + of clock cycles. + + tRAS-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + Row active time in terms of number of clock cycles. + + tRC-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 63 + description: | + ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles. + + tRCD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + RAS-to-CAS delay in terms of number of clock cycles. + + tRFC-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Refresh Cycle time in terms of number of clock cycles. + + tRL-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + READ data latency in terms of number of clock cycles. + + tRPab-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Row precharge time (all banks) in terms of number of clock cycles. + + tRPpb-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Row precharge time (single banks) in terms of number of clock cycles. + + tRRD-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Active bank A to active bank B in terms of number of clock cycles. + + tRTP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Internal READ to PRECHARGE command delay in terms of number of clock + cycles. + + tW2W-C2C-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number + of clock cycles. + + tWL-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + WRITE data latency in terms of number of clock cycles. + + tWR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + WRITE recovery time in terms of number of clock cycles. + + tWTR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + description: | + Internal WRITE-to-READ command delay in terms of number of clock cycles. + + tXP-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 255 + description: | + Exit power-down to next valid command delay in terms of number of clock + cycles. + + tXSR-min-tck: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 1023 + description: | + SELF REFRESH exit to next valid command delay in terms of number of clock + cycles. + +patternProperties: + "^timings((-[0-9])+|(@[0-9a-f]+))?$": + $ref: jedec,lpddr3-timings.yaml + description: | + The lpddr3 node may have one or more child nodes with timings. + Each timing node provides AC timing parameters of the device for a given + speed-bin. The user may provide the timings for as many speed-bins as is + required. + +required: + - compatible + - density + - io-width + +additionalProperties: false + +examples: + - | + lpddr3 { + compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; + density = <16384>; + io-width = <32>; + + tCKE-min-tck = <2>; + tCKESR-min-tck = <2>; + tDQSCK-min-tck = <5>; + tFAW-min-tck = <5>; + tMRD-min-tck = <5>; + tR2R-C2C-min-tck = <0>; + tRAS-min-tck = <5>; + tRC-min-tck = <6>; + tRCD-min-tck = <3>; + tRFC-min-tck = <17>; + tRL-min-tck = <14>; + tRPab-min-tck = <2>; + tRPpb-min-tck = <2>; + tRRD-min-tck = <2>; + tRTP-min-tck = <2>; + tW2W-C2C-min-tck = <0>; + tWL-min-tck = <8>; + tWR-min-tck = <7>; + tWTR-min-tck = <2>; + tXP-min-tck = <2>; + tXSR-min-tck = <12>; + + timings { + compatible = "jedec,lpddr3-timings"; + max-freq = <800000000>; + min-freq = <100000000>; + tCKE = <3750>; + tCKESR = <3750>; + tFAW = <25000>; + tMRD = <7000>; + tR2R-C2C = <0>; + tRAS = <23000>; + tRC = <33750>; + tRCD = <10000>; + tRFC = <65000>; + tRPab = <12000>; + tRPpb = <12000>; + tRRD = <6000>; + tRTP = <3750>; + tW2W-C2C = <0>; + tWR = <7500>; + tWTR = <3750>; + tXP = <3750>; + tXSR = <70000>; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt deleted file mode 100644 index 9ceb19e0c7fd..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr2-timings.txt +++ /dev/null @@ -1,52 +0,0 @@ -* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin - -Required properties: -- compatible : Should be "jedec,lpddr2-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- max-freq : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). Parameters with -a different unit have a suffix indicating the unit such as 'tRAS-max-ns' -- tRCD -- tWR -- tRAS-min -- tRRD -- tWTR -- tXP -- tRTP -- tDQSCK-max -- tFAW -- tZQCS -- tZQinit -- tRPab -- tZQCL -- tCKESR -- tRAS-max-ns -- tDQSCK-max-derated - -Example: - -timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 { - compatible = "jedec,lpddr2-timings"; - min-freq = <10000000>; - max-freq = <400000000>; - tRPab = <21000>; - tRCD = <18000>; - tWR = <15000>; - tRAS-min = <42000>; - tRRD = <10000>; - tWTR = <7500>; - tXP = <7500>; - tRTP = <7500>; - tCKESR = <15000>; - tDQSCK-max = <5500>; - tFAW = <50000>; - tZQCS = <90000>; - tZQCL = <360000>; - tZQinit = <1000000>; - tRAS-max-ns = <70000>; -}; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt deleted file mode 100644 index 84705e50a3fd..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt +++ /dev/null @@ -1,58 +0,0 @@ -* AC timing parameters of LPDDR3 memories for a given speed-bin. - -The structures are based on LPDDR2 and extended where needed. - -Required properties: -- compatible : Should be "jedec,lpddr3-timings" -- min-freq : minimum DDR clock frequency for the speed-bin. Type is -- reg : maximum DDR clock frequency for the speed-bin. Type is - -Optional properties: - -The following properties represent AC timing parameters from the memory -data-sheet of the device for a given speed-bin. All these properties are -of type and the default unit is ps (pico seconds). -- tRFC -- tRRD -- tRPab -- tRPpb -- tRCD -- tRC -- tRAS -- tWTR -- tWR -- tRTP -- tW2W-C2C -- tR2R-C2C -- tFAW -- tXSR -- tXP -- tCKE -- tCKESR -- tMRD - -Example: - -timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { - compatible = "jedec,lpddr3-timings"; - reg = <800000000>; /* workaround: it shows max-freq */ - min-freq = <100000000>; - tRFC = <65000>; - tRRD = <6000>; - tRPab = <12000>; - tRPpb = <12000>; - tRCD = <10000>; - tRC = <33750>; - tRAS = <23000>; - tWTR = <3750>; - tWR = <7500>; - tRTP = <3750>; - tW2W-C2C = <0>; - tR2R-C2C = <0>; - tFAW = <25000>; - tXSR = <70000>; - tXP = <3750>; - tCKE = <3750>; - tCKESR = <3750>; - tMRD = <7000>; -}; diff --git a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt b/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt deleted file mode 100644 index 031af5fb0379..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt +++ /dev/null @@ -1,107 +0,0 @@ -* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C - -Required properties: -- compatible : Should be ",", and generic value "jedec,lpddr3". - Example "," values: - "samsung,K3QF2F20DB" - -- density : representing density in Mb (Mega bits) -- io-width : representing bus width. Possible values are 8, 16, 32, 64 -- #address-cells: Must be set to 1 -- #size-cells: Must be set to 0 - -Optional properties: - -- manufacturer-id : Manufacturer ID value read from Mode Register 5 -- revision-id : Revision IDs read from Mode Registers 6 and 7 - -The following optional properties represent the minimum value of some AC -timing parameters of the DDR device in terms of number of clock cycles. -These values shall be obtained from the device data-sheet. -- tRFC-min-tck -- tRRD-min-tck -- tRPab-min-tck -- tRPpb-min-tck -- tRCD-min-tck -- tRC-min-tck -- tRAS-min-tck -- tWTR-min-tck -- tWR-min-tck -- tRTP-min-tck -- tW2W-C2C-min-tck -- tR2R-C2C-min-tck -- tWL-min-tck -- tDQSCK-min-tck -- tRL-min-tck -- tFAW-min-tck -- tXSR-min-tck -- tXP-min-tck -- tCKE-min-tck -- tCKESR-min-tck -- tMRD-min-tck - -Child nodes: -- The lpddr3 node may have one or more child nodes of type "lpddr3-timings". - "lpddr3-timings" provides AC timing parameters of the device for - a given speed-bin. Please see - Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt - for more information on "lpddr3-timings" - -Example: - -samsung_K3QF2F20DB: lpddr3 { - compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; - density = <16384>; - io-width = <32>; - manufacturer-id = <1>; - revision-id = <123 234>; - #address-cells = <1>; - #size-cells = <0>; - - tRFC-min-tck = <17>; - tRRD-min-tck = <2>; - tRPab-min-tck = <2>; - tRPpb-min-tck = <2>; - tRCD-min-tck = <3>; - tRC-min-tck = <6>; - tRAS-min-tck = <5>; - tWTR-min-tck = <2>; - tWR-min-tck = <7>; - tRTP-min-tck = <2>; - tW2W-C2C-min-tck = <0>; - tR2R-C2C-min-tck = <0>; - tWL-min-tck = <8>; - tDQSCK-min-tck = <5>; - tRL-min-tck = <14>; - tFAW-min-tck = <5>; - tXSR-min-tck = <12>; - tXP-min-tck = <2>; - tCKE-min-tck = <2>; - tCKESR-min-tck = <2>; - tMRD-min-tck = <5>; - - timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { - compatible = "jedec,lpddr3-timings"; - /* workaround: 'reg' shows max-freq */ - reg = <800000000>; - min-freq = <100000000>; - tRFC = <65000>; - tRRD = <6000>; - tRPab = <12000>; - tRPpb = <12000>; - tRCD = <10000>; - tRC = <33750>; - tRAS = <23000>; - tWTR = <3750>; - tWR = <7500>; - tRTP = <3750>; - tW2W-C2C = <0>; - tR2R-C2C = <0>; - tFAW = <25000>; - tXSR = <70000>; - tXP = <3750>; - tCKE = <3750>; - tCKESR = <3750>; - tMRD = <7000>; - }; -} diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml new file mode 100644 index 000000000000..3be1db30bf41 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/fsl,ifc.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FSL/NXP Integrated Flash Controller + +maintainers: + - Li Yang + +description: | + NXP's integrated flash controller (IFC) is an advanced version of the + enhanced local bus controller which includes similar programming and signal + interfaces with an extended feature set. The IFC provides access to multiple + external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM, + SRAM and other memories where address and data are shared on a bus. + +properties: + $nodename: + pattern: "^memory-controller@[0-9a-f]+$" + + compatible: + const: fsl,ifc + + "#address-cells": + enum: [2, 3] + description: | + Should be either two or three. The first cell is the chipselect + number, and the remaining cells are the offset into the chipselect. + + "#size-cells": + enum: [1, 2] + description: | + Either one or two, depending on how large each chipselect can be. + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + description: | + IFC may have one or two interrupts. If two interrupt specifiers are + present, the first is the "common" interrupt (CM_EVTER_STAT), and the + second is the NAND interrupt (NAND_EVTER_STAT). If there is only one, + that interrupt reports both types of event. + + little-endian: + type: boolean + description: | + If this property is absent, the big-endian mode will be in use as default + for registers. + + ranges: + description: | + Each range corresponds to a single chipselect, and covers the entire + access window as configured. + +patternProperties: + "^.*@[a-f0-9]+(,[a-f0-9]+)+$": + type: object + description: | + Child device nodes describe the devices connected to IFC such as NOR (e.g. + cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices + like FPGAs, CPLDs, etc. + + required: + - compatible + - reg + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + memory-controller@ffe1e000 { + compatible = "fsl,ifc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0x0 0xffe1e000 0 0x2000>; + interrupts = <16 2 19 2>; + little-endian; + + /* NOR, NAND Flashes and CPLD on board */ + ranges = <0x0 0x0 0x0 0xee000000 0x02000000>, + <0x1 0x0 0x0 0xffa00000 0x00010000>, + <0x3 0x0 0x0 0xffb00000 0x00020000>; + + flash@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x2000000>; + bank-width = <2>; + device-width = <1>; + + partition@0 { + /* 32MB for user data */ + reg = <0x0 0x02000000>; + label = "NOR Data"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt b/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt deleted file mode 100644 index 89427b018ba7..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt +++ /dev/null @@ -1,82 +0,0 @@ -Integrated Flash Controller - -Properties: -- name : Should be ifc -- compatible : should contain "fsl,ifc". The version of the integrated - flash controller can be found in the IFC_REV register at - offset zero. - -- #address-cells : Should be either two or three. The first cell is the - chipselect number, and the remaining cells are the - offset into the chipselect. -- #size-cells : Either one or two, depending on how large each chipselect - can be. -- reg : Offset and length of the register set for the device -- interrupts: IFC may have one or two interrupts. If two interrupt - specifiers are present, the first is the "common" - interrupt (CM_EVTER_STAT), and the second is the NAND - interrupt (NAND_EVTER_STAT). If there is only one, - that interrupt reports both types of event. - -- little-endian : If this property is absent, the big-endian mode will - be in use as default for registers. - -- ranges : Each range corresponds to a single chipselect, and covers - the entire access window as configured. - -Child device nodes describe the devices connected to IFC such as NOR (e.g. -cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices -like FPGAs, CPLDs, etc. - -Example: - - ifc@ffe1e000 { - compatible = "fsl,ifc", "simple-bus"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x0 0xffe1e000 0 0x2000>; - interrupts = <16 2 19 2>; - little-endian; - - /* NOR, NAND Flashes and CPLD on board */ - ranges = <0x0 0x0 0x0 0xee000000 0x02000000 - 0x1 0x0 0x0 0xffa00000 0x00010000 - 0x3 0x0 0x0 0xffb00000 0x00020000>; - - flash@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x2000000>; - bank-width = <2>; - device-width = <1>; - - partition@0 { - /* 32MB for user data */ - reg = <0x0 0x02000000>; - label = "NOR Data"; - }; - }; - - flash@1,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,ifc-nand"; - reg = <0x1 0x0 0x10000>; - - partition@0 { - /* This location must not be altered */ - /* 1MB for u-boot Bootloader Image */ - reg = <0x0 0x00100000>; - label = "NAND U-Boot Image"; - read-only; - }; - }; - - cpld@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,p1010rdb-cpld"; - reg = <0x3 0x0 0x000001f>; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index 3a82b0b27fa0..a98b359bf909 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -16,7 +16,7 @@ description: | MediaTek SMI have two generations of HW architecture, here is the list which generation the SoCs use: generation 1: mt2701 and mt7623. - generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8192 and mt8195. + generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8192 and mt8195. There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. But @@ -35,6 +35,7 @@ properties: - mediatek,mt8167-smi-common - mediatek,mt8173-smi-common - mediatek,mt8183-smi-common + - mediatek,mt8186-smi-common - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp @@ -88,10 +89,9 @@ allOf: - mediatek,mt2701-smi-common then: properties: - clock: - items: - minItems: 3 - maxItems: 3 + clocks: + minItems: 3 + maxItems: 3 clock-names: items: - const: apb @@ -108,10 +108,9 @@ allOf: required: - mediatek,smi properties: - clock: - items: - minItems: 3 - maxItems: 3 + clocks: + minItems: 3 + maxItems: 3 clock-names: items: - const: apb @@ -127,16 +126,16 @@ allOf: enum: - mediatek,mt6779-smi-common - mediatek,mt8183-smi-common + - mediatek,mt8186-smi-common - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp then: properties: - clock: - items: - minItems: 4 - maxItems: 4 + clocks: + minItems: 4 + maxItems: 4 clock-names: items: - const: apb @@ -146,10 +145,9 @@ allOf: else: # for gen2 HW that don't have gals properties: - clock: - items: - minItems: 2 - maxItems: 2 + clocks: + minItems: 2 + maxItems: 2 clock-names: items: - const: apb diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index eaeff1ada7f8..4db8690829cd 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -23,6 +23,7 @@ properties: - mediatek,mt8167-smi-larb - mediatek,mt8173-smi-larb - mediatek,mt8183-smi-larb + - mediatek,mt8186-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb @@ -75,15 +76,16 @@ allOf: compatible: enum: - mediatek,mt8183-smi-larb + - mediatek,mt8186-smi-larb - mediatek,mt8195-smi-larb then: properties: - clock: - items: - minItems: 3 - maxItems: 3 + clocks: + minItems: 2 + maxItems: 3 clock-names: + minItems: 2 items: - const: apb - const: smi @@ -91,10 +93,9 @@ allOf: else: properties: - clock: - items: - minItems: 2 - maxItems: 2 + clocks: + minItems: 2 + maxItems: 2 clock-names: items: - const: apb @@ -108,7 +109,7 @@ allOf: - mediatek,mt2701-smi-larb - mediatek,mt2712-smi-larb - mediatek,mt6779-smi-larb - - mediatek,mt8167-smi-larb + - mediatek,mt8186-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml index 294f1036420d..9a6dbf54b540 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml @@ -40,7 +40,8 @@ properties: - items: - enum: - renesas,r9a07g044-rpc-if # RZ/G2{L,LC} - - const: renesas,rzg2l-rpc-if # RZ/G2L family + - renesas,r9a07g054-rpc-if # RZ/V2L + - const: renesas,rzg2l-rpc-if reg: items: diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml index fe8639dcffab..044127788695 100644 --- a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml @@ -51,8 +51,7 @@ properties: $ref: '/schemas/types.yaml#/definitions/phandle' description: | phandle of the connected DRAM memory device. For more information please - refer to documentation file: - Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt + refer to jedec,lpddr3.yaml. operating-points-v2: true diff --git a/Documentation/devicetree/bindings/nds32/andestech-boards b/Documentation/devicetree/bindings/nds32/andestech-boards deleted file mode 100644 index f5d75693e3c7..000000000000 --- a/Documentation/devicetree/bindings/nds32/andestech-boards +++ /dev/null @@ -1,40 +0,0 @@ -Andestech(nds32) AE3XX Platform ------------------------------------------------------------------------------ -The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It -is composed of one Andestech(nds32) processor and AE3XX. - -Required properties (in root node): -- compatible = "andestech,ae3xx"; - -Example: -/dts-v1/; -/ { - compatible = "andestech,ae3xx"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; -}; - -Andestech(nds32) AG101P Platform ------------------------------------------------------------------------------ -AG101P is a generic SoC Platform IP that works with any of Andestech(nds32) -processors to provide a cost-effective and high performance solution for -majority of embedded systems in variety of application domains. Users may -simply attach their IP on one of the system buses together with certain glue -logics to complete a SoC solution for a specific application. With -comprehensive simulation and design environments, users may evaluate the -system performance of their applications and track bugs of their designs -efficiently. The optional hardware development platform further provides real -system environment for early prototyping and software/hardware co-development. - -Required properties (in root node): - compatible = "andestech,ag101p"; - -Example: -/dts-v1/; -/ { - compatible = "andestech,ag101p"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; -}; diff --git a/Documentation/devicetree/bindings/nds32/atl2c.txt b/Documentation/devicetree/bindings/nds32/atl2c.txt deleted file mode 100644 index da8ab8e7ae9b..000000000000 --- a/Documentation/devicetree/bindings/nds32/atl2c.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Andestech L2 cache Controller - -The level-2 cache controller plays an important role in reducing memory latency -for high performance systems, such as thoese designs with AndesCore processors. -Level-2 cache controller in general enhances overall system performance -signigicantly and the system power consumption might be reduced as well by -reducing DRAM accesses. - -This binding specifies what properties must be available in the device tree -representation of an Andestech L2 cache controller. - -Required properties: - - compatible: - Usage: required - Value type: - Definition: "andestech,atl2c" - - reg : Physical base address and size of cache controller's memory mapped - - cache-unified : Specifies the cache is a unified cache. - - cache-level : Should be set to 2 for a level 2 cache. - -* Example - - cache-controller@e0500000 { - compatible = "andestech,atl2c"; - reg = <0xe0500000 0x1000>; - cache-unified; - cache-level = <2>; - }; diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt b/Documentation/devicetree/bindings/nds32/cpus.txt deleted file mode 100644 index 6f9e311b6589..000000000000 --- a/Documentation/devicetree/bindings/nds32/cpus.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Andestech Processor Binding - -This binding specifies what properties must be available in the device tree -representation of a Andestech Processor Core, which is the root node in the -tree. - -Required properties: - - - compatible: - Usage: required - Value type: - Definition: Should be "andestech,", "andestech,nds32v3" as fallback. - Must contain "andestech,nds32v3" as the most generic value, in addition to - one of the following identifiers for a particular CPU core: - "andestech,n13" - "andestech,n15" - "andestech,d15" - "andestech,n10" - "andestech,d10" - - device_type - Usage: required - Value type: - Definition: must be "cpu" - - reg: Contains CPU index. - - clock-frequency: Contains the clock frequency for CPU, in Hz. - -* Examples - -/ { - cpus { - cpu@0 { - device_type = "cpu"; - compatible = "andestech,n13", "andestech,nds32v3"; - reg = <0x0>; - clock-frequency = <60000000> - }; - }; -}; diff --git a/Documentation/devicetree/bindings/perf/nds32v3-pmu.txt b/Documentation/devicetree/bindings/perf/nds32v3-pmu.txt deleted file mode 100644 index 1bd15785b4ae..000000000000 --- a/Documentation/devicetree/bindings/perf/nds32v3-pmu.txt +++ /dev/null @@ -1,17 +0,0 @@ -* NDS32 Performance Monitor Units - -NDS32 core have a PMU for counting cpu and cache events like cache misses. -The NDS32 PMU representation in the device tree should be done as under: - -Required properties: - -- compatible : - "andestech,nds32v3-pmu" - -- interrupts : The interrupt number for NDS32 PMU is 13. - -Example: -pmu{ - compatible = "andestech,nds32v3-pmu"; - interrupts = <13>; -} diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt b/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt index b3b75c1e6285..6814dccb390c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom,usb-hs-phy.txt @@ -9,6 +9,7 @@ PROPERTIES following: "qcom,usb-hs-phy-apq8064" + "qcom,usb-hs-phy-msm8226" "qcom,usb-hs-phy-msm8916" "qcom,usb-hs-phy-msm8974" diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-gpio-bank.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-gpio-bank.yaml new file mode 100644 index 000000000000..f73348c54748 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-gpio-bank.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-gpio-bank.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank + +maintainers: + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller. + + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for + additional information and example. + +properties: + '#gpio-cells': + const: 2 + + gpio-controller: true + + '#interrupt-cells': + description: + For GPIO banks supporting external GPIO interrupts or external wake-up + interrupts. + const: 2 + + interrupt-controller: + description: + For GPIO banks supporting external GPIO interrupts or external wake-up + interrupts. + + interrupts: + description: + For GPIO banks supporting direct external wake-up interrupts (without + multiplexing). Number of interrupts must match number of wake-up capable + pins of this bank. + minItems: 1 + maxItems: 8 + +required: + - '#gpio-cells' + - gpio-controller + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml new file mode 100644 index 000000000000..c71939ac8b63 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-pins-cfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration + +maintainers: + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller. + + The values used for config properties should be derived from the hardware + manual and these values are programmed as-is into the pin pull up/down and + driver strength register of the pin-controller. + See also include/dt-bindings/pinctrl/samsung.h with useful constants. + + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for + additional information and example. + +properties: + samsung,pins: + description: | + List of pins to configure. For initial and sleep states, the maximum + number is one pin. In other cases there is no upper limit. + + The pins should use lowercase names matching hardware manual, e.g. for + GPA0 bank: gpa0-0, gpa0-1, gpa0-2. + $ref: /schemas/types.yaml#/definitions/string-array + + samsung,pin-function: + description: | + The pin function selection that should be applied on the pins listed in the + child node is specified using the "samsung,pin-function" property. The value + of this property that should be applied to each of the pins listed in the + "samsung,pins" property should be picked from the hardware manual of the SoC + for the specified pin group. This property is optional in the child node if + no specific function selection is desired for the pins listed in the child + node. The value of this property is used as-is to program the pin-controller + function selector register of the pin-bank. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + + samsung,pin-drv: + description: Drive strength configuration. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + + samsung,pin-pud: + description: Pull up/down configuration. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + samsung,pin-val: + description: Initial value of pin output buffer. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + samsung,pin-con-pdn: + description: Function in power down mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + samsung,pin-pud-pdn: + description: Pull up/down configuration in power down mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + +required: + - samsung,pins + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml new file mode 100644 index 000000000000..a822f70f5702 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller - wake-up interrupt controller + +maintainers: + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller. + For S3C24xx, S3C64xx, S5PV210 and Exynos4210 compatible wake-up interrupt + controllers, only one pin-controller device node can include external wake-up + interrupts child node (in other words, only one External wake-up interrupts + pin-controller is supported). + For newer controllers, multiple pin-controller device node can include + external wake-up interrupts child node. + + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s3c2410-wakeup-eint + - samsung,s3c2412-wakeup-eint + - samsung,s3c64xx-wakeup-eint + - samsung,s5pv210-wakeup-eint + - samsung,exynos4210-wakeup-eint + - samsung,exynos7-wakeup-eint + - samsung,exynos850-wakeup-eint + - samsung,exynosautov9-wakeup-eint + + interrupts: + description: + Interrupt used by multiplexed external wake-up interrupts. + minItems: 1 + maxItems: 6 + +required: + - compatible + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,s3c2410-wakeup-eint + - samsung,s3c2412-wakeup-eint + then: + properties: + interrupts: + minItems: 6 + maxItems: 6 + required: + - interrupts + + - if: + properties: + compatible: + contains: + const: samsung,s3c64xx-wakeup-eint + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + required: + - interrupts + + - if: + properties: + compatible: + contains: + enum: + - samsung,s5pv210-wakeup-eint + - samsung,exynos4210-wakeup-eint + - samsung,exynos7-wakeup-eint + then: + properties: + interrupts: + minItems: 1 + maxItems: 1 + required: + - interrupts + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-wakeup-eint + - samsung,exynosautov9-wakeup-eint + then: + properties: + interrupts: false + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml new file mode 100644 index 000000000000..28f0851d07bb --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -0,0 +1,392 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller + +maintainers: + - Krzysztof Kozlowski + - Sylwester Nawrocki + - Tomasz Figa + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + Pin group settings (like drive strength, pull up/down) are available as + macros in include/dt-bindings/pinctrl/samsung.h. + + All the pin controller nodes should be represented in the aliases node using + the following format 'pinctrl{n}' where n is a unique number for the alias. + + The controller supports three types of interrupts:: + - External GPIO interrupts (see interrupts property in pin controller node); + + - External wake-up interrupts - multiplexed (capable of waking up the system + see interrupts property in external wake-up interrupt controller node - + samsung,pinctrl-wakeup-interrupt.yaml); + + - External wake-up interrupts - direct (capable of waking up the system, see + interrupts property in every bank of pin controller with external wake-up + interrupt controller - samsung,pinctrl-gpio-bank.yaml). + +properties: + $nodename: + pattern: "^pinctrl(@.*)?" + + compatible: + enum: + - samsung,s3c2412-pinctrl + - samsung,s3c2416-pinctrl + - samsung,s3c2440-pinctrl + - samsung,s3c2450-pinctrl + - samsung,s3c64xx-pinctrl + - samsung,s5pv210-pinctrl + - samsung,exynos3250-pinctrl + - samsung,exynos4210-pinctrl + - samsung,exynos4x12-pinctrl + - samsung,exynos5250-pinctrl + - samsung,exynos5260-pinctrl + - samsung,exynos5410-pinctrl + - samsung,exynos5420-pinctrl + - samsung,exynos5433-pinctrl + - samsung,exynos7-pinctrl + - samsung,exynos7885-pinctrl + - samsung,exynos850-pinctrl + - samsung,exynosautov9-pinctrl + + interrupts: + description: + Required for GPIO banks supporting external GPIO interrupts. + maxItems: 1 + + power-domains: + maxItems: 1 + + reg: + description: + Second base address of the pin controller if the specific registers of + the pin controller are separated into the different base address. + Only certain banks of certain pin controller might need it. + minItems: 1 + maxItems: 2 + + wakeup-interrupt-controller: + $ref: samsung,pinctrl-wakeup-interrupt.yaml + +patternProperties: + "^[a-z]+[0-9]*-gpio-bank$": + description: + Pin banks of the controller are represented by child nodes of the + controller node. Bank name is taken from name of the node. + $ref: samsung,pinctrl-gpio-bank.yaml + + "^[a-z0-9-]+-pins$": + oneOf: + - $ref: samsung,pinctrl-pins-cfg.yaml + required: + - samsung,pins + - type: object + patternProperties: + "^[a-z0-9-]+-pins$": + $ref: samsung,pinctrl-pins-cfg.yaml + + additionalProperties: false + + "^(initial|sleep)-state$": + patternProperties: + "^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$": + $ref: samsung,pinctrl-pins-cfg.yaml + + properties: + samsung,pins: + description: See samsung,pinctrl-pins-cfg.yaml + $ref: /schemas/types.yaml#/definitions/string-array + maxItems: 1 + + required: + - samsung,pins + + unevaluatedProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: "pinctrl.yaml#" + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-pinctrl + then: + properties: + reg: + minItems: 1 + maxItems: 2 + else: + properties: + reg: + minItems: 1 + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include + + pinctrl@7f008000 { + compatible = "samsung,s3c64xx-pinctrl"; + reg = <0x7f008000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <21>; + + wakeup-interrupt-controller { + compatible = "samsung,s3c64xx-wakeup-eint"; + interrupts-extended = <&vic0 0>, + <&vic0 1>, + <&vic1 0>, + <&vic1 1>; + }; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpa-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // ... + + uart0-data-pins { + samsung,pins = "gpa-0", "gpa-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + // ... + }; + + - | + #include + #include + + pinctrl@11400000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = ; + + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // ... + + uart0-data-pins { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + // ... + + sleep0: sleep-state { + gpa0-0-pin { + samsung,pins = "gpa0-0"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + gpa0-1-pin { + samsung,pins = "gpa0-1"; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + // ... + }; + }; + + - | + #include + #include + + pinctrl@11000000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpj0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* Pin bank without external interrupts */ + gpy0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + /* Pin bank with external direct wake-up interrupts */ + gpx0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + // ... + + sd0-clk-pins { + samsung,pins = "gpk0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd4-bus-width8-pins { + part-1-pins { + samsung,pins = "gpk0-3", "gpk0-4", + "gpk0-5", "gpk0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + part-2-pins { + samsung,pins = "gpk1-3", "gpk1-4", + "gpk1-5", "gpk1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + }; + + // ... + + otg-gp-pins { + samsung,pins = "gpx3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-val = <0>; + }; + }; + + - | + #include + #include + + pinctrl@10580000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10580000 0x1a20>, <0x11090000 0x100>; + + pinctrl-names = "default"; + pinctrl-0 = <&initial_alive>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + interrupts = ; + }; + + /* Pin bank with external direct wake-up interrupts */ + gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + #interrupt-cells = <2>; + }; + + // ... + + te-irq-pins { + samsung,pins = "gpf1-3"; + samsung,pin-function = <0xf>; + }; + + // .. + + initial_alive: initial-state { + gpa0-0-pin { + samsung,pins = "gpa0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + // ... + }; + }; + + - | + #include + #include + + pinctrl@114b0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x114b0000 0x1000>; + interrupts = ; + power-domains = <&pd_aud>; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpz0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // ... + + i2s0-bus-pins { + samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", + "gpz0-4", "gpz0-5", "gpz0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + // ... + }; diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt deleted file mode 100644 index 9e70edceb21b..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ /dev/null @@ -1,383 +0,0 @@ -Samsung GPIO and Pin Mux/Config controller - -Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware -controller. It controls the input/output settings on the available pads/pins -and also provides ability to multiplex and configure the output of various -on-chip controllers onto these pads. - -Required Properties: -- compatible: should be one of the following. - - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller, - - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller, - - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller, - - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller, - - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller, - - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller, - - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller. - - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller. - - "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller. - - "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller. - - "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller. - - "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller. - - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. - - "samsung,exynos7885-pinctrl": for Exynos7885 compatible pin-controller. - - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. - - "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller. - -- reg: Base address of the pin controller hardware module and length of - the address space it occupies. - - - reg: Second base address of the pin controller if the specific registers - of the pin controller are separated into the different base address. - - Eg: GPF[1-5] of Exynos5433 are separated into the two base address. - - First base address is for GPAx and GPF[1-5] external interrupt - registers. - - Second base address is for GPF[1-5] pinctrl registers. - - pinctrl_0: pinctrl@10580000 { - compatible = "samsung,exynos5433-pinctrl"; - reg = <0x10580000 0x1a20>, <0x11090000 0x100>; - - wakeup-interrupt-controller { - compatible = "samsung,exynos7-wakeup-eint"; - interrupts = <0 16 0>; - }; - }; - -- Pin banks as child nodes: Pin banks of the controller are represented by child - nodes of the controller node. Bank name is taken from name of the node. Each - bank node must contain following properties: - - - gpio-controller: identifies the node as a gpio controller and pin bank. - - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO - binding is used, the amount of cells must be specified as 2. See the below - mentioned gpio binding representation for description of particular cells. - - Eg: <&gpx2 6 0> - <[phandle of the gpio controller node] - [pin number within the gpio controller] - [flags]> - - Values for gpio specifier: - - Pin number: is a value between 0 to 7. - - Flags: 0 - Active High - 1 - Active Low - -- Pin mux/config groups as child nodes: The pin mux (selecting pin function - mode) and pin config (pull up/down, driver strength) settings are represented - as child nodes of the pin-controller node. There should be at least one - child node and there is no limit on the count of these child nodes. It is - also possible for a child node to consist of several further child nodes - to allow grouping multiple pinctrl groups into one. The format of second - level child nodes is exactly the same as for first level ones and is - described below. - - The child node should contain a list of pin(s) on which a particular pin - function selection or pin configuration (or both) have to applied. This - list of pins is specified using the property name "samsung,pins". There - should be at least one pin specified for this property and there is no upper - limit on the count of pins that can be specified. The pins are specified - using pin names which are derived from the hardware manual of the SoC. As - an example, the pins in GPA0 bank of the pin controller can be represented - as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case. - The format of the pin names should be (as per the hardware manual) - "[pin bank name]-[pin number within the bank]". - - The pin function selection that should be applied on the pins listed in the - child node is specified using the "samsung,pin-function" property. The value - of this property that should be applied to each of the pins listed in the - "samsung,pins" property should be picked from the hardware manual of the SoC - for the specified pin group. This property is optional in the child node if - no specific function selection is desired for the pins listed in the child - node. The value of this property is used as-is to program the pin-controller - function selector register of the pin-bank. - - The child node can also optionally specify one or more of the pin - configuration that should be applied on all the pins listed in the - "samsung,pins" property of the child node. The following pin configuration - properties are supported. - - - samsung,pin-val: Initial value of pin output buffer. - - samsung,pin-pud: Pull up/down configuration. - - samsung,pin-drv: Drive strength configuration. - - samsung,pin-pud-pdn: Pull up/down configuration in power down mode. - - samsung,pin-drv-pdn: Drive strength configuration in power down mode. - - The values specified by these config properties should be derived from the - hardware manual and these values are programmed as-is into the pin - pull up/down and driver strength register of the pin-controller. - - Note: A child should include at least a pin function selection property or - pin configuration property (one or more) or both. - - The client nodes that require a particular pin function selection and/or - pin configuration should use the bindings listed in the "pinctrl-bindings.txt" - file. - -External GPIO and Wakeup Interrupts: - -The controller supports two types of external interrupts over gpio. The first -is the external gpio interrupt and second is the external wakeup interrupts. -The difference between the two is that the external wakeup interrupts can be -used as system wakeup events. - -A. External GPIO Interrupts: For supporting external gpio interrupts, the - following properties should be specified in the pin-controller device node. - - - interrupts: interrupt specifier for the controller. The format and value of - the interrupt specifier depends on the interrupt parent for the controller. - - In addition, following properties must be present in node of every bank - of pins supporting GPIO interrupts: - - - interrupt-controller: identifies the controller node as interrupt-parent. - - #interrupt-cells: the value of this property should be 2. - - First Cell: represents the external gpio interrupt number local to the - external gpio interrupt space of the controller. - - Second Cell: flags to identify the type of the interrupt - - 1 = rising edge triggered - - 2 = falling edge triggered - - 3 = rising and falling edge triggered - - 4 = high level triggered - - 8 = low level triggered - -B. External Wakeup Interrupts: For supporting external wakeup interrupts, a - child node representing the external wakeup interrupt controller should be - included in the pin-controller device node. - - Only one pin-controller device node can include external wakeup interrupts - child node (in other words, only one External Wakeup Interrupts - pin-controller is supported). - - This child node should include following properties: - - - compatible: identifies the type of the external wakeup interrupt controller - The possible values are: - - samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller - found on Samsung S3C24xx SoCs except S3C2412 and S3C2413, - - samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller - found on Samsung S3C2412 and S3C2413 SoCs, - - samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller - found on Samsung S3C64xx SoCs, - - samsung,s5pv210-wakeup-eint: represents wakeup interrupt controller - found on Samsung S5Pv210 SoCs, - - samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller - found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs. - - samsung,exynos7-wakeup-eint: represents wakeup interrupt controller - found on Samsung Exynos7 SoC. - - interrupts: interrupt used by multiplexed wakeup interrupts. - - In addition, following properties must be present in node of every bank - of pins supporting wake-up interrupts: - - - interrupt-controller: identifies the node as interrupt-parent. - - #interrupt-cells: the value of this property should be 2 - - First Cell: represents the external wakeup interrupt number local to - the external wakeup interrupt space of the controller. - - Second Cell: flags to identify the type of the interrupt - - 1 = rising edge triggered - - 2 = falling edge triggered - - 3 = rising and falling edge triggered - - 4 = high level triggered - - 8 = low level triggered - - Node of every bank of pins supporting direct wake-up interrupts (without - multiplexing) must contain following properties: - - - interrupts: interrupts of the interrupt parent which are used for external - wakeup interrupts from pins of the bank, must contain interrupts for all - pins of the bank. - -Aliases: - -All the pin controller nodes should be represented in the aliases node using -the following format 'pinctrl{n}' where n is a unique number for the alias. - -Aliases for controllers compatible with "samsung,exynos7-pinctrl": -- pinctrl0: pin controller of ALIVE block, -- pinctrl1: pin controller of BUS0 block, -- pinctrl2: pin controller of NFC block, -- pinctrl3: pin controller of TOUCH block, -- pinctrl4: pin controller of FF block, -- pinctrl5: pin controller of ESE block, -- pinctrl6: pin controller of FSYS0 block, -- pinctrl7: pin controller of FSYS1 block, -- pinctrl8: pin controller of BUS1 block, -- pinctrl9: pin controller of AUDIO block, - -Example: A pin-controller node with pin banks: - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; - - /* ... */ - - /* Pin bank without external interrupts */ - gpy0: gpy0 { - gpio-controller; - #gpio-cells = <2>; - }; - - /* ... */ - - /* Pin bank with external GPIO or muxed wake-up interrupts */ - gpj0: gpj0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - /* ... */ - - /* Pin bank with external direct wake-up interrupts */ - gpx0: gpx0 { - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - interrupt-parent = <&gic>; - interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, - <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>; - #interrupt-cells = <2>; - }; - - /* ... */ - }; - -Example 1: A pin-controller node with pin groups. - - #include - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = <0 47 0>; - - /* ... */ - - uart0_data: uart0-data { - samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart0_fctl: uart0-fctl { - samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_data: uart1-data { - samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - uart1_fctl: uart1-fctl { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - i2c2_bus: i2c2-bus { - samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - sd4_bus8: sd4-bus-width8 { - part-1 { - samsung,pins = "gpk0-3", "gpk0-4", - "gpk0-5", "gpk0-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - part-2 { - samsung,pins = "gpk1-3", "gpk1-4", - "gpk1-5", "gpk1-6"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - }; - }; - -Example 2: A pin-controller node with external wakeup interrupt controller node. - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4210-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = <0 46 0> - - /* ... */ - - wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = <0 32 0>; - }; - }; - -Example 3: A uart client node that supports 'default' and 'flow-control' states. - - uart@13800000 { - compatible = "samsung,exynos4210-uart"; - reg = <0x13800000 0x100>; - interrupts = <0 52 0>; - pinctrl-names = "default", "flow-control; - pinctrl-0 = <&uart0_data>; - pinctrl-1 = <&uart0_data>, <&uart0_fctl>; - }; - -Example 4: Set up the default pin state for uart controller. - - static int s3c24xx_serial_probe(struct platform_device *pdev) { - struct pinctrl *pinctrl; - - /* ... */ - - pinctrl = devm_pinctrl_get_select_default(&pdev->dev); - } - -Example 5: A display port client node that supports 'default' pinctrl state - and gpio binding. - - display-port-controller { - /* ... */ - - samsung,hpd-gpio = <&gpx2 6 0>; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - }; - -Example 6: Request the gpio for display port controller - - static int exynos_dp_probe(struct platform_device *pdev) - { - int hpd_gpio, ret; - struct device *dev = &pdev->dev; - struct device_node *dp_node = dev->of_node; - - /* ... */ - - hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0); - - /* ... */ - - ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN, - "hpd_gpio"); - /* ... */ - } diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml index 5dae04d2936c..7657721a4e96 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml @@ -12,13 +12,14 @@ maintainers: - Jianxin Pan description: |+ - Secure Power Domains used in Meson A1/C1 SoCs, and should be the child node + Secure Power Domains used in Meson A1/C1/S4 SoCs, and should be the child node of secure-monitor. properties: compatible: enum: - amlogic,meson-a1-pwrc + - amlogic,meson-s4-pwrc "#power-domain-cells": const: 1 diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index 01bdda167eef..747622bdc57b 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -28,6 +28,7 @@ properties: - fsl,imx8mn-gpc - fsl,imx8mq-gpc - fsl,imx8mm-gpc + - fsl,imx8mp-gpc reg: maxItems: 1 @@ -57,6 +58,7 @@ properties: include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc + include/dt-bindings/power/imx8mp-power.h for fsl,imx8mp-gpc maxItems: 1 clocks: diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index f234a756c193..135c6f722091 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -26,7 +26,9 @@ properties: - mediatek,mt8167-power-controller - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller + - mediatek,mt8186-power-controller - mediatek,mt8192-power-controller + - mediatek,mt8195-power-controller '#power-domain-cells': const: 1 @@ -64,6 +66,7 @@ patternProperties: "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. + "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. maxItems: 1 clocks: diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index f48bc41d81ec..940e97b565bf 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,mdm9607-rpmpd + - qcom,msm8226-rpmpd - qcom,msm8916-rpmpd - qcom,msm8939-rpmpd - qcom,msm8953-rpmpd diff --git a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml index 84ddc772b003..bb433e75a0ee 100644 --- a/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml @@ -4,14 +4,14 @@ $id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Renesas RZ/G2L System Controller (SYSC) +title: Renesas RZ/{G2L,V2L} System Controller (SYSC) maintainers: - Geert Uytterhoeven description: - The RZ/G2L System Controller (SYSC) performs system control of the LSI and - supports following functions, + The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI + and supports following functions, - External terminal state capture function - 34-bit address space access function - Low power consumption control @@ -21,6 +21,7 @@ properties: compatible: enum: - renesas,r9a07g044-sysc # RZ/G2{L,LC} + - renesas,r9a07g054-sysc # RZ/V2L reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml index c635c181d2c2..64c182428e94 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml @@ -47,6 +47,10 @@ properties: - qcom,sm8350-cdsp-pas - qcom,sm8350-slpi-pas - qcom,sm8350-mpss-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-cdsp-pas + - qcom,sm8450-mpss-pas + - qcom,sm8450-slpi-pas reg: maxItems: 1 @@ -175,6 +179,10 @@ allOf: - qcom,sm8350-cdsp-pas - qcom,sm8350-slpi-pas - qcom,sm8350-mpss-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-cdsp-pas + - qcom,sm8450-slpi-pas + - qcom,sm8450-mpss-pas then: properties: clocks: @@ -283,6 +291,9 @@ allOf: - qcom,sm8350-adsp-pas - qcom,sm8350-cdsp-pas - qcom,sm8350-slpi-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-cdsp-pas + - qcom,sm8450-slpi-pas then: properties: interrupts: @@ -312,6 +323,7 @@ allOf: - qcom,sm6350-mpss-pas - qcom,sm8150-mpss-pas - qcom,sm8350-mpss-pas + - qcom,sm8450-mpss-pas then: properties: interrupts: @@ -434,6 +446,7 @@ allOf: - qcom,sm6350-mpss-pas - qcom,sm8150-mpss-pas - qcom,sm8350-mpss-pas + - qcom,sm8450-mpss-pas then: properties: power-domains: @@ -458,6 +471,8 @@ allOf: - qcom,sm8250-slpi-pas - qcom,sm8350-adsp-pas - qcom,sm8350-slpi-pas + - qcom,sm8450-adsp-pas + - qcom,sm8450-slpi-pas then: properties: power-domains: @@ -475,6 +490,7 @@ allOf: contains: enum: - qcom,sm8350-cdsp-pas + - qcom,sm8450-cdsp-pas then: properties: power-domains: diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml new file mode 100644 index 000000000000..c1e29d94f40e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MP HSIO blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the high-speed IO + (USB an PCIe) peripherals located in the HSIO domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mp-hsio-blk-ctrl + - const: syscon + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 6 + maxItems: 6 + + power-domain-names: + items: + - const: bus + - const: usb + - const: usb-phy1 + - const: usb-phy2 + - const: pcie + - const: pcie-phy + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: usb + - const: pcie + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + hsio_blk_ctrl: blk-ctrl@32f10000 { + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; + reg = <0x32f10000 0x24>; + clocks = <&clk IMX8MP_CLK_USB_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "usb", "pcie"; + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, + <&pgc_usb1_phy>, <&pgc_usb2_phy>, + <&pgc_hsiomix>, <&pgc_pcie_phy>; + power-domain-names = "bus", "usb", "usb-phy1", + "usb-phy2", "pcie", "pcie-phy"; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml new file mode 100644 index 000000000000..7263ebedf09f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8MQ VPU blk-ctrl + +maintainers: + - Lucas Stach + +description: + The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to + the NoC and ensuring proper power sequencing of the VPU peripherals + located in the VPU domain of the SoC. + +properties: + compatible: + items: + - const: fsl,imx8mq-vpu-blk-ctrl + + reg: + maxItems: 1 + + '#power-domain-cells': + const: 1 + + power-domains: + minItems: 3 + maxItems: 3 + + power-domain-names: + items: + - const: bus + - const: g1 + - const: g2 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: g1 + - const: g2 + +required: + - compatible + - reg + - power-domains + - power-domain-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + vpu_blk_ctrl: blk-ctrl@38320000 { + compatible = "fsl,imx8mq-vpu-blk-ctrl"; + reg = <0x38320000 0x100>; + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; + power-domain-names = "bus", "g1", "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g1", "g2"; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt index d74a7a5ae9f2..214a34633824 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -27,6 +27,7 @@ Required properties in pwrap device node. "mediatek,mt8135-pwrap" for MT8135 SoCs "mediatek,mt8173-pwrap" for MT8173 SoCs "mediatek,mt8183-pwrap" for MT8183 SoCs + "mediatek,mt8186-pwrap" for MT8186 SoCs "mediatek,mt8195-pwrap" for MT8195 SoCs "mediatek,mt8516-pwrap" for MT8516 SoCs - interrupts: IRQ for pwrap in SOC diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index dfebf425ca49..b2ba7bed89b2 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -15,6 +15,7 @@ properties: - items: - enum: - rockchip,rk3288-sgrf + - rockchip,rk3568-usb2phy-grf - rockchip,rv1108-usbgrf - const: syscon - items: diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index e72b6a3fae99..ea9c233052f3 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -17,13 +17,6 @@ description: | child nodes, each representing a serial sub-node device. The mode setting selects which particular function will be used. - Refer to next bindings documentation for information on protocol subnodes that - can exist under USI node: - - [1] Documentation/devicetree/bindings/serial/samsung_uart.yaml - [2] Documentation/devicetree/bindings/i2c/i2c-exynos5.txt - [3] Documentation/devicetree/bindings/spi/samsung,spi.yaml - properties: $nodename: pattern: "^usi@[0-9a-f]+$" @@ -71,10 +64,17 @@ properties: This property is optional. patternProperties: - # All other properties should be child nodes - "^(serial|spi|i2c)@[0-9a-f]+$": + "^i2c@[0-9a-f]+$": + $ref: /schemas/i2c/i2c-exynos5.yaml + description: Child node describing underlying I2C + + "^serial@[0-9a-f]+$": + $ref: /schemas/serial/samsung_uart.yaml + description: Child node describing underlying UART/serial + + "^spi@[0-9a-f]+$": type: object - description: Child node describing underlying USI serial protocol + description: Child node describing underlying SPI required: - compatible diff --git a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt deleted file mode 100644 index 4c9ea5989e35..000000000000 --- a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt +++ /dev/null @@ -1,33 +0,0 @@ -Andestech ATCPIT100 timer ------------------------------------------------------------------- -ATCPIT100 is a generic IP block from Andes Technology, embedded in -Andestech AE3XX platforms and other designs. - -This timer is a set of compact multi-function timers, which can be -used as pulse width modulators (PWM) as well as simple timers. - -It supports up to 4 PIT channels. Each PIT channel is a -multi-function timer and provide the following usage scenarios: -One 32-bit timer -Two 16-bit timers -Four 8-bit timers -One 16-bit PWM -One 16-bit timer and one 8-bit PWM -Two 8-bit timer and one 8-bit PWM - -Required properties: -- compatible : Should be "andestech,atcpit100" -- reg : Address and length of the register set -- interrupts : Reference to the timer interrupt -- clocks : a clock to provide the tick rate for "andestech,atcpit100" -- clock-names : should be "PCLK" for the peripheral clock source. - -Examples: - -timer0: timer@f0400000 { - compatible = "andestech,atcpit100"; - reg = <0xf0400000 0x1000>; - interrupts = <2>; - clocks = <&apb>; - clock-names = "PCLK"; -}; diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index e5c57d6e0186..fbd76a8e023b 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -12,6 +12,7 @@ Required properties: For those SoCs that use GPT * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT) * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT) + * "mediatek,mt6582-timer" for MT6582 compatible timers (GPT) * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT) * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT) * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT) diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index 481aaa09f3f2..4cebce682d16 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -41,6 +41,7 @@ properties: - amlogic,meson8b-usb - amlogic,meson-gxbb-usb - amlogic,meson-g12a-usb + - intel,socfpga-agilex-hsotg - const: snps,dwc2 - const: amcc,dwc-otg - const: apm,apm82181-dwc-otg @@ -68,6 +69,13 @@ properties: items: - const: otg + disable-over-current: + type: boolean + description: whether to disable detection of over-current condition. + + iommus: + maxItems: 1 + resets: items: - description: common reset diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 047a83a089ce..baed2b007d0e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -23,6 +23,8 @@ patternProperties: "^(simple-audio-card|st-plgpio|st-spics|ts),.*": true # Keep list in alphabetical order. + "^100ask,.*": + description: Baiwen.com (100ask). "^70mai,.*": description: 70mai Co., Ltd. "^8dev,.*": @@ -61,6 +63,8 @@ patternProperties: description: Aeroflex Gaisler AB "^aesop,.*": description: AESOP Embedded Forum + "^airoha,.*": + description: Airoha "^al,.*": description: Annapurna Labs "^alcatel,.*": @@ -277,12 +281,16 @@ patternProperties: description: Hangzhou C-SKY Microsystems Co., Ltd "^csq,.*": description: Shenzen Chuangsiqi Technology Co.,Ltd. + "^ctera,.*": + description: CTERA Networks Intl. "^cubietech,.*": description: Cubietech, Ltd. "^cui,.*": description: CUI Devices "^cypress,.*": description: Cypress Semiconductor Corporation + "^cyx,.*": + description: Shenzhen CYX Industrial Co., Ltd "^cznic,.*": description: CZ.NIC, z.s.p.o. "^dallas,.*": @@ -489,6 +497,8 @@ patternProperties: deprecated: true "^hannstar,.*": description: HannStar Display Corporation + "^haochuangyi,.*": + description: Shenzhen Haochuangyi Technology Co.,Ltd "^haoyu,.*": description: Haoyu Microelectronic Co. Ltd. "^hardkernel,.*": @@ -769,6 +779,8 @@ patternProperties: description: MiraMEMS Sensing Technology Co., Ltd. "^mitsubishi,.*": description: Mitsubishi Electric Corporation + "^miyoo,.*": + description: Miyoo "^mntre,.*": description: MNT Research GmbH "^modtronix,.*": @@ -892,6 +904,8 @@ patternProperties: description: Ortus Technology Co., Ltd. "^osddisplays,.*": description: OSD Displays + "^osmc,.*": + description: Sam Nazarko Trading Ltd. (Open Source Media Centre) "^ouya,.*": description: Ouya Inc. "^overkiz,.*": @@ -1205,6 +1219,8 @@ patternProperties: description: Shenzhen Techstar Electronics Co., Ltd. "^terasic,.*": description: Terasic Inc. + "^tesla,.*": + description: Tesla, Inc. "^tfc,.*": description: Three Five Corp "^thead,.*": @@ -1350,6 +1366,8 @@ patternProperties: description: WinLink Co., Ltd "^winstar,.*": description: Winstar Display Corp. + "^wirelesstag,.*": + description: Wireless Tag (qiming yunduan) "^wits,.*": description: Shenzhen Merrii Technology Co., Ltd. (WITS) "^wlf,.*": diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 0114871f887a..a97418c74f6b 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -8,6 +8,7 @@ Required properties: - compatible should contain: "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 "mediatek,mt2712-wdt": for MT2712 + "mediatek,mt6582-wdt", "mediatek,mt6589-wdt": for MT6582 "mediatek,mt6589-wdt": for MT6589 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 diff --git a/Documentation/features/core/cBPF-JIT/arch-support.txt b/Documentation/features/core/cBPF-JIT/arch-support.txt index e59b5215402d..77bd6974dd6d 100644 --- a/Documentation/features/core/cBPF-JIT/arch-support.txt +++ b/Documentation/features/core/cBPF-JIT/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/core/eBPF-JIT/arch-support.txt b/Documentation/features/core/eBPF-JIT/arch-support.txt index dcbd8679f514..d5ab547b2be6 100644 --- a/Documentation/features/core/eBPF-JIT/arch-support.txt +++ b/Documentation/features/core/eBPF-JIT/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/core/generic-idle-thread/arch-support.txt b/Documentation/features/core/generic-idle-thread/arch-support.txt index 4efcba7b5239..ddb3762ca7f5 100644 --- a/Documentation/features/core/generic-idle-thread/arch-support.txt +++ b/Documentation/features/core/generic-idle-thread/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | ok | | parisc: | ok | diff --git a/Documentation/features/core/jump-labels/arch-support.txt b/Documentation/features/core/jump-labels/arch-support.txt index 0c801d1bd2da..d5380ef68713 100644 --- a/Documentation/features/core/jump-labels/arch-support.txt +++ b/Documentation/features/core/jump-labels/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/core/thread-info-in-task/arch-support.txt b/Documentation/features/core/thread-info-in-task/arch-support.txt index bc74d8beea72..0654ba3a42ff 100644 --- a/Documentation/features/core/thread-info-in-task/arch-support.txt +++ b/Documentation/features/core/thread-info-in-task/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | nds32: | ok | | nios2: | TODO | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/core/tracehook/arch-support.txt b/Documentation/features/core/tracehook/arch-support.txt index af34308fce7f..8e95dc0c7b90 100644 --- a/Documentation/features/core/tracehook/arch-support.txt +++ b/Documentation/features/core/tracehook/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | ok | | nios2: | ok | | openrisc: | ok | | parisc: | ok | diff --git a/Documentation/features/debug/KASAN/arch-support.txt b/Documentation/features/debug/KASAN/arch-support.txt index c244ac7eee26..407ca1d91242 100644 --- a/Documentation/features/debug/KASAN/arch-support.txt +++ b/Documentation/features/debug/KASAN/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/debug-vm-pgtable/arch-support.txt b/Documentation/features/debug/debug-vm-pgtable/arch-support.txt index fa83403b4aec..83eafe1a7f68 100644 --- a/Documentation/features/debug/debug-vm-pgtable/arch-support.txt +++ b/Documentation/features/debug/debug-vm-pgtable/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/gcov-profile-all/arch-support.txt b/Documentation/features/debug/gcov-profile-all/arch-support.txt index b39c1a5de3f3..49e0dda11227 100644 --- a/Documentation/features/debug/gcov-profile-all/arch-support.txt +++ b/Documentation/features/debug/gcov-profile-all/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | ok | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/kcov/arch-support.txt b/Documentation/features/debug/kcov/arch-support.txt index 7e44013cc320..3d34b724ddae 100644 --- a/Documentation/features/debug/kcov/arch-support.txt +++ b/Documentation/features/debug/kcov/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/kgdb/arch-support.txt b/Documentation/features/debug/kgdb/arch-support.txt index 2cb0576f9180..7aa073d908c5 100644 --- a/Documentation/features/debug/kgdb/arch-support.txt +++ b/Documentation/features/debug/kgdb/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | ok | | mips: | ok | - | nds32: | TODO | | nios2: | ok | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/debug/kmemleak/arch-support.txt b/Documentation/features/debug/kmemleak/arch-support.txt index e9ac415f8aec..5c784ff9768a 100644 --- a/Documentation/features/debug/kmemleak/arch-support.txt +++ b/Documentation/features/debug/kmemleak/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | ok | | mips: | ok | - | nds32: | ok | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt index 96156e8802a7..a1f6e98c6b1f 100644 --- a/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt +++ b/Documentation/features/debug/kprobes-on-ftrace/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/debug/kprobes/arch-support.txt b/Documentation/features/debug/kprobes/arch-support.txt index ee95ed61909a..e7e7015175e7 100644 --- a/Documentation/features/debug/kprobes/arch-support.txt +++ b/Documentation/features/debug/kprobes/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/debug/kretprobes/arch-support.txt b/Documentation/features/debug/kretprobes/arch-support.txt index 612cb97d47b8..838eb53a6fa5 100644 --- a/Documentation/features/debug/kretprobes/arch-support.txt +++ b/Documentation/features/debug/kretprobes/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/debug/optprobes/arch-support.txt b/Documentation/features/debug/optprobes/arch-support.txt index d6ff141a6122..6358b00b1723 100644 --- a/Documentation/features/debug/optprobes/arch-support.txt +++ b/Documentation/features/debug/optprobes/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/stackprotector/arch-support.txt b/Documentation/features/debug/stackprotector/arch-support.txt index ad4de22a71ab..f6cdf781305f 100644 --- a/Documentation/features/debug/stackprotector/arch-support.txt +++ b/Documentation/features/debug/stackprotector/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/uprobes/arch-support.txt b/Documentation/features/debug/uprobes/arch-support.txt index 8bd5548a4485..0b871e797d24 100644 --- a/Documentation/features/debug/uprobes/arch-support.txt +++ b/Documentation/features/debug/uprobes/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/debug/user-ret-profiler/arch-support.txt b/Documentation/features/debug/user-ret-profiler/arch-support.txt index 2a3fe812a5fa..a2feda7adff1 100644 --- a/Documentation/features/debug/user-ret-profiler/arch-support.txt +++ b/Documentation/features/debug/user-ret-profiler/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/io/dma-contiguous/arch-support.txt b/Documentation/features/io/dma-contiguous/arch-support.txt index bece89586efa..9b407f26d45e 100644 --- a/Documentation/features/io/dma-contiguous/arch-support.txt +++ b/Documentation/features/io/dma-contiguous/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | ok | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/locking/cmpxchg-local/arch-support.txt b/Documentation/features/locking/cmpxchg-local/arch-support.txt index 52bdda004f5c..090520b0e02d 100644 --- a/Documentation/features/locking/cmpxchg-local/arch-support.txt +++ b/Documentation/features/locking/cmpxchg-local/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/locking/lockdep/arch-support.txt b/Documentation/features/locking/lockdep/arch-support.txt index a8cd163c8b7e..6d840b103537 100644 --- a/Documentation/features/locking/lockdep/arch-support.txt +++ b/Documentation/features/locking/lockdep/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | ok | | mips: | ok | - | nds32: | ok | | nios2: | TODO | | openrisc: | ok | | parisc: | TODO | diff --git a/Documentation/features/locking/queued-rwlocks/arch-support.txt b/Documentation/features/locking/queued-rwlocks/arch-support.txt index 8c85949752b3..de586be05d64 100644 --- a/Documentation/features/locking/queued-rwlocks/arch-support.txt +++ b/Documentation/features/locking/queued-rwlocks/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | ok | | parisc: | TODO | diff --git a/Documentation/features/locking/queued-spinlocks/arch-support.txt b/Documentation/features/locking/queued-spinlocks/arch-support.txt index 5f4e1b3841af..29d0c8b7b1c5 100644 --- a/Documentation/features/locking/queued-spinlocks/arch-support.txt +++ b/Documentation/features/locking/queued-spinlocks/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | ok | | parisc: | TODO | diff --git a/Documentation/features/perf/kprobes-event/arch-support.txt b/Documentation/features/perf/kprobes-event/arch-support.txt index 78f3fe080f0e..881a8a50e41e 100644 --- a/Documentation/features/perf/kprobes-event/arch-support.txt +++ b/Documentation/features/perf/kprobes-event/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | ok | | nios2: | TODO | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/perf/perf-regs/arch-support.txt b/Documentation/features/perf/perf-regs/arch-support.txt index 5bf3b1854a1f..7639a796a8e1 100644 --- a/Documentation/features/perf/perf-regs/arch-support.txt +++ b/Documentation/features/perf/perf-regs/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/perf/perf-stackdump/arch-support.txt b/Documentation/features/perf/perf-stackdump/arch-support.txt index d88659bb4fc1..df1a4c679a45 100644 --- a/Documentation/features/perf/perf-stackdump/arch-support.txt +++ b/Documentation/features/perf/perf-stackdump/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/sched/membarrier-sync-core/arch-support.txt b/Documentation/features/sched/membarrier-sync-core/arch-support.txt index 883d33b265d6..51b7afc937f1 100644 --- a/Documentation/features/sched/membarrier-sync-core/arch-support.txt +++ b/Documentation/features/sched/membarrier-sync-core/arch-support.txt @@ -40,7 +40,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/sched/numa-balancing/arch-support.txt b/Documentation/features/sched/numa-balancing/arch-support.txt index 9affb7c2c500..d0e308135434 100644 --- a/Documentation/features/sched/numa-balancing/arch-support.txt +++ b/Documentation/features/sched/numa-balancing/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | .. | | microblaze: | .. | | mips: | TODO | - | nds32: | TODO | | nios2: | .. | | openrisc: | .. | | parisc: | .. | diff --git a/Documentation/features/seccomp/seccomp-filter/arch-support.txt b/Documentation/features/seccomp/seccomp-filter/arch-support.txt index 26eec58ab819..05613c5ff560 100644 --- a/Documentation/features/seccomp/seccomp-filter/arch-support.txt +++ b/Documentation/features/seccomp/seccomp-filter/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/time/arch-tick-broadcast/arch-support.txt b/Documentation/features/time/arch-tick-broadcast/arch-support.txt index 8dcaab070c7b..b4c96ebab7e3 100644 --- a/Documentation/features/time/arch-tick-broadcast/arch-support.txt +++ b/Documentation/features/time/arch-tick-broadcast/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/time/clockevents/arch-support.txt b/Documentation/features/time/clockevents/arch-support.txt index 9a81cb03b1fd..3f6976052e2a 100644 --- a/Documentation/features/time/clockevents/arch-support.txt +++ b/Documentation/features/time/clockevents/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | ok | | mips: | ok | - | nds32: | ok | | nios2: | ok | | openrisc: | ok | | parisc: | TODO | diff --git a/Documentation/features/time/context-tracking/arch-support.txt b/Documentation/features/time/context-tracking/arch-support.txt index 4ed116c2ec39..bb1c1801553e 100644 --- a/Documentation/features/time/context-tracking/arch-support.txt +++ b/Documentation/features/time/context-tracking/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/time/irq-time-acct/arch-support.txt b/Documentation/features/time/irq-time-acct/arch-support.txt index bc30c15557c7..3cea25b80c8c 100644 --- a/Documentation/features/time/irq-time-acct/arch-support.txt +++ b/Documentation/features/time/irq-time-acct/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | .. | diff --git a/Documentation/features/time/virt-cpuacct/arch-support.txt b/Documentation/features/time/virt-cpuacct/arch-support.txt index 050de43bbbb9..5163a60a1c1e 100644 --- a/Documentation/features/time/virt-cpuacct/arch-support.txt +++ b/Documentation/features/time/virt-cpuacct/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/vm/ELF-ASLR/arch-support.txt b/Documentation/features/vm/ELF-ASLR/arch-support.txt index 2949c99fbb2f..73ec761f1e27 100644 --- a/Documentation/features/vm/ELF-ASLR/arch-support.txt +++ b/Documentation/features/vm/ELF-ASLR/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | ok | diff --git a/Documentation/features/vm/PG_uncached/arch-support.txt b/Documentation/features/vm/PG_uncached/arch-support.txt index 6cde38458596..9066a90b38d9 100644 --- a/Documentation/features/vm/PG_uncached/arch-support.txt +++ b/Documentation/features/vm/PG_uncached/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/vm/THP/arch-support.txt b/Documentation/features/vm/THP/arch-support.txt index 7dbd6967b37e..f717ab792e5a 100644 --- a/Documentation/features/vm/THP/arch-support.txt +++ b/Documentation/features/vm/THP/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | .. | | microblaze: | .. | | mips: | ok | - | nds32: | TODO | | nios2: | .. | | openrisc: | .. | | parisc: | TODO | diff --git a/Documentation/features/vm/TLB/arch-support.txt b/Documentation/features/vm/TLB/arch-support.txt index e1c3a4c4d107..6fa76a37f299 100644 --- a/Documentation/features/vm/TLB/arch-support.txt +++ b/Documentation/features/vm/TLB/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | .. | | microblaze: | .. | | mips: | TODO | - | nds32: | TODO | | nios2: | .. | | openrisc: | .. | | parisc: | TODO | diff --git a/Documentation/features/vm/huge-vmap/arch-support.txt b/Documentation/features/vm/huge-vmap/arch-support.txt index bc53905a0306..6e1792ee37fe 100644 --- a/Documentation/features/vm/huge-vmap/arch-support.txt +++ b/Documentation/features/vm/huge-vmap/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/vm/ioremap_prot/arch-support.txt b/Documentation/features/vm/ioremap_prot/arch-support.txt index 9a0c8783b84d..a6dcbe5f47b6 100644 --- a/Documentation/features/vm/ioremap_prot/arch-support.txt +++ b/Documentation/features/vm/ioremap_prot/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/Documentation/features/vm/pte_special/arch-support.txt b/Documentation/features/vm/pte_special/arch-support.txt index 40b969f3a6bb..376477749c42 100644 --- a/Documentation/features/vm/pte_special/arch-support.txt +++ b/Documentation/features/vm/pte_special/arch-support.txt @@ -17,7 +17,6 @@ | m68k: | TODO | | microblaze: | TODO | | mips: | ok | - | nds32: | TODO | | nios2: | TODO | | openrisc: | TODO | | parisc: | TODO | diff --git a/MAINTAINERS b/MAINTAINERS index 4807a6f4cc8a..7a66dec3a54d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1239,18 +1239,6 @@ S: Supported F: drivers/clk/analogbits/* F: include/linux/clk/analogbits* -ANDES ARCHITECTURE -M: Nick Hu -M: Greentime Hu -M: Vincent Chen -S: Supported -T: git https://git.kernel.org/pub/scm/linux/kernel/git/greentime/linux.git -F: Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt -F: Documentation/devicetree/bindings/nds32/ -F: arch/nds32/ -N: nds32 -K: nds32 - ANDROID CONFIG FRAGMENTS M: Rob Herring S: Supported @@ -1697,9 +1685,9 @@ S: Maintained F: drivers/clk/sunxi/ ARM/Allwinner sunXi SoC support -M: Maxime Ripard M: Chen-Yu Tsai -R: Jernej Skrabec +M: Jernej Skrabec +M: Samuel Holland L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git @@ -2129,13 +2117,6 @@ F: Documentation/devicetree/bindings/arm/intel,keembay.yaml F: arch/arm64/boot/dts/intel/keembay-evm.dts F: arch/arm64/boot/dts/intel/keembay-soc.dtsi -ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT -M: Jonathan Cameron -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -F: arch/arm/mach-pxa/stargate2.c -F: drivers/pcmcia/pxa2xx_stargate2.c - ARM/INTEL XSC3 (MANZANO) ARM CORE M: Lennert Buytenhek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -2377,6 +2358,7 @@ L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Supported F: Documentation/devicetree/bindings/*/*/*npcm* F: Documentation/devicetree/bindings/*/*npcm* +F: Documentation/devicetree/bindings/arm/npcm/* F: arch/arm/boot/dts/nuvoton-npcm* F: arch/arm/mach-npcm/ F: drivers/*/*npcm* @@ -2387,6 +2369,7 @@ ARM/NUVOTON WPCM450 ARCHITECTURE M: Jonathan Neuschäfer L: openbmc@lists.ozlabs.org (moderated for non-subscribers) S: Maintained +W: https://github.com/neuschaefer/wpcm450/wiki F: Documentation/devicetree/bindings/*/*wpcm* F: arch/arm/boot/dts/nuvoton-wpcm450* F: arch/arm/mach-npcm/wpcm450.c @@ -2541,6 +2524,7 @@ M: Magnus Damm L: linux-renesas-soc@vger.kernel.org S: Supported Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/ +C: irc://irc.libera.chat/renesas-soc T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next F: Documentation/devicetree/bindings/arm/renesas.yaml F: arch/arm64/boot/dts/renesas/ @@ -2657,6 +2641,7 @@ M: Magnus Damm L: linux-renesas-soc@vger.kernel.org S: Supported Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/ +C: irc://irc.libera.chat/renesas-soc T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next F: Documentation/devicetree/bindings/arm/renesas.yaml F: arch/arm/boot/dts/emev2* @@ -2770,6 +2755,14 @@ S: Maintained F: Documentation/devicetree/bindings/media/tegra-cec.txt F: drivers/media/cec/platform/tegra/ +ARM/TESLA FSD SoC SUPPORT +M: Alim Akhtar +M: linux-fsd@tesla.com +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: arch/arm64/boot/dts/tesla* + ARM/TETON BGA MACHINE SUPPORT M: "Mark F. Brown" L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -15400,7 +15393,7 @@ S: Maintained C: irc://irc.libera.chat/linux-exynos Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git -F: Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +F: Documentation/devicetree/bindings/pinctrl/samsung,pinctrl*yaml F: drivers/pinctrl/samsung/ F: include/dt-bindings/pinctrl/samsung.h diff --git a/arch/Kconfig b/arch/Kconfig index 17709ac1030a..9af3a597cc67 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -24,9 +24,6 @@ config KEXEC_ELF config HAVE_IMA_KEXEC bool -config SET_FS - bool - config HOTPLUG_SMT bool @@ -899,6 +896,13 @@ config HAVE_SOFTIRQ_ON_OWN_STACK Architecture provides a function to run __do_softirq() on a separate stack. +config ALTERNATE_USER_ADDRESS_SPACE + bool + help + Architectures set this when the CPU uses separate address + spaces for kernel and user space pointers. In this case, the + access_ok() check on a __user pointer is skipped. + config PGTABLE_LEVELS int default 2 diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig index 14c97acea351..7d0d26b5b3f5 100644 --- a/arch/alpha/Kconfig +++ b/arch/alpha/Kconfig @@ -34,7 +34,6 @@ config ALPHA select OLD_SIGSUSPEND select CPU_NO_EFFICIENT_FFS if !ALPHA_EV67 select MMU_GATHER_NO_RANGE - select SET_FS select SPARSEMEM_EXTREME if SPARSEMEM select ZONE_DMA help diff --git a/arch/alpha/include/asm/processor.h b/arch/alpha/include/asm/processor.h index 090499c99c1c..43e234c518b1 100644 --- a/arch/alpha/include/asm/processor.h +++ b/arch/alpha/include/asm/processor.h @@ -26,10 +26,6 @@ #define TASK_UNMAPPED_BASE \ ((current->personality & ADDR_LIMIT_32BIT) ? 0x40000000 : TASK_SIZE / 2) -typedef struct { - unsigned long seg; -} mm_segment_t; - /* This is dead. Everything has been moved to thread_info. */ struct thread_struct { }; #define INIT_THREAD { } diff --git a/arch/alpha/include/asm/thread_info.h b/arch/alpha/include/asm/thread_info.h index 2592356e3215..fdc485d7787a 100644 --- a/arch/alpha/include/asm/thread_info.h +++ b/arch/alpha/include/asm/thread_info.h @@ -19,7 +19,6 @@ struct thread_info { unsigned int flags; /* low level flags */ unsigned int ieee_state; /* see fpu.h */ - mm_segment_t addr_limit; /* thread address space */ unsigned cpu; /* current CPU */ int preempt_count; /* 0 => preemptable, <0 => BUG */ unsigned int status; /* thread-synchronous flags */ @@ -35,7 +34,6 @@ struct thread_info { #define INIT_THREAD_INFO(tsk) \ { \ .task = &tsk, \ - .addr_limit = KERNEL_DS, \ .preempt_count = INIT_PREEMPT_COUNT, \ } diff --git a/arch/alpha/include/asm/uaccess.h b/arch/alpha/include/asm/uaccess.h index 1b6f25efa247..c32c2584c0b7 100644 --- a/arch/alpha/include/asm/uaccess.h +++ b/arch/alpha/include/asm/uaccess.h @@ -2,47 +2,7 @@ #ifndef __ALPHA_UACCESS_H #define __ALPHA_UACCESS_H -/* - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - * - * Or at least it did once upon a time. Nowadays it is a mask that - * defines which bits of the address space are off limits. This is a - * wee bit faster than the above. - * - * For historical reasons, these macros are grossly misnamed. - */ - -#define KERNEL_DS ((mm_segment_t) { 0UL }) -#define USER_DS ((mm_segment_t) { -0x40000000000UL }) - -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(x) (current_thread_info()->addr_limit = (x)) - -#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) - -/* - * Is a address valid? This does a straightforward calculation rather - * than tests. - * - * Address valid if: - * - "addr" doesn't have any high-bits set - * - AND "size" doesn't have any high-bits set - * - AND "addr+size-(size != 0)" doesn't have any high-bits set - * - OR we are in kernel mode. - */ -#define __access_ok(addr, size) ({ \ - unsigned long __ao_a = (addr), __ao_b = (size); \ - unsigned long __ao_end = __ao_a + __ao_b - !!__ao_b; \ - (get_fs().seg & (__ao_a | __ao_b | __ao_end)) == 0; }) - -#define access_ok(addr, size) \ -({ \ - __chk_user_ptr(addr); \ - __access_ok(((unsigned long)(addr)), (size)); \ -}) - +#include /* * These are the main single-value transfer routines. They automatically * use the right size if we just have the right pointer type. @@ -105,7 +65,7 @@ extern void __get_user_unknown(void); long __gu_err = -EFAULT; \ unsigned long __gu_val = 0; \ const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \ - if (__access_ok((unsigned long)__gu_addr, size)) { \ + if (__access_ok(__gu_addr, size)) { \ __gu_err = 0; \ switch (size) { \ case 1: __get_user_8(__gu_addr); break; \ @@ -200,7 +160,7 @@ extern void __put_user_unknown(void); ({ \ long __pu_err = -EFAULT; \ __typeof__(*(ptr)) __user *__pu_addr = (ptr); \ - if (__access_ok((unsigned long)__pu_addr, size)) { \ + if (__access_ok(__pu_addr, size)) { \ __pu_err = 0; \ switch (size) { \ case 1: __put_user_8(x, __pu_addr); break; \ @@ -316,17 +276,14 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long len) extern long __clear_user(void __user *to, long len); -extern inline long +static inline long clear_user(void __user *to, long len) { - if (__access_ok((unsigned long)to, len)) + if (__access_ok(to, len)) len = __clear_user(to, len); return len; } -#define user_addr_max() \ - (uaccess_kernel() ? ~0UL : TASK_SIZE) - extern long strncpy_from_user(char *dest, const char __user *src, long count); extern __must_check long strnlen_user(const char __user *str, long n); diff --git a/arch/alpha/include/uapi/asm/signal.h b/arch/alpha/include/uapi/asm/signal.h index a69dd8d080a8..1413075f7616 100644 --- a/arch/alpha/include/uapi/asm/signal.h +++ b/arch/alpha/include/uapi/asm/signal.h @@ -100,7 +100,7 @@ struct sigaction { typedef struct sigaltstack { void __user *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; /* sigstack(2) is deprecated, and will be withdrawn in a future version diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 3c2a4753d09b..e0a60a27e14d 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -45,7 +45,6 @@ config ARC select PCI_SYSCALL if PCI select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32 - select SET_FS select TRACE_IRQFLAGS_SUPPORT config LOCKDEP_SUPPORT diff --git a/arch/arc/include/asm/segment.h b/arch/arc/include/asm/segment.h deleted file mode 100644 index 871f8ab11bfd..000000000000 --- a/arch/arc/include/asm/segment.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) - */ - -#ifndef __ASMARC_SEGMENT_H -#define __ASMARC_SEGMENT_H - -#ifndef __ASSEMBLY__ - -typedef unsigned long mm_segment_t; - -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) - -#define KERNEL_DS MAKE_MM_SEG(0) -#define USER_DS MAKE_MM_SEG(TASK_SIZE) -#define uaccess_kernel() (get_fs() == KERNEL_DS) - -#endif /* __ASSEMBLY__ */ -#endif /* __ASMARC_SEGMENT_H */ diff --git a/arch/arc/include/asm/thread_info.h b/arch/arc/include/asm/thread_info.h index d36863e34bfc..1e0b2e3914d5 100644 --- a/arch/arc/include/asm/thread_info.h +++ b/arch/arc/include/asm/thread_info.h @@ -27,7 +27,6 @@ #ifndef __ASSEMBLY__ #include -#include /* * low level task data that entry.S needs immediate access to @@ -40,7 +39,6 @@ struct thread_info { unsigned long flags; /* low level flags */ int preempt_count; /* 0 => preemptable, <0 => BUG */ struct task_struct *task; /* main task structure */ - mm_segment_t addr_limit; /* thread address space */ __u32 cpu; /* current CPU */ unsigned long thr_ptr; /* TLS ptr */ }; @@ -56,7 +54,6 @@ struct thread_info { .flags = 0, \ .cpu = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ } static inline __attribute_const__ struct thread_info *current_thread_info(void) diff --git a/arch/arc/include/asm/uaccess.h b/arch/arc/include/asm/uaccess.h index 783bfdb3bfa3..99712471c96a 100644 --- a/arch/arc/include/asm/uaccess.h +++ b/arch/arc/include/asm/uaccess.h @@ -23,35 +23,6 @@ #include /* for generic string functions */ - -#define __kernel_ok (uaccess_kernel()) - -/* - * Algorithmically, for __user_ok() we want do: - * (start < TASK_SIZE) && (start+len < TASK_SIZE) - * where TASK_SIZE could either be retrieved from thread_info->addr_limit or - * emitted directly in code. - * - * This can however be rewritten as follows: - * (len <= TASK_SIZE) && (start+len < TASK_SIZE) - * - * Because it essentially checks if buffer end is within limit and @len is - * non-ngeative, which implies that buffer start will be within limit too. - * - * The reason for rewriting being, for majority of cases, @len is generally - * compile time constant, causing first sub-expression to be compile time - * subsumed. - * - * The second part would generate weird large LIMMs e.g. (0x6000_0000 - 0x10), - * so we check for TASK_SIZE using get_fs() since the addr_limit load from mem - * would already have been done at this call site for __kernel_ok() - * - */ -#define __user_ok(addr, sz) (((sz) <= TASK_SIZE) && \ - ((addr) <= (get_fs() - (sz)))) -#define __access_ok(addr, sz) (unlikely(__kernel_ok) || \ - likely(__user_ok((addr), (sz)))) - /*********** Single byte/hword/word copies ******************/ #define __get_user_fn(sz, u, k) \ @@ -667,7 +638,6 @@ extern unsigned long arc_clear_user_noinline(void __user *to, #define __clear_user(d, n) arc_clear_user_noinline(d, n) #endif -#include #include #endif diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c index 8e90052f6f05..5f7f5aab361f 100644 --- a/arch/arc/kernel/process.c +++ b/arch/arc/kernel/process.c @@ -43,7 +43,7 @@ SYSCALL_DEFINE0(arc_gettls) return task_thread_info(current)->thr_ptr; } -SYSCALL_DEFINE3(arc_usr_cmpxchg, int *, uaddr, int, expected, int, new) +SYSCALL_DEFINE3(arc_usr_cmpxchg, int __user *, uaddr, int, expected, int, new) { struct pt_regs *regs = current_pt_regs(); u32 uval; diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 49652ef9eff4..c1251856ef77 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -60,6 +60,7 @@ config ARM select GENERIC_CPU_AUTOPROBE select GENERIC_EARLY_IOREMAP select GENERIC_IDLE_POLL_SETUP + select GENERIC_IRQ_MULTI_HANDLER select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW_LEVEL @@ -94,8 +95,8 @@ config ARM select HAVE_EXIT_THREAD select HAVE_FAST_GUP if ARM_LPAE select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL - select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG - select HAVE_FUNCTION_TRACER if !XIP_KERNEL && !(THUMB2_KERNEL && CC_IS_CLANG) + select HAVE_FUNCTION_GRAPH_TRACER + select HAVE_FUNCTION_TRACER if !XIP_KERNEL select HAVE_GCC_PLUGINS select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) select HAVE_IRQ_TIME_ACCOUNTING @@ -129,7 +130,8 @@ config ARM select PERF_USE_VMALLOC select RTC_LIB select SYS_SUPPORTS_APM_EMULATION - select THREAD_INFO_IN_TASK if CURRENT_POINTER_IN_TPIDRURO + select THREAD_INFO_IN_TASK + select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M # Above selects are sorted alphabetically; please add new ones # according to that. Thanks. @@ -141,6 +143,17 @@ config ARM Europe. There is an ARM Linux project with a web page at . +config ARM_HAS_GROUP_RELOCS + def_bool y + depends on !LD_IS_LLD || LLD_VERSION >= 140000 + depends on !COMPILE_TEST + help + Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group + relocations, which have been around for a long time, but were not + supported in LLD until version 14. The combined range is -/+ 256 MiB, + which is usually sufficient, but not for allyesconfig, so we disable + this feature when doing compile testing. + config ARM_HAS_SG_CHAIN bool @@ -220,18 +233,12 @@ config ARCH_MAY_HAVE_PC_FDC config ARCH_SUPPORTS_UPROBES def_bool y -config ARCH_HAS_DMA_SET_COHERENT_MASK - bool - config GENERIC_ISA_DMA bool config FIQ bool -config NEED_RET_TO_USER - bool - config ARCH_MTD_XIP bool @@ -269,7 +276,7 @@ config PHYS_OFFSET hex "Physical address of main memory" if MMU depends on !ARM_PATCH_PHYS_VIRT default DRAM_BASE if !MMU - default 0x00000000 if ARCH_FOOTBRIDGE || ARCH_IXP4XX + default 0x00000000 if ARCH_FOOTBRIDGE default 0x10000000 if ARCH_OMAP1 || ARCH_RPC default 0x30000000 if ARCH_S3C24XX default 0xa0000000 if ARCH_IOP32X || ARCH_PXA @@ -297,6 +304,17 @@ config MMU Select if you want MMU-based virtualised addressing space support by paged memory management. If unsure, say 'Y'. +config ARM_SINGLE_ARMV7M + def_bool !MMU + select ARM_NVIC + select AUTO_ZRELADDR + select TIMER_OF + select COMMON_CLK + select CPU_V7M + select NO_IOPORT_MAP + select SPARSE_IRQ + select USE_OF + config ARCH_MMAP_RND_BITS_MIN default 8 @@ -311,12 +329,11 @@ config ARCH_MMAP_RND_BITS_MAX # choice prompt "ARM system type" - default ARM_SINGLE_ARMV7M if !MMU - default ARCH_MULTIPLATFORM if MMU + depends on MMU + default ARCH_MULTIPLATFORM config ARCH_MULTIPLATFORM bool "Allow multiple platforms to be selected" - depends on MMU select ARCH_FLATMEM_ENABLE select ARCH_SPARSEMEM_ENABLE select ARCH_SELECT_MEMORY_MODEL @@ -325,31 +342,17 @@ config ARCH_MULTIPLATFORM select AUTO_ZRELADDR select TIMER_OF select COMMON_CLK - select GENERIC_IRQ_MULTI_HANDLER select HAVE_PCI select PCI_DOMAINS_GENERIC if PCI select SPARSE_IRQ select USE_OF -config ARM_SINGLE_ARMV7M - bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" - depends on !MMU - select ARM_NVIC - select AUTO_ZRELADDR - select TIMER_OF - select COMMON_CLK - select CPU_V7M - select NO_IOPORT_MAP - select SPARSE_IRQ - select USE_OF - config ARCH_EP93XX bool "EP93xx-based" select ARCH_SPARSEMEM_ENABLE select ARM_AMBA imply ARM_PATCH_PHYS_VIRT select ARM_VIC - select GENERIC_IRQ_MULTI_HANDLER select AUTO_ZRELADDR select CLKSRC_MMIO select CPU_ARM920T @@ -362,7 +365,6 @@ config ARCH_FOOTBRIDGE bool "FootBridge" select CPU_SA110 select FOOTBRIDGE - select NEED_MACH_IO_H if !MMU select NEED_MACH_MEMORY_H help Support for systems based on the DC21285 companion chip @@ -370,11 +372,9 @@ config ARCH_FOOTBRIDGE config ARCH_IOP32X bool "IOP32x-based" - depends on MMU select CPU_XSCALE select GPIO_IOP select GPIOLIB - select NEED_RET_TO_USER select FORCE_PCI select PLAT_IOP help @@ -383,19 +383,15 @@ config ARCH_IOP32X config ARCH_IXP4XX bool "IXP4xx-based" - depends on MMU - select ARCH_HAS_DMA_SET_COHERENT_MASK select ARCH_SUPPORTS_BIG_ENDIAN + select ARM_PATCH_PHYS_VIRT select CPU_XSCALE - select DMABOUNCE if PCI - select GENERIC_IRQ_MULTI_HANDLER select GPIO_IXP4XX select GPIOLIB select HAVE_PCI select IXP4XX_IRQ select IXP4XX_TIMER - # With the new PCI driver this is not needed - select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY + select SPARSE_IRQ select USB_EHCI_BIG_ENDIAN_DESC select USB_EHCI_BIG_ENDIAN_MMIO help @@ -404,7 +400,6 @@ config ARCH_IXP4XX config ARCH_DOVE bool "Marvell Dove" select CPU_PJ4 - select GENERIC_IRQ_MULTI_HANDLER select GPIOLIB select HAVE_PCI select MVEBU_MBUS @@ -418,7 +413,6 @@ config ARCH_DOVE config ARCH_PXA bool "PXA2xx/PXA3xx-based" - depends on MMU select ARCH_MTD_XIP select ARM_CPU_SUSPEND if PM select AUTO_ZRELADDR @@ -427,7 +421,6 @@ config ARCH_PXA select CLKSRC_MMIO select TIMER_OF select CPU_XSCALE if !CPU_XSC3 - select GENERIC_IRQ_MULTI_HANDLER select GPIO_PXA select GPIOLIB select IRQ_DOMAIN @@ -438,7 +431,6 @@ config ARCH_PXA config ARCH_RPC bool "RiscPC" - depends on MMU depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000 select ARCH_ACORN select ARCH_MAY_HAVE_PC_FDC @@ -466,7 +458,6 @@ config ARCH_SA1100 select COMMON_CLK select CPU_FREQ select CPU_SA1100 - select GENERIC_IRQ_MULTI_HANDLER select GPIOLIB select IRQ_DOMAIN select ISA @@ -481,7 +472,6 @@ config ARCH_S3C24XX select CLKSRC_SAMSUNG_PWM select GPIO_SAMSUNG select GPIOLIB - select GENERIC_IRQ_MULTI_HANDLER select NEED_MACH_IO_H select S3C2410_WATCHDOG select SAMSUNG_ATAGS @@ -495,11 +485,9 @@ config ARCH_S3C24XX config ARCH_OMAP1 bool "TI OMAP1" - depends on MMU select ARCH_OMAP select CLKSRC_MMIO select GENERIC_IRQ_CHIP - select GENERIC_IRQ_MULTI_HANDLER select GPIOLIB select HAVE_LEGACY_CLK select IRQ_DOMAIN @@ -575,6 +563,18 @@ config ARCH_VIRT select HAVE_ARM_ARCH_TIMER select ARCH_SUPPORTS_BIG_ENDIAN +config ARCH_AIROHA + bool "Airoha SoC Support" + depends on ARCH_MULTI_V7 + select ARM_AMBA + select ARM_GIC + select ARM_GIC_V3 + select ARM_PSCI + select HAVE_ARM_ARCH_TIMER + select COMMON_CLK + help + Support for Airoha EN7523 SoCs + # # This is sorted alphabetically by mach-* pathname. However, plat-* # Kconfigs may be included either alphabetically (according to the @@ -1166,7 +1166,12 @@ config SMP_ON_UP config CURRENT_POINTER_IN_TPIDRURO def_bool y - depends on SMP && CPU_32v6K && !CPU_V6 + depends on CPU_32v6K && !CPU_V6 + +config IRQSTACKS + def_bool y + select HAVE_IRQ_EXIT_ON_IRQ_STACK + select HAVE_SOFTIRQ_ON_OWN_STACK config ARM_CPU_TOPOLOGY bool "Support cpu topology definition" @@ -1607,10 +1612,14 @@ config XEN help Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. +config CC_HAVE_STACKPROTECTOR_TLS + def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) + config STACKPROTECTOR_PER_TASK bool "Use a unique stack canary value for each task" - depends on GCC_PLUGINS && STACKPROTECTOR && THREAD_INFO_IN_TASK && !XIP_DEFLATED_DATA - select GCC_PLUGIN_ARM_SSP_PER_TASK + depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA + depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS + select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS default y help Due to the fact that GCC uses an ordinary symbol reference from diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 976315dea958..0c9497d549e3 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -65,7 +65,7 @@ config UNWINDER_FRAME_POINTER config UNWINDER_ARM bool "ARM EABI stack unwinder" - depends on AEABI && !FUNCTION_GRAPH_TRACER + depends on AEABI select ARM_UNWIND help This option enables stack unwinding support in the kernel diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 77172d555c7e..a2391b8de5a5 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -160,6 +160,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. machine-$(CONFIG_ARCH_ACTIONS) += actions +machine-$(CONFIG_ARCH_AIROHA) += airoha machine-$(CONFIG_ARCH_ALPINE) += alpine machine-$(CONFIG_ARCH_ARTPEC) += artpec machine-$(CONFIG_ARCH_ASPEED) += aspeed @@ -275,6 +276,14 @@ endif ifeq ($(CONFIG_STACKPROTECTOR_PER_TASK),y) prepare: stack_protector_prepare +ifeq ($(CONFIG_CC_HAVE_STACKPROTECTOR_TLS),y) +stack_protector_prepare: prepare0 + $(eval KBUILD_CFLAGS += \ + -mstack-protector-guard=tls \ + -mstack-protector-guard-offset=$(shell \ + awk '{if ($$2 == "TSK_STACK_CANARY") print $$3;}'\ + include/generated/asm-offsets.h)) +else stack_protector_prepare: prepare0 $(eval SSP_PLUGIN_CFLAGS := \ -fplugin-arg-arm_ssp_per_task_plugin-offset=$(shell \ @@ -283,6 +292,7 @@ stack_protector_prepare: prepare0 $(eval KBUILD_CFLAGS += $(SSP_PLUGIN_CFLAGS)) $(eval GCC_PLUGINS_CFLAGS += $(SSP_PLUGIN_CFLAGS)) endif +endif all: $(notdir $(KBUILD_IMAGE)) diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 954eee8a785a..187a187706cb 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -92,17 +92,13 @@ ifeq ($(CONFIG_USE_OF),y) OBJS += $(libfdt_objs) fdt_check_mem_start.o endif -# -fstack-protector-strong triggers protection checks in this code, -# but it is being used too early to link to meaningful stack_chk logic. -$(foreach o, $(libfdt_objs) atags_to_fdt.o fdt_check_mem_start.o, \ - $(eval CFLAGS_$(o) := -I $(srctree)/scripts/dtc/libfdt -fno-stack-protector)) - targets := vmlinux vmlinux.lds piggy_data piggy.o \ head.o $(OBJS) KBUILD_CFLAGS += -DDISABLE_BRANCH_PROFILING ccflags-y := -fpic $(call cc-option,-mno-single-pic-base,) -fno-builtin \ + -I$(srctree)/scripts/dtc/libfdt -fno-stack-protector \ -I$(obj) $(DISABLE_ARM_SSP_PER_TASK_PLUGIN) ccflags-remove-$(CONFIG_FUNCTION_TRACER) += -pg asflags-y := -DZIMAGE diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index e1e9a5dde853..c3c66ff2d696 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c @@ -128,13 +128,6 @@ asmlinkage void __div0(void) error("Attempting division by 0!"); } -const unsigned long __stack_chk_guard = 0x000a0dff; - -void __stack_chk_fail(void) -{ - error("stack-protector: Kernel stack is corrupted\n"); -} - extern int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x)); diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e41eca79c950..7c16f8a2b738 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -93,6 +93,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb \ + bcm2837-rpi-zero-2-w.dtb \ bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2711-rpi-cm4-io.dtb \ @@ -187,6 +188,8 @@ dtb-$(CONFIG_ARCH_DAVINCI) += \ da850-lego-ev3.dtb dtb-$(CONFIG_ARCH_DIGICOLOR) += \ cx92755_equinox.dtb +dtb-$(CONFIG_ARCH_AIROHA) += \ + en7523-evb.dtb dtb-$(CONFIG_ARCH_EXYNOS3) += \ exynos3250-artik5-eval.dtb \ exynos3250-monk.dtb \ @@ -221,6 +224,8 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5420-arndale-octa.dtb \ exynos5420-peach-pit.dtb \ exynos5420-smdk5420.dtb \ + exynos5420-chagall-wifi.dtb \ + exynos5420-klimt-wifi.dtb \ exynos5422-odroidhc1.dtb \ exynos5422-odroidxu3.dtb \ exynos5422-odroidxu3-lite.dtb \ @@ -269,7 +274,7 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp42x-dlink-dsm-g600.dtb \ intel-ixp42x-gateworks-gw2348.dtb \ intel-ixp43x-gateworks-gw2358.dtb \ - intel-ixp42x-netgear-wg302v2.dtb \ + intel-ixp42x-netgear-wg302v1.dtb \ intel-ixp42x-arcom-vulcan.dtb \ intel-ixp42x-gateway-7001.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += \ @@ -281,6 +286,7 @@ dtb-$(CONFIG_ARCH_KEYSTONE) += \ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-b3.dtb \ kirkwood-blackarmor-nas220.dtb \ + kirkwood-c200-v1.dtb \ kirkwood-cloudbox.dtb \ kirkwood-d2net.dtb \ kirkwood-db-88f6281.dtb \ @@ -735,6 +741,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-com.dtb \ imx7ulp-evk.dtb +dtb-$(CONFIG_SOC_LAN966) += \ + lan966x-pcb8291.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ @@ -895,6 +903,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-regor-rdk.dtb \ am335x-sancloud-bbe.dtb \ am335x-sancloud-bbe-lite.dtb \ + am335x-sancloud-bbe-extended-wifi.dtb \ am335x-shc.dtb \ am335x-sbc-t335.dtb \ am335x-sl50.dtb \ @@ -1162,6 +1171,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-dhcom-picoitx.dtb \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ + stm32mp157c-emsbc-argon.dtb \ stm32mp157c-ev1.dtb \ stm32mp157c-lxa-mc1.dtb \ stm32mp157c-odyssey.dtb @@ -1229,6 +1239,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-bananapro.dtb \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ + sun7i-a20-haoyu-marsboard.dtb \ sun7i-a20-hummingbird.dtb \ sun7i-a20-itead-ibox.dtb \ sun7i-a20-i12-tvbox.dtb \ @@ -1416,6 +1427,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-zybo.dtb \ zynq-zybo-z7.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ + armada-370-c200-v2.dtb \ armada-370-db.dtb \ armada-370-dlink-dns327l.dtb \ armada-370-mirabox.dtb \ @@ -1493,6 +1505,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_MSTARV7) += \ mstar-infinity-msc313-breadbee_crust.dtb \ + mstar-infinity2m-ssd202d-100ask-dongshanpione.dtb \ + mstar-infinity2m-ssd202d-miyoo-mini.dtb \ + mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dtb \ mstar-infinity2m-ssd202d-ssd201htv2.dtb \ mstar-infinity2m-ssd202d-unitv2.dtb \ mstar-infinity3-msc313e-breadbee.dtb \ @@ -1506,6 +1521,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-arm-centriq2400-rep.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-asrock-e3c246d4i.dtb \ + aspeed-bmc-asrock-romed8hm3.dtb \ aspeed-bmc-bytedance-g220a.dtb \ aspeed-bmc-facebook-bletchley.dtb \ aspeed-bmc-facebook-cloudripper.dtb \ @@ -1543,6 +1559,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-opp-zaius.dtb \ aspeed-bmc-portwell-neptune.dtb \ aspeed-bmc-quanta-q71l.dtb \ + aspeed-bmc-quanta-s6q.dtb \ aspeed-bmc-supermicro-x11spi.dtb \ aspeed-bmc-inventec-transformers.dtb \ aspeed-bmc-tyan-s7106.dtb \ diff --git a/arch/arm/boot/dts/am335x-pdu001.dts b/arch/arm/boot/dts/am335x-pdu001.dts index b793beeab245..ce6cc2b96654 100644 --- a/arch/arm/boot/dts/am335x-pdu001.dts +++ b/arch/arm/boot/dts/am335x-pdu001.dts @@ -353,7 +353,7 @@ }; }; - mcp79400: mcp79400@6f { + mcp79400: rtc@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; }; diff --git a/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts b/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts new file mode 100644 index 000000000000..246a1a9b3e44 --- /dev/null +++ b/arch/arm/boot/dts/am335x-sancloud-bbe-extended-wifi.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Sancloud Ltd + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-bone-common.dtsi" +#include "am335x-boneblack-common.dtsi" +#include "am335x-sancloud-bbe-common.dtsi" +#include + +/ { + model = "SanCloud BeagleBone Enhanced Extended WiFi"; + compatible = "sancloud,am335x-boneenhanced", + "ti,am335x-bone-black", + "ti,am335x-bone", + "ti,am33xx"; + + wlan_en_reg: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us= <100000>; + }; +}; + +&am33xx_pinmux { + mmc3_pins: pinmux_mmc3_pins { + pinctrl-single,pins = < + /* gpmc_a9.gpio1_25: RADIO_EN */ + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT_PULLUP, MUX_MODE7) + + /* gpmc_ad12.mmc2_dat0 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad13.mmc2_dat1 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad14.mmc2_dat2 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_ad15.mmc2_dat3 */ + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_csn3.mmc2_cmd */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) + + /* gpmc_clk.mmc2_clk */ + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) + >; + }; + + bluetooth_pins: pinmux_bluetooth_pins { + pinctrl-single,pins = < + /* event_intr0.gpio0_19 */ + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE7) + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + /* uart1_rxd */ + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) + + /* uart1_txd */ + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) + + /* uart1_ctsn */ + AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) + + /* uart1_rtsn */ + AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + >; + }; +}; + +&i2c2 { + status = "disabled"; +}; + +&mmc3 { + status = "okay"; + vmmc-supply = <&wlan_en_reg>; + bus-width = <4>; + non-removable; + cap-power-off-card; + ti,needs-special-hs-handling; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins>; + dmas = <&edma_xbar 12 0 1 + &edma_xbar 13 0 2>; + dma-names = "tx", "rx"; + clock-frequency = <50000000>; + max-frequency = <50000000>; +}; + +&uart1 { + status = "okay"; + + bluetooth { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins &bluetooth_pins>; + compatible = "qcom,qca6174-bt"; + enable-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + clocks = <&l4ls_clkctrl AM3_L4LS_UART2_CLKCTRL 0>; + interrupt-parent = <&gpio0>; + interrupts = <19 IRQ_TYPE_EDGE_RISING>; + }; +}; diff --git a/arch/arm/boot/dts/armada-370-c200-v2.dts b/arch/arm/boot/dts/armada-370-c200-v2.dts new file mode 100644 index 000000000000..1a4a09bdde63 --- /dev/null +++ b/arch/arm/boot/dts/armada-370-c200-v2.dts @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Device Tree file for Ctera C200-V2 + * + * Copyright (C) 2022 Pawel Dembicki + */ + +/dts-v1/; + +#include "armada-370.dtsi" +#include +#include +#include +#include + +/ { + model = "Ctera C200 V2"; + compatible = "ctera,c200-v2", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1024 MB */ + }; + + soc { + ranges = ; + }; + + thermal-zones { + ethphy-thermal { + polling-delay = <20000>; + polling-delay-passive = <2000>; + + thermal-sensors = <ðphy0>; + + trips { + ethphy_alert1: trip1 { + temperature = <65000>; + hysteresis = <4000>; + type = "passive"; + }; + + ethphy_crit: trip2 { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + beeper { + compatible = "pwm-beeper"; + pinctrl-0 = <&pmx_beeper>; + pinctrl-names = "default"; + pwms = <&gpio1 31 4000>; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + + power { + label = "Power Button"; + linux,code = ; + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + }; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + }; + + usb1 { + label = "USB1 Button"; + linux,code = ; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + }; + + usb2 { + label = "USB2 Button"; + linux,code = ; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds1 &pmx_leds2>; + pinctrl-names = "default"; + + led-0 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = ; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + + led-1 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = ; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + + led-2 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = ; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + led-3 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = ; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + + led-4 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + led-5 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = ; + gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + }; + + led-6 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = ; + gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + }; + + led-7 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + }; + + led-8 { + function = LED_FUNCTION_DISK_ERR; + color = ; + gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; + }; + + led-9 { + function = LED_FUNCTION_DISK_ERR; + color = ; + gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + }; + + led-10 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; + }; + + led-11 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = ; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + + led-12 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&coherencyfab { + broken-idle; +}; + +ð1 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy-handle = <ðphy0>; + phy-connection-type = "rgmii-id"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; + + hwmon@2a { + compatible = "nuvoton,nct7802"; + reg = <0x2a>; + }; + + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + + ethphy0: ethernet-phy@0 { /* Marvell 88E1318 */ + reg = <0>; + #thermal-sensor-cells = <0>; + }; +}; + +&nand_controller { + status = "okay"; + + nand@0 { + reg = <0>; + label = "pxa3xx_nand-0"; + nand-rb = <0>; + marvell,nand-keep-config; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x200000>; + read-only; + }; + + partition@200000 { + label = "certificate"; + reg = <0x0200000 0x100000>; + read-only; + }; + + partition@300000 { + label = "preset_cfg"; + reg = <0x0300000 0x100000>; + read-only; + }; + + partition@400000 { + label = "dev_params"; + reg = <0x0400000 0x100000>; + read-only; + }; + partition@500000 { + label = "active_bank"; + reg = <0x0500000 0x0100000>; + }; + + partition@600000 { + label = "magic"; + reg = <0x0600000 0x0100000>; + read-only; + }; + + partition@700000 { + label = "bank1"; + reg = <0x0700000 0x2800000>; + }; + + partition@2f00000 { + label = "bank2"; + reg = <0x2f00000 0x2800000>; + }; + + /* 0x5700000-0x5a00000 undefined in vendor firmware */ + + partition@5a00000 { + label = "reserved"; + reg = <0x5a00000 0x2000000>; + }; + + partition@7a00000 { + label = "rootfs"; + reg = <0x7a00000 0x8600000>; + }; + }; + }; +}; + +&pciec { + status = "okay"; + + pcie@1,0 { /* Renesas uPD720202 USB 3.0 controller */ + pinctrl-0 = <&pmx_pcie>; + pinctrl-names = "default"; + status = "okay"; + reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + + pmx_power_cpu: pmx-power-cpu { + marvell,pins = "mpp4"; + marvell,function = "vdd"; + }; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp6", "mpp10", "mpp14", "mpp32"; + marvell,function = "gpio"; + }; + + pmx_leds1: pmx-leds1 { + marvell,pins = "mpp47"; + marvell,function = "gpo"; + }; + + pmx_leds2: pmx-leds2 { + marvell,pins = "mpp12", "mpp13", "mpp15", "mpp16", "mpp50", "mpp51", + "mpp52", "mpp53", "mpp55", "mpp56", "mpp57", "mpp58"; + marvell,function = "gpio"; + }; + + pmx_pcie: pmx-pcie { + marvell,pins = "mpp59"; + marvell,function = "gpio"; + }; + + pmx_beeper: pmx-beeper { + marvell,pins = "mpp63"; + marvell,function = "gpio"; + }; +}; + +&pmsu { + pinctrl-0 = <&pmx_power_cpu>; + pinctrl-names = "default"; +}; + +&rtc { + status = "disabled"; +}; + +&sata { + nr-ports = <2>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hdd0_temp: sata-port@0 { + reg = <0>; + #thermal-sensor-cells = <0>; + }; + + hdd1_temp: sata-port@1 { + reg = <1>; + #thermal-sensor-cells = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts index 5bd6a66d2c2b..f240018148f6 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -71,16 +71,19 @@ pcie@1,0 { /* Port 0, Lane 0 */ status = "okay"; + slot-power-limit-milliwatt = <10000>; }; pcie@2,0 { /* Port 1, Lane 0 */ status = "okay"; + slot-power-limit-milliwatt = <10000>; }; pcie@3,0 { /* Port 2, Lane 0 */ status = "okay"; + slot-power-limit-milliwatt = <10000>; }; }; }; diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi index f0022d10c715..83392b92dae2 100644 --- a/arch/arm/boot/dts/armada-385.dtsi +++ b/arch/arm/boot/dts/armada-385.dtsi @@ -69,16 +69,25 @@ reg = <0x0800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 0x81000000 0 0 0x81000000 0x1 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; marvell,pcie-port = <0>; marvell,pcie-lane = <0>; clocks = <&gateclk 8>; status = "disabled"; + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -88,16 +97,25 @@ reg = <0x1000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 0x81000000 0 0 0x81000000 0x2 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2_intc 0>, + <0 0 0 2 &pcie2_intc 1>, + <0 0 0 3 &pcie2_intc 2>, + <0 0 0 4 &pcie2_intc 3>; marvell,pcie-port = <1>; marvell,pcie-lane = <0>; clocks = <&gateclk 5>; status = "disabled"; + pcie2_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* x1 port */ @@ -107,16 +125,25 @@ reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 0x81000000 0 0 0x81000000 0x3 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3_intc 0>, + <0 0 0 2 &pcie3_intc 1>, + <0 0 0 3 &pcie3_intc 2>, + <0 0 0 4 &pcie3_intc 3>; marvell,pcie-port = <2>; marvell,pcie-lane = <0>; clocks = <&gateclk 6>; status = "disabled"; + pcie3_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; /* @@ -129,16 +156,25 @@ reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; + interrupt-names = "intx"; + interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <1>; ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 0x81000000 0 0 0x81000000 0x4 0 1 0>; bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie4_intc 0>, + <0 0 0 2 &pcie4_intc 1>, + <0 0 0 3 &pcie4_intc 2>, + <0 0 0 4 &pcie4_intc 3>; marvell,pcie-port = <3>; marvell,pcie-lane = <0>; clocks = <&gateclk 7>; status = "disabled"; + pcie4_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 4c3c3f1a12ea..1b2e7ad37566 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -339,17 +339,8 @@ <&adc10mux 0>, <&adc10mux 1>, <&adc11mux 0>, <&adc11mux 1>, <&adc12mux 0>, <&adc12mux 1>, - <&adc13mux 0>, <&adc13mux 1>; - }; - - iio-hwmon-adc14 { - compatible = "iio-hwmon"; - io-channels = <&adc 14>; - }; - - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 15>; + <&adc13mux 0>, <&adc13mux 1>, + <&adc 14>, <&adc 15>; }; }; @@ -362,6 +353,13 @@ /* spi-max-frequency = <50000000>; */ #include "openbmc-flash-layout-64.dtsi" }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; +#include "openbmc-flash-layout-64-alt.dtsi" + }; }; &spi1 { @@ -853,7 +851,7 @@ /*E0-E7*/ "","","","","","","","", /*F0-F7*/ "","","BMC_SYS_PSON_L","S0_DDR_SAVE","PGOOD", "S1_DDR_SAVE","","", - /*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","", + /*G0-G7*/ "host0-ready","SHD_REQ_L","","S0_OVERTEMP_L","","", "","", /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","", /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT", @@ -869,7 +867,7 @@ /*Q0-Q7*/ "","","","","","UID_BUTTON","","", /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", "OCP_MAIN_PWREN","RESET_BUTTON","","", - /*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","", + /*S0-S7*/ "","","","","rtc-battery-voltage-read-enable","","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "","","","","","","","", @@ -884,7 +882,7 @@ /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", "BMC_OCP_PG"; - i2c4_o_en { + i2c4-o-en-hog { gpio-hog; gpios = ; output-high; diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts new file mode 100644 index 000000000000..e71ccfd1df63 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include +#include + +/{ + model = "ASRock ROMED8HM3 BMC v1.00"; + compatible = "asrock,romed8hm3-bmc", "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=tty0 console=ttyS4,115200 earlycon"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(H, 6) GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + + system-fault { + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; + panic-indicator; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>, <&adc 11>, + <&adc 12>, <&adc 13>, <&adc 14>, <&adc 15>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <100000000>; /* 100 MHz */ +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&uart5 { + status = "okay"; +}; + +&vuart { + status = "okay"; + aspeed,lpc-io-reg = <0x2f8>; + aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>; +}; + +&i2c0 { + status = "okay"; + + /* inlet temp sensor */ + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + /* IPB temp sensor */ + w83773g@4c { + compatible = "nuvoton,w83773g"; + reg = <0x4c>; + }; + + /* IPB PMIC */ + lm25066@40 { + compatible = "lm25066"; + reg = <0x40>; + }; + + /* 12VSB PMIC */ + lm25066@41 { + compatible = "lm25066"; + reg = <0x41>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + + /* Baseboard FRU eeprom */ + eeprom@50 { + compatible = "st,24c128", "atmel,24c128"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&video { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default>; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03 0x0b>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04 0x0c>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05 0x0d>; + }; + + fan@6 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x06 0x0e>; + }; +}; + +&gpio { + status = "okay"; + gpio-line-names = + /* A */ "LOCATORLED_STATUS_N", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI", + "", "", "", "", + /* B */ "DDR_MEM_TEMP", "", "", "", "", "", "", "", + /* C */ "", "", "", "", "PCIE_HP_SEL_N", "PCIE_SATA_SEL_N", "LOCATORBTN", "", + /* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON", + "", "", "", "PSU_FAN_FAIL_N", + /* E */ "", "", "", "", "", "", "", "", + /* F */ "NIC_PWR_GOOD", "PRSNTB0", "PRSNTB1", "PRSNTB2", + "PRSNTB3", "", "3VSB_PCIE1_PG", "12V_PCIE1_PG", + /* G */ "HWM_BAT_EN", "CHASSIS_ID0", "CHASSIS_ID1", "CHASSIS_ID2", + "BMC_ALERT1_N_R", "BMC_ALERT2_N_R", "BMC_ALERT3_N", "BMC_ALERT4_N", + /* H */ "X24_C1_PRSNT", "X24_C2_PRSNT", "X24_C3_PRSNT", "FM_MEM_THERM_EVENT_BMC_R_N", + "FACMODE", "BMC_RTCRST", "BMC_HB_LED_N", "BMC_CASEOPEN", + /* I */ "", "", "", "", "", "", "", "", + /* J */ "BMC_READY", "BMC_PCH_BIOS_CS_N", "", "P0_MA_DDR_QS_CS_N", + "", "", "", "", + /* K */ "", "", "", "", "", "", "", "", + /* L */ "", "", "", "", "", "", "", "", + /* M */ "", "", "MEZZ_PWRBRK_N", "OCP_HP_RST_EN", + "MAIN_PWR_EN_G", "BMC_MAIN_EN", "AUX_PWR_EN_G", "BMC_AUX_EN", + /* N */ "", "", "", "", "", "", "", "", + /* O */ "", "", "", "", "", "", "", "", + /* P */ "", "", "", "", "", "", "", "", + /* Q */ "", "", "", "", + "BMC_SMB_PRESENT_1_N", "BMC_SMB_PRESENT_2_N", + "BMC_SMB_PRESENT_3_N", "BMC_PCIE_WAKE_N", + /* R */ "", "", "THERMALTRIP_CLEAR_N", "", "", "", "", "", + /* S */ "", "", "", "", "", "", "", "", + /* T */ "", "", "", "", "", "", "", "", + /* U */ "", "", "", "", "", "", "", "", + /* V */ "", "", "", "", "", "", "", "", + /* W */ "", "", "", "", "", "", "", "", + /* X */ "", "", "", "", "", "", "", "", + /* Y */ "SLP_S3", "SLP_S4_S5", "NODE_ID_1", "NODE_ID_2", "", "", "", "", + /* Z */ "", "", "SYSTEM_FAULT_LED_N", "FAST_THROTTLE_N", + "", "", "", "", + /* AA */ "FM_CPU0_IBMC_THERMTRIP_N", "", "PROCHOT_L_G", "", + "", "", "", "", + /* AB */ "BMC_FORCE_SELFREFRESH", "PWRGD_OUT", "", "IRQ_BMC_PCH_SMI_LPC_N", + "", "", "", "", + /* AC */ "", "", "", "", "", "", "", ""; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index f973ea883b97..eaf1bc261ee3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -5,6 +5,8 @@ #include "aspeed-g6.dtsi" #include #include +#include +#include / { model = "Facebook Bletchley BMC"; @@ -31,7 +33,7 @@ <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; }; - spi_gpio: spi-gpio { + spi1_gpio: spi1-gpio { compatible = "spi-gpio"; #address-cells = <1>; #size-cells = <0>; @@ -49,119 +51,165 @@ }; }; + spi2_gpio: spi2-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + gpio-sck = <&gpio0 ASPEED_GPIO(X, 3) GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio0 ASPEED_GPIO(X, 4) GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio0 ASPEED_GPIO(X, 5) GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; + }; + switchphy: ethernet-phy@0 { // Fixed link }; - leds { + front_gpio_leds { compatible = "gpio-leds"; - sys_log_id { - retain-state-shutdown; - default-state = "keep"; + default-state = "off"; gpios = <&front_leds 0 GPIO_ACTIVE_HIGH>; }; + }; + + fan_gpio_leds { + compatible = "gpio-leds"; fan0_blue { retain-state-shutdown; default-state = "on"; - gpios = <&fan_ioexp 8 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 8 GPIO_ACTIVE_HIGH>; }; fan1_blue { retain-state-shutdown; default-state = "on"; - gpios = <&fan_ioexp 9 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 9 GPIO_ACTIVE_HIGH>; }; fan2_blue { retain-state-shutdown; default-state = "on"; - gpios = <&fan_ioexp 10 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 10 GPIO_ACTIVE_HIGH>; }; fan3_blue { retain-state-shutdown; default-state = "on"; - gpios = <&fan_ioexp 11 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 11 GPIO_ACTIVE_HIGH>; }; fan0_amber { retain-state-shutdown; default-state = "off"; - gpios = <&fan_ioexp 12 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 12 GPIO_ACTIVE_HIGH>; }; fan1_amber { retain-state-shutdown; default-state = "off"; - gpios = <&fan_ioexp 13 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 13 GPIO_ACTIVE_HIGH>; }; fan2_amber { retain-state-shutdown; default-state = "off"; - gpios = <&fan_ioexp 14 GPIO_ACTIVE_HIGH>; + gpios = <&fan_leds 14 GPIO_ACTIVE_HIGH>; }; fan3_amber { retain-state-shutdown; default-state = "off"; - gpios = <&fan_ioexp 15 GPIO_ACTIVE_HIGH>; - }; - sled0_amber { - retain-state-shutdown; - default-state = "off"; - gpios = <&sled0_leds 0 GPIO_ACTIVE_LOW>; - }; - sled0_blue { - retain-state-shutdown; - default-state = "off"; - gpios = <&sled0_leds 1 GPIO_ACTIVE_LOW>; + gpios = <&fan_leds 15 GPIO_ACTIVE_HIGH>; }; + }; + + sled1_gpio_leds { + compatible = "gpio-leds"; sled1_amber { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled1_leds 0 GPIO_ACTIVE_LOW>; }; sled1_blue { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled1_leds 1 GPIO_ACTIVE_LOW>; }; + }; + + sled2_gpio_leds { + compatible = "gpio-leds"; sled2_amber { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled2_leds 0 GPIO_ACTIVE_LOW>; }; sled2_blue { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled2_leds 1 GPIO_ACTIVE_LOW>; }; + }; + + sled3_gpio_leds { + compatible = "gpio-leds"; sled3_amber { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled3_leds 0 GPIO_ACTIVE_LOW>; }; sled3_blue { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled3_leds 1 GPIO_ACTIVE_LOW>; }; + }; + + sled4_gpio_leds { + compatible = "gpio-leds"; sled4_amber { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled4_leds 0 GPIO_ACTIVE_LOW>; }; sled4_blue { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled4_leds 1 GPIO_ACTIVE_LOW>; }; + }; + + sled5_gpio_leds { + compatible = "gpio-leds"; sled5_amber { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled5_leds 0 GPIO_ACTIVE_LOW>; }; sled5_blue { retain-state-shutdown; - default-state = "off"; + default-state = "keep"; gpios = <&sled5_leds 1 GPIO_ACTIVE_LOW>; }; }; + + sled6_gpio_leds { + compatible = "gpio-leds"; + sled6_amber { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled6_leds 0 GPIO_ACTIVE_LOW>; + }; + sled6_blue { + retain-state-shutdown; + default-state = "keep"; + gpios = <&sled6_leds 1 GPIO_ACTIVE_LOW>; + }; + }; }; &mac2 { @@ -177,10 +225,6 @@ }; }; -&rtc { - status = "okay"; -}; - &fmc { status = "okay"; flash@0 { @@ -190,88 +234,22 @@ spi-max-frequency = <50000000>; #include "openbmc-flash-layout-128.dtsi" }; -}; - -&spi2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2_default>; - - flash@0 { + flash@1 { status = "okay"; m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; + label = "flash1"; + spi-max-frequency = <50000000>; }; }; &i2c0 { status = "okay"; - /* TODO: Add ADC INA230 */ - - mp5023@40 { - compatible = "mps,mp5023"; - reg = <0x40>; + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; }; - tmp421@4f { - compatible = "ti,tmp421"; - reg = <0x4f>; - }; - - sled0_ioexp: pca9539@76 { - compatible = "nxp,pca9539"; - reg = <0x76>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "SLED0_MS_DETECT1","SLED0_VBUS_BMC_EN","SLED0_INA230_ALERT","SLED0_P12V_STBY_ALERT", - "SLED0_SSD_ALERT","SLED0_MS_DETECT0","SLED0_RST_CCG5","SLED0_FUSB302_INT", - "SLED0_MD_STBY_RESET","SLED0_MD_IOEXP_EN_FAULT","SLED0_MD_DIR","SLED0_MD_DECAY", - "SLED0_MD_MODE1","SLED0_MD_MODE2","SLED0_MD_MODE3","power-host0"; - }; - - sled0_leds: pca9552@67 { - compatible = "nxp,pca9552"; - reg = <0x67>; - #address-cells = <1>; - #size-cells = <0>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "led-sled0-amber","led-sled0-blue","SLED0_RST_IOEXP","", - "","","","", - "","","","", - "","","",""; - }; - - sled0_fusb302: typec-portc@22 { - compatible = "fcs,fusb302"; - reg = <0x22>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - power-role = "dual"; - try-power-role = "sink"; - data-role = "dual"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <10000000>; - }; - }; -}; - -&i2c1 { - status = "okay"; - /* TODO: Add ADC INA230 */ - mp5023@40 { compatible = "mps,mp5023"; reg = <0x40>; @@ -290,6 +268,9 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = ; + gpio-line-names = "SLED1_MS_DETECT1","SLED1_VBUS_BMC_EN","SLED1_INA230_ALERT","SLED1_P12V_STBY_ALERT", "SLED1_SSD_ALERT","SLED1_MS_DETECT0","SLED1_RST_CCG5","SLED1_FUSB302_INT", @@ -306,7 +287,7 @@ #gpio-cells = <2>; gpio-line-names = - "led-sled1-amber","led-sled1-blue","SLED1_RST_IOEXP","", + "led-sled1-amber","led-sled1-blue","SLED1_RST_IOEXP","SLED1_MD_REF_PWM", "","","","", "","","","", "","","",""; @@ -333,11 +314,11 @@ &i2c1 { status = "okay"; -}; - -&i2c2 { - status = "okay"; - /* TODO: Add ADC INA230 */ + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; mp5023@40 { compatible = "mps,mp5023"; @@ -357,6 +338,9 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = ; + gpio-line-names = "SLED2_MS_DETECT1","SLED2_VBUS_BMC_EN","SLED2_INA230_ALERT","SLED2_P12V_STBY_ALERT", "SLED2_SSD_ALERT","SLED2_MS_DETECT0","SLED2_RST_CCG5","SLED2_FUSB302_INT", @@ -373,7 +357,7 @@ #gpio-cells = <2>; gpio-line-names = - "led-sled2-amber","led-sled2-blue","SLED2_RST_IOEXP","", + "led-sled2-amber","led-sled2-blue","SLED2_RST_IOEXP","SLED2_MD_REF_PWM", "","","","", "","","","", "","","",""; @@ -398,9 +382,13 @@ }; }; -&i2c3 { +&i2c2 { status = "okay"; - /* TODO: Add ADC INA230 */ + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; mp5023@40 { compatible = "mps,mp5023"; @@ -420,6 +408,9 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = ; + gpio-line-names = "SLED3_MS_DETECT1","SLED3_VBUS_BMC_EN","SLED3_INA230_ALERT","SLED3_P12V_STBY_ALERT", "SLED3_SSD_ALERT","SLED3_MS_DETECT0","SLED3_RST_CCG5","SLED3_FUSB302_INT", @@ -436,7 +427,7 @@ #gpio-cells = <2>; gpio-line-names = - "led-sled3-amber","led-sled3-blue","SLED3_RST_IOEXP","", + "led-sled3-amber","led-sled3-blue","SLED3_RST_IOEXP","SLED3_MD_REF_PWM", "","","","", "","","","", "","","",""; @@ -461,9 +452,13 @@ }; }; -&i2c4 { +&i2c3 { status = "okay"; - /* TODO: Add ADC INA230 */ + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; mp5023@40 { compatible = "mps,mp5023"; @@ -483,6 +478,9 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = ; + gpio-line-names = "SLED4_MS_DETECT1","SLED4_VBUS_BMC_EN","SLED4_INA230_ALERT","SLED4_P12V_STBY_ALERT", "SLED4_SSD_ALERT","SLED4_MS_DETECT0","SLED4_RST_CCG5","SLED4_FUSB302_INT", @@ -499,7 +497,7 @@ #gpio-cells = <2>; gpio-line-names = - "led-sled4-amber","led-sled4-blue","SLED4_RST_IOEXP","", + "led-sled4-amber","led-sled4-blue","SLED4_RST_IOEXP","SLED4_MD_REF_PWM", "","","","", "","","","", "","","",""; @@ -524,9 +522,13 @@ }; }; -&i2c5 { +&i2c4 { status = "okay"; - /* TODO: Add ADC INA230 */ + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; mp5023@40 { compatible = "mps,mp5023"; @@ -546,6 +548,9 @@ gpio-controller; #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = ; + gpio-line-names = "SLED5_MS_DETECT1","SLED5_VBUS_BMC_EN","SLED5_INA230_ALERT","SLED5_P12V_STBY_ALERT", "SLED5_SSD_ALERT","SLED5_MS_DETECT0","SLED5_RST_CCG5","SLED5_FUSB302_INT", @@ -562,7 +567,7 @@ #gpio-cells = <2>; gpio-line-names = - "led-sled5-amber","led-sled5-blue","SLED5_RST_IOEXP","", + "led-sled5-amber","led-sled5-blue","SLED5_RST_IOEXP","SLED5_MD_REF_PWM", "","","","", "","","","", "","","",""; @@ -587,6 +592,76 @@ }; }; +&i2c5 { + status = "okay"; + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + shunt-resistor = <2000>; + }; + + mp5023@40 { + compatible = "mps,mp5023"; + reg = <0x40>; + }; + + tmp421@4f { + compatible = "ti,tmp421"; + reg = <0x4f>; + }; + + sled6_ioexp: pca9539@76 { + compatible = "nxp,pca9539"; + reg = <0x76>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&gpio0>; + interrupts = ; + + gpio-line-names = + "SLED6_MS_DETECT1","SLED6_VBUS_BMC_EN","SLED6_INA230_ALERT","SLED6_P12V_STBY_ALERT", + "SLED6_SSD_ALERT","SLED6_MS_DETECT0","SLED6_RST_CCG5","SLED6_FUSB302_INT", + "SLED6_MD_STBY_RESET","SLED6_MD_IOEXP_EN_FAULT","SLED6_MD_DIR","SLED6_MD_DECAY", + "SLED6_MD_MODE1","SLED6_MD_MODE2","SLED6_MD_MODE3","power-host6"; + }; + + sled6_leds: pca9552@67 { + compatible = "nxp,pca9552"; + reg = <0x67>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "led-sled6-amber","led-sled6-blue","SLED6_RST_IOEXP","SLED6_MD_REF_PWM", + "","","","", + "","","","", + "","","",""; + }; + + sled6_fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <10000000>; + }; + }; +}; + &i2c6 { status = "okay"; @@ -596,6 +671,7 @@ }; rtc@51 { + /* in-chip rtc disabled, use external rtc (battery-backed) */ compatible = "nxp,pcf85263"; reg = <0x51>; }; @@ -655,6 +731,7 @@ adm1278@11 { compatible = "adi,adm1278"; reg = <0x11>; + shunt-resistor-micro-ohms = <300>; }; tmp421@4c { @@ -667,7 +744,7 @@ reg = <0x4d>; }; - fan_ioexp: pca9552@67 { + fan_leds: pca9552@67 { compatible = "nxp,pca9552"; reg = <0x67>; #address-cells = <1>; @@ -700,36 +777,38 @@ /*D0-D7*/ "","","","","","","","", /*E0-E7*/ "","","","","","","","", /*F0-F7*/ "","","","","","","","", - /*G0-G7*/ "","SWITCH_FRU_MUX","","","","","","", + /*G0-G7*/ "BSM_FRU_WP","SWITCH_FRU_MUX","","", + "PWRGD_P1V05_VDDCORE","PWRGD_P1V5_VDD","","", /*H0-H7*/ "presence-riser1","presence-riser2", - "presence-sled0","presence-sled1", - "presence-sled2","presence-sled3", - "presence-sled4","presence-sled5", + "presence-sled1","presence-sled2", + "presence-sled3","presence-sled4", + "presence-sled5","presence-sled6", /*I0-I7*/ "REV_ID0","","REV_ID1","REV_ID2", - "","","","", + "","BSM_FLASH_WP_STATUS","BMC_TPM_PRES","", /*J0-J7*/ "","","","","","","","", /*K0-K7*/ "","","","","","","","", - /*L0-L7*/ "","","","","","","","", - /*M0-M7*/ "ALERT_SLED0","ALERT_SLED1", - "ALERT_SLED2","ALERT_SLED3", - "ALERT_SLED4","ALERT_SLED5", + /*L0-L7*/ "","","","","","BMC_RTC_INT","","", + /*M0-M7*/ "ALERT_SLED1","ALERT_SLED2", + "ALERT_SLED3","ALERT_SLED4", + "ALERT_SLED5","ALERT_SLED6", "P12V_AUX_ALERT1","", /*N0-N7*/ "","","","","","","","", /*O0-O7*/ "","","","", "","BOARD_ID0","BOARD_ID1","BOARD_ID2", - /*P0-P7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","BMC_HEARTBEAT", /*Q0-Q7*/ "","","","","","","","", /*R0-R7*/ "","","","","","","","", /*S0-S7*/ "","","","BAT_DETECT", "BMC_BT_WP0","BMC_BT_WP1","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", - /*V0-V7*/ "","RST_BMC_MVL","","", + /*V0-V7*/ "PWRGD_CNS_PSU","RST_BMC_MVL","","PSU_PRSNT", "USB2_SEL0_A","USB2_SEL1_A", "USB2_SEL0_B","USB2_SEL1_B", /*W0-W7*/ "RST_FRONT_IOEXP","","","","","","","", /*X0-X7*/ "","","","","","","","", - /*Y0-Y7*/ "","","BSM_FLASH_LATCH","","","","","", + /*Y0-Y7*/ "BMC_SELF_HW_RST","BSM_PRSNT","BSM_FLASH_LATCH","", + "","","","", /*Z0-Z7*/ "","","","","","","",""; }; @@ -754,3 +833,8 @@ &pinctrl_adc12_default &pinctrl_adc13_default &pinctrl_adc14_default &pinctrl_adc15_default>; }; + +&mdio3 { + status = "okay"; + /* TODO: Add Marvell 88X3310 */ +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 22c06ff7a7ed..578f9e2fc7ed 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -171,9 +171,10 @@ /* 48MB region from the end of flash to start of vga memory */ ramoops@bc000000 { compatible = "ramoops"; - reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ + reg = <0xbc000000 0x200000>; /* 16 * (4 * 0x8000) */ record-size = <0x8000>; console-size = <0x8000>; + ftrace-size = <0x8000>; pmsg-size = <0x8000>; max-reason = <3>; /* KMSG_DUMP_EMERG */ }; @@ -269,9 +270,7 @@ /*C0-C7*/ "","","","","","","","", /*D0-D7*/ "","","","","","","","", /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "PIN_HOLE_RESET_IN_N","","", - "PIN_HOLE_RESET_OUT_N","","", - "factory-reset-toggle","", + /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","factory-reset-toggle","", /*G0-G7*/ "","","","","","","","", /*H0-H7*/ "led-rtc-battery","led-bmc","led-rear-enc-id0","led-rear-enc-fault0","","","","", /*I0-I7*/ "","","","","","","bmc-secure-boot","", @@ -2394,6 +2393,10 @@ status = "okay"; }; +&uhci { + status = "okay"; +}; + &emmc_controller { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index c47974219832..528b49e2c0f8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -102,9 +102,10 @@ ramoops@bc000000 { compatible = "ramoops"; - reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */ + reg = <0xbc000000 0x200000>; /* 16 * (4 * 0x8000) */ record-size = <0x8000>; console-size = <0x8000>; + ftrace-size = <0x8000>; pmsg-size = <0x8000>; max-reason = <3>; /* KMSG_DUMP_EMERG */ }; @@ -239,6 +240,10 @@ status = "okay"; }; +&uhci { + status = "okay"; +}; + &gpio0 { gpio-line-names = /*A0-A7*/ "","","","","","","","", @@ -246,7 +251,7 @@ /*C0-C7*/ "","","","","","","","", /*D0-D7*/ "","","","","","","","", /*E0-E7*/ "","","","","","","","", - /*F0-F7*/ "","","","","","","factory-reset-toggle","", + /*F0-F7*/ "","","rtc-battery-voltage-read-enable","reset-cause-pinhole","","","factory-reset-toggle","", /*G0-G7*/ "","","","","","","","", /*H0-H7*/ "","bmc-ingraham0","rear-enc-id0","rear-enc-fault0","","","","", /*I0-I7*/ "","","","","","","bmc-secure-boot","", @@ -2360,30 +2365,6 @@ use-ncsi; }; -&fmc { - status = "okay"; - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-128.dtsi" - }; -}; - -&spi1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1_default>; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "pnor"; - spi-max-frequency = <100000000>; - }; -}; - &wdt1 { aspeed,reset-type = "none"; aspeed,external-signal; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts index e39f310d55eb..72b7a6639ed9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -197,7 +197,6 @@ fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; cfam@0,0 { reg = <0 0>; @@ -877,3 +876,14 @@ status = "okay"; memory-region = <&vga_memory>; }; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8 0xcac>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts new file mode 100644 index 000000000000..69e1bd256271 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-quanta-s6q.dts @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2022 Quanta Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "Quanta S6Q BMC"; + compatible = "quanta,s6q-bmc", "aspeed,ast2600"; + + aliases { + // bus 0 + i2c20 = &SMB_HOST_DB2000_3V3AUX_SCL; + i2c21 = &U12_PCA9546_CH1; + i2c22 = &SMB_HOST_DB800_B_SCL; + i2c23 = &SMB_HOST_DB800_C_SCL; + + // bus 1 + i2c24 = &SMB_M2_P0_1V8AUX_SCL; + i2c25 = &SMB_M2_P1_1V8AUX_SCL; + i2c26 = &SMB_CPU_PIROM_3V3AUX_SCL; + i2c27 = &SMB_TEMP_3V3AUX_SCL; + i2c28 = &SMB_IPMB_3V3AUX_SSDSB_SCL; + i2c29 = &SMB_IPMB_3V3AUX_SCL; + i2c31 = &SMB_FB_SCL; + + // bus 1 - Fan board + i2c32 = &SMB_IOEXP_SCL; + i2c33 = &SMB_PROGRAM_SCL; + i2c34 = &SMB_FB_SCL_CH2; + i2c35 = &SMB_FAN_SENSE_SCL; + + // bus 6 + i2c36 = &U197_PCA9546_CH0; + i2c37 = &U197_PCA9546_CH1; + i2c38 = &U197_PCA9546_CH2; + i2c39 = &U197_PCA9546_CH3; + + //bus 7 + i2c40 = &SMB_OCP_SFF_3V3AUX_SCL; //OCP1 + i2c41 = &SMB_OCP_LFF_3V3AUX_SCL; //OCP2 + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + leds { + compatible = "gpio-leds"; + + BMC_HEARTBEAT_N { + label="BMC_HEARTBEAT_N"; + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + BMC_LED_STATUS_AMBER_N { + label="BMC_LED_STATUS_AMBER_N"; + gpios = <&gpio0 ASPEED_GPIO(S, 6) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + FM_ID_LED_N { + label="FM_ID_LED_N"; + gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&gpio0 { + gpio-line-names = + /*A0 - A7*/ "", "", "", "", "", "", "", "", + /*B0 - B7*/ "", "", "", "", "", "", "", "", + /*C0 - C7*/ "", "", "", "", "", "", "", "", + /*D0 - D7*/ "", "", "", "", "", "", "", "", + /*E0 - E7*/ "", "", "", "", "", "", "", "", + /*F0 - F7*/ "PLTRST_N", "", "PWR_DEBUG_N", "", "", "", "", "", + /*G0 - G7*/ "", "", "", "", "", "", "", "", + /*H0 - H7*/ "", "", "", "", "", "", "", "", + /*I0 - I7*/ "", "", "", "", "", "", "", "", + /*J0 - J7*/ "", "", "", "", "", "", "", "", + /*K0 - K7*/ "", "", "", "", "", "", "", "", + /*L0 - L7*/ "", "", "", "", "PREQ_N", "TCK_MUX_SEL", "", "", + /*M0 - M7*/ "", "", "", "PWRGD_SYS_PWROK", "", "PRDY_N", "", "", + /*N0 - N7*/ "", "", "", "", "", "", "", "", + /*O0 - O7*/ "", "", "", "", "", "", "", "", + /*P0 - P7*/ "SYS_BMC_PWRBTN_R_N", "SYS_PWRBTN_N", "FM_MB_RST_BTN", "RST_BMC_RSTBTN_OUT_N", "", "", "", "", + /*Q0 - Q7*/ "", "", "", "", "", "", "", "", + /*R0 - R7*/ "", "", "", "", "", "", "", "", + /*S0 - S7*/ "", "", "", "FP_ID_BTN_SCM_N", "", "", "", "", + /*T0 - T7*/ "", "", "", "", "", "", "", "", + /*U0 - U7*/ "", "", "", "", "", "", "", "", + /*V0 - V7*/ "", "", "", "", "", "SMI", "", "", + /*W0 - W7*/ "", "", "", "", "", "", "", "", + /*X0 - X7*/ "", "", "", "", "", "", "", "", + /*Y0 - Y7*/ "", "", "", "", "", "", "", "", + /*Z0 - Z7*/ "FM_BMC_READY_N", "", "", "", "", "", "", "", + /*AA0 - AA7*/ "", "", "", "", "", "", "", "", + /*AB0 - AB7*/ "", "", "", "", "", "", "", "", + /*AC0 - AC7*/ "", "", "", "", "", "", "", ""; +}; + +&sgpiom0 { + status = "okay"; + ngpios = <128>; + bus-frequency = <48000>; + gpio-line-names = + /* SGPIO input lines */ + /*IOA0-IOA7*/ "","", "SIO_POWER_GOOD","OA1", "XDP_PRST_N","", "","", "FM_SLPS3_PLD_N","", "FM_SLPS4_PLD_N","", "FM_BIOS_POST_CMPLT_BMC_N","", "FM_ADR_TRIGGER_N","OA7", + /*IOB0-IOB7*/ "FM_ADR_COMPLETE","", "FM_PMBUS_ALERT_B_EN","", "PSU0_PRESENT_N","", "PSU1_PRESENT_N","", "PSU0_VIN_BUF_GOOD","", "PSU01_VIN_BUF_GOOD","", "PWRGD_PS0_PWROK_R","", "PWRGD_PS1_PWROK_R","", + /*IOC0-IOC7*/ "PWRGD_PS_PWROK_PLD_R","", "CHASSIS_INTRUSION","", "BMC_MFG_MODE","", "FM_BMC_EN_DET_R","", "FM_ME_BT_DONE","", "CPU1_PRESENCE","", "CPU2_PRESENCE","", "IRQ_PSYS_CRIT_N","", + /*IOD0-IOD7*/ "","", "CPU1_THERMTRIP","", "CPU2_THERMTRIP","", "CPU1_MEM_THERM_EVENT","", "CPU2_MEM_THERM_EVENT","", "CPU1_VRHOT","", "CPU2_VRHOT","", "","", + /*IOE0-IOE7*/ "","", "CPU1_MEM_VRHOT","", "CPU2_MEM_VRHOT","", "","", "PCH_BMC_THERMTRIP","", "","", "","", "","", + /*IOF0-IOF7*/ "CPU_ERR0","", "CPU_ERR1","", "CPU_ERR2","", "","", "","", "CPU_CATERR","", "","", "","", + /*IOG0-IOG7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOH0-IOH7*/ "","", "FP_ID_BTN_R1_N","", "FP_RST_BTN_N","", "","", "","", "FP_PWR_BTN_PLD_N_R","", "","", "","", + /*IOI0-IOI7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOJ0-IOJ7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOK0-IOK7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOL0-IOL7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*IOM0-IOM7*/ "","", "","", "","", "","", "","", "","", "","", "","", + /*ION0-ION7*/ "","BMC_SW_HEARTBEAT_N_R", "","FP_LED_FAULT_N", "","FP_ID_LED_N", "","FM_BMC_RSTBTN_OUT_N", "","FM_THERMTRIP_DLY_LVC1_R_N", "","", "","RST_PCA9548_SENSOR_PLD_N", "","USB_OC1_REAR_N", + /*IOO0-IOO7*/ "","IRQ_TPM_SPI_N", "","", "","IRQ_PCH_SCI_WHEA_R_N", "","IRQ_BMC_PCH_NMI_R", "","H_CPU_NMI_LVC1_R_N", "","", "","", "","FM_JTAG_BMC_PLD_MUX_SEL", + /*IOP0-IOP7*/ "IP0","OP0", "","", "","", "","", "","", "","", "","", "IP7","OP7"; +}; + +&adc0 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&mdio2 { + status = "okay"; + + ethphy2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mac2 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; +}; + +&mac3 { + status = "okay"; + + phy-mode = "rmii"; + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default + &pinctrl_spi2cs2_default>; + status = "okay"; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "spi2:0"; + spi-max-frequency = <50000000>; + }; +}; + +&kcs1 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA0>; +}; + +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA8>; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xCA2>; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + non-removable; + bus-width = <4>; + max-frequency = <100000000>; +}; + +&vhub { + status = "okay"; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + U34_PWR_ADC@48 { + compatible = "ti,ads7830"; + reg = <0x48>; + }; + + U35_PWR_ADC@4b { + compatible = "ti,ads7830"; + reg = <0x4b>; + }; + + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + SMB_HOST_DB2000_3V3AUX_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + U12_PCA9546_CH1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + SMB_HOST_DB800_B_SCL: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + SMB_HOST_DB800_C_SCL: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + i2c-switch@59 { + compatible = "nxp,pca9848"; + reg = <0x59>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + SMB_M2_P0_1V8AUX_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + SMB_M2_P1_1V8AUX_SCL: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + SMB_CPU_PIROM_3V3AUX_SCL: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + SMB_TEMP_3V3AUX_SCL: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + U163_tmp75@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + U114_tmp75@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + }; + + SMB_IPMB_3V3AUX_SSDSB_SCL: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + U4_tmp75@4c { + compatible = "ti,tmp75"; + reg = <0x4c>; + }; + U73_tmp75@4d { + compatible = "ti,tmp75"; + reg = <0x4d>; + }; + }; + + SMB_IPMB_3V3AUX_SCL: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + U190_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + }; + + SMB_FB_SCL: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + + i2c-switch@77 { + compatible = "nxp,pca9546"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + SMB_IOEXP_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + SMB_PROGRAM_SCL: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + SMB_FB_SCL_CH2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + SMB_FAN_SENSE_SCL: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + Current_Meter_U2@45 { + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <1000>; /* = 1 mOhm */ + }; + + Current_Meter_U3@44 { + compatible = "ti,ina219"; + reg = <0x44>; + shunt-resistor = <1000>; /* = 1 mOhm */ + }; + + TEMP_sensor_U2@4b { + compatible = "ti,tmp75"; + reg = <0x4b>; + }; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + bus-frequency = <400000>; + + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c3 { + status = "okay"; + + /* MB FRU (U173) @ 0xA2 */ + mb_fru: mb_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + + /* FP_U1 Inlet */ + FP_U1_tmp75@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + }; + + FP_U4_fru@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + i2c-switch@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + i2c-mux-idle-disconnect; + + U197_PCA9546_CH0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + U197_PCA9546_CH1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + cpu0_pvccin@60 { + compatible = "isil,raa229004"; + reg = <0x60>; + }; + + cpu0_pvccinfaon@61 { + compatible = "isil,isl69260"; + reg = <0x61>; + }; + + cpu0_pvccd_hv@63 { + compatible = "isil,isl69260"; + reg = <0x63>; + }; + }; + + U197_PCA9546_CH2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + cpu1_pvccin@72 { + compatible = "isil,raa229004"; + reg = <0x72>; + }; + + cpu1_pvccinfaon@74 { + compatible = "isil,isl69260"; + reg = <0x74>; + }; + + cpu1_pvccd_hv@76 { + compatible = "isil,isl69260"; + reg = <0x76>; + }; + }; + + U197_PCA9546_CH3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c7 { + status = "okay"; + + i2c-switch@75 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + SMB_OCP_SFF_3V3AUX_SCL: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + SMB_OCP_LFF_3V3AUX_SCL: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; + + /* SCM FRU (U19) @ 0xA2 */ + scm_fru: scm_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <32>; + }; + + scm_tmp75_u4@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + }; +}; + +&i2c15 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index b1068cca4228..7719ea3d4933 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -48,11 +48,11 @@ status = "okay"; }; - vdd_1v5: fixed-regulator-vdd_1v5@1 { + vdd_1v15: fixed-regulator-vdd_1v15@1 { compatible = "regulator-fixed"; - regulator-name = "VDD_1V5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; + regulator-name = "VDD_1V15"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; regulator-always-on; status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index ccf9e224da78..08685a10eda1 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -131,6 +131,18 @@ status = "okay"; }; +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_default>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_default>; + status = "okay"; +}; + &cpu0 { cpu-supply = <&vddcpu>; }; @@ -239,6 +251,7 @@ regulator-state-standby { regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; regulator-mode = <4>; }; @@ -279,6 +292,7 @@ regulator-state-standby { regulator-on-in-suspend; + regulator-suspend-voltage = <1150000>; regulator-mode = <4>; }; @@ -290,7 +304,7 @@ vddcpu: VDD_OTHER { regulator-name = "VDD_OTHER"; - regulator-min-microvolt = <1125000>; + regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1850000>; regulator-initial-mode = <2>; regulator-allowed-modes = <2>, <4>; @@ -299,6 +313,7 @@ regulator-state-standby { regulator-on-in-suspend; + regulator-suspend-voltage = <1050000>; regulator-mode = <4>; }; @@ -315,6 +330,7 @@ regulator-always-on; regulator-state-standby { + regulator-suspend-voltage = <1800000>; regulator-on-in-suspend; }; @@ -329,6 +345,7 @@ regulator-max-microvolt = <3700000>; regulator-state-standby { + regulator-suspend-voltage = <1800000>; regulator-on-in-suspend; }; @@ -454,6 +471,19 @@ }; &pioA { + + pinctrl_can0_default: can0_default { + pinmux = , + ; + bias-disable; + }; + + pinctrl_can1_default: can1_default { + pinmux = , + ; + bias-disable; + }; + pinctrl_flx0_default: flx0_default { pinmux = , , diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi index 21294f775a20..89af57482bc8 100644 --- a/arch/arm/boot/dts/bcm2711.dtsi +++ b/arch/arm/boot/dts/bcm2711.dtsi @@ -459,12 +459,26 @@ #size-cells = <0>; enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/100095/0003 + * /Level-1-Memory-System/About-the-L1-memory-system?lang=en + * Source for d/i-cache-size + * https://www.raspberrypi.com/documentation/computers + * /processors.html#bcm2711 + */ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000d8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -473,6 +487,13 @@ reg = <1>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -481,6 +502,13 @@ reg = <2>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -489,6 +517,28 @@ reg = <3>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000f0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set + next-level-cache = <&l2>; + }; + + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/100095/0003 + * /Level-2-Memory-System/About-the-L2-memory-system?lang=en + * Source for d/i-cache-size + * https://www.raspberrypi.com/documentation/computers + * /processors.html#bcm2711 + */ + l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set + cache-level = <2>; }; }; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 0549686134ea..1c90e5a44283 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -14,6 +14,23 @@ device_type = "cpu"; compatible = "arm,arm1176jzf-s"; reg = <0x0>; + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/ddi0301 + * /h/level-one-memory-system/cache-organization?lang=en + * + * Source for d/i-cache-size + * https://forums.raspberrypi.com/viewtopic.php?t=98428 + * + * NOTE: The BCM2835 has a L2 cache but it is dedicated to the GPU + * It can be shared with the CPU through fw settings, + * but this is not recommended. + */ + d-cache-size = <0x4000>; + d-cache-line-size = <16>; + d-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set + i-cache-size = <0x4000>; + i-cache-line-size = <16>; + i-cache-sets = <256>; // 16KiB(size)/16(line-size)=1024ways/4-way set }; }; diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi index b390006aef79..534dacfc4dd5 100644 --- a/arch/arm/boot/dts/bcm2836.dtsi +++ b/arch/arm/boot/dts/bcm2836.dtsi @@ -41,11 +41,26 @@ #size-cells = <0>; enable-method = "brcm,bcm2836-smp"; + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/ddi0464/f/L1-Memory-System + * /About-the-L1-memory-system?lang=en + * + * Source for d/i-cache-size + * https://forums.raspberrypi.com/viewtopic.php?t=98428 + */ + v7_cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0xf00>; clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; }; v7_cpu1: cpu@1 { @@ -53,6 +68,13 @@ compatible = "arm,cortex-a7"; reg = <0xf01>; clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; }; v7_cpu2: cpu@2 { @@ -60,6 +82,13 @@ compatible = "arm,cortex-a7"; reg = <0xf02>; clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; }; v7_cpu3: cpu@3 { @@ -67,6 +96,27 @@ compatible = "arm,cortex-a7"; reg = <0xf03>; clock-frequency = <800000000>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set + next-level-cache = <&l2>; + }; + + /* Source for cache-line-size + cache-sets + * https://developer.arm.com/documentation/ddi0464/f/L2-Memory-System + * /About-the-L2-Memory-system?lang=en + * Source for cache-size + * https://forums.raspberrypi.com/viewtopic.php?t=98428 + */ + l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set + cache-level = <2>; }; }; }; diff --git a/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts b/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts new file mode 100644 index 000000000000..4a768562985e --- /dev/null +++ b/arch/arm/boot/dts/bcm2837-rpi-zero-2-w.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Stefan Wahren + */ + +/dts-v1/; +#include "bcm2837.dtsi" +#include "bcm2836-rpi.dtsi" +#include "bcm283x-rpi-usb-otg.dtsi" +#include "bcm283x-rpi-wifi-bt.dtsi" + +/ { + compatible = "raspberrypi,model-zero-2-w", "brcm,bcm2837"; + model = "Raspberry Pi Zero 2 W"; + + memory@0 { + device_type = "memory"; + reg = <0 0x20000000>; + }; + + chosen { + /* 8250 auxiliary UART instead of pl011 */ + stdout-path = "serial1:115200n8"; + }; + + leds { + led-act { + gpios = <&gpio 29 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&bt { + shutdown-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; +}; + +&gpio { + /* + * This is based on the official GPU firmware DT blob. + * + * Legend: + * "NC" = not connected (no rail from the SoC) + * "FOO" = GPIO line named "FOO" on the schematic + * "FOO_N" = GPIO line named "FOO" on schematic, active low + */ + gpio-line-names = "ID_SDA", + "ID_SCL", + "SDA1", + "SCL1", + "GPIO_GCLK", + "GPIO5", + "GPIO6", + "SPI_CE1_N", + "SPI_CE0_N", + "SPI_MISO", + "SPI_MOSI", + "SPI_SCLK", + "GPIO12", + "GPIO13", + /* Serial port */ + "TXD0", + "RXD0", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO20", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO24", + "GPIO25", + "GPIO26", + "GPIO27", + "HDMI_HPD_N", + "STATUS_LED_N", + "NC", /* GPIO30 */ + "NC", /* GPIO31 */ + "NC", /* GPIO32 */ + "NC", /* GPIO33 */ + "NC", /* GPIO34 */ + "NC", /* GPIO35 */ + "NC", /* GPIO36 */ + "NC", /* GPIO37 */ + "NC", /* GPIO38 */ + "NC", /* GPIO39 */ + "CAM_GPIO0", /* GPIO40 */ + "WL_ON", /* GPIO41 */ + "BT_ON", /* GPIO42 */ + "WIFI_CLK", /* GPIO43 */ + "SDA0", /* GPIO44 */ + "SCL0", /* GPIO45 */ + "SMPS_SCL", + "SMPS_SDA", + /* Used by SD Card */ + "SD_CLK_R", + "SD_CMD_R", + "SD_DATA0_R", + "SD_DATA1_R", + "SD_DATA2_R", + "SD_DATA3_R"; + + pinctrl-0 = <&gpioout &alt0>; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&sdhci { + pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_gpio14>; + status = "okay"; +}; + +&wifi_pwrseq { + reset-gpios = <&gpio 41 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi index 0199ec98cd61..5dbdebc46259 100644 --- a/arch/arm/boot/dts/bcm2837.dtsi +++ b/arch/arm/boot/dts/bcm2837.dtsi @@ -40,12 +40,26 @@ #size-cells = <0>; enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit + /* Source for d/i-cache-line-size and d/i-cache-sets + * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system + * /about-the-l1-memory-system?lang=en + * + * Source for d/i-cache-size + * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks + */ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000d8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; }; cpu1: cpu@1 { @@ -54,6 +68,13 @@ reg = <1>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; }; cpu2: cpu@2 { @@ -62,6 +83,13 @@ reg = <2>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000e8>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; }; cpu3: cpu@3 { @@ -70,6 +98,27 @@ reg = <3>; enable-method = "spin-table"; cpu-release-addr = <0x0 0x000000f0>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set + next-level-cache = <&l2>; + }; + + /* Source for cache-line-size + cache-sets + * https://developer.arm.com/documentation/ddi0500 + * /e/level-2-memory-system/about-the-l2-memory-system?lang=en + * Source for cache-size + * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf + */ + l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set + cache-level = <2>; }; }; }; diff --git a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts index 249476fdad7a..82f9629f0abb 100644 --- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts @@ -93,6 +93,82 @@ gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; }; }; + + switch { + compatible = "realtek,rtl8365mb"; + /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ + mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>; + mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; + realtek,disable-leds; + dsa,member = <1 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan5"; + phy-handle = <ðphy0>; + }; + + port@1 { + reg = <1>; + label = "lan6"; + phy-handle = <ðphy1>; + }; + + port@2 { + reg = <2>; + label = "lan7"; + phy-handle = <ðphy2>; + }; + + port@3 { + reg = <3>; + label = "lan8"; + phy-handle = <ðphy3>; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&sw0_p5>; + phy-mode = "rgmii"; + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <2100>; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + + mdio { + compatible = "realtek,smi-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + }; + + ethphy3: ethernet-phy@3 { + reg = <3>; + }; + }; + }; }; &srab { diff --git a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts index 24ae3c8a3e09..9efcb2424228 100644 --- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts @@ -25,6 +25,9 @@ nvram@1eff0000 { compatible = "brcm,nvram"; reg = <0x1eff0000 0x10000>; + + et0macaddr: et0macaddr { + }; }; leds { @@ -72,6 +75,11 @@ }; }; +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; + &usb3 { vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi index ba01054a76cf..58b7d9fc7574 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-alamo.dtsi @@ -57,10 +57,9 @@ led-4 { /* amber:power */ - function = LED_FUNCTION_POWER; + function = LED_FUNCTION_FAULT; color = ; gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; - default-state = "on"; }; led-5 { diff --git a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi index 7c487c74fd10..576cfc52567b 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-kingpin.dtsi @@ -106,10 +106,9 @@ led-a { /* amber:power */ - function = LED_FUNCTION_POWER; + function = LED_FUNCTION_FAULT; color = ; gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; - default-state = "on"; }; led-b { diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi index 6519b7c61af1..b0854d881ac6 100644 --- a/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi +++ b/arch/arm/boot/dts/bcm958625-meraki-mx6x-common.dtsi @@ -22,7 +22,7 @@ }; led-2 { - function = LED_FUNCTION_INDICATOR; + function = LED_FUNCTION_POWER; color = ; pwms = <&pwm 2 50000>; max-brightness = <255>; @@ -39,6 +39,8 @@ &amac2 { status = "okay"; + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; }; &ehci0 { @@ -53,6 +55,12 @@ reg = <0x50>; pagesize = <32>; read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; }; }; diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts new file mode 100644 index 000000000000..a8d8bb0419a0 --- /dev/null +++ b/arch/arm/boot/dts/en7523-evb.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7523.dtsi" + +/ { + model = "Airoha EN7523 Evaluation Board"; + compatible = "airoha,en7523-evb", "airoha,en7523"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "console=ttyS0,115200 earlycon"; + stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x80200000 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi new file mode 100644 index 000000000000..36597f587f46 --- /dev/null +++ b/arch/arm/boot/dts/en7523.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + npu_binary@84000000 { + no-map; + reg = <0x84000000 0xA00000>; + }; + + npu_flag@84B0000 { + no-map; + reg = <0x84B00000 0x100000>; + }; + + npu_pkt@85000000 { + no-map; + reg = <0x85000000 0x1A00000>; + }; + + npu_phyaddr@86B00000 { + no-map; + reg = <0x86B00000 0x100000>; + }; + + npu_rxdesc@86D00000 { + no-map; + reg = <0x86D00000 0x100000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@9000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x09000000 0x20000>, + <0x09080000 0x80000>, + <0x09400000 0x2000>, + <0x09500000 0x2000>, + <0x09600000 0x20000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + uart1: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x1fbf0000 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clock-frequency = <1843200>; + status = "okay"; + }; + + gpio0: gpio@1fbf0200 { + compatible = "airoha,en7523-gpio"; + reg = <0x1fbf0204 0x4>, + <0x1fbf0200 0x4>, + <0x1fbf0220 0x4>, + <0x1fbf0214 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio1: gpio@1fbf0270 { + compatible = "airoha,en7523-gpio"; + reg = <0x1fbf0270 0x4>, + <0x1fbf0260 0x4>, + <0x1fbf0264 0x4>, + <0x1fbf0278 0x4>; + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 829c05b2c405..7b429622a288 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -356,7 +356,7 @@ }; &pinctrl_1 { - bten: bten { + bten: bten-pins { samsung,pins ="gpx1-7"; samsung,pin-function = ; samsung,pin-pud = ; @@ -364,7 +364,7 @@ samsung,pin-pud-pdn = ; }; - wlanen: wlanen { + wlanen: wlanen-pins { samsung,pins = "gpx2-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -372,12 +372,12 @@ samsung,pin-val = <1>; }; - s2mps14_irq: s2mps14-irq { + s2mps14_irq: s2mps14-irq-pins { samsung,pins = "gpx3-5"; samsung,pin-pud = ; }; - bthostwake: bthostwake { + bthostwake: bthostwake-pins { samsung,pins = "gpx3-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -385,7 +385,7 @@ samsung,pin-pud-pdn = ; }; - btwake: btwake { + btwake: btwake-pins { samsung,pins = "gpx3-7"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 8b41a9d5e2db..02a9dc479d34 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -69,7 +69,7 @@ reg = <0x25>; wakeup-source; - muic: max77836-muic { + extcon { compatible = "maxim,max77836-muic"; }; diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index dff3c6e3aa1f..cc30d154ec94 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -12,47 +12,22 @@ #include #define PIN_IN(_pin, _pull, _drv) \ - _pin { \ + pin- ## _pin { \ samsung,pins = #_pin; \ samsung,pin-function = ; \ samsung,pin-pud = ; \ samsung,pin-drv = ; \ } -#define PIN_OUT(_pin, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = ; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - } - -#define PIN_OUT_SET(_pin, _val, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = ; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - samsung,pin-val = <_val>; \ - } - -#define PIN_CFG(_pin, _sel, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <_sel>; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ - } - #define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ + pin- ## _pin { \ samsung,pins = #_pin; \ samsung,pin-con-pdn = ; \ samsung,pin-pud-pdn = ; \ } &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -60,7 +35,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -68,7 +43,7 @@ #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -76,7 +51,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -84,7 +59,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -92,7 +67,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -100,7 +75,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -108,84 +83,84 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c4_bus: i2c4-bus { + i2c4_bus: i2c4-bus-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c5_bus: i2c5-bus { + i2c5_bus: i2c5-bus-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = ; @@ -193,7 +168,7 @@ samsung,pin-drv = ; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = ; @@ -201,63 +176,63 @@ samsung,pin-drv = ; }; - i2c6_bus: i2c6-bus { + i2c6_bus: i2c6-bus-pins { samsung,pins = "gpc1-3", "gpc1-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c7_bus: i2c7-bus { + i2c7_bus: i2c7-bus-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - mipi0_clk: mipi0-clk { + mipi0_clk: mipi0-clk-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -266,22 +241,22 @@ }; &pinctrl_1 { - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpe2: gpe2 { + gpe2: gpe2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpk0: gpk0 { + gpk0: gpk0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -289,7 +264,7 @@ #interrupt-cells = <2>; }; - gpk1: gpk1 { + gpk1: gpk1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -297,7 +272,7 @@ #interrupt-cells = <2>; }; - gpk2: gpk2 { + gpk2: gpk2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -305,7 +280,7 @@ #interrupt-cells = <2>; }; - gpl0: gpl0 { + gpl0: gpl0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -313,7 +288,7 @@ #interrupt-cells = <2>; }; - gpm0: gpm0 { + gpm0: gpm0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -321,7 +296,7 @@ #interrupt-cells = <2>; }; - gpm1: gpm1 { + gpm1: gpm1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -329,7 +304,7 @@ #interrupt-cells = <2>; }; - gpm2: gpm2 { + gpm2: gpm2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -337,7 +312,7 @@ #interrupt-cells = <2>; }; - gpm3: gpm3 { + gpm3: gpm3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -345,7 +320,7 @@ #interrupt-cells = <2>; }; - gpm4: gpm4 { + gpm4: gpm4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -353,7 +328,7 @@ #interrupt-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -370,7 +345,7 @@ #interrupt-cells = <2>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -387,7 +362,7 @@ #interrupt-cells = <2>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -395,7 +370,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -403,126 +378,126 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpk0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpk0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpk0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_rdqs: sd0-rdqs { + sd0_rdqs: sd0-rdqs-pins { samsung,pins = "gpk0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpk0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpk1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpk1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpk1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpk1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpk2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpk2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpk2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpk2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_b_io: cam-port-b-io { + cam_port_b_io: cam-port-b-io-pins { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; @@ -531,35 +506,35 @@ samsung,pin-drv = ; }; - cam_port_b_clk_active: cam-port-b-clk-active { + cam_port_b_clk_active: cam-port-b-clk-active-pins { samsung,pins = "gpm2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_b_clk_idle: cam-port-b-clk-idle { + cam_port_b_clk_idle: cam-port-b-clk-idle-pins { samsung,pins = "gpm2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_i2c0: fimc-is-i2c0 { + fimc_is_i2c0: fimc-is-i2c0-pins { samsung,pins = "gpm4-0", "gpm4-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_i2c1: fimc-is-i2c1 { + fimc_is_i2c1: fimc-is-i2c1-pins { samsung,pins = "gpm4-2", "gpm4-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_uart: fimc-is-uart { + fimc_is_uart: fimc-is-uart-pins { samsung,pins = "gpm3-5", "gpm3-7"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 5f7f8fedfb92..6d2c7bb19184 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -70,7 +70,7 @@ reg = <0x25>; wakeup-source; - muic: max77836-muic { + extcon { compatible = "maxim,max77836-muic"; }; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index a10b789d8acf..ae644315855d 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -421,7 +421,7 @@ status = "disabled"; }; - pdma0: pdma@12680000 { + pdma0: dma-controller@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = ; @@ -432,7 +432,7 @@ #dma-requests = <32>; }; - pdma1: pdma@12690000 { + pdma1: dma-controller@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index eab77a66ae8f..e81b3ee4e0f7 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -669,7 +669,7 @@ status = "disabled"; }; - pdma0: pdma@12680000 { + pdma0: dma-controller@12680000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12680000 0x1000>; interrupts = ; @@ -680,7 +680,7 @@ #dma-requests = <32>; }; - pdma1: pdma@12690000 { + pdma1: dma-controller@12690000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12690000 0x1000>; interrupts = ; @@ -691,7 +691,7 @@ #dma-requests = <32>; }; - mdma1: mdma@12850000 { + mdma1: dma-controller@12850000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12850000 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/exynos4210-i9100.dts b/arch/arm/boot/dts/exynos4210-i9100.dts index 33894054b8b0..3c0a18b30837 100644 --- a/arch/arm/boot/dts/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/exynos4210-i9100.dts @@ -672,26 +672,26 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep0>; - sleep0: sleep-states { - gpa0-0 { + sleep0: sleep-state { + gpa0-0-pin { samsung,pins = "gpa0-0"; samsung,pin-con-pdn = ; samsung,pin-pud-pdn = ; }; - gpa0-1 { + gpa0-1-pin { samsung,pins = "gpa0-1"; samsung,pin-con-pdn = ; samsung,pin-pud-pdn = ; }; - gpa0-2 { + gpa0-2-pin { samsung,pins = "gpa0-2"; samsung,pin-con-pdn = ; samsung,pin-pud-pdn = ; }; - gpa0-3 { + gpa0-3-pin { samsung,pins = "gpa0-3"; samsung,pin-con-pdn = ; samsung,pin-pud-pdn = ; @@ -700,19 +700,19 @@ }; &pinctrl_1 { - mhl_int: mhl-int { + mhl_int: mhl-int-pins { samsung,pins = "gpf3-5"; samsung,pin-pud = ; }; - i2c_mhl_bus: i2c-mhl-bus { + i2c_mhl_bus: i2c-mhl-bus-pins { samsung,pins = "gpf0-4", "gpf0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb_sel: usb-sel { + usb_sel: usb-sel-pins { samsung,pins = "gpl0-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -720,7 +720,7 @@ samsung,pin-val = <0>; }; - bt_en: bt-en { + bt_en: bt-en-pins { samsung,pins = "gpl0-4"; samsung,pin-function = ; samsung,pin-pud = ; @@ -728,7 +728,7 @@ samsung,pin-val = <0>; }; - bt_res: bt-res { + bt_res: bt-res-pins { samsung,pins = "gpl1-0"; samsung,pin-function = ; samsung,pin-pud = ; @@ -736,7 +736,7 @@ samsung,pin-val = <0>; }; - otg_gp: otg-gp { + otg_gp: otg-gp-pins { samsung,pins = "gpx3-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -744,23 +744,23 @@ samsung,pin-val = <0>; }; - mag_mhl_gpio: mag-mhl { + mag_mhl_gpio: mag-mhl-pins { samsung,pins = "gpd0-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - max8997_irq: max8997-irq { + max8997_irq: max8997-irq-pins { samsung,pins = "gpx0-7"; samsung,pin-pud = ; }; - max17042_fuel_irq: max17042-fuel-irq { + max17042_fuel_irq: max17042-fuel-irq-pins { samsung,pins = "gpx2-3"; samsung,pin-pud = ; }; - tsp224_irq: tsp224-irq { + tsp224_irq: tsp224-irq-pins { samsung,pins = "gpx0-4"; samsung,pin-pud = ; }; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 435fda60e86d..a08ce2f37ea2 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -316,7 +316,7 @@ }; &pinctrl_1 { - max8997_irq: max8997-irq { + max8997_irq: max8997-irq-pins { samsung,pins = "gpx0-3", "gpx0-4"; samsung,pin-pud = ; }; diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 520c5934a8d4..6373009bb727 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -14,7 +14,7 @@ #include &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -22,7 +22,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -30,7 +30,7 @@ #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -38,7 +38,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -46,7 +46,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -54,7 +54,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -62,7 +62,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -70,7 +70,7 @@ #interrupt-cells = <2>; }; - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -78,7 +78,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -86,7 +86,7 @@ #interrupt-cells = <2>; }; - gpe2: gpe2 { + gpe2: gpe2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -94,7 +94,7 @@ #interrupt-cells = <2>; }; - gpe3: gpe3 { + gpe3: gpe3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -102,7 +102,7 @@ #interrupt-cells = <2>; }; - gpe4: gpe4 { + gpe4: gpe4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -110,7 +110,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -118,7 +118,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -126,7 +126,7 @@ #interrupt-cells = <2>; }; - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -134,7 +134,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -142,112 +142,112 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart_audio_a: uart-audio-a { + uart_audio_a: uart-audio-a-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart_audio_b: uart-audio-b { + uart_audio_b: uart-audio-b-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c4_bus: i2c4-bus { + i2c4_bus: i2c4-bus-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c5_bus: i2c5-bus { + i2c5_bus: i2c5-bus-pins { samsung,pins = "gpb-6", "gpb-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = ; @@ -255,7 +255,7 @@ samsung,pin-drv = ; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = ; @@ -263,7 +263,7 @@ samsung,pin-drv = ; }; - ac97_bus: ac97-bus { + ac97_bus: ac97-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = ; @@ -271,7 +271,7 @@ samsung,pin-drv = ; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = ; @@ -279,7 +279,7 @@ samsung,pin-drv = ; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = ; @@ -287,105 +287,105 @@ samsung,pin-drv = ; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpc1-0", "gpc1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c6_bus: i2c6-bus { + i2c6_bus: i2c6-bus-pins { samsung,pins = "gpc1-3", "gpc1-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c7_bus: i2c7-bus { + i2c7_bus: i2c7-bus-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_ctrl: lcd-ctrl { + lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpd0-0", "gpd0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_sync: lcd-sync { + lcd_sync: lcd-sync-pins { samsung,pins = "gpf0-0", "gpf0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_en: lcd-en { + lcd_en: lcd-en-pins { samsung,pins = "gpe3-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_clk: lcd-clk { + lcd_clk: lcd-clk-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_data16: lcd-data-width16 { + lcd_data16: lcd-data-width16-pins { samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", @@ -395,7 +395,7 @@ samsung,pin-drv = ; }; - lcd_data18: lcd-data-width18 { + lcd_data18: lcd-data-width18-pins { samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", @@ -406,7 +406,7 @@ samsung,pin-drv = ; }; - lcd_data24: lcd-data-width24 { + lcd_data24: lcd-data-width24-pins { samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", @@ -420,7 +420,7 @@ }; &pinctrl_1 { - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -428,7 +428,7 @@ #interrupt-cells = <2>; }; - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -436,7 +436,7 @@ #interrupt-cells = <2>; }; - gpk0: gpk0 { + gpk0: gpk0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -444,7 +444,7 @@ #interrupt-cells = <2>; }; - gpk1: gpk1 { + gpk1: gpk1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -452,7 +452,7 @@ #interrupt-cells = <2>; }; - gpk2: gpk2 { + gpk2: gpk2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -460,7 +460,7 @@ #interrupt-cells = <2>; }; - gpk3: gpk3 { + gpk3: gpk3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -468,7 +468,7 @@ #interrupt-cells = <2>; }; - gpl0: gpl0 { + gpl0: gpl0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -476,7 +476,7 @@ #interrupt-cells = <2>; }; - gpl1: gpl1 { + gpl1: gpl1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -484,7 +484,7 @@ #interrupt-cells = <2>; }; - gpl2: gpl2 { + gpl2: gpl2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -492,42 +492,42 @@ #interrupt-cells = <2>; }; - gpy0: gpy0 { + gpy0: gpy0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy1: gpy1 { + gpy1: gpy1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy2: gpy2 { + gpy2: gpy2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy3: gpy3 { + gpy3: gpy3-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy4: gpy4 { + gpy4: gpy4-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy5: gpy5 { + gpy5: gpy5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy6: gpy6 { + gpy6: gpy6-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -544,7 +544,7 @@ #interrupt-cells = <2>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -561,7 +561,7 @@ #interrupt-cells = <2>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -569,7 +569,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -577,238 +577,238 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpk0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpk0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpk0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpk0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_clk: sd4-clk { + sd4_clk: sd4-clk-pins { samsung,pins = "gpk0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_cmd: sd4-cmd { + sd4_cmd: sd4-cmd-pins { samsung,pins = "gpk0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_cd: sd4-cd { + sd4_cd: sd4-cd-pins { samsung,pins = "gpk0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_bus1: sd4-bus-width1 { + sd4_bus1: sd4-bus-width1-pins { samsung,pins = "gpk0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_bus4: sd4-bus-width4 { + sd4_bus4: sd4-bus-width4-pins { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_bus8: sd4-bus-width8 { + sd4_bus8: sd4-bus-width8-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpk1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpk1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpk1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpk1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpk2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpk2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpk2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpk2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus8: sd2-bus-width8 { + sd2_bus8: sd2-bus-width8-pins { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_clk: sd3-clk { + sd3_clk: sd3-clk-pins { samsung,pins = "gpk3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_cmd: sd3-cmd { + sd3_cmd: sd3-cmd-pins { samsung,pins = "gpk3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_cd: sd3-cd { + sd3_cd: sd3-cd-pins { samsung,pins = "gpk3-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_bus1: sd3-bus-width1 { + sd3_bus1: sd3-bus-width1-pins { samsung,pins = "gpk3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_bus4: sd3-bus-width4 { + sd3_bus4: sd3-bus-width4-pins { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint0: ext-int0 { + eint0: ext-int0-pins { samsung,pins = "gpx0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint8: ext-int8 { + eint8: ext-int8-pins { samsung,pins = "gpx1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint15: ext-int15 { + eint15: ext-int15-pins { samsung,pins = "gpx1-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint16: ext-int16 { + eint16: ext-int16-pins { samsung,pins = "gpx2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint31: ext-int31 { + eint31: ext-int31-pins { samsung,pins = "gpx3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_a_io: cam-port-a-io { + cam_port_a_io: cam-port-a-io-pins { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; @@ -817,21 +817,21 @@ samsung,pin-drv = ; }; - cam_port_a_clk_active: cam-port-a-clk-active { + cam_port_a_clk_active: cam-port-a-clk-active-pins { samsung,pins = "gpj1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_a_clk_idle: cam-port-a-clk-idle { + cam_port_a_clk_idle: cam-port-a-clk-idle-pins { samsung,pins = "gpj1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hdmi_cec: hdmi-cec { + hdmi_cec: hdmi-cec-pins { samsung,pins = "gpx3-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -840,12 +840,12 @@ }; &pinctrl_2 { - gpz: gpz { + gpz: gpz-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; samsung,pin-function = ; @@ -853,7 +853,7 @@ samsung,pin-drv = ; }; - pcm0_bus: pcm0-bus { + pcm0_bus: pcm0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4"; samsung,pin-function = ; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index d5797a67bf48..a5dfd7fd49b3 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -152,14 +152,14 @@ }; &pinctrl_1 { - keypad_rows: keypad-rows { + keypad_rows: keypad-rows-pins { samsung,pins = "gpx2-0", "gpx2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_cols: keypad-cols { + keypad_cols: keypad-cols-pins { samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; samsung,pin-function = ; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 9c4ff7521348..01f44d95f671 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -464,19 +464,19 @@ }; &pinctrl_1 { - bt_shutdown: bt-shutdown { + bt_shutdown: bt-shutdown-pins { samsung,pins = "gpl1-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - bt_host_wakeup: bt-host-wakeup { + bt_host_wakeup: bt-host-wakeup-pins { samsung,pins = "gpx2-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - bt_device_wakeup: bt-device-wakeup { + bt_device_wakeup: bt-device-wakeup-pins { samsung,pins = "gpx3-1"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 9f93e7464aed..138d606d58a5 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -533,37 +533,37 @@ }; &pinctrl_1 { - bt_shutdown: bt-shutdown { + bt_shutdown: bt-shutdown-pins { samsung,pins = "gpe1-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - bt_host_wakeup: bt-host-wakeup { + bt_host_wakeup: bt-host-wakeup-pins { samsung,pins = "gpx2-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - bt_device_wakeup: bt-device-wakeup { + bt_device_wakeup: bt-device-wakeup-pins { samsung,pins = "gpx3-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - lp3974_irq: lp3974-irq { + lp3974_irq: lp3974-irq-pins { samsung,pins = "gpx0-7", "gpx2-7"; samsung,pin-pud = ; }; - hdmi_hpd: hdmi-hpd { + hdmi_hpd: hdmi-hpd-pins { samsung,pins = "gpx3-7"; samsung,pin-pud = ; }; }; &pinctrl_0 { - i2c_ddc_bus: i2c-ddc-bus { + i2c_ddc_bus: i2c-ddc-bus-pins { samsung,pins = "gpe4-2", "gpe4-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -659,7 +659,7 @@ }; &soc { - mdma0: mdma@12840000 { + mdma0: dma-controller@12840000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x12840000 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 7e7d65ce6585..2c25cc37934e 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -527,8 +527,6 @@ compatible = "samsung,exynos4210-tmu"; clocks = <&clock CLK_TMU_APBIF>; clock-names = "tmu_apbif"; - samsung,tmu_gain = <15>; - samsung,tmu_reference_voltage = <7>; }; #include "exynos4210-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index c14e37dc3a9b..03dffc690b79 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -151,13 +151,13 @@ }; &pinctrl_0 { - camera_flash_host: camera-flash-host { + camera_flash_host: camera-flash-host-pins { samsung,pins = "gpj1-0"; samsung,pin-function = ; samsung,pin-val = <0>; }; - camera_flash_isp: camera-flash-isp { + camera_flash_isp: camera-flash-isp-pins { samsung,pins = "gpj1-0"; samsung,pin-function = ; samsung,pin-val = <1>; diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index 47431307cb3c..a9406280b979 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -192,7 +192,7 @@ }; &pinctrl_1 { - ether-reset { + ether-reset-pins { samsung,pins = "gpc0-1"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index b3726d4d7d93..a67cb61e3cbb 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -484,7 +484,7 @@ }; &pinctrl_1 { - hsic_reset: hsic-reset { + hsic_reset: hsic-reset-pins { samsung,pins = "gpm2-4"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 968c7943653e..23f50c9be527 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -987,19 +987,19 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep0>; - mhl_int: mhl-int { + mhl_int: mhl-int-pins { samsung,pins = "gpf3-5"; samsung,pin-pud = ; }; - i2c_mhl_bus: i2c-mhl-bus { + i2c_mhl_bus: i2c-mhl-bus-pins { samsung,pins = "gpf0-4", "gpf0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sleep0: sleep-states { + sleep0: sleep-state { PIN_SLP(gpa0-0, INPUT, NONE); PIN_SLP(gpa0-1, OUT0, NONE); PIN_SLP(gpa0-2, INPUT, NONE); @@ -1102,52 +1102,52 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep1>; - gpio_keys: gpio-keys { + gpio_keys: gpio-keys-pins { samsung,pins = "gpx0-1", "gpx2-2", "gpx2-7", "gpx3-3"; samsung,pin-pud = ; }; - bt_shutdown: bt-shutdown { + bt_shutdown: bt-shutdown-pins { samsung,pins = "gpl0-6"; samsung,pin-pud = ; }; - bt_host_wakeup: bt-host-wakeup { + bt_host_wakeup: bt-host-wakeup-pins { samsung,pins = "gpx2-6"; samsung,pin-pud = ; }; - bt_device_wakeup: bt-device-wakeup { + bt_device_wakeup: bt-device-wakeup-pins { samsung,pins = "gpx3-1"; samsung,pin-pud = ; }; - max77686_irq: max77686-irq { + max77686_irq: max77686-irq-pins { samsung,pins = "gpx0-7"; samsung,pin-pud = ; }; - max77693_irq: max77693-irq { + max77693_irq: max77693-irq-pins { samsung,pins = "gpx1-5"; samsung,pin-pud = ; }; - max77693_fuel_irq: max77693-fuel-irq { + max77693_fuel_irq: max77693-fuel-irq-pins { samsung,pins = "gpx2-3"; samsung,pin-pud = ; }; - sdhci2_cd: sdhci2-cd-irq { + sdhci2_cd: sdhci2-cd-irq-pins { samsung,pins = "gpx3-4"; samsung,pin-pud = ; }; - hdmi_hpd: hdmi-hpd { + hdmi_hpd: hdmi-hpd-pins { samsung,pins = "gpx3-7"; samsung,pin-pud = ; }; - sleep1: sleep-states { + sleep1: sleep-state { PIN_SLP(gpk0-0, PREV, NONE); PIN_SLP(gpk0-1, PREV, NONE); PIN_SLP(gpk0-2, OUT0, NONE); @@ -1300,7 +1300,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep2>; - sleep2: sleep-states { + sleep2: sleep-state { PIN_SLP(gpz-0, INPUT, DOWN); PIN_SLP(gpz-1, INPUT, DOWN); PIN_SLP(gpz-2, INPUT, DOWN); @@ -1315,7 +1315,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep3>; - sleep3: sleep-states { + sleep3: sleep-state { PIN_SLP(gpv0-0, INPUT, DOWN); PIN_SLP(gpv0-1, INPUT, DOWN); PIN_SLP(gpv0-2, INPUT, DOWN); diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 5b1d4591b35c..e7669b9e9edb 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -172,24 +172,24 @@ }; &pinctrl_1 { - gpio_power_key: power-key { + gpio_power_key: power-key-pins { samsung,pins = "gpx1-3"; samsung,pin-pud = ; }; - max77686_irq: max77686-irq { + max77686_irq: max77686-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hdmi_hpd: hdmi-hpd { + hdmi_hpd: hdmi-hpd-pins { samsung,pins = "gpx3-7"; samsung,pin-pud = ; }; - emmc_rstn: emmc-rstn { + emmc_rstn: emmc-rstn-pins { samsung,pins = "gpk1-2"; samsung,pin-pud = ; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 440135d0ff2a..a9fada51eb50 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -112,7 +112,7 @@ }; &pinctrl_1 { - gpio_home_key: home-key { + gpio_home_key: home-key-pins { samsung,pins = "gpx2-2"; samsung,pin-pud = ; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index e6aec5facabf..6db09dba07ff 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -506,14 +506,14 @@ }; &pinctrl_1 { - keypad_rows: keypad-rows { + keypad_rows: keypad-rows-pins { samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_cols: keypad-cols { + keypad_cols: keypad-cols-pins { samsung,pins = "gpx1-0", "gpx1-1"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 22c3086e0076..97f131b1014b 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include / { compatible = "samsung,p4note", "samsung,exynos4412", "samsung,exynos4"; @@ -114,6 +115,17 @@ clock-names = "ext_clock"; }; + battery_cell: battery-cell { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + constant-charge-current-max-microamp = <2200000>; + precharge-current-microamp = <250000>; + charge-term-current-microamp = <250000>; + constant-charge-voltage-max-microvolt = <4200000>; + + power-supplies = <&power_supply>; + }; + i2c-gpio-1 { compatible = "i2c-gpio"; sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; @@ -182,6 +194,28 @@ }; }; }; + + i2c-gpio-4 { + compatible = "i2c-gpio"; + sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + power_supply: charger@6 { + compatible = "summit,smb347"; + reg = <0x6>; + summit,enable-usb-charging; + summit,enable-charge-control = ; + summit,fast-voltage-threshold-microvolt = <2600000>; + summit,chip-temperature-threshold-celsius = <130>; + summit,usb-current-limit-microamp = <1800000>; + + monitored-battery = <&battery_cell>; + }; + }; }; &adc { @@ -641,19 +675,19 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep0>; - tsp_reg_gpio_2: tsp-reg-gpio-2 { + tsp_reg_gpio_2: tsp-reg-gpio-2-pins { samsung,pins = "gpb-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - tsp_reg_gpio_3: tsp-reg-gpio-3 { + tsp_reg_gpio_3: tsp-reg-gpio-3-pins { samsung,pins = "gpb-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - sleep0: sleep-states { + sleep0: sleep-state { PIN_SLP(gpa0-0, INPUT, NONE); PIN_SLP(gpa0-1, OUT0, NONE); PIN_SLP(gpa0-2, INPUT, NONE); @@ -755,19 +789,19 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep1>; - sd3_wifi: sd3-wifi { + sd3_wifi: sd3-wifi-pins { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - bt_shutdown: bt-shutdown { + bt_shutdown: bt-shutdown-pins { samsung,pins = "gpl0-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart_sel: uart-sel { + uart_sel: uart-sel-pins { samsung,pins = "gpl2-7"; samsung,pin-function = ; samsung,pin-pud = ; @@ -775,82 +809,82 @@ /* 0 = CP, 1 = AP (serial output) */ }; - tsp_rst: tsp-rst { + tsp_rst: tsp-rst-pins { samsung,pins = "gpm0-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - tsp_irq: tsp-irq { + tsp_irq: tsp-irq-pins { samsung,pins = "gpm2-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - wifi_reset: wifi-reset { + wifi_reset: wifi-reset-pins { samsung,pins = "gpm3-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - tsp_reg_gpio_1: tsp-reg-gpio-1 { + tsp_reg_gpio_1: tsp-reg-gpio-1-pins { samsung,pins = "gpm4-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - ak8975_irq: ak8975-irq { + ak8975_irq: ak8975-irq-pins { samsung,pins = "gpm4-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - stmpe_adc_irq: stmpe-adc-irq { + stmpe_adc_irq: stmpe-adc-irq-pins { samsung,pins = "gpx0-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - max77686_irq: max77686-irq { + max77686_irq: max77686-irq-pins { samsung,pins = "gpx0-7"; samsung,pin-pud = ; }; - gpio_keys: gpio-keys { + gpio_keys: gpio-keys-pins { samsung,pins = "gpx2-2", "gpx2-7", "gpx3-3"; samsung,pin-pud = ; }; - fuel_alert_irq: fuel-alert-irq { + fuel_alert_irq: fuel-alert-irq-pins { samsung,pins = "gpx2-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - wifi_host_wake: wifi-host-wake { + wifi_host_wake: wifi-host-wake-pins { samsung,pins = "gpx2-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - bt_host_wakeup: bt-host-wakeup { + bt_host_wakeup: bt-host-wakeup-pins { samsung,pins = "gpx2-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - bt_device_wakeup: bt-device-wakeup { + bt_device_wakeup: bt-device-wakeup-pins { samsung,pins = "gpx3-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - sdhci2_cd: sdhci2-cd { + sdhci2_cd: sdhci2-cd-pins { samsung,pins = "gpx3-4"; samsung,pin-pud = ; }; - sleep1: sleep-states { + sleep1: sleep-state { PIN_SLP(gpk0-0, PREV, NONE); PIN_SLP(gpk0-1, PREV, NONE); PIN_SLP(gpk0-2, PREV, NONE); @@ -1004,7 +1038,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep2>; - sleep2: sleep-states { + sleep2: sleep-state { PIN_SLP(gpz-0, INPUT, DOWN); PIN_SLP(gpz-1, INPUT, DOWN); PIN_SLP(gpz-2, INPUT, DOWN); @@ -1019,7 +1053,7 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep3>; - sleep3: sleep-states { + sleep3: sleep-state { PIN_SLP(gpv0-0, INPUT, DOWN); PIN_SLP(gpv0-1, INPUT, DOWN); PIN_SLP(gpv0-2, INPUT, DOWN); diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi index d7d5fdc230d8..88b8afd55664 100644 --- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi @@ -19,7 +19,7 @@ } &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -27,7 +27,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -35,7 +35,7 @@ #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -43,7 +43,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -51,7 +51,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -59,7 +59,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -67,7 +67,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -75,7 +75,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -83,7 +83,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -91,7 +91,7 @@ #interrupt-cells = <2>; }; - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -99,7 +99,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -107,7 +107,7 @@ #interrupt-cells = <2>; }; - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -115,7 +115,7 @@ #interrupt-cells = <2>; }; - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -123,112 +123,112 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart_audio_a: uart-audio-a { + uart_audio_a: uart-audio-a-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart_audio_b: uart-audio-b { + uart_audio_b: uart-audio-b-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c4_bus: i2c4-bus { + i2c4_bus: i2c4-bus-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c5_bus: i2c5-bus { + i2c5_bus: i2c5-bus-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = ; @@ -236,7 +236,7 @@ samsung,pin-drv = ; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = ; @@ -244,7 +244,7 @@ samsung,pin-drv = ; }; - ac97_bus: ac97-bus { + ac97_bus: ac97-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = ; @@ -252,7 +252,7 @@ samsung,pin-drv = ; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = ; @@ -260,7 +260,7 @@ samsung,pin-drv = ; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = ; @@ -268,105 +268,105 @@ samsung,pin-drv = ; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpc1-0", "gpc1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c6_bus: i2c6-bus { + i2c6_bus: i2c6-bus-pins { samsung,pins = "gpc1-3", "gpc1-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_ctrl: lcd-ctrl { + lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpd0-0", "gpd0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c7_bus: i2c7-bus { + i2c7_bus: i2c7-bus-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - mipi0_clk: mipi0-clk { + mipi0_clk: mipi0-clk-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - mipi1_clk: mipi1-clk { + mipi1_clk: mipi1-clk-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_clk: lcd-clk { + lcd_clk: lcd-clk-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_data16: lcd-data-width16 { + lcd_data16: lcd-data-width16-pins { samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", @@ -376,7 +376,7 @@ samsung,pin-drv = ; }; - lcd_data18: lcd-data-width18 { + lcd_data18: lcd-data-width18-pins { samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", @@ -387,7 +387,7 @@ samsung,pin-drv = ; }; - lcd_data24: lcd-data-width24 { + lcd_data24: lcd-data-width24-pins { samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", @@ -399,14 +399,14 @@ samsung,pin-drv = ; }; - lcd_ldi: lcd-ldi { + lcd_ldi: lcd-ldi-pins { samsung,pins = "gpf3-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_a_io: cam-port-a-io { + cam_port_a_io: cam-port-a-io-pins { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; @@ -415,14 +415,14 @@ samsung,pin-drv = ; }; - cam_port_a_clk_active: cam-port-a-clk-active { + cam_port_a_clk_active: cam-port-a-clk-active-pins { samsung,pins = "gpj1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_a_clk_idle: cam-port-a-clk-idle { + cam_port_a_clk_idle: cam-port-a-clk-idle-pins { samsung,pins = "gpj1-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -431,7 +431,7 @@ }; &pinctrl_1 { - gpk0: gpk0 { + gpk0: gpk0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -439,7 +439,7 @@ #interrupt-cells = <2>; }; - gpk1: gpk1 { + gpk1: gpk1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -447,7 +447,7 @@ #interrupt-cells = <2>; }; - gpk2: gpk2 { + gpk2: gpk2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -455,7 +455,7 @@ #interrupt-cells = <2>; }; - gpk3: gpk3 { + gpk3: gpk3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -463,7 +463,7 @@ #interrupt-cells = <2>; }; - gpl0: gpl0 { + gpl0: gpl0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -471,7 +471,7 @@ #interrupt-cells = <2>; }; - gpl1: gpl1 { + gpl1: gpl1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -479,7 +479,7 @@ #interrupt-cells = <2>; }; - gpl2: gpl2 { + gpl2: gpl2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -487,7 +487,7 @@ #interrupt-cells = <2>; }; - gpm0: gpm0 { + gpm0: gpm0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -495,7 +495,7 @@ #interrupt-cells = <2>; }; - gpm1: gpm1 { + gpm1: gpm1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -503,7 +503,7 @@ #interrupt-cells = <2>; }; - gpm2: gpm2 { + gpm2: gpm2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -511,7 +511,7 @@ #interrupt-cells = <2>; }; - gpm3: gpm3 { + gpm3: gpm3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -519,7 +519,7 @@ #interrupt-cells = <2>; }; - gpm4: gpm4 { + gpm4: gpm4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -527,42 +527,42 @@ #interrupt-cells = <2>; }; - gpy0: gpy0 { + gpy0: gpy0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy1: gpy1 { + gpy1: gpy1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy2: gpy2 { + gpy2: gpy2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy3: gpy3 { + gpy3: gpy3-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy4: gpy4 { + gpy4: gpy4-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy5: gpy5 { + gpy5: gpy5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy6: gpy6 { + gpy6: gpy6-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -579,7 +579,7 @@ #interrupt-cells = <2>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -596,7 +596,7 @@ #interrupt-cells = <2>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -604,7 +604,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -612,203 +612,203 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpk0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpk0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpk0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpk0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_clk: sd4-clk { + sd4_clk: sd4-clk-pins { samsung,pins = "gpk0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_cmd: sd4-cmd { + sd4_cmd: sd4-cmd-pins { samsung,pins = "gpk0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_cd: sd4-cd { + sd4_cd: sd4-cd-pins { samsung,pins = "gpk0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_bus1: sd4-bus-width1 { + sd4_bus1: sd4-bus-width1-pins { samsung,pins = "gpk0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_bus4: sd4-bus-width4 { + sd4_bus4: sd4-bus-width4-pins { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd4_bus8: sd4-bus-width8 { + sd4_bus8: sd4-bus-width8-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpk1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpk1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpk1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpk1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpk2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpk2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpk2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpk2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus8: sd2-bus-width8 { + sd2_bus8: sd2-bus-width8-pins { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_clk: sd3-clk { + sd3_clk: sd3-clk-pins { samsung,pins = "gpk3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_cmd: sd3-cmd { + sd3_cmd: sd3-cmd-pins { samsung,pins = "gpk3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_cd: sd3-cd { + sd3_cd: sd3-cd-pins { samsung,pins = "gpk3-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_bus1: sd3-bus-width1 { + sd3_bus1: sd3-bus-width1-pins { samsung,pins = "gpk3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_bus4: sd3-bus-width4 { + sd3_bus4: sd3-bus-width4-pins { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_b_io: cam-port-b-io { + cam_port_b_io: cam-port-b-io-pins { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; @@ -817,77 +817,77 @@ samsung,pin-drv = ; }; - cam_port_b_clk_active: cam-port-b-clk-active { + cam_port_b_clk_active: cam-port-b-clk-active-pins { samsung,pins = "gpm2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_b_clk_idle: cam-port-b-clk-idle { + cam_port_b_clk_idle: cam-port-b-clk-idle-pins { samsung,pins = "gpm2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint0: ext-int0 { + eint0: ext-int0-pins { samsung,pins = "gpx0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint8: ext-int8 { + eint8: ext-int8-pins { samsung,pins = "gpx1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint15: ext-int15 { + eint15: ext-int15-pins { samsung,pins = "gpx1-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint16: ext-int16 { + eint16: ext-int16-pins { samsung,pins = "gpx2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint31: ext-int31 { + eint31: ext-int31-pins { samsung,pins = "gpx3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_i2c0: fimc-is-i2c0 { + fimc_is_i2c0: fimc-is-i2c0-pins { samsung,pins = "gpm4-0", "gpm4-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_i2c1: fimc-is-i2c1 { + fimc_is_i2c1: fimc-is-i2c1-pins { samsung,pins = "gpm4-2", "gpm4-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_uart: fimc-is-uart { + fimc_is_uart: fimc-is-uart-pins { samsung,pins = "gpm3-5", "gpm3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hdmi_cec: hdmi-cec { + hdmi_cec: hdmi-cec-pins { samsung,pins = "gpx3-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -896,7 +896,7 @@ }; &pinctrl_2 { - gpz: gpz { + gpz: gpz-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -904,7 +904,7 @@ #interrupt-cells = <2>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; samsung,pin-function = ; @@ -912,7 +912,7 @@ samsung,pin-drv = ; }; - pcm0_bus: pcm0-bus { + pcm0_bus: pcm0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4"; samsung,pin-function = ; @@ -922,7 +922,7 @@ }; &pinctrl_3 { - gpv0: gpv0 { + gpv0: gpv0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -930,7 +930,7 @@ #interrupt-cells = <2>; }; - gpv1: gpv1 { + gpv1: gpv1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -938,7 +938,7 @@ #interrupt-cells = <2>; }; - gpv2: gpv2 { + gpv2: gpv2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -946,7 +946,7 @@ #interrupt-cells = <2>; }; - gpv3: gpv3 { + gpv3: gpv3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -954,7 +954,7 @@ #interrupt-cells = <2>; }; - gpv4: gpv4 { + gpv4: gpv4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -962,7 +962,7 @@ #interrupt-cells = <2>; }; - c2c_bus: c2c-bus { + c2c_bus: c2c-bus-pins { samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index cc99b955af0c..a40ff394977c 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -133,14 +133,14 @@ }; &pinctrl_1 { - keypad_rows: keypad-rows { + keypad_rows: keypad-rows-pins { samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_cols: keypad-cols { + keypad_cols: keypad-cols-pins { samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; samsung,pin-function = ; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index d3802046c8b8..aa0b61b59970 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -813,7 +813,7 @@ interrupt-parent = <&combiner>; interrupts = <2 4>; reg = <0x100C0000 0x100>; - clocks = <&clock 383>; + clocks = <&clock CLK_TMU_APBIF>; clock-names = "tmu_apbif"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 3583095fbb2a..f7795f2d0f0e 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -590,7 +590,7 @@ }; &pinctrl_0 { - s5m8767_irq: s5m8767-irq { + s5m8767_irq: s5m8767-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-pud = ; }; @@ -632,3 +632,8 @@ #size-cells = <0>; }; }; + +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index d31a68672bfa..918947a3897e 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -12,7 +12,7 @@ #include &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -20,7 +20,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -28,7 +28,7 @@ #interrupt-cells = <2>; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -36,7 +36,7 @@ #interrupt-cells = <2>; }; - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -44,7 +44,7 @@ #interrupt-cells = <2>; }; - gpb1: gpb1 { + gpb1: gpb1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -52,7 +52,7 @@ #interrupt-cells = <2>; }; - gpb2: gpb2 { + gpb2: gpb2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -60,7 +60,7 @@ #interrupt-cells = <2>; }; - gpb3: gpb3 { + gpb3: gpb3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -68,7 +68,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -76,7 +76,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -84,7 +84,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -92,7 +92,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -100,7 +100,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -108,7 +108,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -116,42 +116,42 @@ #interrupt-cells = <2>; }; - gpy0: gpy0 { + gpy0: gpy0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy1: gpy1 { + gpy1: gpy1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy2: gpy2 { + gpy2: gpy2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy3: gpy3 { + gpy3: gpy3-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy4: gpy4 { + gpy4: gpy4-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy5: gpy5 { + gpy5: gpy5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy6: gpy6 { + gpy6: gpy6-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpc4: gpc4 { + gpc4: gpc4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -159,7 +159,7 @@ #interrupt-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -170,7 +170,7 @@ <26 0>, <26 1>, <27 0>, <27 1>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -181,7 +181,7 @@ <30 0>, <30 1>, <31 0>, <31 1>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -189,7 +189,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -197,104 +197,104 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c2_hs_bus: i2c2-hs-bus { + i2c2_hs_bus: i2c2-hs-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c2_gpio_bus: i2c2-gpio-bus { + i2c2_gpio_bus: i2c2-gpio-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c3_hs_bus: i2c3-hs-bus { + i2c3_hs_bus: i2c3-hs-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart3_data: uart3-data { - samsung,pins = "gpa1-4", "gpa1-4"; + uart3_data: uart3-data-pins { + samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c4_bus: i2c4-bus { + i2c4_bus: i2c4-bus-pins { samsung,pins = "gpa2-0", "gpa2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c5_bus: i2c5-bus { + i2c5_bus: i2c5-bus-pins { samsung,pins = "gpa2-2", "gpa2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = ; @@ -302,7 +302,7 @@ samsung,pin-drv = ; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = ; @@ -310,7 +310,7 @@ samsung,pin-drv = ; }; - ac97_bus: ac97-bus { + ac97_bus: ac97-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = ; @@ -318,7 +318,7 @@ samsung,pin-drv = ; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; samsung,pin-function = ; @@ -326,7 +326,7 @@ samsung,pin-drv = ; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; samsung,pin-function = ; @@ -334,280 +334,280 @@ samsung,pin-drv = ; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpb1-0", "gpb1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c6_bus: i2c6-bus { + i2c6_bus: i2c6-bus-pins { samsung,pins = "gpb1-3", "gpb1-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpb2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpb2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpb2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpb2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c7_bus: i2c7-bus { + i2c7_bus: i2c7-bus-pins { samsung,pins = "gpb2-2", "gpb2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c0_hs_bus: i2c0-hs-bus { + i2c0_hs_bus: i2c0-hs-bus-pins { samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c1_hs_bus: i2c1-hs-bus { + i2c1_hs_bus: i2c1-hs-bus-pins { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpc0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpc0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpc0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpc0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpc2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpc2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpc2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpc2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpc3-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpc3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus8: sd2-bus-width8 { + sd2_bus8: sd2-bus-width8-pins { samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_clk: sd3-clk { + sd3_clk: sd3-clk-pins { samsung,pins = "gpc4-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_cmd: sd3-cmd { + sd3_cmd: sd3-cmd-pins { samsung,pins = "gpc4-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_cd: sd3-cd { + sd3_cd: sd3-cd-pins { samsung,pins = "gpc4-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_bus1: sd3-bus-width1 { + sd3_bus1: sd3-bus-width1-pins { samsung,pins = "gpc4-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_bus4: sd3-bus-width4 { + sd3_bus4: sd3-bus-width4-pins { samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpd0-0", "gpd0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - dp_hpd: dp_hpd { + dp_hpd: dp-hpd-pins { samsung,pins = "gpx0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hdmi_cec: hdmi-cec { + hdmi_cec: hdmi-cec-pins { samsung,pins = "gpx3-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hdmi_hpd: hdmi-hpd { + hdmi_hpd: hdmi-hpd-pins { samsung,pins = "gpx3-7"; samsung,pin-pud = ; }; }; &pinctrl_1 { - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -615,7 +615,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -623,7 +623,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -631,7 +631,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -639,7 +639,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -647,7 +647,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -655,7 +655,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -663,7 +663,7 @@ #interrupt-cells = <2>; }; - gph0: gph0 { + gph0: gph0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -671,7 +671,7 @@ #interrupt-cells = <2>; }; - gph1: gph1 { + gph1: gph1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -679,7 +679,7 @@ #interrupt-cells = <2>; }; - cam_gpio_a: cam-gpio-a { + cam_gpio_a: cam-gpio-a-pins { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; @@ -688,7 +688,7 @@ samsung,pin-drv = ; }; - cam_gpio_b: cam-gpio-b { + cam_gpio_b: cam-gpio-b-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = ; @@ -696,42 +696,42 @@ samsung,pin-drv = ; }; - cam_i2c2_bus: cam-i2c2-bus { + cam_i2c2_bus: cam-i2c2-bus-pins { samsung,pins = "gpe0-6", "gpe1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_spi1_bus: cam-spi1-bus { + cam_spi1_bus: cam-spi1-bus-pins { samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_i2c1_bus: cam-i2c1-bus { + cam_i2c1_bus: cam-i2c1-bus-pins { samsung,pins = "gpf0-2", "gpf0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_i2c0_bus: cam-i2c0-bus { + cam_i2c0_bus: cam-i2c0-bus-pins { samsung,pins = "gpf0-0", "gpf0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_spi0_bus: cam-spi0-bus { + cam_spi0_bus: cam-spi0-bus-pins { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_bayrgb_bus: cam-bayrgb-bus { + cam_bayrgb_bus: cam-bayrgb-bus-pins { samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", @@ -742,7 +742,7 @@ samsung,pin-drv = ; }; - cam_port_a: cam-port-a { + cam_port_a: cam-port-a-pins { samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", "gph1-0", "gph1-1", "gph1-2", "gph1-3", "gph1-4", "gph1-5", "gph1-6", "gph1-7"; @@ -753,7 +753,7 @@ }; &pinctrl_2 { - gpv0: gpv0 { + gpv0: gpv0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -761,7 +761,7 @@ #interrupt-cells = <2>; }; - gpv1: gpv1 { + gpv1: gpv1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -769,7 +769,7 @@ #interrupt-cells = <2>; }; - gpv2: gpv2 { + gpv2: gpv2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -777,7 +777,7 @@ #interrupt-cells = <2>; }; - gpv3: gpv3 { + gpv3: gpv3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -785,7 +785,7 @@ #interrupt-cells = <2>; }; - gpv4: gpv4 { + gpv4: gpv4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -793,7 +793,7 @@ #interrupt-cells = <2>; }; - c2c_rxd: c2c-rxd { + c2c_rxd: c2c-rxd-pins { samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3", "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", @@ -803,7 +803,7 @@ samsung,pin-drv = ; }; - c2c_txd: c2c-txd { + c2c_txd: c2c-txd-pins { samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3", "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", @@ -815,7 +815,7 @@ }; &pinctrl_3 { - gpz: gpz { + gpz: gpz-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -823,7 +823,7 @@ #interrupt-cells = <2>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; samsung,pin-function = ; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 39bbe18145cf..21fbbf3d8684 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -118,6 +118,9 @@ status = "okay"; ddc = <&i2c_2>; hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; }; &i2c_0 { @@ -410,10 +413,15 @@ }; &pinctrl_0 { - max77686_irq: max77686-irq { + max77686_irq: max77686-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; }; + +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index 2335c4687349..c15ecfc4077d 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -587,63 +587,63 @@ }; &pinctrl_0 { - wifi_en: wifi-en { + wifi_en: wifi-en-pins { samsung,pins = "gpx0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - wifi_rst: wifi-rst { + wifi_rst: wifi-rst-pins { samsung,pins = "gpx0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - power_key_irq: power-key-irq { + power_key_irq: power-key-irq-pins { samsung,pins = "gpx1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - ec_irq: ec-irq { + ec_irq: ec-irq-pins { samsung,pins = "gpx1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - tps65090_irq: tps65090-irq { + tps65090_irq: tps65090-irq-pins { samsung,pins = "gpx2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb3_vbus_en: usb3-vbus-en { + usb3_vbus_en: usb3-vbus-en-pins { samsung,pins = "gpx2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - max77686_irq: max77686-irq { + max77686_irq: max77686-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lid_irq: lid-irq { + lid_irq: lid-irq-pins { samsung,pins = "gpx3-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = ; samsung,pin-pud = ; @@ -652,14 +652,14 @@ }; &pinctrl_1 { - arb_their_claim: arb-their-claim { + arb_their_claim: arb-their-claim-pins { samsung,pins = "gpe0-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - arb_our_claim: arb-our-claim { + arb_our_claim: arb-our-claim-pins { samsung,pins = "gpf0-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -698,6 +698,11 @@ cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; }; +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + &usbdrd_dwc3 { dr_mode = "host"; }; diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/exynos5250-snow-rev5.dts index f8ca61df6981..0a47597d6f0d 100644 --- a/arch/arm/boot/dts/exynos5250-snow-rev5.dts +++ b/arch/arm/boot/dts/exynos5250-snow-rev5.dts @@ -47,7 +47,7 @@ }; &pinctrl_0 { - max98090_irq: max98090-irq { + max98090_irq: max98090-irq-pins { samsung,pins = "gpx0-4"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index a630bc654a49..906aa7aae710 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -43,7 +43,7 @@ }; &pinctrl_0 { - max98095_en: max98095-en { + max98095_en: max98095-en-pins { samsung,pins = "gpx1-7"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index e0feedcf54bb..24609bb20158 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -451,63 +451,63 @@ }; &pinctrl_0 { - s5m8767_dvs: s5m8767-dvs { + s5m8767_dvs: s5m8767-dvs-pins { samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - dp_hpd_gpio: dp-hpd { + dp_hpd_gpio: dp-hpd-pins { samsung,pins = "gpc3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - trackpad_irq: trackpad-irq { + trackpad_irq: trackpad-irq-pins { samsung,pins = "gpx1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - power_key_irq: power-key-irq { + power_key_irq: power-key-irq-pins { samsung,pins = "gpx1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - ec_irq: ec-irq { + ec_irq: ec-irq-pins { samsung,pins = "gpx1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - s5m8767_ds: s5m8767-ds { + s5m8767_ds: s5m8767-ds-pins { samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - s5m8767_irq: s5m8767-irq { + s5m8767_irq: s5m8767-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lid_irq: lid-irq { + lid_irq: lid-irq-pins { samsung,pins = "gpx3-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = ; samsung,pin-pud = ; @@ -516,7 +516,7 @@ }; &pinctrl_1 { - hsic_reset: hsic-reset { + hsic_reset: hsic-reset-pins { samsung,pins = "gpe1-0"; samsung,pin-function = ; samsung,pin-pud = ; @@ -553,4 +553,9 @@ num-cs = <1>; }; +&usbdrd { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + #include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 139778928b93..5baaa7eb71a4 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -496,8 +496,7 @@ status = "disabled"; reg = <0x12d20000 0x100>; interrupts = ; - dmas = <&pdma0 5 - &pdma0 4>; + dmas = <&pdma0 5>, <&pdma0 4>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -512,8 +511,7 @@ status = "disabled"; reg = <0x12d30000 0x100>; interrupts = ; - dmas = <&pdma1 5 - &pdma1 4>; + dmas = <&pdma1 5>, <&pdma1 4>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -528,8 +526,7 @@ status = "disabled"; reg = <0x12d40000 0x100>; interrupts = ; - dmas = <&pdma0 7 - &pdma0 6>; + dmas = <&pdma0 7>, <&pdma0 6>; dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; @@ -637,7 +634,7 @@ #sound-dai-cells = <1>; }; - usb_dwc3 { + usbdrd: usb3 { compatible = "samsung,exynos5250-dwusb3"; clocks = <&clock CLK_USB3>; clock-names = "usbdrd30"; @@ -695,7 +692,7 @@ samsung,pmureg-phandle = <&pmu_system_controller>; }; - pdma0: pdma@121a0000 { + pdma0: dma-controller@121a0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; interrupts = ; @@ -706,7 +703,7 @@ #dma-requests = <32>; }; - pdma1: pdma@121b0000 { + pdma1: dma-controller@121b0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; interrupts = ; @@ -717,7 +714,7 @@ #dma-requests = <32>; }; - mdma0: mdma@10800000 { + mdma0: dma-controller@10800000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; interrupts = ; @@ -728,7 +725,7 @@ #dma-requests = <1>; }; - mdma1: mdma@11c10000 { + mdma1: dma-controller@11c10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi index 17e2f3e0d71e..150607f8103d 100644 --- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -12,7 +12,7 @@ #include &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -20,7 +20,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -28,7 +28,7 @@ #interrupt-cells = <2>; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -36,7 +36,7 @@ #interrupt-cells = <2>; }; - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -44,7 +44,7 @@ #interrupt-cells = <2>; }; - gpb1: gpb1 { + gpb1: gpb1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -52,7 +52,7 @@ #interrupt-cells = <2>; }; - gpb2: gpb2 { + gpb2: gpb2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -60,7 +60,7 @@ #interrupt-cells = <2>; }; - gpb3: gpb3 { + gpb3: gpb3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -68,7 +68,7 @@ #interrupt-cells = <2>; }; - gpb4: gpb4 { + gpb4: gpb4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -76,7 +76,7 @@ #interrupt-cells = <2>; }; - gpb5: gpb5 { + gpb5: gpb5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -84,7 +84,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -92,7 +92,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -100,7 +100,7 @@ #interrupt-cells = <2>; }; - gpd2: gpd2 { + gpd2: gpd2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -108,7 +108,7 @@ #interrupt-cells = <2>; }; - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -116,7 +116,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -124,7 +124,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -132,7 +132,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -140,7 +140,7 @@ #interrupt-cells = <2>; }; - gpk0: gpk0 { + gpk0: gpk0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -148,7 +148,7 @@ #interrupt-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -164,7 +164,7 @@ #interrupt-cells = <2>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -180,7 +180,7 @@ #interrupt-cells = <2>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -188,7 +188,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -196,63 +196,63 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb3_vbus0_en: usb3-vbus0-en { + usb3_vbus0_en: usb3-vbus0-en-pins { samsung,pins = "gpa2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = ; @@ -260,7 +260,7 @@ samsung,pin-drv = ; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = ; @@ -268,105 +268,105 @@ samsung,pin-drv = ; }; - spdif1_bus: spdif1-bus { + spdif1_bus: spdif1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c0_hs_bus: i2c0-hs-bus { + i2c0_hs_bus: i2c0-hs-bus-pins { samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c1_hs_bus: i2c1-hs-bus { + i2c1_hs_bus: i2c1-hs-bus-pins { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c2_hs_bus: i2c2-hs-bus { + i2c2_hs_bus: i2c2-hs-bus-pins { samsung,pins = "gpb3-4", "gpb3-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c3_hs_bus: i2c3-hs-bus { + i2c3_hs_bus: i2c3-hs-bus-pins { samsung,pins = "gpb3-6", "gpb3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c4_bus: i2c4-bus { + i2c4_bus: i2c4-bus-pins { samsung,pins = "gpb4-0", "gpb4-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c5_bus: i2c5-bus { + i2c5_bus: i2c5-bus-pins { samsung,pins = "gpb4-2", "gpb4-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c6_bus: i2c6-bus { + i2c6_bus: i2c6-bus-pins { samsung,pins = "gpb4-4", "gpb4-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c7_bus: i2c7-bus { + i2c7_bus: i2c7-bus-pins { samsung,pins = "gpb4-6", "gpb4-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c8_bus: i2c8-bus { + i2c8_bus: i2c8-bus-pins { samsung,pins = "gpb5-0", "gpb5-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c9_bus: i2c9-bus { + i2c9_bus: i2c9-bus-pins { samsung,pins = "gpb5-2", "gpb5-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c10_bus: i2c10-bus { + i2c10_bus: i2c10-bus-pins { samsung,pins = "gpb5-4", "gpb5-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c11_bus: i2c11-bus { + i2c11_bus: i2c11-bus-pins { samsung,pins = "gpb5-6", "gpb5-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_gpio_a: cam-gpio-a { + cam_gpio_a: cam-gpio-a-pins { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; @@ -375,7 +375,7 @@ samsung,pin-drv = ; }; - cam_gpio_b: cam-gpio-b { + cam_gpio_b: cam-gpio-b-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = ; @@ -383,28 +383,28 @@ samsung,pin-drv = ; }; - cam_i2c1_bus: cam-i2c1-bus { + cam_i2c1_bus: cam-i2c1-bus-pins { samsung,pins = "gpf0-2", "gpf0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_i2c0_bus: cam-i2c0-bus { + cam_i2c0_bus: cam-i2c0-bus-pins { samsung,pins = "gpf0-0", "gpf0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_spi0_bus: cam-spi0-bus { + cam_spi0_bus: cam-spi0-bus-pins { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_spi1_bus: cam-spi1-bus { + cam_spi1_bus: cam-spi1-bus-pins { samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; samsung,pin-function = ; samsung,pin-pud = ; @@ -413,7 +413,7 @@ }; &pinctrl_1 { - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -421,7 +421,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -429,7 +429,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -437,7 +437,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -445,7 +445,7 @@ #interrupt-cells = <2>; }; - gpc4: gpc4 { + gpc4: gpc4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -453,112 +453,112 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpc0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpc0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpc0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_rdqs: sd0-rdqs { + sd0_rdqs: sd0-rdqs-pins { samsung,pins = "gpc0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpc1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpc1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpc1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus8: sd1-bus-width8 { + sd1_bus8: sd1-bus-width8-pins { samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpc2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpc2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -567,7 +567,7 @@ }; &pinctrl_2 { - gpz0: gpz0 { + gpz0: gpz0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -575,7 +575,7 @@ #interrupt-cells = <2>; }; - gpz1: gpz1 { + gpz1: gpz1-gpio-bank { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index 0dc2ec16aa0a..3c3b751d4360 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -29,6 +29,27 @@ #clock-cells = <0>; }; + ioclk_pcm: clock-pcm-ext { + compatible = "fixed-clock"; + clock-frequency = <2048000>; + clock-output-names = "ioclk_pcm_extclk"; + #clock-cells = <0>; + }; + + ioclk_i2s: clock-i2s-cd { + compatible = "fixed-clock"; + clock-frequency = <147456000>; + clock-output-names = "ioclk_i2s_cdclk"; + #clock-cells = <0>; + }; + + ioclk_spdif: clock-spdif-ext { + compatible = "fixed-clock"; + clock-frequency = <49152000>; + clock-output-names = "ioclk_spdif_extclk"; + #clock-cells = <0>; + }; + xrtcxti: xrtcxti { compatible = "fixed-clock"; clock-frequency = <32768>; @@ -38,7 +59,7 @@ }; &pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 524d244050e0..56271e7c4587 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -113,78 +113,206 @@ compatible = "samsung,exynos5260-clock-top"; reg = <0x10010000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_mif MIF_DOUT_MEM_PLL>, + <&clock_mif MIF_DOUT_BUS_PLL>, + <&clock_mif MIF_DOUT_MEDIA_PLL>; + clock-names = "fin_pll", + "dout_mem_pll", + "dout_bus_pll", + "dout_media_pll"; }; clock_peri: clock-controller@10200000 { compatible = "samsung,exynos5260-clock-peri"; reg = <0x10200000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&ioclk_pcm>, + <&ioclk_i2s>, + <&ioclk_spdif>, + <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_PERI_66>, + <&clock_top TOP_DOUT_SCLK_PERI_UART0>, + <&clock_top TOP_DOUT_SCLK_PERI_UART1>, + <&clock_top TOP_DOUT_SCLK_PERI_UART2>, + <&clock_top TOP_DOUT_SCLK_PERI_SPI0_B>, + <&clock_top TOP_DOUT_SCLK_PERI_SPI1_B>, + <&clock_top TOP_DOUT_SCLK_PERI_SPI2_B>, + <&clock_top TOP_DOUT_ACLK_PERI_AUD>; + clock-names = "fin_pll", + "ioclk_pcm_extclk", + "ioclk_i2s_cdclk", + "ioclk_spdif_extclk", + "phyclk_hdmi_phy_ref_cko", + "dout_aclk_peri_66", + "dout_sclk_peri_uart0", + "dout_sclk_peri_uart1", + "dout_sclk_peri_uart2", + "dout_sclk_peri_spi0_b", + "dout_sclk_peri_spi1_b", + "dout_sclk_peri_spi2_b", + "dout_aclk_peri_aud"; }; clock_egl: clock-controller@10600000 { compatible = "samsung,exynos5260-clock-egl"; reg = <0x10600000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_mif MIF_DOUT_BUS_PLL>; + clock-names = "fin_pll", + "dout_bus_pll"; }; clock_kfc: clock-controller@10700000 { compatible = "samsung,exynos5260-clock-kfc"; reg = <0x10700000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_mif MIF_DOUT_MEDIA_PLL>; + clock-names = "fin_pll", + "dout_media_pll"; }; clock_g2d: clock-controller@10a00000 { compatible = "samsung,exynos5260-clock-g2d"; reg = <0x10A00000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_G2D_333>; + clock-names = "fin_pll", + "dout_aclk_g2d_333"; }; clock_mif: clock-controller@10ce0000 { compatible = "samsung,exynos5260-clock-mif"; reg = <0x10CE0000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; }; clock_mfc: clock-controller@11090000 { compatible = "samsung,exynos5260-clock-mfc"; reg = <0x11090000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_MFC_333>; + clock-names = "fin_pll", + "dout_aclk_mfc_333"; }; clock_g3d: clock-controller@11830000 { compatible = "samsung,exynos5260-clock-g3d"; reg = <0x11830000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; }; clock_fsys: clock-controller@122e0000 { compatible = "samsung,exynos5260-clock-fsys"; reg = <0x122E0000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_FSYS_200>; + clock-names = "fin_pll", + "phyclk_usbhost20_phy_phyclock", + "phyclk_usbhost20_phy_freeclk", + "phyclk_usbhost20_phy_clk48mohci", + "phyclk_usbdrd30_udrd30_pipe_pclk", + "phyclk_usbdrd30_udrd30_phyclock", + "dout_aclk_fsys_200"; }; clock_aud: clock-controller@128c0000 { compatible = "samsung,exynos5260-clock-aud"; reg = <0x128C0000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_FOUT_AUD_PLL>, + <&ioclk_i2s>, + <&ioclk_pcm>; + clock-names = "fin_pll", + "fout_aud_pll", + "ioclk_i2s_cdclk", + "ioclk_pcm_extclk"; }; clock_isp: clock-controller@133c0000 { compatible = "samsung,exynos5260-clock-isp"; reg = <0x133C0000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_ISP1_266>, + <&clock_top TOP_DOUT_ACLK_ISP1_400>, + <&clock_top TOP_MOUT_ACLK_ISP1_266>; + clock-names = "fin_pll", + "dout_aclk_isp1_266", + "dout_aclk_isp1_400", + "mout_aclk_isp1_266"; }; clock_gscl: clock-controller@13f00000 { compatible = "samsung,exynos5260-clock-gscl"; reg = <0x13F00000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_top TOP_DOUT_ACLK_GSCL_400>, + <&clock_top TOP_DOUT_ACLK_GSCL_333>; + clock-names = "fin_pll", + "dout_aclk_gscl_400", + "dout_aclk_gscl_333"; }; clock_disp: clock-controller@14550000 { compatible = "samsung,exynos5260-clock-disp"; reg = <0x14550000 0x10000>; #clock-cells = <1>; + clocks = <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&fin_pll>, + <&ioclk_spdif>, + <&clock_top TOP_DOUT_ACLK_PERI_AUD>, + <&clock_top TOP_DOUT_ACLK_DISP_222>, + <&clock_top TOP_DOUT_SCLK_DISP_PIXEL>, + <&clock_top TOP_DOUT_ACLK_DISP_333>; + clock-names = "fin_pll", + "phyclk_dptx_phy_ch3_txd_clk", + "phyclk_dptx_phy_ch2_txd_clk", + "phyclk_dptx_phy_ch1_txd_clk", + "phyclk_dptx_phy_ch0_txd_clk", + "phyclk_hdmi_phy_tmds_clko", + "phyclk_hdmi_phy_ref_clko", + "phyclk_hdmi_phy_pixel_clko", + "phyclk_hdmi_link_o_tmds_clkhi", + "phyclk_mipi_dphy_4l_m_txbyte_clkhs", + "phyclk_dptx_phy_o_ref_clk_24m", + "phyclk_dptx_phy_clk_div2", + "phyclk_mipi_dphy_4l_m_rxclkesc0", + "phyclk_hdmi_phy_ref_cko", + "ioclk_spdif_extclk", + "dout_aclk_peri_aud", + "dout_aclk_disp_222", + "dout_sclk_disp_pixel", + "dout_aclk_disp_333"; }; gic: interrupt-controller@10481000 { diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 884fef55836c..e54a3391854d 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -188,8 +188,7 @@ interrupt-parent = <&gpx0>; interrupts = <4 IRQ_TYPE_NONE>; pinctrl-names = "default"; - pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>, - <&pmic_dvs_3>; + pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>; wakeup-source; #clock-cells = <1>; @@ -394,10 +393,6 @@ regulator-always-on; }; - ldo16_reg: LDO16 { - regulator-name = "ldo16"; - }; - ldo17_reg: LDO17 { regulator-name = "cam_sensor_core"; regulator-min-microvolt = <1200000>; @@ -427,10 +422,6 @@ regulator-max-microvolt = <2850000>; }; - ldo22_reg: LDO22 { - regulator-name = "ldo22"; - }; - ldo23_reg: LDO23 { regulator-name = "dp_p3v3"; regulator-min-microvolt = <3300000>; @@ -477,10 +468,6 @@ regulator-always-on; }; - ldo31_reg: LDO31 { - regulator-name = "ldo31"; - }; - /* On revisions with ti,ina231 this is sensor VS */ ldo32_reg: LDO32 { regulator-name = "vs_power_meter"; @@ -548,14 +535,14 @@ }; &pinctrl_0 { - emmc_nrst_pin: emmc-nrst { + emmc_nrst_pin: emmc-nrst-pins { samsung,pins = "gpd1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_wp: sd2-wp { + sd2_wp: sd2-wp-pins { samsung,pins = "gpm5-0"; samsung,pin-function = ; /* Pin is floating so be sure to disable write-protect */ @@ -563,21 +550,14 @@ samsung,pin-drv = ; }; - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpx0-0"; + pmic_dvs_2: pmic-dvs-2-pins { + samsung,pins = "gpx0-0", "gpx0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpx0-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_1: pmic-dvs-1 { + pmic_dvs_1: pmic-dvs-1-pins { samsung,pins = "gpx0-2"; samsung,pin-function = ; samsung,pin-pud = ; @@ -585,7 +565,7 @@ samsung,pin-val = <1>; }; - max77802_irq: max77802-irq { + max77802_irq: max77802-irq-pins { samsung,pins = "gpx0-4"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index 9599ba8ba798..6c7814b4372e 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -9,7 +9,7 @@ #include &pinctrl_0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -17,7 +17,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -25,7 +25,7 @@ #interrupt-cells = <2>; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -33,7 +33,7 @@ #interrupt-cells = <2>; }; - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -41,7 +41,7 @@ #interrupt-cells = <2>; }; - gpb1: gpb1 { + gpb1: gpb1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -49,7 +49,7 @@ #interrupt-cells = <2>; }; - gpb2: gpb2 { + gpb2: gpb2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -57,7 +57,7 @@ #interrupt-cells = <2>; }; - gpb3: gpb3 { + gpb3: gpb3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -65,7 +65,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -73,7 +73,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -81,7 +81,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -89,7 +89,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -97,12 +97,12 @@ #interrupt-cells = <2>; }; - gpm5: gpm5 { + gpm5: gpm5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -110,7 +110,7 @@ #interrupt-cells = <2>; }; - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -118,7 +118,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -126,7 +126,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -134,7 +134,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -142,7 +142,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -150,7 +150,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -158,7 +158,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -166,7 +166,7 @@ #interrupt-cells = <2>; }; - gph0: gph0 { + gph0: gph0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -174,7 +174,7 @@ #interrupt-cells = <2>; }; - gph1: gph1 { + gph1: gph1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -182,52 +182,52 @@ #interrupt-cells = <2>; }; - gpm7: gpm7 { + gpm7: gpm7-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy0: gpy0 { + gpy0: gpy0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy1: gpy1 { + gpy1: gpy1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy2: gpy2 { + gpy2: gpy2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy3: gpy3 { + gpy3: gpy3-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy4: gpy4 { + gpy4: gpy4-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy5: gpy5 { + gpy5: gpy5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy6: gpy6 { + gpy6: gpy6-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy7: gpy7 { + gpy7: gpy7-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -244,7 +244,7 @@ <27 1>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -261,7 +261,7 @@ <31 1>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -269,7 +269,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -277,210 +277,210 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c4_hs_bus: i2c4-hs-bus { + i2c4_hs_bus: i2c4-hs-bus-pins { samsung,pins = "gpa2-0", "gpa2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c5_hs_bus: i2c5-hs-bus { + i2c5_hs_bus: i2c5-hs-bus-pins { samsung,pins = "gpa2-2", "gpa2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c6_hs_bus: i2c6-hs-bus { + i2c6_hs_bus: i2c6-hs-bus-pins { samsung,pins = "gpb1-3", "gpb1-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpb2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpb2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpb2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpb2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c7_hs_bus: i2c7-hs-bus { + i2c7_hs_bus: i2c7-hs-bus-pins { samsung,pins = "gpb2-2", "gpb2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpc0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpc0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpc0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpc0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpc2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpc2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -489,7 +489,7 @@ }; &pinctrl_1 { - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -497,7 +497,7 @@ #interrupt-cells = <2>; }; - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -505,7 +505,7 @@ #interrupt-cells = <2>; }; - gpj2: gpj2 { + gpj2: gpj2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -513,7 +513,7 @@ #interrupt-cells = <2>; }; - gpj3: gpj3 { + gpj3: gpj3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -521,7 +521,7 @@ #interrupt-cells = <2>; }; - gpj4: gpj4 { + gpj4: gpj4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -529,7 +529,7 @@ #interrupt-cells = <2>; }; - gpk0: gpk0 { + gpk0: gpk0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -537,7 +537,7 @@ #interrupt-cells = <2>; }; - gpk1: gpk1 { + gpk1: gpk1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -545,7 +545,7 @@ #interrupt-cells = <2>; }; - gpk2: gpk2 { + gpk2: gpk2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -553,7 +553,7 @@ #interrupt-cells = <2>; }; - gpk3: gpk3 { + gpk3: gpk3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -561,28 +561,28 @@ #interrupt-cells = <2>; }; - usb3_1_oc: usb3-1-oc { + usb3_1_oc: usb3-1-oc-pins { samsung,pins = "gpk2-4", "gpk2-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb3_1_vbusctrl: usb3-1-vbusctrl { + usb3_1_vbusctrl: usb3-1-vbusctrl-pins { samsung,pins = "gpk2-6", "gpk2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb3_0_oc: usb3-0-oc { + usb3_0_oc: usb3-0-oc-pins { samsung,pins = "gpk3-0", "gpk3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb3_0_vbusctrl: usb3-0-vbusctrl { + usb3_0_vbusctrl: usb3-0-vbusctrl-pins { samsung,pins = "gpk3-2", "gpk3-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -591,7 +591,7 @@ }; &pinctrl_2 { - gpv0: gpv0 { + gpv0: gpv0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -599,7 +599,7 @@ #interrupt-cells = <2>; }; - gpv1: gpv1 { + gpv1: gpv1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -607,7 +607,7 @@ #interrupt-cells = <2>; }; - gpv2: gpv2 { + gpv2: gpv2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -615,7 +615,7 @@ #interrupt-cells = <2>; }; - gpv3: gpv3 { + gpv3: gpv3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -623,7 +623,7 @@ #interrupt-cells = <2>; }; - gpv4: gpv4 { + gpv4: gpv4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -633,7 +633,7 @@ }; &pinctrl_3 { - gpz: gpz { + gpz: gpz-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -641,7 +641,7 @@ #interrupt-cells = <2>; }; - audi2s0_bus: audi2s0-bus { + audi2s0_bus: audi2s0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4"; samsung,pin-function = <2>; diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 2a3ade77a2de..b8f953c41c73 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -41,6 +41,19 @@ reg = <0x02037000 0x1000>; }; + vdd10_usb3: voltage-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VDD10_USB3"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vdd33_usb3: voltage-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VDD33_USB3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &mmc_0 { @@ -66,14 +79,14 @@ }; &pinctrl_0 { - srom_ctl: srom-ctl { + srom_ctl: srom-ctl-pins { samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5", "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; samsung,pin-function = ; samsung,pin-drv = ; }; - srom_ebi: srom-ebi { + srom_ebi: srom-ebi-pins { samsung,pins = "gpy3-0", "gpy3-1", "gpy3-2", "gpy3-3", "gpy3-4", "gpy3-5", "gpy3-6", "gpy3-7", "gpy5-0", "gpy5-1", "gpy5-2", "gpy5-3", @@ -121,3 +134,13 @@ &serial_2 { status = "okay"; }; + +&usbdrd3_0 { + vdd10-supply = <&vdd10_usb3>; + vdd33-supply = <&vdd33_usb3>; +}; + +&usbdrd3_1 { + vdd10-supply = <&vdd10_usb3>; + vdd33-supply = <&vdd33_usb3>; +}; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 584ce62361b1..4d797a9abba4 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -189,7 +189,7 @@ interrupts = ; }; - pdma0: pdma@121a0000 { + pdma0: dma-controller@121a0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121a0000 0x1000>; interrupts = ; @@ -200,7 +200,7 @@ #dma-requests = <32>; }; - pdma1: pdma@121b0000 { + pdma1: dma-controller@121b0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121b0000 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index dfc7f14f5772..946b791faf85 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -808,7 +808,7 @@ }; &pinctrl_0 { - s2mps11_irq: s2mps11-irq { + s2mps11_irq: s2mps11-irq-pins { samsung,pins = "gpx3-2"; samsung,pin-function = ; samsung,pin-pud = ; @@ -825,3 +825,13 @@ &usbdrd_dwc3_1 { dr_mode = "host"; }; + +&usbdrd3_0 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5420-chagall-wifi.dts b/arch/arm/boot/dts/exynos5420-chagall-wifi.dts new file mode 100644 index 000000000000..1319344a2c74 --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-chagall-wifi.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5420 Chagall WiFi board device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Henrik Grimler + */ + +/dts-v1/; +#include "exynos5420-galaxy-tab-common.dtsi" + +/ { + model = "Samsung Chagall WiFi based on Exynos5420"; + compatible = "samsung,chagall-wifi", "samsung,exynos5420", \ + "samsung,exynos5"; +}; + +&ldo15_reg { + /* Unused */ + regulator-name = "VDD_LDO15"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&ldo17_reg { + regulator-name = "VDD_IRLED_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3350000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo28_reg { + /* Unused */ + regulator-name = "VDD_LDO28"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&ldo29_reg { + regulator-name = "VDD_TCON_1V8"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo31_reg { + regulator-name = "VDD_GRIP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo32_reg { + regulator-name = "VDD_TSP_1V8"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; diff --git a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi new file mode 100644 index 000000000000..d19bc3d266fa --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi @@ -0,0 +1,691 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Base DT for Samsung's family of tablets based on Exynos5420. + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Henrik Grimler + */ + +/dts-v1/; +#include "exynos5420.dtsi" +#include "exynos5420-cpus.dtsi" +#include +#include +#include + +/ { + chassis-type = "tablet"; + + /* + * To successfully boot the mainline kernel with the stock + * bootloader (SBOOT), the tlb needs to be flushed after the + * page table pointer has been updated in __common_mmu_cache_on. + * The same hack is also needed to boot exynos4412-i9300 with + * stock bootloader, and probably other Samsung devices of + * similar age. See + * https://lore.kernel.org/all/1355276466-18295-1-git-send-email-arve@android.com + * for more details. + */ + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0xc0000000>; + }; + + firmware@2073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + + key-power { + debounce-interval = <10>; + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; + label = "Power"; + linux,code = ; + wakeup-source; + }; + + key-home { + debounce-interval = <10>; + gpios = <&gpx0 5 GPIO_ACTIVE_LOW>; + label = "Home"; + linux,code = ; + wakeup-source; + }; + + key-volume-up { + debounce-interval = <10>; + gpios = <&gpx0 2 GPIO_ACTIVE_LOW>; + label = "Volume Up"; + linux,code = ; + }; + + key-volume-down { + debounce-interval = <10>; + gpios = <&gpx0 3 GPIO_ACTIVE_LOW>; + label = "Volume Down"; + linux,code = ; + }; + }; +}; + +&cci { + /* CCI is disabled in hardware */ + status = "disabled"; +}; + +&cpu0 { + cpu-supply = <&buck2_reg>; +}; + +&cpu4 { + cpu-supply = <&buck6_reg>; +}; + +&gpu { + status = "okay"; + mali-supply = <&buck4_reg>; +}; + +&hsi2c_7 { + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + + s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", "s2mps11_cp", + "s2mps11_bt"; + }; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF_1V1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D_1V0"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_MEM_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + buck6_reg: BUCK6 { + regulator-name = "VDD_KFC_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck7_reg: BUCK7 { + regulator-name = "VIN_LLDO_1V4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "VIN_MLDO_2V0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "VIN_HLDO_3V5"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "VDD_CAM_ISP_1V0"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3550000>; + }; + + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_APIO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDD_APIO_MMC01_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_ADC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + /* Unused */ + regulator-name = "VDD_LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD_MIPI_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_MIPI_PLL_ABB1_18V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + /* Unused */ + regulator-name = "VDD_LDO8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD_UOTG_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDDQ_PRE_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_HSIC_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD_HSIC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDD_APIO_MMC2_2V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD_MOTOR_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD_LDO15"; + /* + * LDO15 varies between devices and is + * specified in the device dts + */ + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD_AP_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "VDD_LDO17"; + /* + * LDO17 varies between devices and is + * specified in the device dts + */ + }; + + ldo18_reg: LDO18 { + /* Unused */ + regulator-name = "VDD_LDO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "VDD_VTF_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo20_reg: LDO20 { + regulator-name = "VDD_CAM1_CAM_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD_CAM_IO_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo22_reg: LDO22 { + regulator-name = "VDD_CAM0_S_CORE_1V1"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo23_reg: LDO23 { + regulator-name = "VDD_MIFS_1V1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo24_reg: LDO24 { + regulator-name = "VDD_TSP_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + /* Unused */ + regulator-name = "VDD_LDO25"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "VDD_CAM0_AF_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo27_reg: LDO27 { + regulator-name = "VDD_G3DS_1V0"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo28_reg: LDO28 { + regulator-name = "VDD_LDO28"; + /* + * LDO28 varies between devices and is + * specified in the device dts + */ + }; + + ldo29_reg: LDO29 { + regulator-name = "VDD_LDO29"; + /* + * LDO29 varies between devices and is + * specified in the device dts + */ + }; + + ldo30_reg: LDO30 { + regulator-name = "VDD_TOUCH_1V8"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo31_reg: LDO31 { + regulator-name = "VDD_LDO31"; + /* + * LDO31 varies between devices and is + * specified in the device dts + */ + }; + + ldo32_reg: LDO32 { + regulator-name = "VDD_LDO32"; + /* + * LDO32 varies between devices and is + * specified in the device dts + */ + }; + + ldo33_reg: LDO33 { + regulator-name = "VDD_MHL_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo34_reg: LDO34 { + regulator-name = "VDD_MHL_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo35_reg: LDO35 { + regulator-name = "VDD_SIL_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo36_reg: LDO36 { + /* Unused */ + regulator-name = "VDD_LDO36"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo37_reg: LDO37 { + /* Unused */ + regulator-name = "VDD_LDO37"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo38_reg: LDO38 { + regulator-name = "VDD_KEY_LED_3V3"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&mixer { + status = "okay"; +}; + +/* Internal storage */ +&mmc_0 { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + card-detect-delay = <200>; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-names = "default"; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-sdr-timing = <0 4>; + vqmmc-supply = <&ldo3_reg>; +}; + +/* External sdcard */ +&mmc_2 { + status = "okay"; + bus-width = <4>; + cap-sd-highspeed; + card-detect-delay = <200>; + cd-gpios = <&gpx2 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sd2_clk &sd2_cmd &mmc2_cd &sd2_bus1 &sd2_bus4>; + pinctrl-names = "default"; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-sdr-timing = <0 4>; + sd-uhs-sdr50; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>; +}; + +&pinctrl_0 { + mmc2_cd: mmc2-cd-pins { + samsung,pins = "gpx2-4"; + samsung,pin-pud = ; + }; + + s2mps11_irq: s2mps11-irq-pins { + samsung,pins = "gpx3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "peripheral"; +}; + +&usbdrd3_0 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; diff --git a/arch/arm/boot/dts/exynos5420-klimt-wifi.dts b/arch/arm/boot/dts/exynos5420-klimt-wifi.dts new file mode 100644 index 000000000000..011787b1bbf0 --- /dev/null +++ b/arch/arm/boot/dts/exynos5420-klimt-wifi.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos5420 Klimt WiFi board device tree source + * + * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Henrik Grimler + */ + +/dts-v1/; +#include "exynos5420-galaxy-tab-common.dtsi" + +/ { + model = "Samsung Klimt WiFi based on Exynos5420"; + compatible = "samsung,klimt-wifi", "samsung,exynos5420", \ + "samsung,exynos5"; +}; + +&ldo15_reg { + /* Unused */ + regulator-name = "VDD_LDO15"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&ldo17_reg { + regulator-name = "VDD_VCI_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo28_reg { + regulator-name = "VDD3_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo29_reg { + regulator-name = "VDDR_1V6"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1600000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&ldo31_reg { + /* Unused */ + regulator-name = "VDD_LDO31"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&ldo32_reg { + regulator-name = "VDD_TSP_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&mmc_2 { + sd-uhs-sdr104; +}; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index e76fb104db19..d6434ec86022 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -212,7 +212,7 @@ interrupts = <1 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; + <&pmic_dvs_1>, <&pmic_dvs_2>; wakeup-source; reg = <0x9>; #clock-cells = <1>; @@ -774,14 +774,14 @@ pinctrl-names = "default"; pinctrl-0 = <&mask_tpm_reset>; - wifi_en: wifi-en { + wifi_en: wifi-en-pins { samsung,pins = "gpx0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - max98090_irq: max98090-irq { + max98090_irq: max98090-irq-pins { samsung,pins = "gpx0-2"; samsung,pin-function = ; samsung,pin-pud = ; @@ -789,7 +789,7 @@ }; /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset { + mask_tpm_reset: mask-tpm-reset-pins { samsung,pins = "gpx0-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -797,70 +797,70 @@ samsung,pin-val = <0>; }; - tpm_irq: tpm-irq { + tpm_irq: tpm-irq-pins { samsung,pins = "gpx1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - trackpad_irq: trackpad-irq { + trackpad_irq: trackpad-irq-pins { samsung,pins = "gpx1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - power_key_irq: power-key-irq { + power_key_irq: power-key-irq-pins { samsung,pins = "gpx1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - ec_irq: ec-irq { + ec_irq: ec-irq-pins { samsung,pins = "gpx1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - tps65090_irq: tps65090-irq { + tps65090_irq: tps65090-irq-pins { samsung,pins = "gpx2-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - dp_hpd_gpio: dp_hpd_gpio { + dp_hpd_gpio: dp-hpd-gpio-pins { samsung,pins = "gpx2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - max77802_irq: max77802-irq { + max77802_irq: max77802-irq-pins { samsung,pins = "gpx3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lid_irq: lid-irq { + lid_irq: lid-irq-pins { samsung,pins = "gpx3-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pmic_dvs_1: pmic-dvs-1 { + pmic_dvs_1: pmic-dvs-1-pins { samsung,pins = "gpy7-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -868,74 +868,67 @@ }; }; -&pinctrl_1 { - /* Adjust WiFi drive strengths lower for EMI */ - sd1_clk: sd1-clk { - samsung,pin-drv = ; - }; +/* pinctrl_1 */ +/* Adjust WiFi drive strengths lower for EMI */ +&sd1_bus1 { + samsung,pin-drv = ; +}; - sd1_cmd: sd1-cmd { - samsung,pin-drv = ; - }; +&sd1_bus4 { + samsung,pin-drv = ; +}; - sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = ; - }; +&sd1_bus8 { + samsung,pin-drv = ; +}; - sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = ; - }; +&sd1_clk { + samsung,pin-drv = ; +}; - sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = ; - }; +&sd1_cmd { + samsung,pin-drv = ; }; &pinctrl_2 { - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpj4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpj4-3"; + pmic_dvs_2: pmic-dvs-2-pins { + samsung,pins = "gpj4-2", "gpj4-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; }; -&pinctrl_3 { - /* Drive SPI lines at x2 for better integrity */ - spi2-bus { - samsung,pin-drv = ; - }; +/* pinctrl_3*/ +/* Drive SPI lines at x2 for better integrity */ +&spi2_bus { + samsung,pin-drv = ; +}; +&pinctrl_3 { /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs { + ec_spi_cs: ec-spi-cs-pins { samsung,pins = "gpb1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb300_vbus_en: usb300-vbus-en { + usb300_vbus_en: usb300-vbus-en-pins { samsung,pins = "gph0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb301_vbus_en: usb301-vbus-en { + usb301_vbus_en: usb301-vbus-en-pins { samsung,pins = "gph0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pmic_selb: pmic-selb { + pmic_selb: pmic-selb-pins { samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", "gph0-6"; samsung,pin-function = ; @@ -1090,6 +1083,16 @@ vtmu-supply = <&ldo10_reg>; }; +&usbdrd3_0 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index b82af7c89654..546ba274f4e5 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -12,7 +12,7 @@ #include &pinctrl_0 { - gpy7: gpy7 { + gpy7: gpy7-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -20,7 +20,7 @@ #interrupt-cells = <2>; }; - gpx0: gpx0 { + gpx0: gpx0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -31,7 +31,7 @@ <26 0>, <26 1>, <27 0>, <27 1>; }; - gpx1: gpx1 { + gpx1: gpx1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -42,7 +42,7 @@ <30 0>, <30 1>, <31 0>, <31 1>; }; - gpx2: gpx2 { + gpx2: gpx2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -50,7 +50,7 @@ #interrupt-cells = <2>; }; - gpx3: gpx3 { + gpx3: gpx3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -58,14 +58,14 @@ #interrupt-cells = <2>; }; - dp_hpd: dp_hpd { + dp_hpd: dp-hpd-pins { samsung,pins = "gpx0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hdmi_cec: hdmi-cec { + hdmi_cec: hdmi-cec-pins { samsung,pins = "gpx3-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -74,7 +74,7 @@ }; &pinctrl_1 { - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -82,7 +82,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -90,7 +90,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -98,7 +98,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -106,7 +106,7 @@ #interrupt-cells = <2>; }; - gpc4: gpc4 { + gpc4: gpc4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -114,7 +114,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -122,175 +122,175 @@ #interrupt-cells = <2>; }; - gpy0: gpy0 { + gpy0: gpy0-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy1: gpy1 { + gpy1: gpy1-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy2: gpy2 { + gpy2: gpy2-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy3: gpy3 { + gpy3: gpy3-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy4: gpy4 { + gpy4: gpy4-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy5: gpy5 { + gpy5: gpy5-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpy6: gpy6 { + gpy6: gpy6-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpc0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpc0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpc0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpc0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_rclk: sd0-rclk { + sd0_rclk: sd0-rclk-pins { samsung,pins = "gpc0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpc1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpc1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpc1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_int: sd1-int { + sd1_int: sd1-int-pins { samsung,pins = "gpd1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpc1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus8: sd1-bus-width8 { + sd1_bus8: sd1-bus-width8-pins { samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpc2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpc2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_wp: sd2-wp { + sd2_wp: sd2-wp-pins { samsung,pins = "gpc4-0"; samsung,pin-function = ; samsung,pin-pud = ; @@ -299,7 +299,7 @@ }; &pinctrl_2 { - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -307,7 +307,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -315,7 +315,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -323,7 +323,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -331,7 +331,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -339,7 +339,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -347,7 +347,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -355,7 +355,7 @@ #interrupt-cells = <2>; }; - gpj4: gpj4 { + gpj4: gpj4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -363,7 +363,7 @@ #interrupt-cells = <2>; }; - cam_gpio_a: cam-gpio-a { + cam_gpio_a: cam-gpio-a-pins { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; @@ -372,7 +372,7 @@ samsung,pin-drv = ; }; - cam_gpio_b: cam-gpio-b { + cam_gpio_b: cam-gpio-b-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = ; @@ -380,42 +380,42 @@ samsung,pin-drv = ; }; - cam_i2c2_bus: cam-i2c2-bus { + cam_i2c2_bus: cam-i2c2-bus-pins { samsung,pins = "gpf0-4", "gpf0-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_spi1_bus: cam-spi1-bus { + cam_spi1_bus: cam-spi1-bus-pins { samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_i2c1_bus: cam-i2c1-bus { + cam_i2c1_bus: cam-i2c1-bus-pins { samsung,pins = "gpf0-2", "gpf0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_i2c0_bus: cam-i2c0-bus { + cam_i2c0_bus: cam-i2c0-bus-pins { samsung,pins = "gpf0-0", "gpf0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_spi0_bus: cam-spi0-bus { + cam_spi0_bus: cam-spi0-bus-pins { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_bayrgb_bus: cam-bayrgb-bus { + cam_bayrgb_bus: cam-bayrgb-bus-pins { samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7", "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", @@ -428,7 +428,7 @@ }; &pinctrl_3 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -436,7 +436,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -444,7 +444,7 @@ #interrupt-cells = <2>; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -452,7 +452,7 @@ #interrupt-cells = <2>; }; - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -460,7 +460,7 @@ #interrupt-cells = <2>; }; - gpb1: gpb1 { + gpb1: gpb1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -468,7 +468,7 @@ #interrupt-cells = <2>; }; - gpb2: gpb2 { + gpb2: gpb2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -476,7 +476,7 @@ #interrupt-cells = <2>; }; - gpb3: gpb3 { + gpb3: gpb3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -484,7 +484,7 @@ #interrupt-cells = <2>; }; - gpb4: gpb4 { + gpb4: gpb4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -492,7 +492,7 @@ #interrupt-cells = <2>; }; - gph0: gph0 { + gph0: gph0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -500,98 +500,98 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c3_bus: i2c3-bus { + i2c3_bus: i2c3-bus-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c4_hs_bus: i2c4-hs-bus { + i2c4_hs_bus: i2c4-hs-bus-pins { samsung,pins = "gpa2-0", "gpa2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c5_hs_bus: i2c5-hs-bus { + i2c5_hs_bus: i2c5-hs-bus-pins { samsung,pins = "gpa2-2", "gpa2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = ; @@ -599,7 +599,7 @@ samsung,pin-drv = ; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = ; @@ -607,7 +607,7 @@ samsung,pin-drv = ; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; samsung,pin-function = ; @@ -615,7 +615,7 @@ samsung,pin-drv = ; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; samsung,pin-function = ; @@ -623,91 +623,91 @@ samsung,pin-drv = ; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpb1-0", "gpb1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c6_hs_bus: i2c6-hs-bus { + i2c6_hs_bus: i2c6-hs-bus-pins { samsung,pins = "gpb1-3", "gpb1-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpb2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpb2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpb2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpb2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c7_hs_bus: i2c7-hs-bus { + i2c7_hs_bus: i2c7-hs-bus-pins { samsung,pins = "gpb2-2", "gpb2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c8_hs_bus: i2c8-hs-bus { + i2c8_hs_bus: i2c8-hs-bus-pins { samsung,pins = "gpb3-4", "gpb3-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c9_hs_bus: i2c9-hs-bus { + i2c9_hs_bus: i2c9-hs-bus-pins { samsung,pins = "gpb3-6", "gpb3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c10_hs_bus: i2c10-hs-bus { + i2c10_hs_bus: i2c10-hs-bus-pins { samsung,pins = "gpb4-0", "gpb4-1"; samsung,pin-function = ; samsung,pin-pud = ; @@ -716,7 +716,7 @@ }; &pinctrl_4 { - gpz: gpz { + gpz: gpz-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -724,7 +724,7 @@ #interrupt-cells = <2>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; samsung,pin-function = ; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index a4f0e3ffedbd..4d7b6d9008a7 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -124,6 +124,9 @@ hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; + vdd-supply = <&ldo6_reg>; + vdd_osc-supply = <&ldo7_reg>; + vdd_pll-supply = <&ldo6_reg>; }; &hsi2c_4 { @@ -377,7 +380,7 @@ }; &pinctrl_0 { - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = ; samsung,pin-pud = ; @@ -386,14 +389,14 @@ }; &pinctrl_2 { - usb300_vbus_en: usb300-vbus-en { + usb300_vbus_en: usb300-vbus-en-pins { samsung,pins = "gpg0-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb301_vbus_en: usb301-vbus-en { + usb301_vbus_en: usb301-vbus-en-pins { samsung,pins = "gpg1-4"; samsung,pin-function = ; samsung,pin-pud = ; @@ -407,6 +410,16 @@ clock-names = "rtc", "rtc_src"; }; +&usbdrd3_0 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo11_reg>; + vdd33-supply = <&ldo9_reg>; +}; + &usbdrd_phy0 { vbus-supply = <&usb300_vbus_reg>; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index e23e8ffb093f..21b608705049 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -302,8 +302,8 @@ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; clock-names = "ppmu"; events { - ppmu_event3_dmc0_0: ppmu-event3-dmc0_0 { - event-name = "ppmu-event3-dmc0_0"; + ppmu_event3_dmc0_0: ppmu-event3-dmc0-0 { + event-name = "ppmu-event3-dmc0-0"; }; }; }; @@ -314,8 +314,8 @@ clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; clock-names = "ppmu"; events { - ppmu_event3_dmc0_1: ppmu-event3-dmc0_1 { - event-name = "ppmu-event3-dmc0_1"; + ppmu_event3_dmc0_1: ppmu-event3-dmc0-1 { + event-name = "ppmu-event3-dmc0-1"; }; }; }; @@ -326,8 +326,8 @@ clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; clock-names = "ppmu"; events { - ppmu_event3_dmc1_0: ppmu-event3-dmc1_0 { - event-name = "ppmu-event3-dmc1_0"; + ppmu_event3_dmc1_0: ppmu-event3-dmc1-0 { + event-name = "ppmu-event3-dmc1-0"; }; }; }; @@ -338,8 +338,8 @@ clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; clock-names = "ppmu"; events { - ppmu_event3_dmc1_1: ppmu-event3-dmc1_1 { - event-name = "ppmu-event3-dmc1_1"; + ppmu_event3_dmc1_1: ppmu-event3-dmc1-1 { + event-name = "ppmu-event3-dmc1-1"; }; }; }; @@ -430,7 +430,7 @@ power-domains = <&mau_pd>; }; - adma: adma@3880000 { + adma: dma-controller@3880000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x03880000 0x1000>; interrupts = ; @@ -442,7 +442,7 @@ power-domains = <&mau_pd>; }; - pdma0: pdma@121a0000 { + pdma0: dma-controller@121a0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121A0000 0x1000>; interrupts = ; @@ -453,7 +453,7 @@ #dma-requests = <32>; }; - pdma1: pdma@121b0000 { + pdma1: dma-controller@121b0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x121B0000 0x1000>; interrupts = ; @@ -464,7 +464,7 @@ #dma-requests = <32>; }; - mdma0: mdma@10800000 { + mdma0: dma-controller@10800000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10800000 0x1000>; interrupts = ; @@ -475,7 +475,7 @@ #dma-requests = <1>; }; - mdma1: mdma@11c10000 { + mdma1: dma-controller@11c10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11C10000 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index e7958dbecfd2..2f65dcf6ba73 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -358,7 +358,7 @@ tCKESR-min-tck = <2>; tMRD-min-tck = <5>; - timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { + timings_samsung_K3QF2F20DB_800mhz: timings@800000000 { compatible = "jedec,lpddr3-timings"; /* workaround: 'reg' shows max-freq */ reg = <800000000>; @@ -999,7 +999,7 @@ }; &pinctrl_0 { - s2mps11_irq: s2mps11-irq { + s2mps11_irq: s2mps11-irq-pins { samsung,pins = "gpx0-4"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index e35af40a55cb..a6961ff24030 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -480,14 +480,14 @@ }; &pinctrl_0 { - power_key: power-key { + power_key: power-key-pins { samsung,pins = "gpx0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = ; samsung,pin-pud = ; @@ -496,7 +496,7 @@ }; &pinctrl_1 { - emmc_nrst_pin: emmc-nrst { + emmc_nrst_pin: emmc-nrst-pins { samsung,pins = "gpd1-0"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 77013ee586f8..4ee76281979c 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -221,7 +221,7 @@ interrupts = <1 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&max77802_irq>, <&pmic_selb>, - <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; + <&pmic_dvs_1>, <&pmic_dvs_2>; wakeup-source; reg = <0x9>; #clock-cells = <1>; @@ -756,14 +756,14 @@ pinctrl-names = "default"; pinctrl-0 = <&mask_tpm_reset>; - wifi_en: wifi-en { + wifi_en: wifi-en-pins { samsung,pins = "gpx0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - max98091_irq: max98091-irq { + max98091_irq: max98091-irq-pins { samsung,pins = "gpx0-2"; samsung,pin-function = ; samsung,pin-pud = ; @@ -771,7 +771,7 @@ }; /* We need GPX0_6 to be low at sleep time; just keep it low always */ - mask_tpm_reset: mask-tpm-reset { + mask_tpm_reset: mask-tpm-reset-pins { samsung,pins = "gpx0-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -779,70 +779,70 @@ samsung,pin-val = <0>; }; - tpm_irq: tpm-irq { + tpm_irq: tpm-irq-pins { samsung,pins = "gpx1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - trackpad_irq: trackpad-irq { + trackpad_irq: trackpad-irq-pins { samsung,pins = "gpx1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - power_key_irq: power-key-irq { + power_key_irq: power-key-irq-pins { samsung,pins = "gpx1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - ec_irq: ec-irq { + ec_irq: ec-irq-pins { samsung,pins = "gpx1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - tps65090_irq: tps65090-irq { + tps65090_irq: tps65090-irq-pins { samsung,pins = "gpx2-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - dp_hpd_gpio: dp_hpd_gpio { + dp_hpd_gpio: dp-hpd-gpio-pins { samsung,pins = "gpx2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - max77802_irq: max77802-irq { + max77802_irq: max77802-irq-pins { samsung,pins = "gpx3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lid_irq: lid-irq { + lid_irq: lid-irq-pins { samsung,pins = "gpx3-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hdmi_hpd_irq: hdmi-hpd-irq { + hdmi_hpd_irq: hdmi-hpd-irq-pins { samsung,pins = "gpx3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pmic_dvs_1: pmic-dvs-1 { + pmic_dvs_1: pmic-dvs-1-pins { samsung,pins = "gpy7-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -850,74 +850,67 @@ }; }; -&pinctrl_1 { - /* Adjust WiFi drive strengths lower for EMI */ - sd1_clk: sd1-clk { - samsung,pin-drv = ; - }; +/* pinctrl_1 */ +/* Adjust WiFi drive strengths lower for EMI */ +&sd1_bus1 { + samsung,pin-drv = ; +}; - sd1_cmd: sd1-cmd { - samsung,pin-drv = ; - }; +&sd1_bus4 { + samsung,pin-drv = ; +}; - sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = ; - }; +&sd1_bus8 { + samsung,pin-drv = ; +}; - sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = ; - }; +&sd1_clk { + samsung,pin-drv = ; +}; - sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = ; - }; +&sd1_cmd { + samsung,pin-drv = ; }; &pinctrl_2 { - pmic_dvs_2: pmic-dvs-2 { - samsung,pins = "gpj4-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - pmic_dvs_3: pmic-dvs-3 { - samsung,pins = "gpj4-3"; + pmic_dvs_2: pmic-dvs-2-pins { + samsung,pins = "gpj4-2", "gpj4-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; }; -&pinctrl_3 { - /* Drive SPI lines at x2 for better integrity */ - spi2-bus { - samsung,pin-drv = ; - }; +/* pinctrl_3*/ +/* Drive SPI lines at x2 for better integrity */ +&spi2_bus { + samsung,pin-drv = ; +}; +&pinctrl_3 { /* Drive SPI chip select at x2 for better integrity */ - ec_spi_cs: ec-spi-cs { + ec_spi_cs: ec-spi-cs-pins { samsung,pins = "gpb1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb300_vbus_en: usb300-vbus-en { + usb300_vbus_en: usb300-vbus-en-pins { samsung,pins = "gph0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb301_vbus_en: usb301-vbus-en { + usb301_vbus_en: usb301-vbus-en-pins { samsung,pins = "gph0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pmic_selb: pmic-selb { + pmic_selb: pmic-selb-pins { samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", "gph0-6"; samsung,pin-function = ; @@ -1072,6 +1065,16 @@ vtmu-supply = <&ldo10_reg>; }; +&usbdrd3_0 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + +&usbdrd3_1 { + vdd10-supply = <&ldo15_reg>; + vdd33-supply = <&ldo12_reg>; +}; + &usbdrd_dwc3_0 { dr_mode = "host"; }; diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 9e5651c7ea6b..6d7b044fec5b 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -338,7 +338,7 @@ }; ds1339: rtc@68 { - compatible = "mxim,ds1339"; + compatible = "dallas,ds1339"; reg = <0x68>; trickle-resistor-ohms = <250>; trickle-diode-disable; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 84d0176d5193..130b4145af82 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -110,6 +110,8 @@ interrupt-names = "bch"; clocks = <&clks 50>; clock-names = "gpmi_io"; + assigned-clocks = <&clks 13>; + assigned-clock-parents = <&clks 10>; dmas = <&dma_apbh 4>; dma-names = "rx-tx"; status = "disabled"; diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts index 6ecb83e7f336..85654d6baf28 100644 --- a/arch/arm/boot/dts/imx51-ts4800.dts +++ b/arch/arm/boot/dts/imx51-ts4800.dts @@ -102,7 +102,7 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - rtc: m41t00@68 { + rtc: rtc@68 { compatible = "st,m41t00"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts index 4f88e96d81dd..d5c68d1ea707 100644 --- a/arch/arm/boot/dts/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/imx53-m53menlo.dts @@ -53,6 +53,31 @@ }; }; + lvds-decoder { + compatible = "ti,ds90cf364a", "lvds-decoder"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_decoder_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@1 { + reg = <1>; + + lvds_decoder_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + panel { compatible = "edt,etm0700g0dh6"; pinctrl-0 = <&pinctrl_display_gpio>; @@ -61,7 +86,7 @@ port { panel_in: endpoint { - remote-endpoint = <&lvds0_out>; + remote-endpoint = <&lvds_decoder_out>; }; }; }; @@ -450,7 +475,7 @@ reg = <2>; lvds0_out: endpoint { - remote-endpoint = <&panel_in>; + remote-endpoint = <&lvds_decoder_in>; }; }; }; diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 81c2726a328a..8712e9851465 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -241,7 +241,7 @@ clock-frequency = <400000>; status = "okay"; - rtc1: ds1339@68 { + rtc1: rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts index 60fe5f14666e..c4ce23d8ac9f 100644 --- a/arch/arm/boot/dts/imx6dl-plym2m.dts +++ b/arch/arm/boot/dts/imx6dl-plym2m.dts @@ -50,6 +50,11 @@ }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&vdiv_vaccu>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -101,6 +106,64 @@ regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + }; + + touch-thermal0 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp0>; + }; + + touch-thermal1 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp1>; + }; + }; + + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, + <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <64687>; + touchscreen-inverted-x; + touchscreen-inverted-y; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; + }; + + touch_temp0: touch-temperature-sensor0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 736 + 85000 474>; + }; + + touch_temp1: touch-temperature-sensor1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 7>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 826 + 85000 609>; + }; + + vdiv_vaccu: voltage-divider-vaccu { + compatible = "voltage-divider"; + io-channels = <&adc_ts 2>; + output-ohms = <2500>; + full-ohms = <64000>; + #io-channel-cells = <0>; + }; }; &can1 { @@ -129,26 +192,61 @@ pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - touchscreen@0 { - compatible = "ti,tsc2046"; + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; reg = <0>; pinctrl-0 = <&pinctrl_tsc2046>; pinctrl-names ="default"; - spi-max-frequency = <100000>; - interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; - pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; - touchscreen-inverted-x; - touchscreen-inverted-y; - touchscreen-max-pressure = <4095>; + #address-cells = <1>; + #size-cells = <0>; - ti,vref-delay-usecs = /bits/ 16 <100>; - ti,x-plate-ohms = /bits/ 16 <800>; - ti,y-plate-ohms = /bits/ 16 <300>; - ti,debounce-max = /bits/ 16 <3>; - ti,debounce-tol = /bits/ 16 <70>; - ti,debounce-rep = /bits/ 16 <3>; - wakeup-source; + channel@0 { + reg = <0>; + settling-time-us = <300>; + oversampling-ratio = <5>; + }; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@2 { + reg = <2>; + settling-time-us = <300>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + /* channel 6 is not connected */ + + channel@7 { + reg = <7>; + settling-time-us = <300>; + oversampling-ratio = <5>; + }; }; }; @@ -233,9 +331,10 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - temperature-sensor@70 { + tsens0: temperature-sensor@70 { compatible = "ti,tmp103"; reg = <0x70>; + #thermal-sensor-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-prtvt7.dts b/arch/arm/boot/dts/imx6dl-prtvt7.dts index 190d26642bc8..b86deebef7b7 100644 --- a/arch/arm/boot/dts/imx6dl-prtvt7.dts +++ b/arch/arm/boot/dts/imx6dl-prtvt7.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "imx6dl.dtsi" #include "imx6qdl-prti6q.dtsi" +#include #include #include #include @@ -28,6 +29,35 @@ power-supply = <®_bl_12v0>; }; + display { + compatible = "fsl,imx-parallel-display"; + pinctrl-0 = <&pinctrl_ipu1_disp>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&vdiv_vaccu>; + }; + keys { compatible = "gpio-keys"; autorepeat; @@ -135,6 +165,30 @@ }; }; + panel { + compatible = "innolux,g070y2-t02"; + backlight = <&backlight_lcd>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + connector { + compatible = "composite-video-connector"; + label = "Composite0"; + sdtv-standards = ; + + port { + comp0_out: endpoint { + remote-endpoint = <&tvp5150_comp0_in>; + }; + }; + }; + reg_bl_12v0: regulator-bl-12v0 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -146,6 +200,13 @@ enable-active-high; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_1v8: regulator-1v8 { compatible = "regulator-fixed"; regulator-name = "1v8"; @@ -179,6 +240,64 @@ frame-master; }; }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + }; + + touch-thermal0 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp0>; + }; + + touch-thermal1 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp1>; + }; + }; + + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, + <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <64687>; + touchscreen-inverted-x; + touchscreen-inverted-y; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; + }; + + touch_temp0: touch-temperature-sensor0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 736 + 85000 474>; + }; + + touch_temp1: touch-temperature-sensor1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 7>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 826 + 85000 609>; + }; + + vdiv_vaccu: voltage-divider-vaccu { + compatible = "voltage-divider"; + io-channels = <&adc_ts 2>; + output-ohms = <2500>; + full-ohms = <64000>; + #io-channel-cells = <0>; + }; }; &audmux { @@ -221,22 +340,41 @@ pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - touchscreen@0 { - compatible = "ti,tsc2046"; + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; reg = <0>; pinctrl-0 = <&pinctrl_tsc>; pinctrl-names ="default"; - spi-max-frequency = <100000>; - interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>; - pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; - touchscreen-max-pressure = <4095>; - ti,vref-delay-usecs = /bits/ 16 <100>; - ti,x-plate-ohms = /bits/ 16 <800>; - ti,y-plate-ohms = /bits/ 16 <300>; - ti,debounce-max = /bits/ 16 <3>; - ti,debounce-tol = /bits/ 16 <70>; - ti,debounce-rep = /bits/ 16 <3>; - wakeup-source; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; }; }; @@ -252,6 +390,31 @@ VDDIO-supply = <®_3v3>; VDDD-supply = <®_1v8>; }; + + video@5c { + compatible = "ti,tvp5150"; + reg = <0x5c>; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tvp5150_comp0_in: endpoint { + remote-endpoint = <&comp0_out>; + }; + }; + + /* Output port 2 is video output pad */ + port@2 { + reg = <2>; + + tvp5151_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + }; + }; + }; }; &i2c3 { @@ -260,6 +423,12 @@ reg = <0x51>; }; + tsens0: temperature-sensor@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + #thermal-sensor-cells = <0>; + }; + gpio_pca: gpio@74 { compatible = "nxp,pca9539"; reg = <0x74>; @@ -275,6 +444,14 @@ status = "okay"; }; +&ipu1_di0_disp0 { + remote-endpoint = <&display_in>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tvp5151_to_ipu1_csi0_mux>; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; diff --git a/arch/arm/boot/dts/imx6dl-victgo.dts b/arch/arm/boot/dts/imx6dl-victgo.dts index d37ba4ed847d..227c952543d4 100644 --- a/arch/arm/boot/dts/imx6dl-victgo.dts +++ b/arch/arm/boot/dts/imx6dl-victgo.dts @@ -66,6 +66,11 @@ }; }; + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&vdiv_vaccu>, <&vdiv_hitch_pos>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -181,6 +186,72 @@ frame-master; }; }; + + thermal-zones { + chassis-thermal { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&tsens0>; + }; + + touch-thermal0 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp0>; + }; + + touch-thermal1 { + polling-delay = <20000>; + polling-delay-passive = <0>; + thermal-sensors = <&touch_temp1>; + }; + }; + + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, + <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <64687>; + touchscreen-inverted-x; + touchscreen-inverted-y; + touchscreen-x-plate-ohms = <300>; + touchscreen-y-plate-ohms = <800>; + }; + + touch_temp0: touch-temperature-sensor0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 736 + 85000 474>; + }; + + touch_temp1: touch-temperature-sensor1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&adc_ts 7>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = < (-40000) 826 + 85000 609>; + }; + + vdiv_vaccu: voltage-divider-vaccu { + compatible = "voltage-divider"; + io-channels = <&adc_ts 2>; + output-ohms = <2500>; + full-ohms = <64000>; + #io-channel-cells = <0>; + }; + + vdiv_hitch_pos: voltage-divider-hitch-pos { + compatible = "voltage-divider"; + io-channels = <&adc_ts 6>; + output-ohms = <3300>; + full-ohms = <13300>; + #io-channel-cells = <0>; + }; }; &audmux { @@ -244,22 +315,41 @@ pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; - touchscreen@0 { - compatible = "ti,tsc2046"; + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; reg = <0>; - pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touchscreen>; - spi-max-frequency = <200000>; - interrupts-extended = <&gpio5 8 IRQ_TYPE_EDGE_FALLING>; - pendown-gpio = <&gpio5 8 GPIO_ACTIVE_LOW>; - touchscreen-size-x = <800>; - touchscreen-size-y = <480>; - touchscreen-inverted-y; - touchscreen-max-pressure = <4095>; - ti,vref-delay-usecs = /bits/ 16 <100>; - ti,x-plate-ohms = /bits/ 16 <800>; - ti,y-plate-ohms = /bits/ 16 <300>; - wakeup-source; + pinctrl-names ="default"; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; }; }; @@ -446,9 +536,10 @@ reg = <0x51>; }; - temperature-sensor@70 { + tsens0: temperature-sensor@70 { compatible = "ti,tmp103"; reg = <0x70>; + #thermal-sensor-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index 343364d3e4f7..8daef65d5bb3 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -159,7 +159,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - rtc: ds1307@68 { + rtc: rtc@68 { compatible = "dallas,ds1307"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi index dc89b554e694..fe72650295a5 100644 --- a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi @@ -4,7 +4,10 @@ * Copyright (C) 2018 Marek Vasut */ +#include +#include #include +#include / { chosen { diff --git a/arch/arm/boot/dts/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/imx6qdl-mba6.dtsi index daf76345b179..f4dca20669d6 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-mba6.dtsi @@ -17,6 +17,7 @@ mmc1 = &usdhc2; /delete-property/ mmc2; /delete-property/ mmc3; + rtc0 = &rtc0; }; chosen { @@ -39,18 +40,21 @@ label = "s6"; linux,code = ; gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + wakeup-source; }; button2 { label = "s7"; linux,code = ; gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + wakeup-source; }; button3 { label = "s8"; linux,code = ; gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + wakeup-source; }; }; @@ -82,6 +86,8 @@ reg_pcie: regulator-pcie { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regpcie>; regulator-name = "supply-pcie"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -392,7 +398,6 @@ pinctrl_hog: hoggrp { fsl,pins = < - /* LCD.CONTRAST -> Rev 0100 only, not used on Rev.0200*/ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0001b099 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x0001b099 @@ -433,8 +438,6 @@ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x001b0f0 /* #PCIE.WAKE */ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x001b0f0 /* #PCIE.RST */ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x001b0f0 /* #PCIE.DIS */ - /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ >; }; @@ -459,6 +462,13 @@ >; }; + pinctrl_regpcie: regpciegrp { + fsl,pins = < + /* HYS = 1, DSE = 110, PUE+PKE, SPEED = HIGH (11)*/ + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00130f0 /* PCIE.PWR_EN */ + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b099 diff --git a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi index a61f2705a340..df8fa169e9f6 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6a.dtsi +++ b/arch/arm/boot/dts/imx6qdl-mba6a.dtsi @@ -6,12 +6,6 @@ * Author: Markus Niebel */ -/ { - aliases { - rtc0 = &rtc0; - }; -}; - &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>, <&pinctrl_enet_fix>; diff --git a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi index 9f9f7037c9e4..7d1cd7454c7f 100644 --- a/arch/arm/boot/dts/imx6qdl-mba6b.dtsi +++ b/arch/arm/boot/dts/imx6qdl-mba6b.dtsi @@ -6,12 +6,6 @@ * Author: Markus Niebel */ -/ { - aliases { - rtc0 = &rtc0; - }; -}; - &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; @@ -19,8 +13,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_recovery>; + scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index f3236204cb5a..1f2ba6f6254e 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -205,6 +205,19 @@ regulator-always-on; }; }; + + da9063_rtc: rtc { + compatible = "dlg,da9063-rtc"; + }; + + da9063_wdog: watchdog { + compatible = "dlg,da9063-watchdog"; + }; + + onkey { + compatible = "dlg,da9063-onkey"; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index 94b254bfd054..28a805384668 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -116,6 +116,16 @@ dlg,use-sw-pm; }; + thermal { + compatible = "dlg,da9062-thermal"; + status = "disabled"; + }; + + gpio { + compatible = "dlg,da9062-gpio"; + status = "disabled"; + }; + regulators { vdd_arm: buck1 { regulator-name = "vdd_arm"; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi index 51a3a5392c95..344ea935c7da 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi @@ -52,6 +52,13 @@ >; }; + pinctrl_i2c1_recovery: i2c1recoverygrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b899 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b899 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b899 @@ -59,6 +66,13 @@ >; }; + pinctrl_i2c3_recovery: i2c3recoverygrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b899 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b899 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b099 /* PMIC irq */ diff --git a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi index bfb67da64b96..7dc3f0005b0f 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6a.dtsi @@ -4,6 +4,8 @@ * Copyright 2013-2017 Markus Niebel */ +#include + &fec { interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; @@ -11,8 +13,11 @@ }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_recovery>; + scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi index 49c472285c06..dd0925766440 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6b.dtsi @@ -4,9 +4,14 @@ * Copyright 2013-2017 Markus Niebel */ +#include + &i2c3 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_recovery>; + scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi b/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi index 410972e1dca9..99ec7a838f8d 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6-mb7.dtsi @@ -85,7 +85,7 @@ }; &i2c3 { - rtc: mcp7940x@6f { + rtc: rtc@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; }; diff --git a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi index b9e305774fed..1ac7e13249d2 100644 --- a/arch/arm/boot/dts/imx6qdl-vicut1.dtsi +++ b/arch/arm/boot/dts/imx6qdl-vicut1.dtsi @@ -126,15 +126,6 @@ regulator-max-microvolt = <3300000>; }; - reg_h1_vbus: regulator-h1-vbus { - compatible = "regulator-fixed"; - regulator-name = "h1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - reg_otg_vbus: regulator-otg-vbus { compatible = "regulator-fixed"; regulator-name = "otg-vbus"; @@ -212,6 +203,8 @@ &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1>; + termination-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + termination-ohms = <150>; status = "okay"; }; @@ -492,7 +485,6 @@ }; &usbh1 { - vbus-supply = <®_h1_vbus>; pinctrl-names = "default"; phy_type = "utmi"; dr_mode = "host"; diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts index 480e73183f6b..f69eec18d865 100644 --- a/arch/arm/boot/dts/imx6qp-sabresd.dts +++ b/arch/arm/boot/dts/imx6qp-sabresd.dts @@ -50,8 +50,12 @@ }; }; +&vgen3_reg { + regulator-always-on; +}; + &pcie { - status = "disabled"; + status = "okay"; }; &sata { diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi index ee645655090d..35861bbea94e 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi +++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi @@ -183,6 +183,27 @@ status = "okay"; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; + status = "okay"; + + hdmi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + interrupts-extended = <&gpio3 27 IRQ_TYPE_LEVEL_LOW>; + + ports { + port { + hdmi: endpoint { + remote-endpoint = <&lcdc>; + }; + }; + }; + }; +}; + &i2c4 { /* Onboard Motion sensors */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4>; @@ -190,6 +211,18 @@ status = "disabled"; }; +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + status = "okay"; + + port { + lcdc: endpoint { + remote-endpoint = <&hdmi>; + }; + }; +}; + &iomuxc { pinctrl_bt_reg: btreggrp { fsl,pins = @@ -227,12 +260,53 @@ ; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = + , + ; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = , ; }; + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + + pinctrl_uart1: uart1grp { fsl,pins = , diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts index 97686097a86e..92ac0edcb608 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts +++ b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts @@ -119,7 +119,7 @@ /delete-node/ codec@a; /delete-node/ touchscreen@48; - rtc: mcp7940x@6f { + rtc: rtc@6f { compatible = "microchip,mcp7940x"; reg = <0x6f>; }; diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi index 139188eb9f40..b770fc937970 100644 --- a/arch/arm/boot/dts/imx7-colibri-aster.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-aster.dtsi @@ -103,7 +103,7 @@ }; /* M41T0M6 real time clock on carrier board */ - rtc: m41t0m6@68 { + rtc: rtc@68 { compatible = "st,m41t0"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi index 3caf450735d7..3b9df8c82ae3 100644 --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi @@ -129,7 +129,7 @@ }; /* M41T0M6 real time clock on carrier board */ - rtc: m41t0m6@68 { + rtc: rtc@68 { compatible = "st,m41t0"; reg = <0x68>; }; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 62b771c1d5a9..f1c60b0cb143 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -40,7 +40,7 @@ dailink_master: simple-audio-card,codec { sound-dai = <&codec>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; }; }; }; @@ -293,7 +293,7 @@ compatible = "fsl,sgtl5000"; #sound-dai-cells = <0>; reg = <0x0a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1_mclk>; VDDA-supply = <®_module_3v3_avdd>; diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 49086c6b6a0a..3df6dff7734a 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -302,7 +302,7 @@ tlv320aic32x4: audio-codec@18 { compatible = "ti,tlv320aic32x4"; reg = <0x18>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; clock-names = "mclk"; ldoin-supply = <®_audio_3v3>; iov-supply = <®_audio_3v3>; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index e0751e6ba3c0..a31de900139d 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -288,7 +288,7 @@ codec: wm8960@1a { compatible = "wlf,wm8960"; reg = <0x1a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; clock-names = "mclk"; wlf,shared-lrclk; }; diff --git a/arch/arm/boot/dts/imx7d-pico-hobbit.dts b/arch/arm/boot/dts/imx7d-pico-hobbit.dts index 7b2198a9372c..d917dc4f2f22 100644 --- a/arch/arm/boot/dts/imx7d-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx7d-pico-hobbit.dts @@ -31,7 +31,7 @@ dailink_master: simple-audio-card,codec { sound-dai = <&sgtl5000>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; }; }; }; @@ -41,7 +41,7 @@ #sound-dai-cells = <0>; reg = <0x0a>; compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_vref_1v8>; }; diff --git a/arch/arm/boot/dts/imx7d-pico-pi.dts b/arch/arm/boot/dts/imx7d-pico-pi.dts index 70bea95c06d8..f263e391e24c 100644 --- a/arch/arm/boot/dts/imx7d-pico-pi.dts +++ b/arch/arm/boot/dts/imx7d-pico-pi.dts @@ -31,7 +31,7 @@ dailink_master: simple-audio-card,codec { sound-dai = <&sgtl5000>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; }; }; }; @@ -41,7 +41,7 @@ #sound-dai-cells = <0>; reg = <0x0a>; compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_vref_1v8>; }; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 7813ef960f6e..f053f5122741 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -385,14 +385,14 @@ codec: wm8960@1a { compatible = "wlf,wm8960"; reg = <0x1a>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; clock-names = "mclk"; wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, <&clks IMX7D_PLL_AUDIO_POST_DIV>, - <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; assigned-clock-rates = <0>, <884736000>, <12288000>; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index b7735979b7e4..f8cba47536a0 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -113,6 +113,49 @@ <0x31004000 0x2000>, <0x31006000 0x2000>; }; + + pcie: pcie@33800000 { + compatible = "fsl,imx7d-pcie"; + reg = <0x33800000 0x4000>, + <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */ + <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + /* + * Reference manual lists pci irqs incorrectly + * Real hardware ordering is same as imx6: D+MSI, C, B, A + */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, + <&clks IMX7D_PCIE_PHY_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie_phy>; + resets = <&src IMX7_RESET_PCIEPHY>, + <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + status = "disabled"; + }; }; }; @@ -162,49 +205,6 @@ fsl,stop-mode = <&gpr 0x10 4>; status = "disabled"; }; - - pcie: pcie@33800000 { - compatible = "fsl,imx7d-pcie"; - reg = <0x33800000 0x4000>, - <0x4ff00000 0x80000>; - reg-names = "dbi", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */ - <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ - num-lanes = <1>; - interrupts = ; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - /* - * Reference manual lists pci irqs incorrectly - * Real hardware ordering is same as imx6: D+MSI, C, B, A - */ - interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, - <&clks IMX7D_PCIE_PHY_ROOT_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy"; - assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, - <&clks IMX7D_PCIE_PHY_ROOT_SRC>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - - fsl,max-link-speed = <2>; - power-domains = <&pgc_pcie_phy>; - resets = <&src IMX7_RESET_PCIEPHY>, - <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, - <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; - reset-names = "pciephy", "apps", "turnoff"; - fsl,imx7d-pcie-phy = <&pcie_phy>; - status = "disabled"; - }; }; &ca_funnel_in_ports { diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 4f1edef06c92..e8734d218b9d 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -75,7 +75,7 @@ dailink_master: simple-audio-card,codec { sound-dai = <&codec>; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; }; }; }; @@ -232,7 +232,7 @@ #sound-dai-cells = <0>; reg = <0x0a>; compatible = "fsl,sgtl5000"; - clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1_mclk>; VDDA-supply = <&vgen4_reg>; diff --git a/arch/arm/boot/dts/imxrt1050-pinfunc.h b/arch/arm/boot/dts/imxrt1050-pinfunc.h new file mode 100644 index 000000000000..22c14a3262ad --- /dev/null +++ b/arch/arm/boot/dts/imxrt1050-pinfunc.h @@ -0,0 +1,993 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#ifndef _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H +#define _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H + +#define IMX_PAD_SION 0x40000000 + +/* + * The pin function ID is a tuple of + * + */ + +#define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_01_XBAR_INOUT3 0x018 0x208 0x610 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXIO1_D01 0x018 0x208 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x018 0x208 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02 0x01C 0x20C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXPWM4_PWM1_A 0x01C 0x20C 0x498 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x01C 0x20C 0x508 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_02_XBAR_INOUT4 0x01C 0x20C 0x614 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_FLEXIO1_D02 0x01C 0x20C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x01C 0x20C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03 0x020 0x210 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXPWM4_PWM1_B 0x020 0x210 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x020 0x210 0x504 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_03_XBAR_INOUT5 0x020 0x210 0x618 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_FLEXIO1_D03 0x020 0x210 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x020 0x210 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04 0x024 0x214 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXPWM4_PWM2_A 0x024 0x214 0x49C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x024 0x214 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_XBAR_INOUT6 0x024 0x214 0x61C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_FLEXIO1_D04 0x024 0x214 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x024 0x214 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05 0x028 0x218 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXPWM4_PWM2_B 0x028 0x218 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x028 0x218 0x5C4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_XBAR_INOUT7 0x028 0x218 0x620 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_FLEXIO1_D05 0x028 0x218 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x028 0x218 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06 0x02C 0x21C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXPWM2_PWM0_A 0x02C 0x21C 0x478 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x02C 0x21C 0x5C0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_XBAR_INOUT8 0x02C 0x21C 0x624 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_FLEXIO1_D06 0x02C 0x21C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x02C 0x21C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07 0x030 0x220 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXPWM2_PWM0_B 0x030 0x220 0x488 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x030 0x220 0x5B0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_XBAR_INOUT9 0x030 0x220 0x628 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_FLEXIO1_D07 0x030 0x220 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x030 0x220 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00 0x034 0x224 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXPWM2_PWM1_A 0x034 0x224 0x47C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x034 0x224 0x5B8 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_XBAR_INOUT17 0x034 0x224 0x62C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_FLEXIO1_D08 0x034 0x224 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x034 0x224 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x038 0x228 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXPWM2_PWM1_B 0x038 0x228 0x48C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x038 0x228 0x5BC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x038 0x228 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_FLEXIO1_D09 0x038 0x228 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x038 0x228 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x03C 0x22C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXPWM2_PWM2_A 0x03C 0x22C 0x480 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x03C 0x22C 0x5B4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x03C 0x22C 0x450 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_FLEXIO1_D10 0x03C 0x22C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x03C 0x22C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x040 0x230 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXPWM2_PWM2_B 0x040 0x230 0x490 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x040 0x230 0x4E8 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x040 0x230 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_FLEXIO1_D11 0x040 0x230 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x040 0x230 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x044 0x234 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_XBAR_INOUT24 0x044 0x234 0x640 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x044 0x234 0x4E4 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_USDHC2_WP 0x044 0x234 0x5D8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_12_FLEXPWM1_PWM3_A 0x044 0x234 0x454 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x044 0x234 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x048 0x238 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_XBAR_INOUT25 0x048 0x238 0x650 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_13_LPUART3_TXD 0x048 0x238 0x53C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x048 0x238 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_13_FLEXPWM1_PWM3_B 0x048 0x238 0x464 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x048 0x238 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x04C 0x23C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_XBAR_INOUT19 0x04C 0x23C 0x654 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_LPUART3_RXD 0x04C 0x23C 0x538 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_MQS_LEFT 0x04C 0x23C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x04C 0x23C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x04C 0x23C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x050 0x240 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_XBAR_INOUT20 0x050 0x240 0x634 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x050 0x240 0x534 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x050 0x240 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_TMR3_TIMER0 0x050 0x240 0x57C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x050 0x240 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x054 0x244 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_XBAR_INOUT21 0x054 0x244 0x658 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x054 0x244 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_SPDIF_IN 0x054 0x244 0x5C8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_16_TMR3_TIMER1 0x054 0x244 0x580 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x054 0x244 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x058 0x248 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXPWM4_PWM3_A 0x058 0x248 0x4A0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x058 0x248 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x058 0x248 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_TMR3_TIMER2 0x058 0x248 0x584 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x058 0x248 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x05C 0x24C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXPWM4_PWM3_B 0x05C 0x24C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x05C 0x24C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x05C 0x24C 0x44C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_18_TMR3_TIMER3 0x05C 0x24C 0x588 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x05C 0x24C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x05C 0x24C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x060 0x250 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_FLEXPWM2_PWM3_A 0x060 0x250 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_LPUART4_TXD 0x060 0x250 0x544 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_19_ENET_RX_DATA01 0x060 0x250 0x438 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_TMR2_TIMER0 0x060 0x250 0x56C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x060 0x250 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x060 0x250 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x064 0x254 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_FLEXPWM2_PWM3_B 0x064 0x254 0x484 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_20_LPUART4_RXD 0x064 0x254 0x540 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_20_ENET_RX_DATA00 0x064 0x254 0x434 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_TMR2_TIMER0 0x064 0x254 0x570 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x064 0x254 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0 0x068 0x258 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_FLEXPWM3_PWM3_A 0x068 0x258 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x068 0x258 0x4E0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_ENET_TX_DATA01 0x068 0x258 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_TMR2_TIMER2 0x068 0x258 0x574 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x068 0x258 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1 0x06C 0x25C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_FLEXPWM3_PWM3_B 0x06C 0x25C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x06C 0x25C 0x4DC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_ENET_TX_DATA00 0x06C 0x25C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_TMR2_TIMER3 0x06C 0x25C 0x578 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x06C 0x25C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x070 0x260 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_FLEXPWM1_PWM0_A 0x070 0x260 0x458 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_LPUART5_TXD 0x070 0x260 0x54C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x070 0x260 0x43C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x070 0x260 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x070 0x260 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS 0x074 0x264 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_FLEXPWM1_PWM0_B 0x074 0x264 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_LPUART5_RXD 0x074 0x264 0x548 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x074 0x264 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x074 0x264 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x074 0x264 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS 0x078 0x268 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_FLEXPWM1_PWM1_A 0x078 0x268 0x45C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_LPUART6_TXD 0x078 0x268 0x554 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x078 0x268 0x448 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x078 0x268 0x42C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x078 0x268 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK 0x07C 0x26C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXPWM1_PWM1_B 0x07C 0x26C 0x46C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_LPUART6_RXD 0x07C 0x26C 0x550 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x07C 0x26C 0x440 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_FLEXIO1_D12 0x07C 0x26C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x07C 0x26C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE 0x080 0x270 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXPWM1_PWM2_A 0x080 0x270 0x460 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x080 0x270 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x080 0x270 0x4F0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_FLEXIO1_D13 0x080 0x270 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x080 0x270 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE 0x084 0x274 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXPWM1_PWM2_B 0x084 0x274 0x470 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x084 0x274 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x084 0x274 0x4F8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_FLEXIO1_D14 0x084 0x274 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x084 0x274 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0 0x088 0x278 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXPWM3_PWM0_A 0x088 0x278 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x088 0x278 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x088 0x278 0x4F4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_FLEXIO1_D15 0x088 0x278 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x088 0x278 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08 0x08C 0x27C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_FLEXPWM3_PWM0_B 0x08C 0x27C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x08C 0x27C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x08C 0x27C 0x4EC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_30_CSI_DATA23 0x08C 0x27C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x08C 0x27C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09 0x090 0x280 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_FLEXPWM3_PWM1_A 0x090 0x280 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_LPUART7_TXD 0x090 0x280 0x55C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x090 0x280 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_CSI_DATA22 0x090 0x280 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x090 0x280 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10 0x094 0x284 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_FLEXPWM3_PWM1_B 0x094 0x284 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_LPUART7_RXD 0x094 0x284 0x558 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_32_CCM_PMIC_READY 0x094 0x284 0x3FC 0x3 0x4 +#define MXRT1050_IOMUXC_GPIO_EMC_32_CSI_DATA21 0x094 0x284 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x094 0x284 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11 0x098 0x288 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_FLEXPWM3_PWM2_A 0x098 0x288 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x098 0x288 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x098 0x288 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_CSI_DATA20 0x098 0x288 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x098 0x288 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12 0x09C 0x28C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_FLEXPWM3_PWM2_B 0x09C 0x28C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x09C 0x28C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x09C 0x28C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_CSI_DATA19 0x09C 0x28C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x09C 0x28C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13 0x0A0 0x290 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_XBAR_INOUT18 0x0A0 0x290 0x630 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x0A0 0x290 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x0A0 0x290 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_CSI_DATA18 0x0A0 0x290 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x0A0 0x290 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x0A0 0x290 0x5D4 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14 0x0A4 0x294 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_XBAR_INOUT22 0x0A4 0x294 0x638 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x0A4 0x294 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x0A4 0x294 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_CSI_DATA17 0x0A4 0x294 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x0A4 0x294 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_36_USDHC1_WP 0x0A4 0x294 0x5D8 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15 0x0A8 0x298 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_XBAR_INOUT23 0x0A8 0x298 0x63C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x0A8 0x298 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x0A8 0x298 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_CSI_DATA16 0x0A8 0x298 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x0A8 0x298 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_37_USDHC2_WP 0x0A8 0x298 0x608 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01 0x0AC 0x29C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_FLEXPWM1_PWM3_A 0x0AC 0x29C 0x454 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_38_LPUART8_TXD 0x0AC 0x29C 0x564 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x0AC 0x29C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_CSI_FIELD 0x0AC 0x29C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x0AC 0x29C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x0AC 0x29C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS 0x0B0 0x2A0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_FLEXPWM1_PWM3_B 0x0B0 0x2A0 0x464 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_39_LPUART8_RXD 0x0B0 0x2A0 0x560 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x0B0 0x2A0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_WDOG1_B 0x0B0 0x2A0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x0B0 0x2A0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x0B0 0x2A0 0x5E0 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_EMC_40_SEMC_RDY 0x0B4 0x2A4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x0B4 0x2A4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x0B4 0x2A4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x0B4 0x2A4 0x5CC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_40_ENET_MDC 0x0B4 0x2A4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x0B4 0x2A4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x0B4 0x2A4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_EMC_41_SEMC_CSX0 0x0B8 0x2A8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x0B8 0x2A8 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x0B8 0x2A8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x0B8 0x2A8 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_ENET_MDIO 0x0B8 0x2A8 0x430 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x0B8 0x2A8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_EMC_41_USDHC2_VSELECT 0x0B8 0x2A8 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWM3_A 0x0BC 0x2AC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_XBAR_INOUT14 0x0BC 0x2AC 0x644 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x0BC 0x2AC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x0BC 0x2AC 0x3F8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x0BC 0x2AC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x0BC 0x2AC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x0BC 0x2AC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x0BC 0x2AC 0x510 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWM3_B 0x0C0 0x2B0 0x484 0x0 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_XBAR_INOUT15 0x0C0 0x2B0 0x648 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x0C0 0x2B0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x0C0 0x2B0 0x3F4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x0C0 0x2B0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x0C0 0x2B0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x0C0 0x2B0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x0C0 0x2B0 0x518 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x0C4 0x2B4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_XBAR_INOUT16 0x0C4 0x2B4 0x64C 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPUART6_TXD 0x0C4 0x2B4 0x554 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x0C4 0x2B4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWM0_X 0x0C4 0x2B4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x0C4 0x2B4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x0C4 0x2B4 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x0C4 0x2B4 0x514 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x0C8 0x2B8 0x450 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_XBAR_INOUT17 0x0C8 0x2B8 0x62C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPUART6_RXD 0x0C8 0x2B8 0x550 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x0C8 0x2B8 0x5D0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWM1_X 0x0C8 0x2B8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x0C8 0x2B8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x0C8 0x2B8 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x0C8 0x2B8 0x50C 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x0CC 0x2BC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x0CC 0x2BC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x0CC 0x2BC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x0CC 0x2BC 0x5C4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x0CC 0x2BC 0x41C 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x0CC 0x2BC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x0CC 0x2BC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x0CC 0x2BC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x0D0 0x2C0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x0D0 0x2C0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x0D0 0x2C0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x0D0 0x2C0 0x5C0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x0D0 0x2C0 0x418 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x0D0 0x2C0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_XBAR_INOUT17 0x0D0 0x2C0 0x62C 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x0D0 0x2C0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x0D4 0x2C4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x0D4 0x2C4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x0D4 0x2C4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x0D4 0x2C4 0x5B4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x0D4 0x2C4 0x414 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x0D4 0x2C4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_XBAR_INOUT18 0x0D4 0x2C4 0x630 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x0D4 0x2C4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x0D8 0x2C8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x0D8 0x2C8 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x0D8 0x2C8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x0D8 0x2C8 0x5BC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x0D8 0x2C8 0x410 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x0D8 0x2C8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_XBAR_INOUT19 0x0D8 0x2C8 0x654 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x0D8 0x2C8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x0DC 0x2CC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x0DC 0x2CC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x0DC 0x2CC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x0DC 0x2CC 0x5B8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x0DC 0x2CC 0x40C 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x0DC 0x2CC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_XBAR_INOUT20 0x0DC 0x2CC 0x634 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x0DC 0x2CC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x0E0 0x2D0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWM3_A 0x0E0 0x2D0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x0E0 0x2D0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x0E0 0x2D0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x0E0 0x2D0 0x408 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x0E0 0x2D0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_XBAR_INOUT21 0x0E0 0x2D0 0x658 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x0E0 0x2D0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x0E4 0x2D4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWM3_A 0x0E4 0x2D4 0x454 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x0E4 0x2D4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x0E4 0x2D4 0x5B0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x0E4 0x2D4 0x404 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x0E4 0x2D4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_XBAR_INOUT22 0x0E4 0x2D4 0x638 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x0E4 0x2D4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x0E8 0x2D8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWM3_B 0x0E8 0x2D8 0x464 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_COL 0x0E8 0x2D8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_WDOG1_B 0x0E8 0x2D8 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x0E8 0x2D8 0x400 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x0E8 0x2D8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_XBAR_INOUT23 0x0E8 0x2D8 0x63C 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x0E8 0x2D8 0x444 0x7 0x1 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x0EC 0x2DC 0x4E4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x0EC 0x2DC 0x3FC 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0x0EC 0x2DC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_WDOG2_B 0x0EC 0x2DC 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWM2_X 0x0EC 0x2DC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x0EC 0x2DC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x0EC 0x2DC 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_12_NMI 0x0EC 0x2DC 0x568 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x0F0 0x2E0 0x4E8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x0F0 0x2E0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0x0F0 0x2E0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x0F0 0x2E0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWM3_X 0x0F0 0x2E0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x0F0 0x2E0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x0F0 0x2E0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x0F0 0x2E0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x0F4 0x2E4 0x5CC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_XBAR_INOUT24 0x0F4 0x2E4 0x640 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x0F4 0x2E4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x0F4 0x2E4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x0F4 0x2E4 0x428 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x0F4 0x2E4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x0F4 0x2E4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x0F8 0x2E8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_XBAR_INOUT25 0x0F8 0x2E8 0x650 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x0F8 0x2E8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x0F8 0x2E8 0x444 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x0F8 0x2E8 0x420 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x0F8 0x2E8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x0F8 0x2E8 0x450 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x0F8 0x2E8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x0FC 0x2EC 0x3F8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_TMR3_TIMER0 0x0FC 0x2EC 0x57C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x0FC 0x2EC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x0FC 0x2EC 0x4CC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x0FC 0x2EC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x0FC 0x2EC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x0FC 0x2EC 0x5D8 0x6 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x0FC 0x2EC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x100 0x2F0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_TMR3_TIMER1 0x100 0x2F0 0x580 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x100 0x2F0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x100 0x2F0 0x4D0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x100 0x2F0 0x3FC 0x4 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x100 0x2F0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x100 0x2F0 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x100 0x2F0 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x104 0x2F4 0x3F4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_TMR3_TIMER2 0x104 0x2F4 0x584 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_LPUART2_TXD 0x104 0x2F4 0x530 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x104 0x2F4 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x104 0x2F4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x104 0x2F4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x104 0x2F4 0x5D4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x104 0x2F4 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x108 0x2F8 0x5D0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_TMR3_TIMER3 0x108 0x2F8 0x588 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_LPUART2_RXD 0x108 0x2F8 0x52C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x108 0x2F8 0x5C8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x108 0x2F8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x108 0x2F8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x108 0x2F8 0x5E0 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x108 0x2F8 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_FLEXSPI_B_DATA3 0x10C 0x2FC 0x4C4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x10C 0x2FC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x10C 0x2FC 0x534 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x10C 0x2FC 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x10C 0x2FC 0x424 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x10C 0x2FC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x10C 0x2FC 0x5E8 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x10C 0x2FC 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_FLEXSPI_B_DATA2 0x110 0x300 0x4C0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x110 0x300 0x430 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x110 0x300 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x110 0x300 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x110 0x300 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x110 0x300 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x110 0x300 0x5EC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x110 0x300 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_FLEXSPI_B_DATA0 0x118 0x308 0x4B8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x118 0x308 0x4DC 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_LPUART3_RXD 0x118 0x308 0x538 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x118 0x308 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x118 0x308 0x420 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x118 0x308 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x118 0x308 0x5F4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x118 0x308 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXSPI_A_SS1_B 0x11C 0x30C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWM0_A 0x11C 0x30C 0x494 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x11C 0x30C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x11C 0x30C 0x3FC 0x3 0x3 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x11C 0x30C 0x41C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x11C 0x30C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x11C 0x30C 0x5E4 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x11C 0x30C 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXSPI_A_DQS 0x120 0x310 0x4A4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWM1_A 0x120 0x310 0x498 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x120 0x310 0x44C 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x120 0x310 0x58C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x120 0x310 0x418 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x120 0x310 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x120 0x310 0x5DC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x120 0x310 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_FLEXSPI_A_DATA3 0x124 0x314 0x4B4 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x124 0x314 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_LPUART8_TXD 0x124 0x314 0x564 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x124 0x314 0x5A4 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x124 0x314 0x414 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x124 0x314 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x124 0x314 0x608 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x124 0x314 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_FLEXSPI_A_DATA2 0x128 0x318 0x4B0 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x128 0x318 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_LPUART8_RXD 0x128 0x318 0x560 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x128 0x318 0x590 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x128 0x318 0x410 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x128 0x318 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x128 0x318 0x000 0x6 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x128 0x318 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_FLEXSPI_A_DATA1 0x12C 0x31C 0x4AC 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_ACMP1_OUT 0x12C 0x31C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x12C 0x31C 0x50C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x12C 0x31C 0x594 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x12C 0x31C 0x40C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x12C 0x31C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x12C 0x31C 0x5F8 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x12C 0x31C 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_FLEXSPI_A_DATA0 0x130 0x320 0x4A8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_ACMP2_OUT 0x130 0x320 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x130 0x320 0x514 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x130 0x320 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x130 0x320 0x408 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x130 0x320 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x130 0x320 0x5FC 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x130 0x320 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_FLEXSPI_A_SCLK 0x134 0x324 0x4C8 0x0 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_ACMP3_OUT 0x134 0x324 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x134 0x324 0x518 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x134 0x324 0x5A8 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x134 0x324 0x404 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x134 0x324 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x134 0x324 0x600 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x134 0x324 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_FLEXSPI_A_SS0_B 0x138 0x328 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_ACMP4_OUT 0x138 0x328 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x138 0x328 0x510 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x138 0x328 0x5AC 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x138 0x328 0x400 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x138 0x328 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x138 0x328 0x604 0x6 0x1 +#define MXRT1050_IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x138 0x328 0x000 0x7 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x13C 0x32C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_TMR1_TIMER0 0x13C 0x32C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_MQS_RIGHT 0x13C 0x32C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x13C 0x32C 0x51C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_FLEXIO2_D00 0x13C 0x32C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_GPIO2_IO00 0x13C 0x32C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_00_SEMC_CSX1 0x13C 0x32C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x140 0x330 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_TMR1_TIMER1 0x140 0x330 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_MQS_LEFT 0x140 0x330 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x140 0x330 0x524 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_FLEXIO2_D01 0x140 0x330 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_GPIO2_IO01 0x140 0x330 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_01_SEMC_CSX2 0x140 0x330 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_02_LCD_HSYNC 0x144 0x334 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_TMR1_TIMER2 0x144 0x334 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x144 0x334 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x144 0x334 0x528 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_FLEXIO2_D02 0x144 0x334 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_GPIO2_IO02 0x144 0x334 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_02_SEMC_CSX3 0x144 0x334 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_03_LCD_VSYNC 0x148 0x338 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_TMR2_TIMER0 0x148 0x338 0x56C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x148 0x338 0x44C 0x2 0x3 +#define MXRT1050_IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x148 0x338 0x520 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_FLEXIO2_D03 0x148 0x338 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_GPIO2_IO03 0x148 0x338 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x148 0x338 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_04_LCD_DATA00 0x14C 0x33C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_TMR2_TIMER1 0x14C 0x33C 0x570 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x14C 0x33C 0x4D4 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_04_ARM_TRACE00 0x14C 0x33C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_FLEXIO2_D04 0x14C 0x33C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_GPIO2_IO04 0x14C 0x33C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_04_SRC_BT_CFG00 0x14C 0x33C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_05_LCD_DATA01 0x150 0x340 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_TMR2_TIMER2 0x150 0x340 0x574 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x150 0x340 0x4D8 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_05_ARM_TRACE01 0x150 0x340 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_FLEXIO2_D05 0x150 0x340 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_GPIO2_IO05 0x150 0x340 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_05_SRC_BT_CFG01 0x150 0x340 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_06_LCD_DATA02 0x154 0x344 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_TMR3_TIMER0 0x154 0x344 0x57C 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXPWM2_PWM0_A 0x154 0x344 0x478 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_06_ARM_TRACE02 0x154 0x344 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_FLEXIO2_D06 0x154 0x344 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_GPIO2_IO06 0x154 0x344 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_06_SRC_BT_CFG02 0x154 0x344 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_07_LCD_DATA03 0x158 0x348 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_TMR3_TIMER1 0x158 0x348 0x580 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXPWM2_PWM0_B 0x158 0x348 0x488 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_07_ARM_TRACE03 0x158 0x348 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_FLEXIO2_D07 0x158 0x348 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_GPIO2_IO07 0x158 0x348 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_07_SRC_BT_CFG03 0x158 0x348 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_08_LCD_DATA04 0x15C 0x34C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_TMR3_TIMER2 0x15C 0x34C 0x584 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXPWM2_PWM1_A 0x15C 0x34C 0x47C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_08_LPUART3_TXD 0x15C 0x34C 0x53C 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_08_FLEXIO2_D08 0x15C 0x34C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_GPIO2_IO08 0x15C 0x34C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_08_SRC_BT_CFG04 0x15C 0x34C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_09_LCD_DATA05 0x160 0x350 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_TMR4_TIMER0 0x160 0x350 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXPWM2_PWM1_B 0x160 0x350 0x48C 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_09_LPUART3_RXD 0x160 0x350 0x538 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_09_FLEXIO2_D09 0x160 0x350 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_GPIO2_IO09 0x160 0x350 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_09_SRC_BT_CFG05 0x160 0x350 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_10_LCD_DATA06 0x164 0x354 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_TMR4_TIMER1 0x164 0x354 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXPWM2_PWM2_A 0x164 0x354 0x480 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x164 0x354 0x598 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_10_FLEXIO2_D10 0x164 0x354 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_GPIO2_IO10 0x164 0x354 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_10_SRC_BT_CFG06 0x164 0x354 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_11_LCD_DATA07 0x168 0x358 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_TMR4_TIMER2 0x168 0x358 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXPWM2_PWM2_B 0x168 0x358 0x490 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x168 0x358 0x59C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_11_FLEXIO2_D11 0x168 0x358 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_GPIO2_IO11 0x168 0x358 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_11_SRC_BT_CFG07 0x168 0x358 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_12_LCD_DATA08 0x16C 0x35C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_XBAR_INOUT10 0x16C 0x35C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x16C 0x35C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x16C 0x35C 0x5A0 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B0_12_FLEXIO2_D12 0x16C 0x35C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_GPIO2_IO12 0x16C 0x35C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_12_SRC_BT_CFG08 0x16C 0x35C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_13_LCD_DATA09 0x170 0x360 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_XBAR_INOUT11 0x170 0x360 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x170 0x360 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_SAI1_MCLK 0x170 0x360 0x58C 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_13_FLEXIO2_D13 0x170 0x360 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_GPIO2_IO13 0x170 0x360 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_13_SRC_BT_CFG09 0x170 0x360 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_14_LCD_DATA10 0x174 0x364 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_XBAR_INOUT12 0x174 0x364 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_ARM_CM7_TXEV 0x174 0x364 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x174 0x364 0x5A4 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_14_FLEXIO2_D14 0x174 0x364 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_GPIO2_IO14 0x174 0x364 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_14_SRC_BT_CFG10 0x174 0x364 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B0_15_LCD_DATA11 0x178 0x368 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_XBAR_INOUT13 0x178 0x368 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_ARM_CM7_RXEV 0x178 0x368 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x178 0x368 0x590 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B0_15_FLEXIO2_D15 0x178 0x368 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_GPIO2_IO15 0x178 0x368 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B0_15_SRC_BT_CFG11 0x178 0x368 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_00_LCD_DATA12 0x17C 0x36C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_XBAR_INOUT14 0x17C 0x36C 0x644 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_00_LPUART4_TXD 0x17C 0x36C 0x544 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x17C 0x36C 0x594 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXIO2_D16 0x17C 0x36C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_GPIO2_IO16 0x17C 0x36C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_00_FLEXPWM1_PWM3_A 0x17C 0x36C 0x454 0x6 0x4 + +#define MXRT1050_IOMUXC_GPIO_B1_01_LCD_DATA13 0x180 0x370 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_XBAR_INOUT15 0x180 0x370 0x648 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_01_LPUART4_RXD 0x180 0x370 0x540 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x180 0x370 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXIO2_D17 0x180 0x370 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_GPIO2_IO17 0x180 0x370 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_01_FLEXPWM1_PWM3_B 0x180 0x370 0x464 0x6 0x4 + +#define MXRT1050_IOMUXC_GPIO_B1_02_LCD_DATA14 0x184 0x374 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_XBAR_INOUT16 0x184 0x374 0x64C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x184 0x374 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x184 0x374 0x5A8 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXIO2_D18 0x184 0x374 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_GPIO2_IO18 0x184 0x374 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_02_FLEXPWM2_PWM3_A 0x184 0x374 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_03_LCD_DATA15 0x188 0x378 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_XBAR_INOUT17 0x188 0x378 0x62C 0x1 0x3 +#define MXRT1050_IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x188 0x378 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x188 0x378 0x5AC 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXIO2_D19 0x188 0x378 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_GPIO2_IO19 0x188 0x378 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_03_FLEXPWM2_PWM3_B 0x188 0x378 0x484 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_04_LCD_DATA16 0x18C 0x37C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x18C 0x37C 0x51C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_04_CSI_DATA15 0x18C 0x37C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x18C 0x37C 0x434 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_04_FLEXIO2_D20 0x18C 0x37C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_04_GPIO2_IO20 0x18C 0x37C 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_05_LCD_DATA17 0x190 0x380 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x190 0x380 0x524 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_05_CSI_DATA14 0x190 0x380 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x190 0x380 0x438 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_05_FLEXIO2_D21 0x190 0x380 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_05_GPIO2_IO21 0x190 0x380 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_06_LCD_DATA18 0x194 0x384 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x194 0x384 0x528 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_06_CSI_DATA13 0x194 0x384 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_ENET_RX_EN 0x194 0x384 0x43C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_06_FLEXIO2_D22 0x194 0x384 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_06_GPIO2_IO22 0x194 0x384 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_07_LCD_DATA19 0x198 0x388 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x198 0x388 0x520 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_07_CSI_DATA12 0x198 0x388 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x198 0x388 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_FLEXIO2_D23 0x198 0x388 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_07_GPIO2_IO23 0x198 0x388 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_08_LCD_DATA20 0x19C 0x38C 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_TMR1_TIMER3 0x19C 0x38C 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_CSI_DATA11 0x19C 0x38C 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x19C 0x38C 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXIO2_D24 0x19C 0x38C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_GPIO2_IO24 0x19C 0x38C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x19C 0x38C 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_09_LCD_DATA21 0x1A0 0x390 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_TMR2_TIMER3 0x1A0 0x390 0x578 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_09_CSI_DATA10 0x1A0 0x390 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_ENET_TX_EN 0x1A0 0x390 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXIO2_D25 0x1A0 0x390 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_GPIO2_IO25 0x1A0 0x390 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x1A0 0x390 0x450 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_10_LCD_DATA22 0x1A4 0x394 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_TMR3_TIMER3 0x1A4 0x394 0x588 0x1 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_10_CSI_DATA00 0x1A4 0x394 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x1A4 0x394 0x448 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_10_FLEXIO2_D26 0x1A4 0x394 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_GPIO2_IO26 0x1A4 0x394 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x1A4 0x394 0x42C 0x6 0x1 + +#define MXRT1050_IOMUXC_GPIO_B1_11_LCD_DATA23 0x1A8 0x398 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_TMR4_TIMER3 0x1A8 0x398 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_CSI_DATA01 0x1A8 0x398 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_ENET_RX_ER 0x1A8 0x398 0x440 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_11_FLEXIO2_D27 0x1A8 0x398 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_GPIO2_IO27 0x1A8 0x398 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x1A8 0x398 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_12_LPUART5_TXD 0x1AC 0x39C 0x54C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x1AC 0x39C 0x424 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x1AC 0x39C 0x444 0x3 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_12_FLEXIO2_D28 0x1AC 0x39C 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_12_GPIO2_IO28 0x1AC 0x39C 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1AC 0x39C 0x5D4 0x6 0x2 + +#define MXRT1050_IOMUXC_GPIO_B1_13_WDOG1_B 0x1B0 0x3A0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_LPUART5_RXD 0x1B0 0x3A0 0x548 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_13_CSI_VSYNC 0x1B0 0x3A0 0x428 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x1B0 0x3A0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_FLEXIO2_D29 0x1B0 0x3A0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_GPIO2_IO29 0x1B0 0x3A0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_13_USDHC1_WP 0x1B0 0x3A0 0x5D8 0x6 0x3 + +#define MXRT1050_IOMUXC_GPIO_B1_14_ENET_MDC 0x1B4 0x3A4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXPWM4_PWM2_A 0x1B4 0x3A4 0x49C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_14_CSI_HSYNC 0x1B4 0x3A4 0x420 0x2 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_14_XBAR_INOUT02 0x1B4 0x3A4 0x60C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_14_FLEXIO2_D30 0x1B4 0x3A4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_GPIO2_IO30 0x1B4 0x3A4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x1B4 0x3A4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_B1_15_ENET_MDIO 0x1B8 0x3A8 0x430 0x0 0x2 +#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXPWM4_PWM3_A 0x1B8 0x3A8 0x4A0 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_15_CSI_MCLK 0x1B8 0x3A8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_XBAR_INOUT03 0x1B8 0x3A8 0x610 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_B1_15_FLEXIO2_D31 0x1B8 0x3A8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_GPIO2_IO31 0x1B8 0x3A8 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x1B8 0x3A8 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x1BC 0x3AC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWM0_A 0x1BC 0x3AC 0x458 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x1BC 0x3AC 0x4DC 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_XBAR_INOUT04 0x1BC 0x3AC 0x614 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x1BC 0x3AC 0x4F0 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x1BC 0x3AC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_00_FLEXSPI_A_SS1_B 0x1BC 0x3AC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x1C0 0x3B0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWM0_B 0x1C0 0x3B0 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x1C0 0x3B0 0x4E0 0x2 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_XBAR_INOUT05 0x1C0 0x3B0 0x618 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x1C0 0x3B0 0x4EC 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x1C0 0x3B0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_01_FLEXSPI_B_SS1_B 0x1C0 0x3B0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x1C4 0x3B4 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWM1_A 0x1C4 0x3B4 0x45C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x1C4 0x3B4 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_XBAR_INOUT06 0x1C4 0x3B4 0x61C 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x1C4 0x3B4 0x4F8 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x1C4 0x3B4 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x1C8 0x3B8 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWM1_B 0x1C8 0x3B8 0x46C 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x1C8 0x3B8 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_XBAR_INOUT07 0x1C8 0x3B8 0x620 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x1C8 0x3B8 0x4F4 0x4 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x1C8 0x3B8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x1CC 0x3BC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWM2_A 0x1CC 0x3BC 0x460 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_LPUART8_TXD 0x1CC 0x3BC 0x564 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_XBAR_INOUT08 0x1CC 0x3BC 0x624 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_FLEXSPI_B_SS0_B 0x1CC 0x3BC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x1CC 0x3BC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x1CC 0x3BC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x1D0 0x3C0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWM2_B 0x1D0 0x3C0 0x470 0x1 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_LPUART8_RXD 0x1D0 0x3C0 0x560 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_XBAR_INOUT09 0x1D0 0x3C0 0x628 0x3 0x1 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_FLEXSPI_B_DQS 0x1D0 0x3C0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x1D0 0x3C0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x1D0 0x3C0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x1D4 0x3C4 0x5F4 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXSPI_B_DATA3 0x1D4 0x3C4 0x4C4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWM3_A 0x1D4 0x3C4 0x454 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x1D4 0x3C4 0x598 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_LPUART4_TXD 0x1D4 0x3C4 0x544 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x1D4 0x3C4 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x1D8 0x3C8 0x5F0 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXSPI_B_DATA2 0x1D8 0x3C8 0x4C0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWM3_B 0x1D8 0x3C8 0x464 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x1D8 0x3C8 0x59C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_LPUART4_RXD 0x1D8 0x3C8 0x540 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x1D8 0x3C8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x1DC 0x3CC 0x5EC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXSPI_B_DATA1 0x1DC 0x3CC 0x4BC 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWM3_A 0x1DC 0x3CC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x1DC 0x3CC 0x5A0 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x1DC 0x3CC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x1DC 0x3CC 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x1DC 0x3CC 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x1E0 0x3D0 0x5E8 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXSPI_B_DATA0 0x1E0 0x3D0 0x4B8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWM3_B 0x1E0 0x3D0 0x484 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x1E0 0x3D0 0x58C 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x1E0 0x3D0 0x44C 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x1E0 0x3D0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x1E0 0x3D0 0x3FC 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x1E4 0x3D4 0x5DC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXSPI_B_SCLK 0x1E4 0x3D4 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x1E4 0x3D4 0x4CC 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x1E4 0x3D4 0x5A4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_FLEXCAN1_A_SS1_B 0x1E4 0x3D4 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x1E4 0x3D4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x1E4 0x3D4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x1E8 0x3D8 0x5E4 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXSPI_A_DQS 0x1E8 0x3D8 0x4A4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x1E8 0x3D8 0x4D0 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x1E8 0x3D8 0x590 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_FLEXCAN1_B_SS0_B 0x1E8 0x3D8 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x1E8 0x3D8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x1EC 0x3DC 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_FLEXSPI_A_SS0_B 0x1EC 0x3DC 0x000 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x1EC 0x3DC 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x1EC 0x3DC 0x594 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x1EC 0x3DC 0x4FC 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x1EC 0x3DC 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SEMC_CSX1 0x1F0 0x3E0 0x000 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_FLEXSPI_A_SCLK 0x1F0 0x3E0 0x4C8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x1F0 0x3E0 0x000 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x1F0 0x3E0 0x000 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x1F0 0x3E0 0x500 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x1F0 0x3E0 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x1F0 0x3E0 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x1F4 0x3E4 0x5F8 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_FLEXSPI_A_DATA0 0x1F4 0x3E4 0x4A8 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPUART7_TXD 0x1F4 0x3E4 0x55C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SAI1_TX_BLCK 0x1F4 0x3E4 0x5A8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_LPSPI2_SDO 0x1F4 0x3E4 0x508 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x1F4 0x3E4 0x000 0x5 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_08_SEMC_CSX2 0x1F4 0x3E4 0x000 0x6 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x1F8 0x3E8 0x5FC 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_FLEXSPI_A_DATA1 0x1F8 0x3E8 0x4AC 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPUART7_RXD 0x1F8 0x3E8 0x558 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x1F8 0x3E8 0x5AC 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x1F8 0x3E8 0x504 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x1F8 0x3E8 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x1FC 0x3EC 0x600 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_FLEXSPI_A_DATA2 0x1FC 0x3EC 0x4B0 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPUART2_RXD 0x1FC 0x3EC 0x52C 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x1FC 0x3EC 0x4D8 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x1FC 0x3EC 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x1FC 0x3EC 0x000 0x5 0x0 + +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x200 0x3F0 0x604 0x0 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_DATA3 0x200 0x3F0 0x4B4 0x1 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPUART2_TXD 0x200 0x3F0 0x530 0x2 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x200 0x3F0 0x4D4 0x3 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x200 0x3F0 0x000 0x4 0x0 +#define MXRT1050_IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x200 0x3F0 0x000 0x5 0x0 + +#endif /* _DT_BINDINGS_PINCTRL_IMXRT1050_PINFUNC_H */ diff --git a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts index a1c03c965f17..b7cbc90e1c18 100644 --- a/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts +++ b/arch/arm/boot/dts/intel-ixp42x-gateway-7001.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: ISC /* - * Device Tree file for Gateway 7001 AP + * Device Tree file for Gateway 7001 AP based on IXP422 * Derived from boardfiles written by Imre Kaloz */ @@ -29,7 +29,6 @@ aliases { /* second UART is the primary console */ serial0 = &uart1; - serial1 = &uart0; }; soc { diff --git a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts similarity index 77% rename from arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts rename to arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts index a57009436ed8..df2ca6d95ee5 100644 --- a/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v2.dts +++ b/arch/arm/boot/dts/intel-ixp42x-netgear-wg302v1.dts @@ -10,26 +10,26 @@ #include / { - model = "Netgear WG302 v2"; - compatible = "netgear,wg302v2", "intel,ixp42x"; + model = "Netgear WG302 v1"; + compatible = "netgear,wg302v1", "intel,ixp42x"; #address-cells = <1>; #size-cells = <1>; memory@0 { - /* 16 MB SDRAM according to OpenWrt database */ + /* 32 MB SDRAM according to boot arguments */ device_type = "memory"; - reg = <0x00000000 0x01000000>; + reg = <0x00000000 0x02000000>; }; chosen { - bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; - stdout-path = "uart1:115200n8"; + /* The RedBoot comes up in 9600 baud so let's keep this */ + bootargs = "console=ttyS0,9600n8"; + stdout-path = "uart1:9600n8"; }; aliases { /* These are switched around */ serial0 = &uart1; - serial1 = &uart0; }; soc { @@ -38,18 +38,17 @@ compatible = "intel,ixp4xx-flash", "cfi-flash"; bank-width = <2>; /* - * 32 MB of Flash in 128 0x20000 sized blocks - * mapped in at CS0 and CS1 + * 8 MB of Flash in 64 0x20000 sized blocks + * mapped in at CS0. */ - reg = <0 0x00000000 0x2000000>; + reg = <0 0x00000000 0x800000>; /* Configure expansion bus to allow writes */ intel,ixp4xx-eb-write-enable = <1>; partitions { compatible = "redboot-fis"; - /* CHECKME: guess this is Redboot FIS */ - fis-index-block = <0xff>; + fis-index-block = <0x3f>; }; }; }; @@ -82,14 +81,14 @@ queue-rx = <&qmgr 3>; queue-txready = <&qmgr 20>; phy-mode = "rgmii"; - phy-handle = <&phy8>; + phy-handle = <&phy30>; mdio { #address-cells = <1>; #size-cells = <0>; - phy8: ethernet-phy@8 { - reg = <8>; + phy30: ethernet-phy@30 { + reg = <30>; }; }; }; diff --git a/arch/arm/boot/dts/intel-ixp42x.dtsi b/arch/arm/boot/dts/intel-ixp42x.dtsi index d0e0f8afb7c9..84cee8ec3ab8 100644 --- a/arch/arm/boot/dts/intel-ixp42x.dtsi +++ b/arch/arm/boot/dts/intel-ixp42x.dtsi @@ -9,7 +9,7 @@ soc { bus@c4000000 { compatible = "intel,ixp42x-expansion-bus-controller", "syscon"; - reg = <0xc4000000 0x28>; + reg = <0xc4000000 0x30>; }; pci@c0000000 { diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi index 849034a49a3f..03caea6fc6ff 100644 --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi @@ -181,7 +181,7 @@ }; &gpio2 { - touch-interrupt { + touch-interrupt-hog { gpio-hog; gpios = <12 GPIO_ACTIVE_LOW>; input; diff --git a/arch/arm/boot/dts/kirkwood-c200-v1.dts b/arch/arm/boot/dts/kirkwood-c200-v1.dts new file mode 100644 index 000000000000..f59ff7578dfc --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-c200-v1.dts @@ -0,0 +1,310 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Ctera C200 V1 Board Description + * Copyright 2021-2022 Pawel Dembicki + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" +#include + +/ { + model = "Ctera C200 V1"; + compatible = "ctera,c200-v1", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_buttons>; + pinctrl-names = "default"; + + power { + label = "Power Button"; + linux,code = ; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + + usb1 { + label = "USB1 Button"; + linux,code = ; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + + usb2 { + label = "USB2 Button"; + linux,code = ; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_poweroff>; + pinctrl-names = "default"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_leds>; + pinctrl-names = "default"; + + led-0 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = ; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + }; + + led-1 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = ; + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + + led-2 { + function = LED_FUNCTION_DISK; + function-enumerator = <2>; + color = ; + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + }; + + led-3 { + function = LED_FUNCTION_DISK; + function-enumerator = <1>; + color = ; + gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + + led-4 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + led-5 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + led-6 { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led-7 { + function = LED_FUNCTION_DISK_ERR; + color = ; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + led-8 { + function = LED_FUNCTION_DISK_ERR; + color = ; + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + led-9 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = ; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + }; + + led-10 { + function = LED_FUNCTION_USB; + function-enumerator = <1>; + color = ; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port2>; + }; + + led-11 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = ; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + + led-12 { + function = LED_FUNCTION_USB; + function-enumerator = <2>; + color = ; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port1>; + }; + }; +}; + +ð0 { + status = "okay"; +}; + +ð0port { + phy-handle = <ðphy9>; +}; + +&i2c0 { + status = "okay"; + + rtc@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + + lm63@4c { + compatible = "national,lm63"; + reg = <0x4c>; + }; +}; + +&mdio { + status = "okay"; + + ethphy9: ethernet-phy@9 { + reg = <9>; + }; +}; + +&nand { + status = "okay"; + chip-delay = <40>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x200000>; + }; + + partition@200000 { + label = "certificate"; + reg = <0x0200000 0x100000>; + }; + + partition@300000 { + label = "preset_cfg"; + reg = <0x0300000 0x100000>; + }; + + partition@400000 { + label = "dev_params"; + reg = <0x0400000 0x100000>; + }; + + partition@500000 { + label = "active_bank"; + reg = <0x0500000 0x0100000>; + }; + + partition@600000 { + label = "magic"; + reg = <0x0600000 0x0100000>; + }; + + partition@700000 { + label = "bank1"; + reg = <0x0700000 0x2800000>; + }; + + partition@2f00000 { + label = "bank2"; + reg = <0x2f00000 0x2800000>; + }; + + /* 0x5700000-0x5a00000 undefined in vendor firmware */ + + partition@5a00000 { + label = "reserved"; + reg = <0x5a00000 0x2000000>; + }; + + partition@7a00000 { + label = "rootfs"; + reg = <0x7a00000 0x8600000>; + }; +}; + +&pinctrl { + /* Buzzer gpios are connected to two pins of buzzer. + * This buzzer require a modulated signal from gpio. + * Leave it as is due lack of proper driver. + */ + pmx_buzzer: pmx-buzzer { + marvell,pins = "mpp12", "mpp13"; + marvell,function = "gpio"; + }; + + pmx_leds: pmx-leds { + marvell,pins = "mpp14", "mpp15", "mpp16", "mpp17", "mpp38", + "mpp39", "mpp40", "mpp42", "mpp43", "mpp44", + "mpp45", "mpp46", "mpp47"; + marvell,function = "gpio"; + }; + + pmx_buttons: pmx-buttons { + marvell,pins = "mpp28", "mpp29", "mpp48", "mpp49"; + marvell,function = "gpio"; + }; + + pmx_poweroff: pmx-poweroff { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; +}; + +&rtc { + status = "disabled"; +}; + +&sata { + status = "okay"; + nr-ports = <2>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + #trigger-source-cells = <0>; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + hub_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts new file mode 100644 index 000000000000..3281af90ac6d --- /dev/null +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x_pcb8291.dts - Device Tree file for PCB8291 + */ +/dts-v1/; +#include "lan966x.dtsi" + +/ { + model = "Microchip EVB - LAN9662"; + compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &usart3; + }; +}; + +&gpio { + fc_shrd7_pins: fc_shrd7-pins { + pins = "GPIO_49"; + function = "fc_shrd7"; + }; + + fc_shrd8_pins: fc_shrd8-pins { + pins = "GPIO_54"; + function = "fc_shrd8"; + }; + + fc3_b_pins: fcb3-spi-pins { + /* SCK, RXD, TXD */ + pins = "GPIO_51", "GPIO_52", "GPIO_53"; + function = "fc3_b"; + }; + + can0_b_pins: can0_b_pins { + /* RX, TX */ + pins = "GPIO_35", "GPIO_36"; + function = "can0_b"; + }; +}; + +&can0 { + pinctrl-0 = <&can0_b_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; + + usart3: serial@200 { + pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi new file mode 100644 index 000000000000..7d2869648050 --- /dev/null +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC + * + * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries + * + * Author: Kavyasree Kotagiri + * + */ + +#include +#include +#include +#include +#include +#include + +/ { + model = "Microchip LAN966 family SoC"; + compatible = "microchip,lan966"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + clock-frequency = <600000000>; + reg = <0x0>; + }; + }; + + clocks { + sys_clk: sys_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <162500000>; + }; + + cpu_clk: cpu_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + ddr_clk: ddr_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + nic_clk: nic_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + clks: clock-controller@e00c00a8 { + compatible = "microchip,lan966x-gck"; + #clock-cells = <1>; + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>; + clock-names = "cpu", "ddr", "sys"; + reg = <0xe00c00a8 0x38>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <37500000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flx0: flexcom@e0040000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0040000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + status = "disabled"; + }; + + flx1: flexcom@e0044000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0044000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0044000 0x800>; + status = "disabled"; + }; + + trng: rng@e0048000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xe0048000 0x100>; + clocks = <&nic_clk>; + }; + + aes: crypto@e004c000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xe004c000 0x100>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>, + <&dma0 AT91_XDMAC_DT_PERID(12)>; + dma-names = "rx", "tx"; + clocks = <&nic_clk>; + clock-names = "aes_clk"; + }; + + flx2: flexcom@e0060000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0060000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0060000 0x800>; + status = "disabled"; + }; + + flx3: flexcom@e0064000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0064000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0064000 0x800>; + status = "disabled"; + + usart3: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = ; + clocks = <&nic_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + + dma0: dma-controller@e0068000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe0068000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&nic_clk>; + clock-names = "dma_clk"; + }; + + sha: crypto@e006c000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe006c000 0xec>; + interrupts = ; + dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>; + dma-names = "tx"; + clocks = <&nic_clk>; + clock-names = "sha_clk"; + }; + + flx4: flexcom@e0070000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0070000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0070000 0x800>; + status = "disabled"; + }; + + timer0: timer@e008c000 { + compatible = "snps,dw-apb-timer"; + reg = <0xe008c000 0x400>; + clocks = <&nic_clk>; + clock-names = "timer"; + interrupts = ; + }; + + watchdog: watchdog@e0090000 { + compatible = "snps,dw-wdt"; + reg = <0xe0090000 0x1000>; + interrupts = ; + clocks = <&nic_clk>; + status = "disabled"; + }; + + can0: can@e081c000 { + compatible = "bosch,m_can"; + reg = <0xe081c000 0xfc>, <0x00100000 0x4000>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&clks GCK_ID_MCAN0>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + gpio: pinctrl@e2004064 { + compatible = "microchip,lan966x-pinctrl"; + reg = <0xe2004064 0xb4>, + <0xe2010024 0x138>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 78>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,gic-400", "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupts = ; + interrupt-controller; + reg = <0xe8c11000 0x1000>, + <0xe8c12000 0x2000>, + <0xe8c14000 0x2000>, + <0xe8c16000 0x2000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts index 57bae2aa910e..cb08aa62d967 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-35xx-devkit.dts @@ -11,3 +11,11 @@ model = "LogicPD Zoom OMAP35xx Torpedo Development Kit"; compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3430", "ti,omap3"; }; + +&omap3_pmx_core { + isp1763_pins: pinmux_isp1763_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE4) /* sdmmc1_dat6.gpio_128 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts index 5532db04046c..07ea822fe405 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts +++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts @@ -85,3 +85,12 @@ >; }; }; + +/* The gpio muxing between omap3530 and dm3730 is different for GPIO_128 */ +&omap3_pmx_wkup { + isp1763_pins: pinmux_isp1763_pins { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a58, PIN_INPUT_PULLUP | MUX_MODE4) /* reserved.gpio_128 */ + >; + }; +}; diff --git a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi index 533a47bc4a53..b4664ab00256 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi @@ -93,7 +93,8 @@ &gpmc { ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */ - 1 0 0x2c000000 0x1000000>; /* CS1: 16MB for LAN9221 */ + 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */ + 6 0 0x28000000 0x1000000>; /* CS6: 16MB for ISP1763 */ ethernet@gpmc { pinctrl-names = "default"; @@ -102,6 +103,44 @@ interrupts = <1 IRQ_TYPE_LEVEL_LOW>; /* gpio129 */ reg = <1 0 0xff>; }; + + usb@6,0 { + pinctrl-names = "default"; + pinctrl-0 = <&isp1763_pins>; + compatible = "nxp,usb-isp1763"; + reg = <0x6 0x0 0xff>; + interrupt-parent = <&gpio5>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host"; + bus-width = <16>; + dr_mode = "host"; + gpmc,mux-add-data = <0>; + gpmc,device-width = <2>; + gpmc,wait-pin = <0>; + gpmc,burst-length = <4>; + gpmc,cycle2cycle-samecsen = <1>; + gpmc,cycle2cycle-diffcsen = <1>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <45>; + gpmc,cs-wr-off-ns = <45>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <0>; + gpmc,adv-wr-off-ns = <0>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <45>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <25>; + gpmc,rd-cycle-ns = <60>; + gpmc,wr-cycle-ns = <45>; + gpmc,access-ns = <35>; + gpmc,page-burst-access-ns = <0>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <60>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <5>; + gpmc,wr-access-ns = <20>; + }; }; &hdqw1w { diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi index 0bee517797f4..441a917b88ba 100644 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -8,6 +8,40 @@ #include +/ { + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + &imi { reg = <0xa0000000 0x16000>; }; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi new file mode 100644 index 000000000000..34df472fed71 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd201-som2d01.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + * Author: Romain Perier + */ + +/ { + reg_vcc_dram: regulator-vcc-dram { + compatible = "regulator-fixed"; + regulator-name = "vcc_dram"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts new file mode 100644 index 000000000000..f25a04c98ccb --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-100ask-dongshanpione.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" + +/ { + model = "DongShanPi One"; + compatible = "100ask,dongshanpione", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts new file mode 100644 index 000000000000..1bbbf47132dc --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-miyoo-mini.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" + +/ { + model = "Miyoo Mini"; + compatible = "miyoo,miyoo-mini", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&pm_uart { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts new file mode 100644 index 000000000000..b15c40762bc0 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-sbc2d06-v1b-22w.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + * Author: Romain Perier + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi" +#include + +/ { + model = "Wireless Tag IDO-SBC2D06-1VB-22W"; + compatible = "wirelesstag,ido-sbc2d06-v1b-22w", "mstar,infinity2m"; + + leds { + compatible = "gpio-leds"; + sys_led { + gpios = <&gpio SSD20XD_GPIO_GPIO85 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi new file mode 100644 index 000000000000..d877aff85033 --- /dev/null +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-wirelesstag-ido-som2d01.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 thingy.jp. + * Author: Daniel Palmer + * Author: Romain Perier + */ + +/dts-v1/; +#include "mstar-infinity2m-ssd202d.dtsi" +#include "mstar-infinity2m-ssd201-som2d01.dtsi" + +/ { + model = "Wireless Tag IDO-SOM2D01 (SSD202D)"; + compatible = "wirelesstag,ido-som2d01", "mstar,infinity2m"; + + aliases { + serial0 = &pm_uart; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +®_vcc_dram { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; +}; diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi index 7a5e28b33f96..6f067da61ba3 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi @@ -6,6 +6,11 @@ #include "mstar-infinity2m.dtsi" +&gpio { + compatible = "sstar,ssd20xd-gpio"; + status = "okay"; +}; + &smpctrl { compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; status = "okay"; diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi index 6d4d1d224e96..1b485efd7156 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -6,11 +6,28 @@ #include "mstar-infinity.dtsi" +&cpu0_opp_table { + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; +}; + &cpus { cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; + operating-points-v2 = <&cpu0_opp_table>; reg = <0x1>; + clocks = <&cpupll>; + clock-names = "cpuclk"; }; }; diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mstar-infinity3.dtsi index 9857e2a9934d..a56cf29e5d82 100644 --- a/arch/arm/boot/dts/mstar-infinity3.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3.dtsi @@ -6,6 +6,64 @@ #include "mstar-infinity.dtsi" +&cpu0_opp_table { + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + // overclock frequencies below, shown to work fine up to 1.3 GHz + opp-108000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1188000000 { + opp-hz = /bits/ 64 <1188000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1404000000 { + opp-hz = /bits/ 64 <1404000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1458000000 { + opp-hz = /bits/ 64 <1458000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; +}; + &imi { reg = <0xa0000000 0x20000>; }; diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 89ebfe4f29da..c26ba9b7b6dd 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -21,6 +21,8 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; + clocks = <&cpupll>; + clock-names = "cpuclk"; }; }; @@ -155,6 +157,13 @@ clocks = <&xtal>; }; + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <0>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; + gpio: gpio@207800 { #gpio-cells = <2>; reg = <0x207800 0x200>; diff --git a/arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts b/arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts new file mode 100644 index 000000000000..b057e037f940 --- /dev/null +++ b/arch/arm/boot/dts/mt6582-prestigio-pmt5008-3g.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Maxim Kutnij + */ + +/dts-v1/; +#include "mt6582.dtsi" + +/ { + model = "Prestigio PMT5008 3G"; + compatible = "prestigio,pmt5008-3g", "mediatek,mt6582"; + + aliases { + bootargs = "console=ttyS0,921600n8 earlyprintk"; + serial0 = &uart0; + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mt6582.dtsi b/arch/arm/boot/dts/mt6582.dtsi new file mode 100644 index 000000000000..4263371784cd --- /dev/null +++ b/arch/arm/boot/dts/mt6582.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Maxim Kutnij + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt6582"; + interrupt-parent = <&sysirq>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + uart_clk: dummy26m { + compatible = "fixed-clock"; + clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + timer: timer@11008000 { + compatible = "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = ; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + sysirq: interrupt-controller@10200100 { + compatible = "mediatek,mt6582-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10200100 0x1c>; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0x10211000 0x1000>, + <0x10212000 0x2000>, + <0x10214000 0x2000>, + <0x10216000 0x2000>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11002000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11003000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11004000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart3: serial@11005000 { + compatible = "mediatek,mt6582-uart", + "mediatek,mt6577-uart"; + reg = <0x11005000 0x400>; + interrupts = ; + clocks = <&uart_clk>; + status = "disabled"; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt6582-wdt", + "mediatek,mt6589-wdt"; + reg = <0x10007000 0x100>; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts index 83f27fbf4e93..3ee61251a16d 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts +++ b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts @@ -8,6 +8,9 @@ #include "nuvoton-wpcm450.dtsi" +#include +#include + / { model = "Supermicro X9SCi-LN4F BMC"; compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450"; @@ -20,6 +23,46 @@ device_type = "memory"; reg = <0 0x08000000>; /* 128 MiB */ }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_pins>; + + uid { + label = "UID button"; + linux,code = ; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + uid { + label = "UID"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + + heartbeat { + label = "heartbeat"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pinctrl { + key_pins: mux-keys { + groups = "gspi", "sspi"; + function = "gpio"; + }; + + led_pins: mux-leds { + groups = "hg3", "hg0", "pwm4"; + function = "gpio"; + }; }; &serial0 { diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index d7cbeb187484..93595850a4c3 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -8,6 +8,17 @@ #address-cells = <1>; #size-cells = <1>; + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -33,12 +44,19 @@ interrupt-parent = <&aic>; ranges; + gcr: syscon@b0000000 { + compatible = "nuvoton,wpcm450-gcr", "syscon", "simple-mfd"; + reg = <0xb0000000 0x200>; + }; + serial0: serial@b8000000 { compatible = "nuvoton,wpcm450-uart"; reg = <0xb8000000 0x20>; reg-shift = <2>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk24m>; + pinctrl-names = "default"; + pinctrl-0 = <&bsp_pins>; status = "disabled"; }; @@ -72,5 +90,371 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0: gpio@0 { + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>, + <4 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + + gpio1: gpio@1 { + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + }; + + gpio2: gpio@2 { + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@3 { + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio4: gpio@4 { + reg = <4>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio5: gpio@5 { + reg = <5>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio6: gpio@6 { + reg = <6>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio7: gpio@7 { + reg = <7>; + gpio-controller; + #gpio-cells = <2>; + }; + + smb3_pins: mux-smb3 { + groups = "smb3"; + function = "smb3"; + }; + + smb4_pins: mux-smb4 { + groups = "smb4"; + function = "smb4"; + }; + + smb5_pins: mux-smb5 { + groups = "smb5"; + function = "smb5"; + }; + + scs1_pins: mux-scs1 { + groups = "scs1"; + function = "scs1"; + }; + + scs2_pins: mux-scs2 { + groups = "scs2"; + function = "scs2"; + }; + + scs3_pins: mux-scs3 { + groups = "scs3"; + function = "scs3"; + }; + + smb0_pins: mux-smb0 { + groups = "smb0"; + function = "smb0"; + }; + + smb1_pins: mux-smb1 { + groups = "smb1"; + function = "smb1"; + }; + + smb2_pins: mux-smb2 { + groups = "smb2"; + function = "smb2"; + }; + + bsp_pins: mux-bsp { + groups = "bsp"; + function = "bsp"; + }; + + hsp1_pins: mux-hsp1 { + groups = "hsp1"; + function = "hsp1"; + }; + + hsp2_pins: mux-hsp2 { + groups = "hsp2"; + function = "hsp2"; + }; + + r1err_pins: mux-r1err { + groups = "r1err"; + function = "r1err"; + }; + + r1md_pins: mux-r1md { + groups = "r1md"; + function = "r1md"; + }; + + rmii2_pins: mux-rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + r2err_pins: mux-r2err { + groups = "r2err"; + function = "r2err"; + }; + + r2md_pins: mux-r2md { + groups = "r2md"; + function = "r2md"; + }; + + kbcc_pins: mux-kbcc { + groups = "kbcc"; + function = "kbcc"; + }; + + dvo0_pins: mux-dvo0 { + groups = "dvo"; + function = "dvo0"; + }; + + dvo3_pins: mux-dvo3 { + groups = "dvo"; + function = "dvo3"; + }; + + clko_pins: mux-clko { + groups = "clko"; + function = "clko"; + }; + + smi_pins: mux-smi { + groups = "smi"; + function = "smi"; + }; + + uinc_pins: mux-uinc { + groups = "uinc"; + function = "uinc"; + }; + + gspi_pins: mux-gspi { + groups = "gspi"; + function = "gspi"; + }; + + mben_pins: mux-mben { + groups = "mben"; + function = "mben"; + }; + + xcs2_pins: mux-xcs2 { + groups = "xcs2"; + function = "xcs2"; + }; + + xcs1_pins: mux-xcs1 { + groups = "xcs1"; + function = "xcs1"; + }; + + sdio_pins: mux-sdio { + groups = "sdio"; + function = "sdio"; + }; + + sspi_pins: mux-sspi { + groups = "sspi"; + function = "sspi"; + }; + + fi0_pins: mux-fi0 { + groups = "fi0"; + function = "fi0"; + }; + + fi1_pins: mux-fi1 { + groups = "fi1"; + function = "fi1"; + }; + + fi2_pins: mux-fi2 { + groups = "fi2"; + function = "fi2"; + }; + + fi3_pins: mux-fi3 { + groups = "fi3"; + function = "fi3"; + }; + + fi4_pins: mux-fi4 { + groups = "fi4"; + function = "fi4"; + }; + + fi5_pins: mux-fi5 { + groups = "fi5"; + function = "fi5"; + }; + + fi6_pins: mux-fi6 { + groups = "fi6"; + function = "fi6"; + }; + + fi7_pins: mux-fi7 { + groups = "fi7"; + function = "fi7"; + }; + + fi8_pins: mux-fi8 { + groups = "fi8"; + function = "fi8"; + }; + + fi9_pins: mux-fi9 { + groups = "fi9"; + function = "fi9"; + }; + + fi10_pins: mux-fi10 { + groups = "fi10"; + function = "fi10"; + }; + + fi11_pins: mux-fi11 { + groups = "fi11"; + function = "fi11"; + }; + + fi12_pins: mux-fi12 { + groups = "fi12"; + function = "fi12"; + }; + + fi13_pins: mux-fi13 { + groups = "fi13"; + function = "fi13"; + }; + + fi14_pins: mux-fi14 { + groups = "fi14"; + function = "fi14"; + }; + + fi15_pins: mux-fi15 { + groups = "fi15"; + function = "fi15"; + }; + + pwm0_pins: mux-pwm0 { + groups = "pwm0"; + function = "pwm0"; + }; + + pwm1_pins: mux-pwm1 { + groups = "pwm1"; + function = "pwm1"; + }; + + pwm2_pins: mux-pwm2 { + groups = "pwm2"; + function = "pwm2"; + }; + + pwm3_pins: mux-pwm3 { + groups = "pwm3"; + function = "pwm3"; + }; + + pwm4_pins: mux-pwm4 { + groups = "pwm4"; + function = "pwm4"; + }; + + pwm5_pins: mux-pwm5 { + groups = "pwm5"; + function = "pwm5"; + }; + + pwm6_pins: mux-pwm6 { + groups = "pwm6"; + function = "pwm6"; + }; + + pwm7_pins: mux-pwm7 { + groups = "pwm7"; + function = "pwm7"; + }; + + hg0_pins: mux-hg0 { + groups = "hg0"; + function = "hg0"; + }; + + hg1_pins: mux-hg1 { + groups = "hg1"; + function = "hg1"; + }; + + hg2_pins: mux-hg2 { + groups = "hg2"; + function = "hg2"; + }; + + hg3_pins: mux-hg3 { + groups = "hg3"; + function = "hg3"; + }; + + hg4_pins: mux-hg4 { + groups = "hg4"; + function = "hg4"; + }; + + hg5_pins: mux-hg5 { + groups = "hg5"; + function = "hg5"; + }; + + hg6_pins: mux-hg6 { + groups = "hg6"; + function = "hg6"; + }; + + hg7_pins: mux-hg7 { + groups = "hg7"; + function = "hg7"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi index 31f59de5190b..7af41361c480 100644 --- a/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi +++ b/arch/arm/boot/dts/openbmc-flash-layout-64.dtsi @@ -28,7 +28,7 @@ partitions { label = "rofs"; }; - rwfs@6000000 { + rwfs@2a00000 { reg = <0x2a00000 0x1600000>; // 22MB label = "rwfs"; }; diff --git a/arch/arm/boot/dts/openbmc-flash-layout.dtsi b/arch/arm/boot/dts/openbmc-flash-layout.dtsi index 6c26524e93e1..b47e14063c38 100644 --- a/arch/arm/boot/dts/openbmc-flash-layout.dtsi +++ b/arch/arm/boot/dts/openbmc-flash-layout.dtsi @@ -20,7 +20,7 @@ partitions { label = "kernel"; }; - rofs@c0000 { + rofs@4c0000 { reg = <0x4c0000 0x1740000>; label = "rofs"; }; diff --git a/arch/arm/boot/dts/ox810se-wd-mbwe.dts b/arch/arm/boot/dts/ox810se-wd-mbwe.dts index 7e2fcb220aea..c59e06ff2423 100644 --- a/arch/arm/boot/dts/ox810se-wd-mbwe.dts +++ b/arch/arm/boot/dts/ox810se-wd-mbwe.dts @@ -103,6 +103,10 @@ }; }; +ða { + status = "okay"; +}; + &uart1 { status = "okay"; diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi index 0755e5864c4a..96c0745f7b70 100644 --- a/arch/arm/boot/dts/ox810se.dtsi +++ b/arch/arm/boot/dts/ox810se.dtsi @@ -81,6 +81,24 @@ ranges; interrupt-parent = <&intc>; + etha: ethernet@40400000 { + compatible = "oxsemi,ox810se-dwmac", "snps,dwmac"; + reg = <0x40400000 0x2000>; + interrupts = <8>; + interrupt-names = "macirq"; + mac-address = [000000000000]; /* Filled in by U-Boot */ + phy-mode = "rgmii"; + + clocks = <&stdclk 6>, <&gmacclk>; + clock-names = "gmac", "stmmaceth"; + resets = <&reset 6>; + + /* Regmap for sys registers */ + oxsemi,sys-ctrl = <&sys>; + + status = "disabled"; + }; + apb-bridge@44000000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts b/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts index f350c4e8c194..2b7e52fda6a7 100644 --- a/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts +++ b/arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts @@ -16,11 +16,35 @@ aliases { serial0 = &blsp1_uart3; + serial1 = &blsp1_uart4; }; chosen { stdout-path = "serial0:115200n8"; }; + + vreg_wlan: wlan-regulator { + compatible = "regulator-fixed"; + + regulator-name = "wl-reg"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_regulator_default_state>; + }; +}; + +&blsp1_i2c1 { + status = "okay"; + + fuel-gauge@55 { + compatible = "ti,bq27421"; + reg = <0x55>; + }; }; &blsp1_i2c5 { @@ -57,14 +81,30 @@ status = "okay"; }; +&blsp1_uart4 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&blsp1_uart4_default_state>; + + bluetooth { + compatible = "brcm,bcm43430a0-bt"; + + max-speed = <3000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&bluetooth_default_state>; + + host-wakeup-gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + }; +}; + &rpm_requests { pm8226-regulators { compatible = "qcom,rpm-pm8226-regulators"; - pm8226_s1: s1 { - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1275000>; - }; pm8226_s3: s3 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; @@ -195,24 +235,55 @@ bus-width = <8>; non-removable; +}; - pinctrl-names = "default"; - pinctrl-0 = <&sdhc1_pin_a>; +&sdhc_3 { + status = "okay"; + + max-frequency = <100000000>; + non-removable; + + vmmc-supply = <&vreg_wlan>; + vqmmc-supply = <&pm8226_l6>; + + #address-cells = <1>; + #size-cells = <0>; + + wifi@1 { + compatible = "brcm,bcm43430a0-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "host-wake"; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_hostwake_default_state>; + }; +}; + +&smbb { + qcom,fast-charge-safe-current = <450000>; + qcom,fast-charge-current-limit = <400000>; + qcom,fast-charge-safe-voltage = <4350000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,auto-recharge-threshold-voltage = <4240000>; + qcom,minimum-input-voltage = <4450000>; }; &tlmm { - sdhc1_pin_a: sdhc1-pin-active { - clk { - pins = "sdc1_clk"; - drive-strength = <10>; - bias-disable; - }; + blsp1_uart4_default_state: blsp1-uart4-default-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + function = "blsp_uart4"; + drive-strength = <8>; + bias-disable; + }; - cmd-data { - pins = "sdc1_cmd", "sdc1_data"; - drive-strength = <10>; - bias-pull-up; - }; + bluetooth_default_state: bluetooth-default-state { + pins = "gpio47", "gpio48"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; }; touch_pins: touch { @@ -234,4 +305,31 @@ output-high; }; }; + + wlan_hostwake_default_state: wlan-hostwake-default-state { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + + wlan_regulator_default_state: wlan-regulator-default-state { + pins = "gpio46"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; +}; + +&usb { + status = "okay"; + extcon = <&smbb>; + dr_mode = "peripheral"; +}; + +&usb_hs_phy { + extcon = <&smbb>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; }; diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index d664ccd454c5..138d6478ac84 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -83,7 +83,7 @@ soc { pinctrl@800000 { - /* eMMMC pins, all 8 data lines connected */ + /* eMMC pins, all 8 data lines connected */ dragon_sdcc1_pins: sdcc1 { mux { pins = "gpio159", "gpio160", "gpio161", @@ -674,14 +674,14 @@ bias-pull-down; }; - /* LVS0 thru 3 and mvs0 are just switches */ + /* LVS0 thru 3 and mvs are just switches */ lvs0 { regulator-always-on; }; lvs1 { }; lvs2 { }; lvs3 { }; - mvs0 {}; + mvs { }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index 9a835335bf78..ca9f73528196 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -212,13 +212,12 @@ }; }; - dsi0: mdss_dsi@4700000 { + dsi0: dsi@4700000 { status = "okay"; vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/ vdd-supply = <&pm8921_l8>; vddio-supply = <&pm8921_lvs7>; avdd-supply = <&pm8921_l11>; - vcss-supply = <&ext_3p3v>; panel@0 { reg = <0>; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 4d562c94c31c..a1c8ae516d21 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -815,6 +815,7 @@ nvmem-cells = <&tsens_calib>, <&tsens_backup>; nvmem-cell-names = "calib", "calib_backup"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; #thermal-sensor-cells = <1>; }; @@ -830,11 +831,12 @@ compatible = "qcom,mmcc-apq8064"; reg = <0x4000000 0x1000>; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; }; l2cc: clock-controller@2011000 { - compatible = "syscon"; + compatible = "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; }; @@ -1238,7 +1240,7 @@ reg = <0x5700000 0x70>; }; - dsi0: mdss_dsi@4700000 { + dsi0: dsi@4700000 { compatible = "qcom,mdss-dsi-ctrl"; label = "MDSS DSI CTRL->0"; #address-cells = <1>; @@ -1268,6 +1270,7 @@ <&dsi0_phy 1>; syscon-sfpb = <&mmss_sfpb>; phys = <&dsi0_phy>; + phy-names = "dsi"; ports { #address-cells = <1>; #size-cells = <0>; @@ -1368,10 +1371,10 @@ pcie: pci@1b500000 { compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; - reg = <0x1b500000 0x1000 - 0x1b502000 0x80 - 0x1b600000 0x100 - 0x0ff00000 0x100000>; + reg = <0x1b500000 0x1000>, + <0x1b502000 0x80>, + <0x1b600000 0x100>, + <0x0ff00000 0x100000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; @@ -1379,8 +1382,8 @@ num-lanes = <1>; #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */ + ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, /* I/O */ + <0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* mem */ interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 7dec0553636e..a9d0566a3190 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -142,7 +142,8 @@ clocks { sleep_clk: sleep_clk { compatible = "fixed-clock"; - clock-frequency = <32768>; + clock-frequency = <32000>; + clock-output-names = "gcc_sleep_clk_src"; #clock-cells = <0>; }; @@ -186,6 +187,7 @@ gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq4019"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x1800000 0x60000>; }; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index c32415f0e66d..4d4f37cebf21 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -139,6 +139,7 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-mdm9615"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; }; @@ -151,7 +152,7 @@ }; l2cc: clock-controller@2011000 { - compatible = "syscon"; + compatible = "qcom,kpss-gcc", "syscon"; reg = <0x02011000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 7d48599502b3..85e56992d2d0 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -72,6 +73,35 @@ rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8226"; qcom,smd-channels = "rpm_requests"; + + rpmpd: power-controller { + compatible = "qcom,msm8226-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; }; }; }; @@ -115,6 +145,8 @@ <&gcc GCC_SDCC1_AHB_CLK>, <&xo_board>; clock-names = "core", "iface", "xo"; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc1_default_state>; status = "disabled"; }; @@ -129,6 +161,8 @@ <&gcc GCC_SDCC2_AHB_CLK>, <&xo_board>; clock-names = "core", "iface", "xo"; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc2_default_state>; status = "disabled"; }; @@ -143,6 +177,8 @@ <&gcc GCC_SDCC3_AHB_CLK>, <&xo_board>; clock-names = "core", "iface", "xo"; + pinctrl-names = "default"; + pinctrl-0 = <&sdhc3_default_state>; status = "disabled"; }; @@ -229,6 +265,44 @@ #size-cells = <0>; }; + usb: usb@f9a55000 { + compatible = "qcom,ci-hdrc"; + reg = <0xf9a55000 0x200>, + <0xf9a55200 0x200>; + interrupts = ; + clocks = <&gcc GCC_USB_HS_AHB_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + clock-names = "iface", "core"; + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <75000000>; + resets = <&gcc GCC_USB_HS_BCR>; + reset-names = "core"; + phy_type = "ulpi"; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + ahb-burst-config = <0>; + phy-names = "usb-phy"; + phys = <&usb_hs_phy>; + status = "disabled"; + #reset-cells = <1>; + + ulpi { + usb_hs_phy: phy { + compatible = "qcom,usb-hs-phy-msm8226", + "qcom,usb-hs-phy"; + #phy-cells = <0>; + clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "sleep"; + resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; + reset-names = "phy", "por"; + qcom,init-seq = /bits/ 8 <0x0 0x44 + 0x1 0x68 0x2 0x24 0x3 0x13>; + }; + }; + }; + gcc: clock-controller@fc400000 { compatible = "qcom,gcc-msm8226"; reg = <0xfc400000 0x4000>; @@ -281,6 +355,57 @@ drive-strength = <2>; bias-disable; }; + + sdhc1_default_state: sdhc1-default-state { + clk { + pins = "sdc1_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc2_default_state: sdhc2-default-state { + clk { + pins = "sdc2_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data { + pins = "sdc2_cmd", "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + sdhc3_default_state: sdhc3-default-state { + clk { + pins = "gpio44"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; + + cmd { + pins = "gpio43"; + function = "sdc3"; + drive-strength = <8>; + bias-pull-up; + }; + + data { + pins = "gpio39", "gpio40", "gpio41", "gpio42"; + function = "sdc3"; + drive-strength = <8>; + bias-pull-up; + }; + }; }; restart@fc4ab000 { diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 1e8aab357f9c..a258abb23a64 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -126,6 +126,7 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8660"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; }; @@ -390,7 +391,7 @@ }; l2cc: clock-controller@2082000 { - compatible = "syscon"; + compatible = "qcom,kpss-gcc", "syscon"; reg = <0x02082000 0x1000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 4af01039c3b2..d1fd0fe12ffe 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -279,7 +279,7 @@ pinctrl-0 = <&spi1_default>; spi@16080000 { status = "okay"; - eth@0 { + ethernet@0 { compatible = "micrel,ks8851"; reg = <0>; interrupt-parent = <&msmgpio>; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 2a0ec97a264f..4a2d74cf01d2 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -78,6 +78,15 @@ }; }; + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -118,6 +127,7 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8960"; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; }; @@ -133,11 +143,12 @@ compatible = "qcom,mmcc-msm8960"; reg = <0x4000000 0x1000>; #clock-cells = <1>; + #power-domain-cells = <1>; #reset-cells = <1>; }; l2cc: clock-controller@2011000 { - compatible = "syscon"; + compatible = "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; }; @@ -146,7 +157,9 @@ reg = <0x108000 0x1000>; qcom,ipc = <&l2cc 0x8 2>; - interrupts = <0 19 0>, <0 21 0>, <0 22 0>; + interrupts = , + , + ; interrupt-names = "ack", "err", "wakeup"; regulators { @@ -192,7 +205,7 @@ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; reg = <0x16440000 0x1000>, <0x16400000 0x1000>; - interrupts = <0 154 0x0>; + interrupts = ; clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -249,15 +262,6 @@ clock-names = "core"; }; - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; - amba { compatible = "simple-bus"; #address-cells = <1>; @@ -318,7 +322,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x16080000 0x1000>; - interrupts = <0 147 0>; + interrupts = ; spi-max-frequency = <24000000>; cs-gpios = <&msmgpio 8 0>; diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi index dddb5150dfd7..b3d0f7b5874d 100644 --- a/arch/arm/boot/dts/qcom-pm8226.dtsi +++ b/arch/arm/boot/dts/qcom-pm8226.dtsi @@ -16,6 +16,39 @@ debounce = <15625>; bias-pull-up; }; + + smbb: charger@1000 { + compatible = "qcom,pm8226-charger"; + reg = <0x1000>; + interrupts = <0x0 0x10 7 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x10 4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x14 1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "chg-done", + "chg-fast", + "chg-trkl", + "bat-temp-ok", + "bat-present", + "chg-gone", + "usb-valid", + "dc-valid"; + + chg_otg: otg-vbus { }; + }; + + pm8226_mpps: mpps@a000 { + compatible = "qcom,pm8226-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8226_mpps 0 0 8>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pm8226_1: pm8226@1 { @@ -23,5 +56,15 @@ reg = <0x1 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm8226_spmi_regulators: pm8226-regulators { + compatible = "qcom,pm8226-regulators"; + }; + + pm8226_vib: vibrator@c000 { + compatible = "qcom,pm8916-vib"; + reg = <0xc000>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 8ac0492c7659..d455795da44c 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -413,7 +413,7 @@ <0x40000000 0xf1d>, <0x40000f20 0xc8>, <0x40001000 0x1000>, - <0x40002000 0x10000>, + <0x40200000 0x100000>, <0x01c03000 0x3000>; reg-names = "parf", "dbi", "elbi", "atu", "addr_space", "mmio"; @@ -536,7 +536,7 @@ reg = <0x0c264000 0x1000>; }; - spmi_bus: qcom,spmi@c440000 { + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0c440000 0x0000d00>, <0x0c600000 0x2000000>, diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index a01f3def1c69..0af63ddc4473 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -266,7 +266,7 @@ function = "lcd0"; }; - lcd0_mux { + lcd0-mux-hog { /* DBGMD/LCDC0/FSIA MUX */ gpio-hog; gpios = <176 0>; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 3c8a7c8b1fdd..4e58c54cde17 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -91,10 +91,10 @@ &gpio0 { /* Disable hogging GP0_18 to output LOW */ - /delete-node/ qspi_en; + /delete-node/ qspi-en-hog; /* Hog GP0_18 to output HIGH to enable VIN2 */ - vin2_en { + vin2-en-hog { gpio-hog; gpios = <18 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index a5a79cdbcd0e..64102b664055 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -226,7 +226,7 @@ }; &gpio0 { - touch-interrupt { + touch-interrupt-hog { gpio-hog; gpios = <24 GPIO_ACTIVE_LOW>; input; @@ -234,7 +234,7 @@ }; &gpio1 { - can-trx-en-gpio{ + can-trx-en-hog { gpio-hog; gpios = <28 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi index 5621c9ed698f..b281a4d164b0 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi @@ -37,7 +37,7 @@ &gpio0 { /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */ - qspi_en { + qspi-en-hog { gpio-hog; gpios = <18 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts index b024621c9981..644802285249 100644 --- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts +++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts @@ -116,7 +116,7 @@ }; &gpio2 { - interrupt-fixup { + interrupt-fixup-hog { gpio-hog; gpios = <29 GPIO_ACTIVE_HIGH>; line-name = "hdmi-hpd-int"; diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts index 4e57ae2688fc..3f8f3ce87e12 100644 --- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts @@ -26,3 +26,8 @@ &uart0 { status = "okay"; }; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index c47896e4ab58..636a6ab31c58 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -66,6 +66,22 @@ interrupt-parent = <&gic>; ranges; + wdt0: watchdog@40008000 { + compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; + reg = <0x40008000 0x1000>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; + + wdt1: watchdog@40009000 { + compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; + reg = <0x40009000 0x1000>; + interrupts = ; + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; + status = "disabled"; + }; + sysctrl: system-controller@4000c000 { compatible = "renesas,r9a06g032-sysctrl"; reg = <0x4000c000 0x1000>; @@ -173,6 +189,17 @@ status = "okay"; }; + nand_controller: nand-controller@40102000 { + compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc"; + reg = <0x40102000 0x2000>; + interrupts = ; + clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; + clock-names = "hclk", "eclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@44101000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller; diff --git a/arch/arm/boot/dts/rk3188-px3-evb.dts b/arch/arm/boot/dts/rk3188-px3-evb.dts index 39c60426c9c9..fc478ac4e781 100644 --- a/arch/arm/boot/dts/rk3188-px3-evb.dts +++ b/arch/arm/boot/dts/rk3188-px3-evb.dts @@ -212,7 +212,7 @@ regulator-name = "wl_18"; }; - lcd_33: SWITCH_REG1 { + lcd_33: SWITCH_REG { regulator-name = "lcd_33"; }; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 45a9d9b908d2..26b9bbe310af 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -980,7 +980,6 @@ clock-names = "aclk", "hclk", "sclk", "apb_pclk"; resets = <&cru SRST_CRYPTO>; reset-names = "crypto-rst"; - status = "okay"; }; iep_mmu: iommu@ff900800 { diff --git a/arch/arm/boot/dts/rv1108-elgin-r1.dts b/arch/arm/boot/dts/rv1108-elgin-r1.dts index f62c9f7af79d..0c99a5934ebf 100644 --- a/arch/arm/boot/dts/rv1108-elgin-r1.dts +++ b/arch/arm/boot/dts/rv1108-elgin-r1.dts @@ -72,6 +72,7 @@ interrupt-parent = <&gpio0>; interrupts = ; rockchip,system-power-controller; + #clock-cells = <0>; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; diff --git a/arch/arm/boot/dts/rv1108-evb.dts b/arch/arm/boot/dts/rv1108-evb.dts index fe5fc9bf75c9..46cad7cb94bf 100644 --- a/arch/arm/boot/dts/rv1108-evb.dts +++ b/arch/arm/boot/dts/rv1108-evb.dts @@ -85,6 +85,7 @@ interrupt-parent = <&gpio0>; interrupts = ; rockchip,system-power-controller; + #clock-cells = <0>; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi index 92439ee5d7de..20a7d72827c2 100644 --- a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi @@ -12,66 +12,66 @@ * Pin banks */ - gpa: gpa { + gpa: gpa-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpc: gpc { + gpc: gpc-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpd: gpd { + gpd: gpd-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpe: gpe { + gpe: gpe-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpf: gpf { + gpf: gpf-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpg: gpg { + gpg: gpg-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gph: gph { + gph: gph-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpj: gpj { + gpj: gpj-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpk: gpk { + gpk: gpk-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpl: gpl { + gpl: gpl-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpm: gpm { + gpm: gpm-gpio-bank { gpio-controller; #gpio-cells = <2>; }; @@ -80,92 +80,92 @@ * Pin groups */ - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gph-0", "gph-1"; samsung,pin-function = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gph-8", "gph-9"; samsung,pin-function = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gph-2", "gph-3"; samsung,pin-function = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gph-10", "gph-11"; samsung,pin-function = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gph-4", "gph-5"; samsung,pin-function = ; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gph-6", "gph-7"; samsung,pin-function = ; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gph-6", "gph-7"; samsung,pin-function = ; }; - extuart_clk: extuart-clk { + extuart_clk: extuart-clk-pins { samsung,pins = "gph-12"; samsung,pin-function = ; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpe-14", "gpe-15"; samsung,pin-function = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpe-11", "gpe-12", "gpe-13"; samsung,pin-function = ; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpe-5"; samsung,pin-function = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpe-6"; samsung,pin-function = ; }; - sd0_bus1: sd0-bus1 { + sd0_bus1: sd0-bus1-pins { samsung,pins = "gpe-7"; samsung,pin-function = ; }; - sd0_bus4: sd0-bus4 { + sd0_bus4: sd0-bus4-pins { samsung,pins = "gpe-8", "gpe-9", "gpe-10"; samsung,pin-function = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpl-8"; samsung,pin-function = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpl-9"; samsung,pin-function = ; }; - sd1_bus1: sd1-bus1 { + sd1_bus1: sd1-bus1-pins { samsung,pins = "gpl-0"; samsung,pin-function = ; }; - sd1_bus4: sd1-bus4 { + sd1_bus4: sd1-bus4-pins { samsung,pins = "gpl-1", "gpl-2", "gpl-3"; samsung,pin-function = ; }; diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 285555b9ed94..17097da36f5e 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -193,12 +193,12 @@ }; &pinctrl0 { - gpio_leds: gpio-leds { + gpio_leds: gpio-leds-pins { samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; samsung,pin-pud = ; }; - gpio_keys: gpio-keys { + gpio_keys: gpio-keys-pins { samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", "gpn-4", "gpn-5", "gpl-11", "gpl-12"; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi index 8e9594d64b57..0a3186d57cb5 100644 --- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi @@ -16,111 +16,111 @@ * Pin banks */ - gpa: gpa { + gpa: gpa-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpc: gpc { + gpc: gpc-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpd: gpd { + gpd: gpd-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpe: gpe { + gpe: gpe-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpf: gpf { + gpf: gpf-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpg: gpg { + gpg: gpg-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gph: gph { + gph: gph-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpi: gpi { + gpi: gpi-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpj: gpj { + gpj: gpj-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpk: gpk { + gpk: gpk-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpl: gpl { + gpl: gpl-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpm: gpm { + gpm: gpm-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpn: gpn { + gpn: gpn-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpo: gpo { + gpo: gpo-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpp: gpp { + gpp: gpp-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpq: gpq { + gpq: gpq-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -131,225 +131,225 @@ * Pin groups */ - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa-0", "gpa-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa-2", "gpa-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa-4", "gpa-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa-6", "gpa-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - ext_dma_0: ext-dma-0 { + ext_dma_0: ext-dma-0-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - ext_dma_1: ext-dma-1 { + ext_dma_1: ext-dma-1-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - irda_data_0: irda-data-0 { + irda_data_0: irda-data-0-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - irda_data_1: irda-data-1 { + irda_data_1: irda-data-1-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - irda_sdbw: irda-sdbw { + irda_sdbw: irda-sdbw-pins { samsung,pins = "gpb-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpb-5", "gpb-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { /* S3C6410-only */ samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpc-0", "gpc-1", "gpc-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi0_cs: spi0-cs { + spi0_cs: spi0-cs-pins { samsung,pins = "gpc-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpc-4", "gpc-5", "gpc-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi1_cs: spi1-cs { + spi1_cs: spi1-cs-pins { samsung,pins = "gpc-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpg-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpg-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_bus1: sd0-bus1 { + sd0_bus1: sd0-bus1-pins { samsung,pins = "gpg-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_bus4: sd0-bus4 { + sd0_bus4: sd0-bus4-pins { samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpg-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gph-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gph-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_bus1: sd1-bus1 { + sd1_bus1: sd1-bus1-pins { samsung,pins = "gph-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_bus4: sd1-bus4 { + sd1_bus4: sd1-bus4-pins { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_bus8: sd1-bus8 { + sd1_bus8: sd1-bus8-pins { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", "gph-6", "gph-7", "gph-8", "gph-9"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpg-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_bus1: sd2-bus1 { + sd2_bus1: sd2-bus1-pins { samsung,pins = "gph-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_bus4: sd2-bus4 { + sd2_bus4: sd2-bus4-pins { samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s0_cdclk: i2s0-cdclk { + i2s0_cdclk: i2s0-cdclk-pins { samsung,pins = "gpd-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s1_cdclk: i2s1-cdclk { + i2s1_cdclk: i2s1-cdclk-pins { samsung,pins = "gpe-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { /* S3C6410-only */ samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", "gph-8", "gph-9"; @@ -357,50 +357,50 @@ samsung,pin-pud = ; }; - i2s2_cdclk: i2s2-cdclk { + i2s2_cdclk: i2s2-cdclk-pins { /* S3C6410-only */ samsung,pins = "gph-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm0_bus: pcm0-bus { + pcm0_bus: pcm0-bus-pins { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm0_extclk: pcm0-extclk { + pcm0_extclk: pcm0-extclk-pins { samsung,pins = "gpd-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm1_extclk: pcm1-extclk { + pcm1_extclk: pcm1-extclk-pins { samsung,pins = "gpe-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - ac97_bus_0: ac97-bus-0 { + ac97_bus_0: ac97-bus-0-pins { samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - ac97_bus_1: ac97-bus-1 { + ac97_bus_1: ac97-bus-1-pins { samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - cam_port: cam-port { + cam_port: cam-port-pins { samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", "gpf-5", "gpf-6", "gpf-7", "gpf-8", "gpf-9", "gpf-10", "gpf-11", "gpf-12"; @@ -408,242 +408,242 @@ samsung,pin-pud = ; }; - cam_rst: cam-rst { + cam_rst: cam-rst-pins { samsung,pins = "gpf-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - cam_field: cam-field { + cam_field: cam-field-pins { /* S3C6410-only */ samsung,pins = "gpb-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - pwm_extclk: pwm-extclk { + pwm_extclk: pwm-extclk-pins { samsung,pins = "gpf-13"; samsung,pin-function = ; samsung,pin-pud = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpf-14"; samsung,pin-function = ; samsung,pin-pud = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpf-15"; samsung,pin-function = ; samsung,pin-pud = ; }; - clkout0: clkout-0 { + clkout0: clkout-0-pins { samsung,pins = "gpf-14"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col0_0: keypad-col0-0 { + keypad_col0_0: keypad-col0-0-pins { samsung,pins = "gph-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col1_0: keypad-col1-0 { + keypad_col1_0: keypad-col1-0-pins { samsung,pins = "gph-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col2_0: keypad-col2-0 { + keypad_col2_0: keypad-col2-0-pins { samsung,pins = "gph-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col3_0: keypad-col3-0 { + keypad_col3_0: keypad-col3-0-pins { samsung,pins = "gph-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col4_0: keypad-col4-0 { + keypad_col4_0: keypad-col4-0-pins { samsung,pins = "gph-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col5_0: keypad-col5-0 { + keypad_col5_0: keypad-col5-0-pins { samsung,pins = "gph-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col6_0: keypad-col6-0 { + keypad_col6_0: keypad-col6-0-pins { samsung,pins = "gph-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col7_0: keypad-col7-0 { + keypad_col7_0: keypad-col7-0-pins { samsung,pins = "gph-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col0_1: keypad-col0-1 { + keypad_col0_1: keypad-col0-1-pins { samsung,pins = "gpl-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col1_1: keypad-col1-1 { + keypad_col1_1: keypad-col1-1-pins { samsung,pins = "gpl-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col2_1: keypad-col2-1 { + keypad_col2_1: keypad-col2-1-pins { samsung,pins = "gpl-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col3_1: keypad-col3-1 { + keypad_col3_1: keypad-col3-1-pins { samsung,pins = "gpl-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col4_1: keypad-col4-1 { + keypad_col4_1: keypad-col4-1-pins { samsung,pins = "gpl-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col5_1: keypad-col5-1 { + keypad_col5_1: keypad-col5-1-pins { samsung,pins = "gpl-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col6_1: keypad-col6-1 { + keypad_col6_1: keypad-col6-1-pins { samsung,pins = "gpl-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col7_1: keypad-col7-1 { + keypad_col7_1: keypad-col7-1-pins { samsung,pins = "gpl-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row0_0: keypad-row0-0 { + keypad_row0_0: keypad-row0-0-pins { samsung,pins = "gpk-8"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row1_0: keypad-row1-0 { + keypad_row1_0: keypad-row1-0-pins { samsung,pins = "gpk-9"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row2_0: keypad-row2-0 { + keypad_row2_0: keypad-row2-0-pins { samsung,pins = "gpk-10"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row3_0: keypad-row3-0 { + keypad_row3_0: keypad-row3-0-pins { samsung,pins = "gpk-11"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row4_0: keypad-row4-0 { + keypad_row4_0: keypad-row4-0-pins { samsung,pins = "gpk-12"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row5_0: keypad-row5-0 { + keypad_row5_0: keypad-row5-0-pins { samsung,pins = "gpk-13"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row6_0: keypad-row6-0 { + keypad_row6_0: keypad-row6-0-pins { samsung,pins = "gpk-14"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row7_0: keypad-row7-0 { + keypad_row7_0: keypad-row7-0-pins { samsung,pins = "gpk-15"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row0_1: keypad-row0-1 { + keypad_row0_1: keypad-row0-1-pins { samsung,pins = "gpn-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row1_1: keypad-row1-1 { + keypad_row1_1: keypad-row1-1-pins { samsung,pins = "gpn-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row2_1: keypad-row2-1 { + keypad_row2_1: keypad-row2-1-pins { samsung,pins = "gpn-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row3_1: keypad-row3-1 { + keypad_row3_1: keypad-row3-1-pins { samsung,pins = "gpn-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row4_1: keypad-row4-1 { + keypad_row4_1: keypad-row4-1-pins { samsung,pins = "gpn-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row5_1: keypad-row5-1 { + keypad_row5_1: keypad-row5-1-pins { samsung,pins = "gpn-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row6_1: keypad-row6-1 { + keypad_row6_1: keypad-row6-1-pins { samsung,pins = "gpn-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row7_1: keypad-row7-1 { + keypad_row7_1: keypad-row7-1-pins { samsung,pins = "gpn-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - lcd_ctrl: lcd-ctrl { + lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; samsung,pin-function = ; samsung,pin-pud = ; }; - lcd_data16: lcd-data-width16 { + lcd_data16: lcd-data-width16-pins { samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-3", @@ -652,7 +652,7 @@ samsung,pin-pud = ; }; - lcd_data18: lcd-data-width18 { + lcd_data18: lcd-data-width18-pins { samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", @@ -662,7 +662,7 @@ samsung,pin-pud = ; }; - lcd_data24: lcd-data-width24 { + lcd_data24: lcd-data-width24-pins { samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-8", "gpi-9", "gpi-10", "gpi-11", @@ -673,7 +673,7 @@ samsung,pin-pud = ; }; - hsi_bus: hsi-bus { + hsi_bus: hsi-bus-pins { samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", "gpk-4", "gpk-5", "gpk-6", "gpk-7"; samsung,pin-function = ; diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index cb11a87dbc42..67a7a66e11d5 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -178,20 +178,12 @@ interrupt-parent = <&vic1>; interrupts = <21>; - pctrl_int_map: pinctrl-interrupt-map { - interrupt-map = <0 &vic0 0>, - <1 &vic0 1>, - <2 &vic1 0>, - <3 &vic1 1>; - #address-cells = <0>; - #size-cells = <0>; - #interrupt-cells = <1>; - }; - wakeup-interrupt-controller { compatible = "samsung,s3c64xx-wakeup-eint"; - interrupts = <0>, <1>, <2>, <3>; - interrupt-parent = <&pctrl_int_map>; + interrupts-extended = <&vic0 0>, + <&vic0 1>, + <&vic1 0>, + <&vic1 1>; }; }; }; diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index 6423348034b6..54de3bc77c30 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -391,7 +391,7 @@ }; &pinctrl0 { - t_flash_detect: t-flash-detect { + t_flash_detect: t-flash-detect-pins { samsung,pins = "gph3-4"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 160f8cd9a68d..c8f1c324a6c2 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -645,21 +645,21 @@ }; &pinctrl0 { - bt_reset: bt-reset { + bt_reset: bt-reset-pins { samsung,pins = "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - wlan_bt_en: wlan-bt-en { + wlan_bt_en: wlan-bt-en-pins { samsung,pins = "gpb-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-val = <1>; }; - codec_ldo: codec-ldo { + codec_ldo: codec-ldo-pins { samsung,pins = "gpf3-4"; samsung,pin-function = ; samsung,pin-pud = ; @@ -671,19 +671,19 @@ samsung,pin-drv = ; }; - wlan_gpio_rst: wlan-gpio-rst { + wlan_gpio_rst: wlan-gpio-rst-pins { samsung,pins = "gpg1-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - bt_wake: bt-wake { + bt_wake: bt-wake-pins { samsung,pins = "gpg3-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - gp2a_irq: gp2a-irq { + gp2a_irq: gp2a-irq-pins { samsung,pins = "gph0-2"; samsung,pin-function = ; samsung,pin-pud = ; @@ -698,67 +698,67 @@ samsung,pin-val = <0>; }; - pmic_irq: pmic-irq { + pmic_irq: pmic-irq-pins { samsung,pins = "gph0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - wifi_host_wake: wifi-host-wake { + wifi_host_wake: wifi-host-wake-pins { samsung,pins = "gph2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - bt_host_wake: bt-host-wake { + bt_host_wake: bt-host-wake-pins { samsung,pins = "gph2-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - musb_irq: musq-irq { + musb_irq: musq-irq-pins { samsung,pins = "gph2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - tf_detect: tf-detect { + tf_detect: tf-detect-pins { samsung,pins = "gph3-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - wifi_wake: wifi-wake { + wifi_wake: wifi-wake-pins { samsung,pins = "gph3-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - magnetometer_i2c_pins: yas529-i2c-pins { + magnetometer_i2c_pins: yas529-i2c-pins-pins { samsung,pins = "gpj0-0", "gpj0-1"; samsung,pin-pud = ; samsung,pin-drv = ; }; - ts_irq: ts-irq { + ts_irq: ts-irq-pins { samsung,pins = "gpj0-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - vibrator_ena: vibrator-ena { + vibrator_ena: vibrator-ena-pins { samsung,pins = "gpj1-1"; samsung,pin-pud = ; samsung,pin-drv = ; }; - gp2a_power: gp2a-power { + gp2a_power: gp2a-power-pins { samsung,pins = "gpj1-4"; samsung,pin-function = ; samsung,pin-pud = ; @@ -771,7 +771,7 @@ samsung,pin-drv = ; }; - touchkey_vdd_ena: touchkey-vdd-ena { + touchkey_vdd_ena: touchkey-vdd-ena-pins { samsung,pins = "gpj3-2"; samsung,pin-pud = ; samsung,pin-drv = ; @@ -789,13 +789,13 @@ samsung,pin-drv = ; }; - pmic_i2c_pins: pmic-i2c-pins { + pmic_i2c_pins: pmic-i2c-pins-pins { samsung,pins = "gpj4-0", "gpj4-3"; samsung,pin-pud = ; samsung,pin-drv = ; }; - touchkey_irq: touchkey-irq { + touchkey_irq: touchkey-irq-pins { samsung,pins = "gpj4-1"; samsung,pin-function = ; samsung,pin-pud = ; @@ -820,7 +820,7 @@ samsung,pin-drv = ; }; - panel_rst: panel-rst { + panel_rst: panel-rst-pins { samsung,pins = "mp05-5"; samsung,pin-pud = ; samsung,pin-drv = ; diff --git a/arch/arm/boot/dts/s5pv210-fascinate4g.dts b/arch/arm/boot/dts/s5pv210-fascinate4g.dts index 7427c84f1126..dfb2ee65e4a8 100644 --- a/arch/arm/boot/dts/s5pv210-fascinate4g.dts +++ b/arch/arm/boot/dts/s5pv210-fascinate4g.dts @@ -126,39 +126,39 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep_cfg>; - headset_det: headset-det { + headset_det: headset-det-pins { samsung,pins = "gph0-6", "gph3-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - fg_irq: fg-irq { + fg_irq: fg-irq-pins { samsung,pins = "gph3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - headset_micbias_ena: headset-micbias-ena { + headset_micbias_ena: headset-micbias-ena-pins { samsung,pins = "gpj2-5"; samsung,pin-pud = ; samsung,pin-drv = ; }; - earpath_sel: earpath-sel { + earpath_sel: earpath-sel-pins { samsung,pins = "gpj2-6"; samsung,pin-pud = ; samsung,pin-drv = ; }; - main_micbias_ena: main-micbias-ena { + main_micbias_ena: main-micbias-ena-pins { samsung,pins = "gpj4-2"; samsung,pin-pud = ; samsung,pin-drv = ; }; /* Based on vendor kernel v2.6.35.7 */ - sleep_cfg: sleep-cfg { + sleep_cfg: sleep-state { PIN_SLP(gpa0-0, PREV, NONE); PIN_SLP(gpa0-1, PREV, NONE); PIN_SLP(gpa0-2, PREV, NONE); diff --git a/arch/arm/boot/dts/s5pv210-galaxys.dts b/arch/arm/boot/dts/s5pv210-galaxys.dts index eeec2bdece11..a78caaa1f3c5 100644 --- a/arch/arm/boot/dts/s5pv210-galaxys.dts +++ b/arch/arm/boot/dts/s5pv210-galaxys.dts @@ -150,53 +150,53 @@ pinctrl-names = "default"; pinctrl-0 = <&sleep_cfg>; - fm_i2c_pins: fm-i2c-pins { + fm_i2c_pins: fm-i2c-pins-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-pud = ; samsung,pin-drv = ; }; - headset_det: headset-det { + headset_det: headset-det-pins { samsung,pins = "gph0-6", "gph3-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - fm_irq: fm-irq { + fm_irq: fm-irq-pins { samsung,pins = "gpj2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fm_rst: fm-rst { + fm_rst: fm-rst-pins { samsung,pins = "gpj2-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - earpath_sel: earpath-sel { + earpath_sel: earpath-sel-pins { samsung,pins = "gpj2-6"; samsung,pin-pud = ; samsung,pin-drv = ; }; - massmemory_en: massmemory-en { + massmemory_en: massmemory-en-pins { samsung,pins = "gpj2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - micbias_reg_ena: micbias-reg-ena { + micbias_reg_ena: micbias-reg-ena-pins { samsung,pins = "gpj4-2"; samsung,pin-pud = ; samsung,pin-drv = ; }; /* Based on CyanogenMod 3.0.101 kernel */ - sleep_cfg: sleep-cfg { + sleep_cfg: sleep-state { PIN_SLP(gpa0-0, PREV, NONE); PIN_SLP(gpa0-1, PREV, NONE); PIN_SLP(gpa0-2, PREV, NONE); diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index b8c5172c31dd..ae34e7e57892 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -26,7 +26,7 @@ } &pinctrl0 { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -34,7 +34,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -42,7 +42,7 @@ #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -50,7 +50,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -58,7 +58,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -66,7 +66,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -74,7 +74,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -82,7 +82,7 @@ #interrupt-cells = <2>; }; - gpe0: gpe0 { + gpe0: gpe0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -90,7 +90,7 @@ #interrupt-cells = <2>; }; - gpe1: gpe1 { + gpe1: gpe1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -98,7 +98,7 @@ #interrupt-cells = <2>; }; - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -106,7 +106,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -114,7 +114,7 @@ #interrupt-cells = <2>; }; - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -122,7 +122,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -130,7 +130,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -138,7 +138,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -146,7 +146,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -154,7 +154,7 @@ #interrupt-cells = <2>; }; - gpg3: gpg3 { + gpg3: gpg3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -162,7 +162,7 @@ #interrupt-cells = <2>; }; - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -170,7 +170,7 @@ #interrupt-cells = <2>; }; - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -178,7 +178,7 @@ #interrupt-cells = <2>; }; - gpj2: gpj2 { + gpj2: gpj2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -186,7 +186,7 @@ #interrupt-cells = <2>; }; - gpj3: gpj3 { + gpj3: gpj3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -194,7 +194,7 @@ #interrupt-cells = <2>; }; - gpj4: gpj4 { + gpj4: gpj4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -202,47 +202,47 @@ #interrupt-cells = <2>; }; - gpi: gpi { + gpi: gpi-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp01: mp01 { + mp01: mp01-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp02: mp02 { + mp02: mp02-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp03: mp03 { + mp03: mp03-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp04: mp04 { + mp04: mp04-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp05: mp05 { + mp05: mp05-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp06: mp06 { + mp06: mp06-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - mp07: mp07 { + mp07: mp07-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gph0: gph0 { + gph0: gph0-gpio-bank { gpio-controller; interrupt-controller; interrupt-parent = <&vic0>; @@ -252,7 +252,7 @@ #interrupt-cells = <2>; }; - gph1: gph1 { + gph1: gph1-gpio-bank { gpio-controller; interrupt-controller; interrupt-parent = <&vic0>; @@ -262,7 +262,7 @@ #interrupt-cells = <2>; }; - gph2: gph2 { + gph2: gph2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -270,7 +270,7 @@ #interrupt-cells = <2>; }; - gph3: gph3 { + gph3: gph3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -278,77 +278,77 @@ #interrupt-cells = <2>; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa0-4", "gpa0-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa0-6", "gpa0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_fctl: uart2-fctl { + uart2_fctl: uart2-fctl-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart_audio: uart-audio { + uart_audio: uart-audio-pins { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6"; samsung,pin-function = ; @@ -356,7 +356,7 @@ samsung,pin-drv = ; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = ; @@ -364,7 +364,7 @@ samsung,pin-drv = ; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = ; @@ -372,7 +372,7 @@ samsung,pin-drv = ; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = ; @@ -380,7 +380,7 @@ samsung,pin-drv = ; }; - ac97_bus: ac97-bus { + ac97_bus: ac97-bus-pins { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; samsung,pin-function = ; @@ -388,7 +388,7 @@ samsung,pin-drv = ; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = ; @@ -396,7 +396,7 @@ samsung,pin-drv = ; }; - pcm2_bus: pcm2-bus { + pcm2_bus: pcm2-bus-pins { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = ; @@ -404,371 +404,371 @@ samsung,pin-drv = ; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpc1-0", "gpc1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2c2_bus: i2c2-bus { + i2c2_bus: i2c2-bus-pins { samsung,pins = "gpd1-4", "gpd1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_row0: keypad-row-0 { + keypad_row0: keypad-row-0-pins { samsung,pins = "gph3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_row1: keypad-row-1 { + keypad_row1: keypad-row-1-pins { samsung,pins = "gph3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_row2: keypad-row-2 { + keypad_row2: keypad-row-2-pins { samsung,pins = "gph3-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_row3: keypad-row-3 { + keypad_row3: keypad-row-3-pins { samsung,pins = "gph3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_row4: keypad-row-4 { + keypad_row4: keypad-row-4-pins { samsung,pins = "gph3-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_row5: keypad-row-5 { + keypad_row5: keypad-row-5-pins { samsung,pins = "gph3-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_row6: keypad-row-6 { + keypad_row6: keypad-row-6-pins { samsung,pins = "gph3-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_row7: keypad-row-7 { + keypad_row7: keypad-row-7-pins { samsung,pins = "gph3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_col0: keypad-col-0 { + keypad_col0: keypad-col-0-pins { samsung,pins = "gph2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_col1: keypad-col-1 { + keypad_col1: keypad-col-1-pins { samsung,pins = "gph2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_col2: keypad-col-2 { + keypad_col2: keypad-col-2-pins { samsung,pins = "gph2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_col3: keypad-col-3 { + keypad_col3: keypad-col-3-pins { samsung,pins = "gph2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_col4: keypad-col-4 { + keypad_col4: keypad-col-4-pins { samsung,pins = "gph2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_col5: keypad-col-5 { + keypad_col5: keypad-col-5-pins { samsung,pins = "gph2-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_col6: keypad-col-6 { + keypad_col6: keypad-col-6-pins { samsung,pins = "gph2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - keypad_col7: keypad-col-7 { + keypad_col7: keypad-col-7-pins { samsung,pins = "gph2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpg0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpg0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpg0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpg0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpg1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpg1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpg1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpg1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpg2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpg2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpg2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpg2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus8: sd2-bus-width8 { + sd2_bus8: sd2-bus-width8-pins { samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_clk: sd3-clk { + sd3_clk: sd3-clk-pins { samsung,pins = "gpg3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_cmd: sd3-cmd { + sd3_cmd: sd3-cmd-pins { samsung,pins = "gpg3-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_cd: sd3-cd { + sd3_cd: sd3-cd-pins { samsung,pins = "gpg3-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_bus1: sd3-bus-width1 { + sd3_bus1: sd3-bus-width1-pins { samsung,pins = "gpg3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd3_bus4: sd3-bus-width4 { + sd3_bus4: sd3-bus-width4-pins { samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint0: ext-int0 { + eint0: ext-int0-pins { samsung,pins = "gph0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint8: ext-int8 { + eint8: ext-int8-pins { samsung,pins = "gph1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint15: ext-int15 { + eint15: ext-int15-pins { samsung,pins = "gph1-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint16: ext-int16 { + eint16: ext-int16-pins { samsung,pins = "gph2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - eint31: ext-int31 { + eint31: ext-int31-pins { samsung,pins = "gph3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_a_io: cam-port-a-io { + cam_port_a_io: cam-port-a-io-pins { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4"; @@ -777,21 +777,21 @@ samsung,pin-drv = ; }; - cam_port_a_clk_active: cam-port-a-clk-active { + cam_port_a_clk_active: cam-port-a-clk-active-pins { samsung,pins = "gpe1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_a_clk_idle: cam-port-a-clk-idle { + cam_port_a_clk_idle: cam-port-a-clk-idle-pins { samsung,pins = "gpe1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_b_io: cam-port-b-io { + cam_port_b_io: cam-port-b-io-pins { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; @@ -800,42 +800,42 @@ samsung,pin-drv = ; }; - cam_port_b_clk_active: cam-port-b-clk-active { + cam_port_b_clk_active: cam-port-b-clk-active-pins { samsung,pins = "gpj1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - cam_port_b_clk_idle: cam-port-b-clk-idle { + cam_port_b_clk_idle: cam-port-b-clk-idle-pins { samsung,pins = "gpj1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_ctrl: lcd-ctrl { + lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpd0-0", "gpd0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_sync: lcd-sync { + lcd_sync: lcd-sync-pins { samsung,pins = "gpf0-0", "gpf0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_clk: lcd-clk { + lcd_clk: lcd-clk-pins { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - lcd_data24: lcd-data-width24 { + lcd_data24: lcd-data-width24-pins { samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index ec45ced3cde6..998629a3c34f 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -270,7 +270,7 @@ clock-names = "pclk", "gclk"; }; - sha: sha@f002c000 { + sha: crypto@f002c000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xf002c000 0x100>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; @@ -280,7 +280,6 @@ dma-names = "tx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; clock-names = "sha_clk"; - status = "okay"; }; trng: trng@f0030000 { @@ -288,10 +287,9 @@ reg = <0xf0030000 0x100>; interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; - status = "okay"; }; - aes: aes@f0034000 { + aes: crypto@f0034000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xf0034000 0x100>; interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; @@ -304,10 +302,9 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; clock-names = "aes_clk"; - status = "okay"; }; - tdes: tdes@f0038000 { + tdes: crypto@f0038000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xf0038000 0x100>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; @@ -320,7 +317,6 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; clock-names = "tdes_clk"; - status = "okay"; }; classd: classd@f003c000 { diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 09c741e8ecb8..89c71d419f82 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -306,7 +306,7 @@ status = "disabled"; }; - sha@f0028000 { + sha: crypto@f0028000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xf0028000 0x100>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; @@ -316,10 +316,9 @@ dma-names = "tx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "sha_clk"; - status = "okay"; }; - aes@f002c000 { + aes: crypto@f002c000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xf002c000 0x100>; interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; @@ -332,7 +331,6 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; clock-names = "aes_clk"; - status = "okay"; }; spi0: spi@f8000000 { @@ -415,7 +413,7 @@ pmecc: ecc-engine@f8014070 { compatible = "atmel,sama5d2-pmecc"; reg = <0xf8014070 0x490>, - <0xf8014500 0x100>; + <0xf8014500 0x200>; }; }; @@ -1084,7 +1082,7 @@ #gpio-cells = <2>; }; - tdes@fc044000 { + tdes: crypto@fc044000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xfc044000 0x100>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; @@ -1097,7 +1095,6 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; clock-names = "tdes_clk"; - status = "okay"; }; classd: classd@fc048000 { diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index d1841bffe3c5..8fa423c52592 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -381,7 +381,7 @@ status = "disabled"; }; - sha@f8034000 { + sha: crypto@f8034000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xf8034000 0x100>; interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; @@ -391,7 +391,7 @@ clock-names = "sha_clk"; }; - aes@f8038000 { + aes: crypto@f8038000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xf8038000 0x100>; interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; @@ -402,7 +402,7 @@ clock-names = "aes_clk"; }; - tdes@f803c000 { + tdes: crypto@f803c000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xf803c000 0x100>; interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index f6e3e6f57252..7b9242664875 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -673,7 +673,7 @@ status = "disabled"; }; - aes@fc044000 { + aes: crypto@fc044000 { compatible = "atmel,at91sam9g46-aes"; reg = <0xfc044000 0x100>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; @@ -684,10 +684,9 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; clock-names = "aes_clk"; - status = "okay"; }; - tdes@fc04c000 { + tdes: crpyto@fc04c000 { compatible = "atmel,at91sam9g46-tdes"; reg = <0xfc04c000 0x100>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; @@ -698,10 +697,9 @@ dma-names = "tx", "rx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; clock-names = "tdes_clk"; - status = "okay"; }; - sha@fc050000 { + sha: crypto@fc050000 { compatible = "atmel,at91sam9g46-sha"; reg = <0xfc050000 0x100>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; @@ -710,7 +708,6 @@ dma-names = "tx"; clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; clock-names = "sha_clk"; - status = "okay"; }; hsmc: smc@fc05c000 { diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index eddcfbf4d223..4decd3a91a76 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -30,6 +30,44 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; + clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; + clock-names = "cpu"; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-90000000 { + opp-hz = /bits/ 64 <90000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1050000 1050000 1225000>; + clock-latency-ns = <320000>; + opp-suspend; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1150000 1125000 1225000>; + clock-latency-ns = <320000>; + }; + + opp-1000000002 { + opp-hz = /bits/ 64 <1000000002>; + opp-microvolt = <1250000 1225000 1300000>; + clock-latency-ns = <320000>; }; }; @@ -75,6 +113,45 @@ #size-cells = <1>; ranges; + nfc_sram: sram@600000 { + compatible = "mmio-sram"; + no-memory-wc; + reg = <0x00600000 0x2400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00600000 0x2400>; + }; + + nfc_io: nfc-io@10000000 { + compatible = "atmel,sama5d3-nfc-io", "syscon"; + reg = <0x10000000 0x8000000>; + }; + + ebi: ebi@40000000 { + compatible = "atmel,sama5d3-ebi"; + #address-cells = <2>; + #size-cells = <1>; + atmel,smc = <&hsmc>; + reg = <0x40000000 0x20000000>; + ranges = <0x0 0x0 0x40000000 0x8000000 + 0x1 0x0 0x48000000 0x8000000 + 0x2 0x0 0x50000000 0x8000000 + 0x3 0x0 0x58000000 0x8000000>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK1>; + status = "disabled"; + + nand_controller: nand-controller { + compatible = "atmel,sama5d3-nand-controller"; + atmel,nfc-sram = <&nfc_sram>; + atmel,nfc-io = <&nfc_io>; + ecc-engine = <&pmecc>; + #address-cells = <2>; + #size-cells = <1>; + ranges; + status = "disabled"; + }; + }; + securam: securam@e0000000 { compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram"; reg = <0xe0000000 0x4000>; @@ -83,7 +160,6 @@ #size-cells = <1>; ranges = <0 0xe0000000 0x4000>; no-memory-wc; - status = "okay"; }; secumod: secumod@e0004000 { @@ -181,6 +257,22 @@ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; + hsmc: hsmc@e0808000 { + compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; + reg = <0xe0808000 0x1000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmecc: ecc-engine@e0808070 { + compatible = "atmel,sama5d2-pmecc"; + reg = <0xe0808070 0x490>, + <0xe0808500 0x200>; + }; + }; + qspi0: spi@e080c000 { compatible = "microchip,sama7g5-ospi"; reg = <0xe080c000 0x400>, <0x20000000 0x10000000>; @@ -211,6 +303,102 @@ status = "disabled"; }; + can0: can@e0828000 { + compatible = "bosch,m_can"; + reg = <0xe0828000 0x100>, <0x100000 0x7800>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 61>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can1: can@e082c000 { + compatible = "bosch,m_can"; + reg = <0xe082c000 0x100>, <0x100000 0xbc00>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 62>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can2: can@e0830000 { + compatible = "bosch,m_can"; + reg = <0xe0830000 0x100>, <0x100000 0x10000>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 63>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can3: can@e0834000 { + compatible = "bosch,m_can"; + reg = <0xe0834000 0x100>, <0x110000 0x4400>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 64>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can4: can@e0838000 { + compatible = "bosch,m_can"; + reg = <0xe0838000 0x100>, <0x110000 0x8800>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 65>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; + status = "disabled"; + }; + + can5: can@e083c000 { + compatible = "bosch,m_can"; + reg = <0xe083c000 0x100>, <0x110000 0xcc00>; + reg-names = "m_can", "message_ram"; + interrupts = ; + interrupt-names = "int0", "int1"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; + clock-names = "hclk", "cclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 66>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_SYSPLL>; + assigned-clock-rates = <40000000>; + bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>; + status = "disabled"; + }; + adc: adc@e1000000 { compatible = "microchip,sama7g5-adc"; reg = <0xe1000000 0x200>; @@ -322,6 +510,19 @@ status = "disabled"; }; + eic: interrupt-controller@e1628000 { + compatible = "microchip,sama7g5-eic"; + reg = <0xe1628000 0xec>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "pclk"; + status = "disabled"; + }; + pit64b0: timer@e1800000 { compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b"; reg = <0xe1800000 0x4000>; @@ -338,6 +539,27 @@ clock-names = "pclk", "gclk"; }; + aes: crypto@e1810000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xe1810000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; + clock-names = "aes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, + <&dma0 AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + }; + + sha: crypto@e1814000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe1814000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 83>; + clock-names = "sha_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; + dma-names = "tx"; + }; + flx0: flexcom@e1818000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe1818000 0x200>; @@ -382,8 +604,6 @@ dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>, <&dma0 AT91_XDMAC_DT_PERID(8)>; dma-names = "rx", "tx"; - atmel,use-dma-rx; - atmel,use-dma-tx; status = "disabled"; }; }; @@ -420,6 +640,17 @@ status = "disabled"; }; + tdes: crypto@e2014000 { + compatible = "atmel,at91sam9g46-tdes"; + reg = <0xe2014000 0x100>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 96>; + clock-names = "tdes_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, + <&dma0 AT91_XDMAC_DT_PERID(53)>; + dma-names = "tx", "rx"; + }; + flx4: flexcom@e2018000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xe2018000 0x200>; @@ -558,8 +789,6 @@ dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>, <&dma0 AT91_XDMAC_DT_PERID(22)>; dma-names = "rx", "tx"; - atmel,use-dma-rx; - atmel,use-dma-tx; status = "disabled"; }; }; @@ -584,8 +813,6 @@ dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>, <&dma0 AT91_XDMAC_DT_PERID(24)>; dma-names = "rx", "tx"; - atmel,use-dma-rx; - atmel,use-dma-tx; status = "disabled"; }; }; @@ -618,13 +845,11 @@ uddrc: uddrc@e3800000 { compatible = "microchip,sama7g5-uddrc"; reg = <0xe3800000 0x4000>; - status = "okay"; }; ddr3phy: ddr3phy@e3804000 { compatible = "microchip,sama7g5-ddr3phy"; reg = <0xe3804000 0x1000>; - status = "okay"; }; gic: interrupt-controller@e8c11000 { diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts index 2a3364b26361..a75c059b6727 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts @@ -6,7 +6,7 @@ / { model = "Enclustra Mercury AA1"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; + compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga"; aliases { ethernet0 = &gmac0; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 7edebe20e859..ec7365444a3b 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -6,7 +6,7 @@ / { model = "Altera SOCFPGA Arria 10"; - compatible = "altr,socfpga-arria10", "altr,socfpga"; + compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga"; aliases { ethernet0 = &gmac0; diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index 1b02d46496a8..7f5458d8fccc 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -7,7 +7,7 @@ / { model = "Altera SOCFPGA Arria V SoC Development Kit"; - compatible = "altr,socfpga-arria5", "altr,socfpga"; + compatible = "altr,socfpga-arria5-socdk", "altr,socfpga-arria5", "altr,socfpga"; chosen { bootargs = "earlyprintk"; @@ -50,7 +50,7 @@ }; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts index f6561766d83f..76262f1e5e03 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_chameleon96.dts @@ -24,7 +24,7 @@ reg = <0x0 0x20000000>; /* 512MB */ }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts index 67076e1b1c7f..c8f051fb2bf6 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts @@ -24,7 +24,7 @@ ethernet0 = &gmac1; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 51bb436784e2..253ef139181d 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -50,7 +50,7 @@ }; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index cae9ddd5ed38..3dd99c7c95e0 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -111,7 +111,7 @@ }; }; - regulator_3_3v: vcc3p3-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "VCC3P3"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts index 3f7aa7bf0863..b0003f350e65 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts @@ -26,7 +26,7 @@ ethernet0 = &gmac1; }; - regulator_3_3v: 3-3-v-regulator { + regulator_3_3v: regulator { compatible = "regulator-fixed"; regulator-name = "3.3V"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/ste-ab8500.dtsi b/arch/arm/boot/dts/ste-ab8500.dtsi index 2cf19386a525..35137c6e52ee 100644 --- a/arch/arm/boot/dts/ste-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-ab8500.dtsi @@ -28,26 +28,28 @@ interrupts = ; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; ab8500_clock: clock-controller { compatible = "stericsson,ab8500-clk"; #clock-cells = <1>; }; - ab8500_gpio: ab8500-gpiocontroller { + ab8500_gpio: gpio { compatible = "stericsson,ab8500-gpio"; gpio-controller; #gpio-cells = <2>; }; - ab8500-rtc { + rtc { compatible = "stericsson,ab8500-rtc"; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; - gpadc: ab8500-gpadc { + gpadc: adc { compatible = "stericsson,ab8500-gpadc"; interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, <39 IRQ_TYPE_LEVEL_HIGH>; @@ -120,13 +122,10 @@ }; }; - ab8500_temp { + thermal { compatible = "stericsson,abx500-temp"; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ABX500_TEMP_WARM"; - io-channels = <&gpadc 0x06>, - <&gpadc 0x07>; - io-channel-names = "aux1", "aux2"; }; ab8500_fg { @@ -212,7 +211,7 @@ monitored-battery = <&battery>; }; - ab8500_usb: ab8500_usb { + ab8500_usb: phy { compatible = "stericsson,ab8500-usb"; interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, <96 IRQ_TYPE_LEVEL_HIGH>, @@ -236,7 +235,7 @@ #phy-cells = <0>; }; - ab8500-ponkey { + key { compatible = "stericsson,ab8500-poweron-key"; interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, <7 IRQ_TYPE_LEVEL_HIGH>; @@ -247,29 +246,31 @@ compatible = "stericsson,ab8500-sysctrl"; }; - ab8500-pwm-1 { + pwm@1 { compatible = "stericsson,ab8500-pwm"; + reg = <1>; clocks = <&ab8500_clock AB8500_SYSCLK_INT>; clock-names = "intclk"; + #pwm-cells = <1>; }; - ab8500-pwm-2 { + pwm@2 { compatible = "stericsson,ab8500-pwm"; + reg = <2>; clocks = <&ab8500_clock AB8500_SYSCLK_INT>; clock-names = "intclk"; + #pwm-cells = <1>; }; - ab8500-pwm-3 { + pwm@3 { compatible = "stericsson,ab8500-pwm"; + reg = <3>; clocks = <&ab8500_clock AB8500_SYSCLK_INT>; clock-names = "intclk"; + #pwm-cells = <1>; }; - ab8500-debugfs { - compatible = "stericsson,ab8500-debug"; - }; - - codec: ab8500-codec { + codec: codec { compatible = "stericsson,ab8500-codec"; V-AUD-supply = <&ab8500_ldo_audio_reg>; @@ -283,7 +284,7 @@ stericsson,earpeice-cmv = <950>; /* Units in mV. */ }; - ext_regulators: ab8500-ext-regulators { + ext_regulators: regulator-external { compatible = "stericsson,ab8500-ext-regulator"; ab8500_ext1_reg: ab8500_ext1 { @@ -307,7 +308,7 @@ }; }; - ab8500-regulators { + regulator { compatible = "stericsson,ab8500-regulator"; vin-supply = <&ab8500_ext3_reg>; diff --git a/arch/arm/boot/dts/ste-ab8505.dtsi b/arch/arm/boot/dts/ste-ab8505.dtsi index e98335e9d1cb..131c82508e82 100644 --- a/arch/arm/boot/dts/ste-ab8505.dtsi +++ b/arch/arm/boot/dts/ste-ab8505.dtsi @@ -25,26 +25,28 @@ interrupts = ; interrupt-controller; #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; ab8500_clock: clock-controller { compatible = "stericsson,ab8500-clk"; #clock-cells = <1>; }; - ab8505_gpio: ab8505-gpiocontroller { + ab8505_gpio: gpio { compatible = "stericsson,ab8505-gpio"; gpio-controller; #gpio-cells = <2>; }; - ab8500-rtc { + rtc { compatible = "stericsson,ab8500-rtc"; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; - gpadc: ab8500-gpadc { + gpadc: adc { compatible = "stericsson,ab8500-gpadc"; interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "SW_CONV_END"; @@ -92,8 +94,13 @@ }; }; + thermal { + compatible = "stericsson,abx500-temp"; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ABX500_TEMP_WARM"; + }; + ab8500_fg { - status = "disabled"; compatible = "stericsson,ab8500-fg"; interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, <8 IRQ_TYPE_LEVEL_HIGH>, @@ -111,7 +118,6 @@ }; ab8500_btemp { - status = "disabled"; compatible = "stericsson,ab8500-btemp"; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, <80 IRQ_TYPE_LEVEL_HIGH>, @@ -131,7 +137,6 @@ }; ab8500_charger { - status = "disabled"; compatible = "stericsson,ab8500-charger"; interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, <11 IRQ_TYPE_LEVEL_HIGH>, @@ -170,12 +175,11 @@ }; ab8500_chargalg { - status = "disabled"; compatible = "stericsson,ab8500-chargalg"; monitored-battery = <&battery>; }; - ab8500_usb: ab8500_usb { + ab8500_usb: phy { compatible = "stericsson,ab8500-usb"; interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, <96 IRQ_TYPE_LEVEL_HIGH>, @@ -199,7 +203,7 @@ #phy-cells = <0>; }; - ab8500-ponkey { + key { compatible = "stericsson,ab8500-poweron-key"; interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, <7 IRQ_TYPE_LEVEL_HIGH>; @@ -210,17 +214,15 @@ compatible = "stericsson,ab8500-sysctrl"; }; - ab8500-pwm { + pwm@1 { compatible = "stericsson,ab8500-pwm"; + reg = <1>; clocks = <&ab8500_clock AB8500_SYSCLK_INT>; clock-names = "intclk"; + #pwm-cells = <1>; }; - ab8500-debugfs { - compatible = "stericsson,ab8500-debug"; - }; - - codec: ab8500-codec { + codec: codec { compatible = "stericsson,ab8500-codec"; V-AUD-supply = <&ab8500_ldo_audio_reg>; @@ -233,7 +235,7 @@ stericsson,earpeice-cmv = <950>; /* Units in mV. */ }; - ab8505-regulators { + regulator { compatible = "stericsson,ab8505-regulator"; ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi index 3ccb7b5c7162..9fa024900d53 100644 --- a/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi @@ -9,7 +9,7 @@ soc { prcmu@80157000 { ab8500 { - ab8500-gpiocontroller { + gpio { /* Hog a few default settings */ pinctrl-names = "default"; pinctrl-0 = <&gpio2_default_mode>, diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 718752a0248e..fbaa0ce46427 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -16,7 +16,24 @@ battery: battery { compatible = "simple-battery"; battery-type = "lithium-ion-polymer"; - thermistor-on-batctrl; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + }; + }; + + bat_therm: thermistor { + compatible = "murata,ncp18wb473"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; }; soc { @@ -219,16 +236,16 @@ prcmu@80157000 { ab8500 { - ab8500-gpiocontroller { + gpio { }; - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8500-regulators { + regulator { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; }; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index fb719c8a8eb2..1c9094f24893 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -20,7 +20,24 @@ battery: battery { compatible = "simple-battery"; battery-type = "lithium-ion-polymer"; - thermistor-on-batctrl; + }; + + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + }; + }; + + bat_therm: thermistor { + compatible = "murata,ncp18wb473"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; }; en_3v3_reg: en_3v3 { @@ -384,7 +401,7 @@ prcmu@80157000 { ab8500 { - ab8500-gpiocontroller { + gpio { /* * AB8500 GPIOs are numbered starting from 1, so the first * index 0 is what in the datasheet is called "GPIO1", and @@ -406,13 +423,13 @@ "PM_GPIO42"; /* AB8500 GPIO42 */ }; - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ext_regulators: ab8500-ext-regulators { + ext_regulators: regulator-external { ab8500_ext1_reg: ab8500_ext1 { regulator-name = "ab8500-ext-supply1"; }; @@ -426,7 +443,7 @@ }; }; - ab8500-regulators { + regulator { ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { regulator-name = "V-DISPLAY"; }; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts index fbd60065542d..1c1725d31c7c 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-codina.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-codina.dts @@ -47,6 +47,24 @@ compatible = "samsung,eb425161lu"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + /* TI TXS0206 level translator for 2.9 V */ sd_level_translator: regulator-gpio { compatible = "regulator-fixed"; @@ -459,13 +477,13 @@ prcmu@80157000 { ab8500 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8500-regulators { + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ regulator-name = "V-SENSORS-VDD"; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts index 1c0e5cfeddac..fd170974765f 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-gavini.dts @@ -24,6 +24,24 @@ compatible = "samsung,eb585157lu"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + /* TI TXS0206 level translator for 2.9 V */ sd_level_translator: regulator-gpio { compatible = "regulator-fixed"; @@ -432,13 +450,13 @@ prcmu@80157000 { ab8500 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8500-regulators { + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ regulator-name = "V-SENSORS-VDD"; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts index fc4c5166d85b..290ab59e863d 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-golden.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-golden.dts @@ -29,6 +29,24 @@ compatible = "samsung,eb-l1m7flu"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + i2c-gpio-0 { compatible = "i2c-gpio"; sda-gpios = <&gpio2 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; @@ -280,13 +298,13 @@ prcmu@80157000 { ab8505 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8505-regulators { + regulator { ab8500_ldo_aux1 { regulator-name = "sensor_3v"; regulator-min-microvolt = <3000000>; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts index 5ddcbc1a855d..42762bfcd878 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts @@ -24,6 +24,24 @@ compatible = "samsung,eb535151vu"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + /* External LDO for eMMC LDO VMEM_3V3 controlled by GPIO6 */ ldo_3v3_reg: regulator-gpio-ldo-3v3 { compatible = "regulator-fixed"; @@ -480,13 +498,13 @@ prcmu@80157000 { ab8500 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8500-regulators { + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ regulator-name = "V-SENSORS-VDD"; @@ -594,7 +612,7 @@ reg = <0x08>; mount-matrix = "0", "1", "0", "-1", "0", "0", - "0", "0", "-1"; + "0", "0", "1"; vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V }; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts index 9ec3f85b1a18..2a5bf54137ce 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-kyle.dts @@ -28,6 +28,24 @@ compatible = "samsung,eb425161la"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + /* TI TXS0206 level translator for 2.9 V */ sd_level_translator: regulator-gpio { compatible = "regulator-fixed"; @@ -301,13 +319,13 @@ prcmu@80157000 { ab8505 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8505-regulators { + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ regulator-name = "AUX1"; diff --git a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts index f8c5899fbdba..dcb03ce7cbd4 100644 --- a/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts +++ b/arch/arm/boot/dts/ste-ux500-samsung-skomer.dts @@ -24,6 +24,24 @@ compatible = "samsung,eb485159lu"; }; + thermal-zones { + battery-thermal { + /* This zone will be polled by the battery temperature code */ + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&bat_therm>; + }; + }; + + bat_therm: thermistor { + compatible = "samsung,1404-001221"; + io-channels = <&gpadc 0x02>; /* BatTemp */ + pullup-uv = <1800000>; + pullup-ohm = <230000>; + pulldown-ohm = <0>; + #thermal-sensor-cells = <0>; + }; + /* TI TXS0206 level translator for 2.9 V */ sd_level_translator: regulator-gpio { compatible = "regulator-fixed"; @@ -281,13 +299,13 @@ prcmu@80157000 { ab8505 { - ab8500_usb { + phy { pinctrl-names = "default", "sleep"; pinctrl-0 = <&usb_a_1_default>; pinctrl-1 = <&usb_a_1_sleep>; }; - ab8505-regulators { + regulator { ab8500_ldo_aux1 { /* Used for VDD for sensors */ regulator-name = "AUX1"; diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 9cce9541e26b..350bcfcf498b 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -29,7 +29,7 @@ */ clockgen-a9@92b0000 { compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; + reg = <0x92b0000 0x10000>; clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; @@ -37,32 +37,27 @@ clocks = <&clk_sysin>; }; - }; - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; - - - /* - * ARM Peripheral clock for timers - */ - arm_periph_clk: clk-m-a9-periphs { + clk_m_a9: clk-m-a9 { #clock-cells = <0>; - compatible = "fixed-factor-clock"; + compatible = "st,stih407-clkgen-a9-mux"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -87,14 +82,6 @@ }; }; - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - }; - clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -113,6 +100,13 @@ clocks = <&clk_sysin>; }; + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-pll"; + + clocks = <&clk_sysin>; + }; + clk_s_c0_flexgen: clk-s-c0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-c0"; @@ -142,18 +136,17 @@ }; }; - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs-d0"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d0"; + + clocks = <&clk_sysin>; + }; + clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d0"; @@ -166,18 +159,17 @@ }; }; - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs-d2"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d2"; + + clocks = <&clk_sysin>; + }; + clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d2"; @@ -192,18 +184,17 @@ }; }; - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs-d3"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d3@9107000 { compatible = "st,clkgen-c32"; reg = <0x9107000 0x1000>; + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d3"; + + clocks = <&clk_sysin>; + }; + clk_s_d3_flexgen: clk-s-d3-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d3"; diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 21f3347a91d6..1713f7878117 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -115,6 +115,134 @@ status = "okay"; }; + restart: restart-controller { + compatible = "st,stih407-restart"; + st,syscfg = <&syscfg_sbc_reg>; + status = "okay"; + }; + + powerdown: powerdown-controller { + compatible = "st,stih407-powerdown"; + #reset-cells = <1>; + }; + + softreset: softreset-controller { + compatible = "st,stih407-softreset"; + #reset-cells = <1>; + }; + + picophyreset: picophyreset-controller { + compatible = "st,stih407-picophyreset"; + #reset-cells = <1>; + }; + + irq-syscfg { + compatible = "st,stih407-irq-syscfg"; + st,syscfg = <&syscfg_core>; + st,irq-device = , + ; + st,fiq-device = , + ; + }; + + usb2_picophy0: phy1 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0x100 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY2_RESET>; + reset-names = "global", "port"; + }; + + miphy28lp_phy: miphy28lp { + compatible = "st,miphy28lp-phy"; + st,syscfg = <&syscfg_core>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + phy_port0: port@9b22000 { + reg = <0x9b22000 0xff>, + <0x9b09000 0xff>, + <0x9b04000 0xff>; + reg-names = "sata-up", + "pcie-up", + "pipew"; + + st,syscfg = <0x114 0x818 0xe0 0xec>; + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY0_SOFTRESET>; + }; + + phy_port1: port@9b2a000 { + reg = <0x9b2a000 0xff>, + <0x9b19000 0xff>, + <0x9b14000 0xff>; + reg-names = "sata-up", + "pcie-up", + "pipew"; + + st,syscfg = <0x118 0x81c 0xe4 0xf0>; + + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY1_SOFTRESET>; + }; + + phy_port2: port@8f95000 { + reg = <0x8f95000 0xff>, + <0x8f90000 0xff>; + reg-names = "pipew", + "usb3-up"; + + st,syscfg = <0x11c 0x820>; + + #phy-cells = <1>; + + reset-names = "miphy-sw-rst"; + resets = <&softreset STIH407_MIPHY2_SOFTRESET>; + }; + }; + + st231_gp0: st231-gp0 { + compatible = "st,st231-rproc"; + memory-region = <&gp0_reserved>; + resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x22c>; + #mbox-cells = <1>; + mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; + mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; + }; + + st231_delta: st231-delta { + compatible = "st,st231-rproc"; + memory-region = <&delta_reserved>; + resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x224>; + #mbox-cells = <1>; + mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; + mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; + }; + + delta0 { + compatible = "st,st-delta"; + clock-names = "delta", + "delta-st231", + "delta-flash-promip"; + clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, + <&clk_s_c0_flexgen CLK_ST231_DMU>, + <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -122,31 +250,6 @@ ranges; compatible = "simple-bus"; - restart: restart-controller@0 { - compatible = "st,stih407-restart"; - reg = <0 0>; - st,syscfg = <&syscfg_sbc_reg>; - status = "okay"; - }; - - powerdown: powerdown-controller@0 { - compatible = "st,stih407-powerdown"; - reg = <0 0>; - #reset-cells = <1>; - }; - - softreset: softreset-controller@0 { - compatible = "st,stih407-softreset"; - reg = <0 0>; - #reset-cells = <1>; - }; - - picophyreset: picophyreset-controller@0 { - compatible = "st,stih407-picophyreset"; - reg = <0 0>; - #reset-cells = <1>; - }; - syscfg_sbc: sbc-syscfg@9620000 { compatible = "st,stih407-sbc-syscfg", "syscon"; reg = <0x9620000 0x1000>; @@ -189,16 +292,6 @@ reg = <0x94b5100 0x1000>; }; - irq-syscfg@0 { - compatible = "st,stih407-irq-syscfg"; - reg = <0 0>; - st,syscfg = <&syscfg_core>; - st,irq-device = , - ; - st,fiq-device = , - ; - }; - /* Display */ vtg_main: sti-vtg-main@8d02800 { compatible = "st,vtg"; @@ -389,70 +482,6 @@ status = "disabled"; }; - usb2_picophy0: phy1@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0x100 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY2_RESET>; - reset-names = "global", "port"; - }; - - miphy28lp_phy: miphy28lp@0 { - compatible = "st,miphy28lp-phy"; - st,syscfg = <&syscfg_core>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - reg = <0 0>; - - phy_port0: port@9b22000 { - reg = <0x9b22000 0xff>, - <0x9b09000 0xff>, - <0x9b04000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x114 0x818 0xe0 0xec>; - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY0_SOFTRESET>; - }; - - phy_port1: port@9b2a000 { - reg = <0x9b2a000 0xff>, - <0x9b19000 0xff>, - <0x9b14000 0xff>; - reg-names = "sata-up", - "pcie-up", - "pipew"; - - st,syscfg = <0x118 0x81c 0xe4 0xf0>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY1_SOFTRESET>; - }; - - phy_port2: port@8f95000 { - reg = <0x8f95000 0xff>, - <0x8f90000 0xff>; - reg-names = "pipew", - "usb3-up"; - - st,syscfg = <0x11c 0x820>; - - #phy-cells = <1>; - - reset-names = "miphy-sw-rst"; - resets = <&softreset STIH407_MIPHY2_SOFTRESET>; - }; - }; - spi@9840000 { compatible = "st,comms-ssc4-spi"; reg = <0x9840000 0x110>; @@ -815,34 +844,6 @@ status = "okay"; }; - st231_gp0: st231-gp0@0 { - compatible = "st,st231-rproc"; - reg = <0 0>; - memory-region = <&gp0_reserved>; - resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x22c>; - #mbox-cells = <1>; - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; - }; - - st231_delta: st231-delta@0 { - compatible = "st,st231-rproc"; - reg = <0 0>; - memory-region = <&delta_reserved>; - resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; - reset-names = "sw_reset"; - clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; - clock-frequency = <600000000>; - st,syscfg = <&syscfg_core 0x224>; - #mbox-cells = <1>; - mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; - mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; - }; - /* fdma audio */ fdma0: dma-controller@8e20000 { compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; @@ -986,16 +987,5 @@ status = "disabled"; }; - - delta0@0 { - compatible = "st,st-delta"; - reg = <0 0>; - clock-names = "delta", - "delta-st231", - "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; }; }; diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts index 9d3b118f5f0f..538ff98ca1b1 100644 --- a/arch/arm/boot/dts/stih410-b2120.dts +++ b/arch/arm/boot/dts/stih410-b2120.dts @@ -24,6 +24,14 @@ ethernet0 = ðernet0; }; + usb2_picophy1: phy2 { + status = "okay"; + }; + + usb2_picophy2: phy3 { + status = "okay"; + }; + soc { mmc0: sdhci@9060000 { @@ -33,14 +41,6 @@ sd-uhs-ddr50; }; - usb2_picophy1: phy2@0 { - status = "okay"; - }; - - usb2_picophy2: phy3@0 { - status = "okay"; - }; - ohci0: usb@9a03c00 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts index 9d579c16c295..26d93f26f6d0 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -75,6 +75,21 @@ }; }; + miphy28lp_phy: miphy28lp { + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + + usb2_picophy1: phy2 { + status = "okay"; + }; + + usb2_picophy2: phy3 { + status = "okay"; + }; + soc { /* Low speed expansion connector */ uart0: serial@9830000 { @@ -145,14 +160,6 @@ status = "okay"; }; - usb2_picophy1: phy2@0 { - status = "okay"; - }; - - usb2_picophy2: phy3@0 { - status = "okay"; - }; - ohci0: usb@9a03c00 { status = "okay"; }; @@ -196,13 +203,6 @@ status = "okay"; }; - miphy28lp_phy: miphy28lp@0 { - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - sata1: sata@9b28000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index 6b0e6d4477a3..abac98a1810b 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -32,7 +32,7 @@ */ clockgen-a9@92b0000 { compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; + reg = <0x92b0000 0x10000>; clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; @@ -40,29 +40,29 @@ clocks = <&clk_sysin>; }; - }; - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; /* - * ARM Peripheral clock for timers + * ARM CPU related clocks. */ - arm_periph_clk: clk-m-a9-periphs { + clk_m_a9: clk-m-a9 { #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -87,14 +87,6 @@ }; }; - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - }; - clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -113,6 +105,13 @@ clocks = <&clk_sysin>; }; + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-pll"; + + clocks = <&clk_sysin>; + }; + clk_s_c0_flexgen: clk-s-c0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih410-c0"; @@ -142,18 +141,17 @@ }; }; - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs-d0"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d0"; + + clocks = <&clk_sysin>; + }; + clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih410-d0"; @@ -166,18 +164,17 @@ }; }; - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs-d2"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d2"; + + clocks = <&clk_sysin>; + }; + clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d2"; @@ -192,18 +189,17 @@ }; }; - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs-d3"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d3@9107000 { compatible = "st,clkgen-c32"; reg = <0x9107000 0x1000>; + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d3"; + + clocks = <&clk_sysin>; + }; + clk_s_d3_flexgen: clk-s-d3-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d3"; diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index 6d847019c554..ce2f62cf129b 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -12,31 +12,29 @@ bdisp0 = &bdisp0; }; + usb2_picophy1: phy2 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xf8 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY0_RESET>; + reset-names = "global", "port"; + + status = "disabled"; + }; + + usb2_picophy2: phy3 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xfc 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY1_RESET>; + reset-names = "global", "port"; + + status = "disabled"; + }; + soc { - usb2_picophy1: phy2@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xf8 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; - - status = "disabled"; - }; - - usb2_picophy2: phy3@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xfc 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names = "global", "port"; - - status = "disabled"; - }; - ohci0: usb@9a03c00 { compatible = "st,st-ohci-300x"; reg = <0x9a03c00 0x100>; @@ -274,16 +272,6 @@ interrupts = ; }; - delta0@0 { - compatible = "st,st-delta"; - clock-names = "delta", - "delta-st231", - "delta-flash-promip"; - clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, - <&clk_s_c0_flexgen CLK_ST231_DMU>, - <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; - }; - sti-cec@94a087c { compatible = "st,stih-cec"; reg = <0x94a087c 0x64>; diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index b66e2b29edea..d21bcc7c1271 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -37,6 +37,17 @@ }; }; + miphy28lp_phy: miphy28lp { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + soc { sbc_serial0: serial@9530000 { status = "okay"; @@ -84,17 +95,6 @@ non-removable; }; - miphy28lp_phy: miphy28lp@0 { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - st_dwc3: dwc3@8f94000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index e84c476b83ed..e1749e92a2e7 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -32,7 +32,7 @@ */ clockgen-a9@92b0000 { compatible = "st,clkgen-c32"; - reg = <0x92b0000 0xffff>; + reg = <0x92b0000 0x10000>; clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; @@ -40,30 +40,29 @@ clocks = <&clk_sysin>; }; - }; - - /* - * ARM CPU related clocks. - */ - clk_m_a9: clk-m-a9@92b0000 { - #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; - reg = <0x92b0000 0x10000>; - - clocks = <&clockgen_a9_pll 0>, - <&clockgen_a9_pll 0>, - <&clk_s_c0_flexgen 13>, - <&clk_m_a9_ext2f_div2>; /* - * ARM Peripheral clock for timers + * ARM CPU related clocks. */ - arm_periph_clk: clk-m-a9-periphs { + clk_m_a9: clk-m-a9 { #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&clk_m_a9>; - clock-div = <2>; - clock-mult = <1>; + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; }; }; @@ -88,14 +87,6 @@ }; }; - clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { - #clock-cells = <1>; - compatible = "st,quadfs-pll"; - reg = <0x9103000 0x1000>; - - clocks = <&clk_sysin>; - }; - clk_s_c0: clockgen-c@9103000 { compatible = "st,clkgen-c32"; reg = <0x9103000 0x1000>; @@ -114,6 +105,13 @@ clocks = <&clk_sysin>; }; + clk_s_c0_quadfs: clk-s-c0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-pll"; + + clocks = <&clk_sysin>; + }; + clk_s_c0_flexgen: clk-s-c0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih418-c0"; @@ -143,18 +141,17 @@ }; }; - clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { - #clock-cells = <1>; - compatible = "st,quadfs-d0"; - reg = <0x9104000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d0@9104000 { compatible = "st,clkgen-c32"; reg = <0x9104000 0x1000>; + clk_s_d0_quadfs: clk-s-d0-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d0"; + + clocks = <&clk_sysin>; + }; + clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih410-d0"; @@ -167,18 +164,17 @@ }; }; - clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { - #clock-cells = <1>; - compatible = "st,quadfs-d2"; - reg = <0x9106000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d2@9106000 { compatible = "st,clkgen-c32"; reg = <0x9106000 0x1000>; + clk_s_d2_quadfs: clk-s-d2-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d2"; + + clocks = <&clk_sysin>; + }; + clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih418-d2"; @@ -193,18 +189,17 @@ }; }; - clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { - #clock-cells = <1>; - compatible = "st,quadfs-d3"; - reg = <0x9107000 0x1000>; - - clocks = <&clk_sysin>; - }; - clockgen-d3@9107000 { compatible = "st,clkgen-c32"; reg = <0x9107000 0x1000>; + clk_s_d3_quadfs: clk-s-d3-quadfs { + #clock-cells = <1>; + compatible = "st,quadfs-d3"; + + clocks = <&clk_sysin>; + }; + clk_s_d3_flexgen: clk-s-d3-flexgen { #clock-cells = <1>; compatible = "st,flexgen", "st,flexgen-stih407-d3"; diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi index 97eda4392fbe..b35b9b7a7ccc 100644 --- a/arch/arm/boot/dts/stih418.dtsi +++ b/arch/arm/boot/dts/stih418.dtsi @@ -26,31 +26,29 @@ }; }; + usb2_picophy1: phy2 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xf8 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY0_RESET>; + reset-names = "global", "port"; + }; + + usb2_picophy2: phy3 { + compatible = "st,stih407-usb2-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_core 0xfc 0xf4>; + resets = <&softreset STIH407_PICOPHY_SOFTRESET>, + <&picophyreset STIH407_PICOPHY1_RESET>; + reset-names = "global", "port"; + }; + soc { rng11: rng@8a8a000 { status = "disabled"; }; - usb2_picophy1: phy2@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xf8 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY0_RESET>; - reset-names = "global", "port"; - }; - - usb2_picophy2: phy3@0 { - compatible = "st,stih407-usb2-phy"; - reg = <0 0>; - #phy-cells = <0>; - st,syscfg = <&syscfg_core 0xfc 0xf4>; - resets = <&softreset STIH407_PICOPHY_SOFTRESET>, - <&picophyreset STIH407_PICOPHY1_RESET>; - reset-names = "global", "port"; - }; - ohci0: usb@9a03c00 { compatible = "st,st-ohci-300x"; reg = <0x9a03c00 0x100>; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index d051f080e52e..4c72dedcd1be 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -71,6 +71,17 @@ }; }; + miphy28lp_phy: miphy28lp { + + phy_port0: port@9b22000 { + st,osc-rdy; + }; + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + soc { sbc_serial0: serial@9530000 { status = "okay"; @@ -128,17 +139,6 @@ st,i2c-min-sda-pulse-width-us = <5>; }; - miphy28lp_phy: miphy28lp@0 { - - phy_port0: port@9b22000 { - st,osc-rdy; - }; - - phy_port1: port@9b2a000 { - st,osc-force-ext; - }; - }; - st_dwc3: dwc3@8f94000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index cb46326a8c75..0d98aca01736 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -308,6 +308,18 @@ }; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32746g-eval.dts b/arch/arm/boot/dts/stm32746g-eval.dts index 327613fd9666..a293e65141c6 100644 --- a/arch/arm/boot/dts/stm32746g-eval.dts +++ b/arch/arm/boot/dts/stm32746g-eval.dts @@ -194,6 +194,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts index 6435e099c632..3b81228d46a2 100644 --- a/arch/arm/boot/dts/stm32f429-disco.dts +++ b/arch/arm/boot/dts/stm32f429-disco.dts @@ -205,6 +205,18 @@ }; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 8748d5850298..c31ceb821231 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -93,14 +93,6 @@ }; }; - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -123,14 +115,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -153,14 +137,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -183,13 +159,6 @@ }; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>; - }; - timers5: timers@40000c00 { #address-cells = <1>; #size-cells = <0>; @@ -212,14 +181,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -236,14 +197,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; @@ -759,6 +712,16 @@ status = "disabled"; }; + dma2d: dma2d@4002b000 { + compatible = "st,stm32-dma2d"; + reg = <0x4002b000 0xc00>; + interrupts = <90>; + resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>; + clock-names = "dma2d"; + status = "disabled"; + }; + usbotg_hs: usb@40040000 { compatible = "snps,dwc2"; reg = <0x40040000 0x40000>; diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts index 30905ce672a0..5a0daf8e8b11 100644 --- a/arch/arm/boot/dts/stm32f469-disco.dts +++ b/arch/arm/boot/dts/stm32f469-disco.dts @@ -132,6 +132,10 @@ clock-frequency = <8000000>; }; +&dma2d { + status = "okay"; +}; + &dsi { #address-cells = <1>; #size-cells = <0>; @@ -224,6 +228,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart3 { pinctrl-0 = <&usart3_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f746-disco.dts b/arch/arm/boot/dts/stm32f746-disco.dts index 569d23cc61e5..c11616ed5fc6 100644 --- a/arch/arm/boot/dts/stm32f746-disco.dts +++ b/arch/arm/boot/dts/stm32f746-disco.dts @@ -109,6 +109,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_b>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index 014b416f57e6..dc868e6da40e 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -75,14 +75,6 @@ }; soc { - timer2: timer@40000000 { - compatible = "st,stm32-timer"; - reg = <0x40000000 0x400>; - interrupts = <28>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>; - status = "disabled"; - }; - timers2: timers@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -105,14 +97,6 @@ }; }; - timer3: timer@40000400 { - compatible = "st,stm32-timer"; - reg = <0x40000400 0x400>; - interrupts = <29>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>; - status = "disabled"; - }; - timers3: timers@40000400 { #address-cells = <1>; #size-cells = <0>; @@ -135,14 +119,6 @@ }; }; - timer4: timer@40000800 { - compatible = "st,stm32-timer"; - reg = <0x40000800 0x400>; - interrupts = <30>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>; - status = "disabled"; - }; - timers4: timers@40000800 { #address-cells = <1>; #size-cells = <0>; @@ -165,13 +141,6 @@ }; }; - timer5: timer@40000c00 { - compatible = "st,stm32-timer"; - reg = <0x40000c00 0x400>; - interrupts = <50>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>; - }; - timers5: timers@40000c00 { #address-cells = <1>; #size-cells = <0>; @@ -194,14 +163,6 @@ }; }; - timer6: timer@40001000 { - compatible = "st,stm32-timer"; - reg = <0x40001000 0x400>; - interrupts = <54>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>; - status = "disabled"; - }; - timers6: timers@40001000 { #address-cells = <1>; #size-cells = <0>; @@ -218,14 +179,6 @@ }; }; - timer7: timer@40001400 { - compatible = "st,stm32-timer"; - reg = <0x40001400 0x400>; - interrupts = <55>; - clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>; - status = "disabled"; - }; - timers7: timers@40001400 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32f769-disco.dts b/arch/arm/boot/dts/stm32f769-disco.dts index be943b701980..b038d0ed39e8 100644 --- a/arch/arm/boot/dts/stm32f769-disco.dts +++ b/arch/arm/boot/dts/stm32f769-disco.dts @@ -137,6 +137,18 @@ bus-width = <4>; }; +&timers5 { + /* Override timer5 to act as clockevent */ + compatible = "st,stm32-timer"; + interrupts = <50>; + status = "okay"; + /delete-property/#address-cells; + /delete-property/#size-cells; + /delete-property/clock-names; + /delete-node/pwm; + /delete-node/timer@4; +}; + &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index 069f95f2b628..d2472cd8f1d0 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -7,7 +7,7 @@ &pinctrl { sdmmc1_b4_pins_a: sdmmc1-b4-0 { - pins1 { + pins { pinmux = , /* SDMMC1_D0 */ , /* SDMMC1_D1 */ , /* SDMMC1_D2 */ @@ -17,12 +17,6 @@ drive-push-pull; bias-disable; }; - pins2 { - pinmux = ; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; }; sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { @@ -36,12 +30,6 @@ bias-disable; }; pins2 { - pinmux = ; /* SDMMC1_CK */ - slew-rate = <2>; - drive-push-pull; - bias-disable; - }; - pins3 { pinmux = ; /* SDMMC1_CMD */ slew-rate = <1>; drive-open-drain; @@ -49,6 +37,77 @@ }; }; + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_clk_pins_a: sdmmc1-clk-0 { + pins { + pinmux = ; /* SDMMC1_CK */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + sdmmc2_clk_pins_a: sdmmc2-clk-0 { + pins { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = ; /* UART4_TX */ diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index 86126dc0d898..1708c79b5254 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -92,10 +92,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-parent = <&intc>; always-on; }; @@ -115,15 +115,76 @@ status = "disabled"; }; + dma1: dma-controller@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&clk_pclk4>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dma2: dma-controller@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&clk_pclk4>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x40>; + clocks = <&clk_pclk4>; + #dma-cells = <3>; + dma-masters = <&dma1 &dma2>; + dma-requests = <128>; + dma-channels = <16>; + }; + + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp13-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + }; + syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; clocks = <&clk_pclk3>; }; + mdma: dma-controller@58000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x58000000 0x1000>; + interrupts = ; + clocks = <&clk_pclk4>; + #dma-cells = <5>; + dma-channels = <32>; + dma-requests = <48>; + }; + sdmmc1: mmc@58005000 { - compatible = "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x00253180>; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; reg = <0x58005000 0x1000>, <0x58006000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; @@ -131,7 +192,21 @@ clock-names = "apb_pclk"; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <120000000>; + max-frequency = <130000000>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&clk_pll4_p>; + clock-names = "apb_pclk"; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index 7e96d9e36217..ee100d108ea2 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -38,9 +38,10 @@ }; &sdmmc1 { - pinctrl-names = "default", "opendrain"; - pinctrl-0 = <&sdmmc1_b4_pins_a>; - pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; broken-cd; disable-wp; st,neg-edge; diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 3b65130affec..f0d66d8c6e3b 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -338,6 +338,47 @@ }; }; + ethernet0_rmii_pins_b: rmii-1 { + pins1 { + pinmux = , /* ETH1_CLK */ + , /* ETH1_MDC */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* ETH1_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH1_CRS_DV */ + , /* ETH1_RXD0 */ + ; /* ETH1_RXD1 */ + bias-disable; + }; + pins4 { + pinmux = ; /* ETH1_TX_EN */ + }; + }; + + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { + pins1 { + pinmux = , /* ETH1_MDIO */ + , /* ETH1_CRS_DV */ + , /* ETH1_CLK */ + , /* ETH1_TX_EN */ + , /* ETH1_MDC */ + , /* ETH1_RXD0 */ + , /* ETH1_RXD1 */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = , /* FMC_NOE */ @@ -927,6 +968,21 @@ }; }; + pwm1_pins_b: pwm1-1 { + pins { + pinmux = ; /* TIM1_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_b: pwm1-sleep-1 { + pins { + pinmux = ; /* TIM1_CH1 */ + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = ; /* TIM2_CH4 */ @@ -1190,7 +1246,7 @@ }; }; - sai2a_sleep_pins_c: sai2a-2 { + sai2a_sleep_pins_c: sai2a-sleep-2 { pins { pinmux = , /* SAI2_SCK_A */ , /* SAI2_SD_A */ @@ -2042,6 +2098,42 @@ }; }; + usart3_pins_d: usart3-3 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usart3_idle_pins_d: usart3-idle-3 { + pins1 { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + ; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_d: usart3-sleep-3 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_CTS_NSS */ + ; /* USART3_RX */ + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = ; /* OTG_ID */ diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 1cfc2f011e70..f9aa9af31efd 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -45,10 +45,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-parent = <&intc>; }; @@ -455,6 +455,9 @@ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART2_K>; wakeup-source; + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -464,6 +467,9 @@ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART3_K>; wakeup-source; + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -473,6 +479,9 @@ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART4_K>; wakeup-source; + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -482,6 +491,9 @@ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART5_K>; wakeup-source; + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -588,6 +600,9 @@ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART7_K>; wakeup-source; + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -597,6 +612,9 @@ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART8_K>; wakeup-source; + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -678,6 +696,9 @@ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART6_K>; wakeup-source; + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1059,7 +1080,7 @@ }; sdmmc3: mmc@48004000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = ; @@ -1381,7 +1402,7 @@ }; sdmmc1: mmc@58005000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = ; @@ -1396,7 +1417,7 @@ }; sdmmc2: mmc@58007000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = ; @@ -1560,7 +1581,7 @@ reg = <0x5c004000 0x400>; clocks = <&rcc RTCAPB>, <&rcc RTC>; clock-names = "pclk", "rtc_ck"; - interrupts = ; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi index 1c1889b194cf..486084e0b80b 100644 --- a/arch/arm/boot/dts/stm32mp153.dtsi +++ b/arch/arm/boot/dts/stm32mp153.dtsi @@ -22,6 +22,13 @@ interrupt-affinity = <&cpu0>, <&cpu1>; }; + timer { + interrupts = , + , + , + ; + }; + soc { m_can1: can@4400e000 { compatible = "bosch,m_can"; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts index d3058a036c74..1f75f1d45181 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -43,5 +43,7 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index a797eaa917b7..ba92d7d8ed00 100644 --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -128,5 +128,7 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157a-iot-box.dts b/arch/arm/boot/dts/stm32mp157a-iot-box.dts index 70f394b4d3c0..6a5a4af25bd9 100644 --- a/arch/arm/boot/dts/stm32mp157a-iot-box.dts +++ b/arch/arm/boot/dts/stm32mp157a-iot-box.dts @@ -58,6 +58,8 @@ /delete-property/st,hw-flow-ctrl; cts-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; rts-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; bluetooth { diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 5670b23812a2..fae656edd820 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -143,6 +143,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -150,5 +152,7 @@ &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts index 7a75868164dc..b9d0d3d6ad15 100644 --- a/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +++ b/arch/arm/boot/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -44,6 +44,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -51,5 +53,7 @@ &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi index a4b14ef3caee..3a36f7fe0a2c 100644 --- a/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi +++ b/arch/arm/boot/dts/stm32mp157a-stinger96.dtsi @@ -288,6 +288,8 @@ pinctrl-0 = <&usart2_pins_b>; pinctrl-1 = <&usart2_sleep_pins_b>; st,hw-flow-ctrl; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -296,6 +298,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_c>; st,hw-flow-ctrl; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -303,6 +307,8 @@ &uart7 { pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 46b471d09c50..b1eb688a278a 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -384,6 +384,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts b/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts new file mode 100644 index 000000000000..33b3f11d24bb --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-emsbc-argon.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (c) 2021 emtrion GmbH +// Author: Reinhold Müller . +// + +/dts-v1/; + +#include "stm32mp157c-emstamp-argon.dtsi" + +/ { + model = "emtrion STM32MP157C emSBC-Argon Developer Board"; + compatible = "emtrion,stm32mp157c-emsbc-argon", "emtrion,stm32mp157c-emstamp-argon", + "st,stm32mp157"; + + led: gpio_leds { + compatible = "gpio-leds"; + led-2 { + label = "red"; + gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + led-3 { + label = "green"; + gpios = <&gpioe 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + }; +}; + +&dac { + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi new file mode 100644 index 000000000000..33ae5e0590df --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (c) 2021 emtrion GmbH +// Author: Reinhold Müller . +// + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include + +/ { + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &usart2; + serial2 = &usart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x2000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x2000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10044000 { + compatible = "shared-dma-pool"; + reg = <0x10044000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + gpu_reserved: gpu@dc000000 { + reg = <0xdc000000 0x4000000>; + no-map; + }; + }; + + led: gpio_leds { + compatible = "gpio-leds"; + led-0 { + label = "panic"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + panic-indicator; + }; + led-1 { + label = "heartbeat"; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; +}; + +&adc { + vdd-supply = <&vdd>; + vdda-supply = <&vdd>; + vref-supply = <&vrefbuf>; + status = "okay"; + + adc1: adc@0 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_in6_pins_a>; + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <6>; + status = "disabled"; + }; + + adc2: adc@100 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + channel@12 { + reg = <12>; + label = "sense_temp"; + st,min-sample-time-ns = <9000>; + }; + channel@15 { + reg = <15>; + label = "vbat"; + st,min-sample-time-ns = <9000>; + }; + channel@16 { + reg = <16>; + label = "dac_out1"; + st,min-sample-time-ns = <9000>; + }; + channel@17 { + reg = <17>; + label = "dac_out1"; + st,min-sample-time-ns = <9000>; + }; + }; +}; + +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dac { + pinctrl-names = "default"; + pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>; + vref-supply = <&vdda>; + status = "disabled"; + + dac1: dac@1 { + status = "okay"; + }; + dac2: dac@2 { + status = "okay"; + }; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + status = "okay"; + snps,reset-gpio = <&gpioa 1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 30000 50000>; + pinctrl-0 = <ðernet0_rmii_pins_b>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth-ref-clk-sel; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; +}; + +&hash1 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c4_pins_a>; + pinctrl-1 = <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdd_sd: ldo5 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + regulator-always-on; + }; + + vdda: ldo6 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + interrupts = ; + regulator-boot-on; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + regulator-active-discharge; + }; + + vbus_usbh: pwr_sw2 { + regulator-name = "usbh_vbus"; + interrupts = ; + regulator-always-on; + regulator-boot-on; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + interrupt-names = "wdg"; + recovery; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: is25lp016d@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <133000000>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc2 { + arm,primecell-periphid = <0x10153180>; + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + cs-gpios = <&gpioz 3 0>; + status = "disabled"; + + spidev@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <100000>; + }; +}; + +&timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm1_pins_b>; + pinctrl-1 = <&pwm1_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@0 { + status = "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm4_pins_b>; + pinctrl-1 = <&pwm4_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@3 { + status = "okay"; + }; +}; + +&timers5 { + /delete-property/dmas; + /delete-property/dma-names; + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@4 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_sleep_pins_a>; + status = "okay"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_d>; + pinctrl-1 = <&usart3_sleep_pins_d>; + pinctrl-2 = <&usart3_idle_pins_d>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&usbotg_hs_pins_a>; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdd>; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index 1e9bf7eea0f1..e8d2ec41d537 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -248,5 +248,7 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts index 554f5d3bcdc3..ed66d25b8bf3 100644 --- a/arch/arm/boot/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts @@ -81,6 +81,8 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi index 4b10b013ffd5..35b1034aa3cf 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi @@ -131,6 +131,8 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -144,6 +146,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index fbf3826933e4..5f586f024060 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -287,6 +287,8 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -294,6 +296,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi index ba816ef8b9b2..abc595350e71 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-picoitx.dtsi @@ -105,12 +105,16 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 8c41f819f776..83e2c87713f8 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -196,7 +196,6 @@ "", "", "DHCOM-E", "", "", "", "", "", "", "", "", ""; - status = "okay"; }; &gpiod { @@ -521,5 +520,7 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 6885948f3024..61e17f44ce81 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -376,6 +376,8 @@ label = "LS-UART1"; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -385,6 +387,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_a>; uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -394,6 +398,8 @@ pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_sleep_pins_a>; st,hw-flow-ctrl; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; bluetooth { diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index 44ecc4708587..6336c3ca0f0e 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -19,6 +19,48 @@ device_type = "memory"; reg = <0xc0000000 0x40000000>; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; }; &crc1 { @@ -179,11 +221,25 @@ }; }; +&ipcc { + status = "okay"; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; }; +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + &pwr_regulators { vdd-supply = <&vdd>; vdd_3v3_usbfs-supply = <&vdd_usb>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 6caeb448c190..333c2af97130 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -650,6 +650,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -658,6 +660,8 @@ pinctrl-0 = <&uart7_pins_c>; pinctrl-1 = <&uart7_sleep_pins_c>; pinctrl-2 = <&uart7_idle_pins_c>; + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts b/arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts new file mode 100644 index 000000000000..097e479c2772 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-haoyu-marsboard.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Conley Lee + * Conley Lee + */ + +/dts-v1/; +#include "sun7i-a20.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "HAOYU Electronics Marsboard A20"; + compatible = "haoyu,a20-marsboard", "allwinner,sun7i-a20"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; +}; + +&ahci { + target-supply = <®_ahci_5v>; + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&gmac { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>; + phy-handle = <&phy0>; + phy-mode = "mii"; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */ + status = "okay"; +}; + +&gmac_mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + gmac_txerr: gmac-txerr-pin { + pins = "PA17"; + function = "gmac"; + }; +}; + +®_ahci_5v { + status = "okay"; +}; + +#include "axp209.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1450000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb1_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */ + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts index be49eabbff94..cd3df12b6573 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts @@ -103,12 +103,40 @@ }; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pa_pins>; status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc 1>; + clock-names = "lpo"; + vbat-supply = <®_vcc3v3>; + vddio-supply = <®_vcc3v3>; + device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */ + shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */ + }; +}; + &usbphy { /* USB VBUS is always on */ status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts index 9f33f6fae595..df71fab3cf4e 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -45,6 +45,10 @@ / { model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; + + aliases { + ethernet0 = &emac; + }; }; &ehci0 { diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 845f25235407..eac2349a2380 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -245,7 +245,7 @@ cpu_thermal: cpu-thermal { polling-delay-passive = <0>; polling-delay = <0>; - thermal-sensors = <&ths 0>; + thermal-sensors = <&ths>; trips { cpu_hot_trip: cpu-hot { diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index b30bc1a25ebb..084323d5c61c 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -593,6 +593,17 @@ #size-cells = <0>; }; + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + csi1: camera@1cb4000 { compatible = "allwinner,sun8i-v3s-csi"; reg = <0x01cb4000 0x3000>; @@ -604,16 +615,5 @@ resets = <&ccu RST_BUS_CSI>; status = "disabled"; }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = ; - }; }; }; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 4aeca9e7e30d..d7e9f977f986 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -913,6 +913,19 @@ #size-cells = <0>; }; + r_uart: serial@1f02800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01f02800 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&r_ccu CLK_APB0_UART>; + resets = <&r_ccu RST_APB0_UART>; + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins>; + status = "disabled"; + }; + r_pio: pinctrl@1f02c00 { compatible = "allwinner,sun8i-h3-r-pinctrl"; reg = <0x01f02c00 0x400>; @@ -939,6 +952,11 @@ pins = "PL10"; function = "s_pwm"; }; + + r_uart_pins: r-uart-pins { + pins = "PL2", "PL3"; + function = "s_uart"; + }; }; r_pwm: pwm@1f03800 { diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts index 020172ee7340..a054d39db466 100644 --- a/arch/arm/boot/dts/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -436,17 +436,27 @@ }; }; + spdif@70002400 { + status = "okay"; + + nvidia,fixed-parent-rate; + }; + i2s@70002800 { status = "okay"; + + nvidia,fixed-parent-rate; }; serial@70006040 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; /* GPS BCM4751 */ }; serial@70006200 { compatible = "nvidia,tegra20-hsuart"; + /delete-property/ reg-shift; status = "okay"; /* Azurewave AW-NH615 BCM4329B1 */ @@ -756,7 +766,7 @@ lpddr2 { compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; - revision-id1 = <1>; + revision-id = <1 0>; density = <2048>; io-width = <16>; }; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 1eefb9ee4ac8..8ebd8afc857d 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -691,7 +691,7 @@ #address-cells = <1>; #size-cells = <0>; - asix@1 { + ethernet@1 { compatible = "usbb95,772b"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index d53a175dc17a..0fb4b1f5bc1c 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -13,6 +13,8 @@ compatible = "compal,paz00", "nvidia,tegra20"; aliases { + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* MicroSD */ rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; serial0 = &uarta; @@ -558,7 +560,7 @@ status = "okay"; }; - mmc@c8000000 { + sdmmc1: mmc@c8000000 { status = "okay"; cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>; wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; @@ -566,7 +568,7 @@ bus-width = <4>; }; - mmc@c8000600 { + sdmmc4: mmc@c8000600 { status = "okay"; bus-width = <8>; non-removable; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index de39c5465c0a..0e19bd0a847c 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -183,8 +183,8 @@ }; conf_ata { nvidia,pins = "ata", "atb", "atc", "atd", "ate", - "cdev1", "cdev2", "dap1", "dtb", "gma", - "gmb", "gmc", "gmd", "gme", "gpu7", + "cdev1", "cdev2", "dap1", "dtb", "dtf", + "gma", "gmb", "gmc", "gmd", "gme", "gpu7", "gpv", "i2cp", "irrx", "irtx", "pta", "rm", "slxa", "slxk", "spia", "spib", "uac"; @@ -203,7 +203,7 @@ }; conf_crtp { nvidia,pins = "crtp", "dap2", "dap3", "dap4", - "dtc", "dte", "dtf", "gpu", "sdio1", + "dtc", "dte", "gpu", "sdio1", "slxc", "slxd", "spdi", "spdo", "spig", "uda"; nvidia,pull = ; diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts index 18a9bfa5e97b..1a331dec3cfe 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf700t.dts @@ -742,7 +742,7 @@ #address-cells = <1>; #size-cells = <0>; - dsi-bridge@7 { + dsi@7 { compatible = "toshiba,tc358768"; reg = <0x7>; diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi index 85b43a86a26d..c662ab261ed5 100644 --- a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi @@ -1080,6 +1080,7 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; /* Broadcom GPS BCM47511 */ @@ -1087,6 +1088,7 @@ serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; nvidia,adjust-baud-rates = <0 9600 100>, diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index be691a1c33a1..22231d450b1b 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -960,7 +960,7 @@ #address-cells = <1>; #size-cells = <0>; - asix@1 { + ethernet@1 { compatible = "usbb95,772b"; reg = <1>; local-mac-address = [00 00 00 00 00 00]; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index a5cfbab5f565..e58dda4f9d2c 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -4553,7 +4553,7 @@ #address-cells = <1>; #size-cells = <0>; - smsc@2 { /* SMSC 10/100T Ethernet Controller */ + ethernet@2 { /* SMSC 10/100T Ethernet Controller */ compatible = "usb424,9e00"; reg = <2>; local-mac-address = [00 11 22 33 44 55]; diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts index f4b2d4218849..8ce61035290b 100644 --- a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts +++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts @@ -1103,6 +1103,7 @@ uartb: serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; /* Broadcom GPS BCM47511 */ @@ -1110,6 +1111,7 @@ uartc: serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + /delete-property/ reg-shift; status = "okay"; nvidia,adjust-baud-rates = <0 9600 100>, diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi index c12a1b8bc086..14c411f146f5 100644 --- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi @@ -103,7 +103,7 @@ status = "okay"; /* M41T0M6 real time clock on carrier board */ - rtc: m41t0m6@68 { + rtc: rtc@68 { compatible = "st,m41t0"; reg = <0x68>; }; diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index cae09010a799..aa061074db78 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -158,6 +158,7 @@ CONFIG_CHARGER_MAX14577=y CONFIG_CHARGER_MAX77693=y CONFIG_CHARGER_MAX8997=y CONFIG_CHARGER_MAX8998=y +CONFIG_CHARGER_SMB347=y CONFIG_CHARGER_TPS65090=y CONFIG_SENSORS_LM90=y CONFIG_SENSORS_NTC_THERMISTOR=y diff --git a/arch/arm/configs/imxrt_defconfig b/arch/arm/configs/imxrt_defconfig new file mode 100644 index 000000000000..52dba3762996 --- /dev/null +++ b/arch/arm/configs/imxrt_defconfig @@ -0,0 +1,35 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BPF_SYSCALL=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_MMU is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMXRT=y +CONFIG_SET_MEM_PARAM=y +CONFIG_DRAM_BASE=0x80000000 +CONFIG_DRAM_SIZE=0x02000000 +CONFIG_BINFMT_FLAT=y +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_IMX_WEIM=y +CONFIG_LEGACY_PTY_COUNT=2 +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_PINCTRL_IMXRT1050=y +CONFIG_GPIO_MXC=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_DMADEVICES=y +CONFIG_FSL_EDMA=y +CONFIG_CLK_IMXRT1050=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_EXFAT_FS=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_UTF8=y diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig index fe8d760256a4..70241ad2b550 100644 --- a/arch/arm/configs/multi_v5_defconfig +++ b/arch/arm/configs/multi_v5_defconfig @@ -24,11 +24,6 @@ CONFIG_MACH_DM355_LEOPARD=y CONFIG_MACH_MITYOMAPL138=y CONFIG_MACH_OMAPL138_HAWKBOARD=y CONFIG_ARCH_MXC=y -CONFIG_MACH_MX21ADS=y -CONFIG_MACH_MX27ADS=y -CONFIG_MACH_MX27_3DS=y -CONFIG_MACH_IMX27_VISSTRIM_M10=y -CONFIG_MACH_PCA100=y CONFIG_SOC_IMX25=y CONFIG_SOC_IMX27=y CONFIG_ARCH_MVEBU=y @@ -57,11 +52,9 @@ CONFIG_MACH_WNR854T=y CONFIG_MACH_RD88F5181L_GE=y CONFIG_MACH_RD88F5181L_FXO=y CONFIG_MACH_RD88F6183AP_GE=y -CONFIG_ARCH_U300=y +CONFIG_ARCH_SUNXI=y CONFIG_AEABI=y CONFIG_HIGHMEM=y -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CPU_FREQ=y @@ -85,6 +78,8 @@ CONFIG_NET_PKTGEN=m CONFIG_CFG80211=y CONFIG_MAC80211=y CONFIG_PCI_MVEBU=y +CONFIG_ARCH_VERSATILE=y +CONFIG_PCI_VERSATILE=y CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_IMX_WEIM=y @@ -111,6 +106,9 @@ CONFIG_EEPROM_AT24=y # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_BLK=y CONFIG_CHR_DEV_SG=m CONFIG_ATA=y CONFIG_SATA_AHCI=y @@ -143,7 +141,10 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=6 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_ASPEED_VUART=m +CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_ATMEL=y CONFIG_SERIAL_ATMEL_CONSOLE=y CONFIG_SERIAL_ATMEL_TTYAT=y @@ -159,11 +160,11 @@ CONFIG_I2C_ASPEED=m CONFIG_I2C_AT91=y CONFIG_I2C_IMX=y CONFIG_I2C_MV64XXX=y -CONFIG_I2C_NOMADIK=y CONFIG_SPI=y CONFIG_SPI_ATMEL=y CONFIG_SPI_IMX=y CONFIG_SPI_ORION=y +CONFIG_SPI_SUN6I=y CONFIG_GPIO_ASPEED=m CONFIG_GPIO_ASPEED_SGPIO=y CONFIG_GPIO_MXC=y @@ -180,14 +181,15 @@ CONFIG_THERMAL=y CONFIG_KIRKWOOD_THERMAL=y CONFIG_AT91SAM9X_WATCHDOG=y CONFIG_ORION_WATCHDOG=y +CONFIG_SUNXI_WATCHDOG=y CONFIG_NPCM7XX_WATCHDOG=y CONFIG_IMX2_WDT=y CONFIG_MFD_ATMEL_HLCDC=y -# CONFIG_ABX500_CORE is not set CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_MEDIA_SUPPORT=y CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_VIDEO_ASPEED=m CONFIG_VIDEO_ATMEL_ISI=m @@ -196,6 +198,7 @@ CONFIG_DRM_ATMEL_HLCDC=m CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y CONFIG_DRM_ASPEED_GFX=m +CONFIG_FB=y CONFIG_FB_IMX=y CONFIG_FB_ATMEL=y CONFIG_BACKLIGHT_ATMEL_LCDC=y @@ -249,6 +252,7 @@ CONFIG_MMC_SDHCI_PLTFM=m CONFIG_MMC_SDHCI_OF_ASPEED=m CONFIG_MMC_ATMELMCI=y CONFIG_MMC_MVSDIO=y +CONFIG_MMC_SUNXI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y @@ -303,8 +307,8 @@ CONFIG_CRYPTO_DEV_MARVELL_CESA=y CONFIG_CRC_CCITT=y CONFIG_LIBCRC32C=y CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SCHED_DEBUG is not set # CONFIG_DEBUG_PREEMPT is not set diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 8863fa969ede..6e0c8c19b35c 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -24,7 +24,9 @@ CONFIG_ARCH_BCM_NSP=y CONFIG_ARCH_BCM_5301X=y CONFIG_ARCH_BCM_281XX=y CONFIG_ARCH_BCM_21664=y +CONFIG_ARCH_BCM_23550=y CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BCM_53573=y CONFIG_ARCH_BCM_63XX=y CONFIG_ARCH_BRCMSTB=y CONFIG_ARCH_BERLIN=y @@ -32,6 +34,7 @@ CONFIG_MACH_BERLIN_BG2=y CONFIG_MACH_BERLIN_BG2CD=y CONFIG_MACH_BERLIN_BG2Q=y CONFIG_ARCH_DIGICOLOR=y +CONFIG_ARCH_AIROHA=y CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_HIGHBANK=y CONFIG_ARCH_HISI=y @@ -75,6 +78,7 @@ CONFIG_SOC_AM43XX=y CONFIG_SOC_DRA7XX=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_MSM8X60=y +CONFIG_ARCH_MSM8916=y CONFIG_ARCH_MSM8960=y CONFIG_ARCH_MSM8974=y CONFIG_ARCH_ROCKCHIP=y @@ -109,11 +113,13 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPUFREQ_DT=y CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y CONFIG_ARM_RASPBERRYPI_CPUFREQ=y CONFIG_ARM_SCMI_CPUFREQ=y CONFIG_QORIQ_CPUFREQ=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y CONFIG_ARM_ZYNQ_CPUIDLE=y CONFIG_ARM_EXYNOS_CPUIDLE=y CONFIG_ARM_TEGRA_CPUIDLE=y @@ -157,6 +163,8 @@ CONFIG_IPV6_MIP6=m CONFIG_IPV6_TUNNEL=m CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_NET_DSA=m +CONFIG_QRTR=m +CONFIG_QRTR_SMD=m CONFIG_CAN=y CONFIG_CAN_AT91=m CONFIG_CAN_FLEXCAN=m @@ -169,6 +177,7 @@ CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_BCM=y CONFIG_BT_MRVL=m CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_QCOMSMD=m CONFIG_CFG80211=m CONFIG_MAC80211=m CONFIG_RFKILL=y @@ -225,6 +234,7 @@ CONFIG_AD525X_DPOT_I2C=y CONFIG_ICS932S401=y CONFIG_ATMEL_SSC=m CONFIG_QCOM_COINCELL=m +CONFIG_QCOM_FASTRPC=m CONFIG_APDS9802ALS=y CONFIG_ISL29003=y CONFIG_PCI_ENDPOINT_TEST=m @@ -282,12 +292,14 @@ CONFIG_MARVELL_PHY=y CONFIG_AT803X_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_DP83867_PHY=y +CONFIG_USB_BRCMSTB=m CONFIG_USB_PEGASUS=y CONFIG_USB_RTL8152=m CONFIG_USB_LAN78XX=m CONFIG_USB_USBNET=y CONFIG_USB_NET_SMSC75XX=y CONFIG_USB_NET_SMSC95XX=y +CONFIG_WCN36XX=m CONFIG_BRCMFMAC=m CONFIG_MWIFIEX=m CONFIG_MWIFIEX_SDIO=m @@ -316,6 +328,7 @@ CONFIG_TOUCHSCREEN_ST1232=m CONFIG_TOUCHSCREEN_STMPE=y CONFIG_TOUCHSCREEN_SUN4I=y CONFIG_INPUT_MISC=y +CONFIG_INPUT_PM8941_PWRKEY=y CONFIG_INPUT_MAX77693_HAPTIC=m CONFIG_INPUT_MAX8997_HAPTIC=m CONFIG_INPUT_CPCAP_PWRBUTTON=m @@ -398,6 +411,8 @@ CONFIG_I2C_IMX=y CONFIG_I2C_MESON=y CONFIG_I2C_MV64XXX=y CONFIG_I2C_OWL=y +CONFIG_I2C_QCOM_CCI=m +CONFIG_I2C_QUP=y CONFIG_I2C_RIIC=y CONFIG_I2C_RK3X=y CONFIG_I2C_S3C2410=y @@ -426,6 +441,7 @@ CONFIG_SPI_ORION=y CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=m CONFIG_SPI_RSPI=y +CONFIG_SPI_QUP=m CONFIG_SPI_S3C64XX=m CONFIG_SPI_SH_MSIOF=m CONFIG_SPI_SH_HSPI=y @@ -476,6 +492,8 @@ CONFIG_GPIO_TWL4030=y CONFIG_POWER_RESET_AS3722=y CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_QCOM_PON=y CONFIG_POWER_RESET_ST=y CONFIG_POWER_RESET_KEYSTONE=y CONFIG_POWER_RESET_RMOBILE=y @@ -493,6 +511,7 @@ CONFIG_CHARGER_MAX14577=m CONFIG_CHARGER_MAX77693=m CONFIG_CHARGER_MAX8997=m CONFIG_CHARGER_MAX8998=m +CONFIG_CHARGER_SMB347=m CONFIG_CHARGER_TPS65090=y CONFIG_SENSORS_ARM_SCMI=y CONFIG_SENSORS_ASPEED=m @@ -516,6 +535,7 @@ CONFIG_ST_THERMAL_MEMMAP=y CONFIG_TEGRA_SOCTHERM=m CONFIG_TEGRA30_TSENSOR=m CONFIG_GENERIC_ADC_THERMAL=m +CONFIG_QCOM_TSENS=y CONFIG_UNIPHIER_THERMAL=y CONFIG_DA9063_WATCHDOG=m CONFIG_XILINX_WATCHDOG=y @@ -531,11 +551,13 @@ CONFIG_SUNXI_WATCHDOG=y CONFIG_IMX2_WDT=y CONFIG_ST_LPC_WATCHDOG=y CONFIG_TEGRA_WATCHDOG=m +CONFIG_QCOM_WDT=m CONFIG_MESON_WATCHDOG=y CONFIG_DIGICOLOR_WATCHDOG=y CONFIG_RENESAS_WDT=m CONFIG_RENESAS_RZAWDT=m CONFIG_STPMIC1_WATCHDOG=y +CONFIG_PM8916_WATCHDOG=m CONFIG_BCM47XX_WDT=y CONFIG_BCM2835_WDT=y CONFIG_BCM_KONA_WDT=y @@ -602,7 +624,8 @@ CONFIG_REGULATOR_PALMAS=y CONFIG_REGULATOR_PBIAS=y CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_RPM=y -CONFIG_REGULATOR_QCOM_SMD_RPM=m +CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_RN5T618=y CONFIG_REGULATOR_S2MPA01=m @@ -691,6 +714,7 @@ CONFIG_DRM_PANEL_RAYDIUM_RM68200=m CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m CONFIG_DRM_LVDS_CODEC=m +CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_NXP_PTN3460=m CONFIG_DRM_PARADE_PS8622=m CONFIG_DRM_SII902X=m @@ -741,6 +765,8 @@ CONFIG_SND_SOC_FSL_SAI=m CONFIG_SND_PXA_SOC_SSP=m CONFIG_SND_MMP_SOC_SSPA=m CONFIG_SND_PXA910_SOC=m +CONFIG_SND_SOC_QCOM=m +CONFIG_SND_SOC_APQ8016_SBC=m CONFIG_SND_SOC_ROCKCHIP=m CONFIG_SND_SOC_ROCKCHIP_SPDIF=m CONFIG_SND_SOC_ROCKCHIP_MAX98090=m @@ -774,6 +800,8 @@ CONFIG_SND_SOC_TEGRA_MAX98090=m CONFIG_SND_SOC_AK4642=m CONFIG_SND_SOC_CPCAP=m CONFIG_SND_SOC_CS42L51_I2C=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_STI_SAS=m CONFIG_SND_SOC_WM8978=m @@ -936,6 +964,7 @@ CONFIG_RTC_DRV_AT91SAM9=m CONFIG_RTC_DRV_VT8500=y CONFIG_RTC_DRV_SUNXI=y CONFIG_RTC_DRV_MV=y +CONFIG_RTC_DRV_PM8XXX=m CONFIG_RTC_DRV_TEGRA=y CONFIG_RTC_DRV_ST_LPC=y CONFIG_RTC_DRV_STM32=y @@ -984,26 +1013,47 @@ CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_S2MPS11=m CONFIG_CLK_RASPBERRYPI=y CONFIG_COMMON_CLK_QCOM=y +CONFIG_QCOM_A53PLL=y +CONFIG_QCOM_CLK_APCS_MSM8916=y CONFIG_QCOM_CLK_RPM=y +CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_APQ_MMCC_8084=y CONFIG_MSM_GCC_8660=y +CONFIG_MSM_GCC_8916=y CONFIG_MSM_MMCC_8960=y CONFIG_MSM_MMCC_8974=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y CONFIG_MICROCHIP_PIT64B=y CONFIG_BCM2835_MBOX=y +CONFIG_QCOM_APCS_IPC=y +CONFIG_QCOM_IPCC=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_EXYNOS_IOMMU=y +CONFIG_QCOM_IOMMU=y CONFIG_REMOTEPROC=y +CONFIG_QCOM_Q6V5_MSS=m +CONFIG_QCOM_SYSMON=m +CONFIG_QCOM_WCNSS_PIL=m CONFIG_ST_REMOTEPROC=m +CONFIG_RPMSG_QCOM_SMD=y CONFIG_RPMSG_VIRTIO=m CONFIG_ASPEED_LPC_CTRL=m CONFIG_ASPEED_LPC_SNOOP=m CONFIG_ASPEED_P2A_CTRL=m CONFIG_RASPBERRYPI_POWER=y +CONFIG_QCOM_CPR=y CONFIG_QCOM_GSBI=y -CONFIG_QCOM_SMD_RPM=m +CONFIG_QCOM_RMTFS_MEM=m +CONFIG_QCOM_RPMPD=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMD_RPM=y +CONFIG_QCOM_SMP2P=y +CONFIG_QCOM_SMSM=y +CONFIG_QCOM_SOCINFO=m +CONFIG_QCOM_STATS=m CONFIG_QCOM_WCNSS_CTRL=m CONFIG_ARCH_EMEV2=y CONFIG_ARCH_R8A7794=y @@ -1036,6 +1086,7 @@ CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=m CONFIG_EXTCON_MAX14577=m CONFIG_EXTCON_MAX77693=m CONFIG_EXTCON_MAX8997=m +CONFIG_EXTCON_USB_GPIO=y CONFIG_TI_AEMIF=y CONFIG_STM32_FMC2_EBI=y CONFIG_EXYNOS5422_DMC=m @@ -1048,6 +1099,7 @@ CONFIG_BERLIN2_ADC=m CONFIG_CPCAP_ADC=m CONFIG_EXYNOS_ADC=m CONFIG_MESON_SARADC=m +CONFIG_QCOM_SPMI_VADC=m CONFIG_ROCKCHIP_SARADC=m CONFIG_STM32_ADC_CORE=m CONFIG_STM32_ADC=m @@ -1090,9 +1142,11 @@ CONFIG_PHY_SUN9I_USB=y CONFIG_PHY_HIX5HD2_SATA=y CONFIG_PHY_BERLIN_SATA=y CONFIG_PHY_BERLIN_USB=y +CONFIG_PHY_BRCM_USB=m CONFIG_PHY_MMP3_USB=m CONFIG_PHY_CPCAP_USB=m CONFIG_PHY_QCOM_APQ8064_SATA=m +CONFIG_PHY_QCOM_USB_HS=y CONFIG_PHY_RCAR_GEN2=m CONFIG_PHY_ROCKCHIP_DP=m CONFIG_PHY_ROCKCHIP_USB=y @@ -1110,6 +1164,7 @@ CONFIG_TI_PIPE3=y CONFIG_TWL4030_USB=m CONFIG_RAS=y CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_QCOM_QFPROM=y CONFIG_ROCKCHIP_EFUSE=m CONFIG_NVMEM_SUNXI_SID=y CONFIG_NVMEM_VF610_OCOTP=y @@ -1122,6 +1177,8 @@ CONFIG_FSI_MASTER_ASPEED=m CONFIG_FSI_SCOM=m CONFIG_FSI_SBEFIFO=m CONFIG_FSI_OCC=m +CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_MSM8916=y CONFIG_COUNTER=m CONFIG_STM32_TIMER_CNT=m CONFIG_STM32_LPTIMER_CNT=m @@ -1161,6 +1218,8 @@ CONFIG_CRYPTO_DEV_ATMEL_AES=m CONFIG_CRYPTO_DEV_ATMEL_TDES=m CONFIG_CRYPTO_DEV_ATMEL_SHA=m CONFIG_CRYPTO_DEV_MARVELL_CESA=m +CONFIG_CRYPTO_DEV_QCE=m +CONFIG_CRYPTO_DEV_QCOM_RNG=m CONFIG_CRYPTO_DEV_ROCKCHIP=m CONFIG_CRYPTO_DEV_STM32_CRC=m CONFIG_CRYPTO_DEV_STM32_HASH=m diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index dedaaae3d0d8..29b1f192afbb 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig @@ -41,8 +41,6 @@ CONFIG_MACH_EXEDA=y CONFIG_MACH_CM_X300=y CONFIG_MACH_CAPC7117=y CONFIG_ARCH_GUMSTIX=y -CONFIG_MACH_INTELMOTE2=y -CONFIG_MACH_STARGATE2=y CONFIG_MACH_XCEP=y CONFIG_TRIZEPS_PXA=y CONFIG_MACH_TRIZEPS4WL=y @@ -487,7 +485,6 @@ CONFIG_SND_SOC_ZYLONITE=m CONFIG_SND_PXA2XX_SOC_HX4700=m CONFIG_SND_PXA2XX_SOC_MAGICIAN=m CONFIG_SND_PXA2XX_SOC_MIOA701=m -CONFIG_SND_PXA2XX_SOC_IMOTE2=m CONFIG_SND_SOC_AK4642=m CONFIG_SND_SOC_WM8978=m CONFIG_SND_SIMPLE_CARD=m diff --git a/arch/arm/configs/sama7_defconfig b/arch/arm/configs/sama7_defconfig index 0368068e04d9..07b0494ef743 100644 --- a/arch/arm/configs/sama7_defconfig +++ b/arch/arm/configs/sama7_defconfig @@ -26,6 +26,13 @@ CONFIG_FORCE_MAX_ZONEORDER=15 CONFIG_UACCESS_WITH_MEMCPY=y # CONFIG_ATAGS is not set CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk ignore_loglevel" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_IDLE=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_KERNEL_MODE_NEON=y @@ -82,7 +89,11 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_MTD=y CONFIG_MTD_TESTS=m CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_ATMEL=y +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 @@ -170,21 +181,21 @@ CONFIG_RTC_DRV_AT91RM9200=y CONFIG_RTC_DRV_AT91SAM9=y CONFIG_DMADEVICES=y CONFIG_AT_XDMAC=y -CONFIG_DMATEST=y CONFIG_STAGING=y CONFIG_MICROCHIP_PIT64B=y # CONFIG_IOMMU_SUPPORT is not set -# CONFIG_ATMEL_EBI is not set CONFIG_IIO=y CONFIG_IIO_SW_TRIGGER=y CONFIG_AT91_SAMA5D2_ADC=y CONFIG_PWM=y CONFIG_PWM_ATMEL=y +CONFIG_MCHP_EIC=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_FANOTIFY=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y +CONFIG_UBIFS_FS=y CONFIG_NFS_FS=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y @@ -192,9 +203,19 @@ CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y CONFIG_LSM="N" -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_HW is not set +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CFB=y +CONFIG_CRYPTO_OFB=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_DEV_ATMEL_AES=y +CONFIG_CRYPTO_DEV_ATMEL_TDES=y +CONFIG_CRYPTO_DEV_ATMEL_SHA=y CONFIG_CRC_CCITT=y CONFIG_CRC_ITU_T=y CONFIG_DMA_CMA=y diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 2c2702ec6d02..db8df8a3a7b1 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -69,9 +69,13 @@ CONFIG_INPUT_DA9063_ONKEY=y CONFIG_INPUT_ADXL34X=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_8250_EM=y +# CONFIG_SERIAL_8250_PERICOM is not set CONFIG_SERIAL_SH_SCI=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_DEMUX_PINCTRL=y diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index aee73ef5b3dc..34fe8d2dd5d1 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -86,6 +86,10 @@ #define IMM12_MASK 0xfff +/* the frame pointer used for stack unwinding */ +ARM( fpreg .req r11 ) +THUMB( fpreg .req r7 ) + /* * Enable and disable interrupts */ @@ -209,43 +213,12 @@ .endm .endr - .macro get_current, rd -#ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO - mrc p15, 0, \rd, c13, c0, 3 @ get TPIDRURO register -#else - get_thread_info \rd - ldr \rd, [\rd, #TI_TASK] -#endif - .endm - - .macro set_current, rn -#ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO - mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register -#endif - .endm - - .macro reload_current, t1:req, t2:req -#ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO - adr_l \t1, __entry_task @ get __entry_task base address - mrc p15, 0, \t2, c13, c0, 4 @ get per-CPU offset - ldr \t1, [\t1, \t2] @ load variable - mcr p15, 0, \t1, c13, c0, 3 @ store in TPIDRURO -#endif - .endm - /* * Get current thread_info. */ .macro get_thread_info, rd -#ifdef CONFIG_THREAD_INFO_IN_TASK /* thread_info is the first member of struct task_struct */ get_current \rd -#else - ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT ) - THUMB( mov \rd, sp ) - THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT ) - mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT -#endif .endm /* @@ -320,6 +293,80 @@ #define ALT_UP_B(label) b label #endif + /* + * this_cpu_offset - load the per-CPU offset of this CPU into + * register 'rd' + */ + .macro this_cpu_offset, rd:req +#ifdef CONFIG_SMP +ALT_SMP(mrc p15, 0, \rd, c13, c0, 4) +#ifdef CONFIG_CPU_V6 +ALT_UP_B(.L1_\@) +.L0_\@: + .subsection 1 +.L1_\@: ldr_va \rd, __per_cpu_offset + b .L0_\@ + .previous +#endif +#else + mov \rd, #0 +#endif + .endm + + /* + * set_current - store the task pointer of this CPU's current task + */ + .macro set_current, rn:req, tmp:req +#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP) +9998: mcr p15, 0, \rn, c13, c0, 3 @ set TPIDRURO register +#ifdef CONFIG_CPU_V6 +ALT_UP_B(.L0_\@) + .subsection 1 +.L0_\@: str_va \rn, __current, \tmp + b .L1_\@ + .previous +.L1_\@: +#endif +#else + str_va \rn, __current, \tmp +#endif + .endm + + /* + * get_current - load the task pointer of this CPU's current task + */ + .macro get_current, rd:req +#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP) +9998: mrc p15, 0, \rd, c13, c0, 3 @ get TPIDRURO register +#ifdef CONFIG_CPU_V6 +ALT_UP_B(.L0_\@) + .subsection 1 +.L0_\@: ldr_va \rd, __current + b .L1_\@ + .previous +.L1_\@: +#endif +#else + ldr_va \rd, __current +#endif + .endm + + /* + * reload_current - reload the task pointer of this CPU's current task + * into the TLS register + */ + .macro reload_current, t1:req, t2:req +#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP) +#ifdef CONFIG_CPU_V6 +ALT_SMP(nop) +ALT_UP_B(.L0_\@) +#endif + ldr_this_cpu \t1, __entry_task, \t1, \t2 + mcr p15, 0, \t1, c13, c0, 3 @ store in TPIDRURO +.L0_\@: +#endif + .endm + /* * Instruction barrier */ @@ -576,12 +623,12 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) /* * mov_l - move a constant value or [relocated] address into a register */ - .macro mov_l, dst:req, imm:req + .macro mov_l, dst:req, imm:req, cond .if __LINUX_ARM_ARCH__ < 7 - ldr \dst, =\imm + ldr\cond \dst, =\imm .else - movw \dst, #:lower16:\imm - movt \dst, #:upper16:\imm + movw\cond \dst, #:lower16:\imm + movt\cond \dst, #:upper16:\imm .endif .endm @@ -619,6 +666,78 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) __adldst_l str, \src, \sym, \tmp, \cond .endm + .macro __ldst_va, op, reg, tmp, sym, cond +#if __LINUX_ARM_ARCH__ >= 7 || \ + !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \ + (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) + mov_l \tmp, \sym, \cond + \op\cond \reg, [\tmp] +#else + /* + * Avoid a literal load, by emitting a sequence of ADD/LDR instructions + * with the appropriate relocations. The combined sequence has a range + * of -/+ 256 MiB, which should be sufficient for the core kernel and + * for modules loaded into the module region. + */ + .globl \sym + .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym + .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym + .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym +.L0_\@: sub\cond \tmp, pc, #8 +.L1_\@: sub\cond \tmp, \tmp, #4 +.L2_\@: \op\cond \reg, [\tmp, #0] +#endif + .endm + + /* + * ldr_va - load a 32-bit word from the virtual address of \sym + */ + .macro ldr_va, rd:req, sym:req, cond + __ldst_va ldr, \rd, \rd, \sym, \cond + .endm + + /* + * str_va - store a 32-bit word to the virtual address of \sym + */ + .macro str_va, rn:req, sym:req, tmp:req, cond + __ldst_va str, \rn, \tmp, \sym, \cond + .endm + + /* + * ldr_this_cpu_armv6 - Load a 32-bit word from the per-CPU variable 'sym', + * without using a temp register. Supported in ARM mode + * only. + */ + .macro ldr_this_cpu_armv6, rd:req, sym:req + this_cpu_offset \rd + .globl \sym + .reloc .L0_\@, R_ARM_ALU_PC_G0_NC, \sym + .reloc .L1_\@, R_ARM_ALU_PC_G1_NC, \sym + .reloc .L2_\@, R_ARM_LDR_PC_G2, \sym + add \rd, \rd, pc +.L0_\@: sub \rd, \rd, #4 +.L1_\@: sub \rd, \rd, #0 +.L2_\@: ldr \rd, [\rd, #4] + .endm + + /* + * ldr_this_cpu - Load a 32-bit word from the per-CPU variable 'sym' + * into register 'rd', which may be the stack pointer, + * using 't1' and 't2' as general temp registers. These + * are permitted to overlap with 'rd' if != sp + */ + .macro ldr_this_cpu, rd:req, sym:req, t1:req, t2:req +#if __LINUX_ARM_ARCH__ >= 7 || \ + !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \ + (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) + this_cpu_offset \t1 + mov_l \t2, \sym + ldr \rd, [\t1, \t2] +#else + ldr_this_cpu_armv6 \rd, \sym +#endif + .endm + /* * rev_l - byte-swap a 32-bit value * @@ -636,4 +755,19 @@ THUMB( orr \reg , \reg , #PSR_T_BIT ) .endif .endm + /* + * bl_r - branch and link to register + * + * @dst: target to branch to + * @c: conditional opcode suffix + */ + .macro bl_r, dst:req, c + .if __LINUX_ARM_ARCH__ < 6 + mov\c lr, pc + mov\c pc, \dst + .else + blx\c \dst + .endif + .endm + #endif /* __ASM_ASSEMBLER_H__ */ diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 5e56288e343b..a094f964c869 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -445,15 +445,10 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size) * however some exceptions may exist. Caveat emptor. * * - The clobber list is dictated by the call to v7_flush_dcache_*. - * fp is preserved to the stack explicitly prior disabling the cache - * since adding it to the clobber list is incompatible with having - * CONFIG_FRAME_POINTER=y. ip is saved as well if ever r12-clobbering - * trampoline are inserted by the linker and to keep sp 64-bit aligned. */ #define v7_exit_coherency_flush(level) \ asm volatile( \ ".arch armv7-a \n\t" \ - "stmfd sp!, {fp, ip} \n\t" \ "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR \n\t" \ "bic r0, r0, #"__stringify(CR_C)" \n\t" \ "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \ @@ -463,10 +458,9 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size) "bic r0, r0, #(1 << 6) @ disable local coherency \n\t" \ "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \ "isb \n\t" \ - "dsb \n\t" \ - "ldmfd sp!, {fp, ip}" \ - : : : "r0","r1","r2","r3","r4","r5","r6","r7", \ - "r9","r10","lr","memory" ) + "dsb" \ + : : : "r0","r1","r2","r3","r4","r5","r6", \ + "r9","r10","ip","lr","memory" ) void flush_uprobe_xol_access(struct page *page, unsigned long uaddr, void *kaddr, unsigned long len); diff --git a/arch/arm/include/asm/current.h b/arch/arm/include/asm/current.h index 6bf0aad672c3..1e1178bf176d 100644 --- a/arch/arm/include/asm/current.h +++ b/arch/arm/include/asm/current.h @@ -8,25 +8,18 @@ #define _ASM_ARM_CURRENT_H #ifndef __ASSEMBLY__ +#include struct task_struct; -static inline void set_current(struct task_struct *cur) -{ - if (!IS_ENABLED(CONFIG_CURRENT_POINTER_IN_TPIDRURO)) - return; +extern struct task_struct *__current; - /* Set TPIDRURO */ - asm("mcr p15, 0, %0, c13, c0, 3" :: "r"(cur) : "memory"); -} - -#ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO - -static inline struct task_struct *get_current(void) +static __always_inline __attribute_const__ struct task_struct *get_current(void) { struct task_struct *cur; #if __has_builtin(__builtin_thread_pointer) && \ + defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) && \ !(defined(CONFIG_THUMB2_KERNEL) && \ defined(CONFIG_CC_IS_CLANG) && CONFIG_CLANG_VERSION < 130001) /* @@ -39,16 +32,39 @@ static inline struct task_struct *get_current(void) * https://github.com/ClangBuiltLinux/linux/issues/1485 */ cur = __builtin_thread_pointer(); +#elif defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP) + asm("0: mrc p15, 0, %0, c13, c0, 3 \n\t" +#ifdef CONFIG_CPU_V6 + "1: \n\t" + " .subsection 1 \n\t" +#if defined(CONFIG_ARM_HAS_GROUP_RELOCS) && \ + !(defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) + "2: " LOAD_SYM_ARMV6(%0, __current) " \n\t" + " b 1b \n\t" #else - asm("mrc p15, 0, %0, c13, c0, 3" : "=r"(cur)); + "2: ldr %0, 3f \n\t" + " ldr %0, [%0] \n\t" + " b 1b \n\t" + "3: .long __current \n\t" +#endif + " .previous \n\t" + " .pushsection \".alt.smp.init\", \"a\" \n\t" + " .long 0b - . \n\t" + " b . + (2b - 0b) \n\t" + " .popsection \n\t" +#endif + : "=r"(cur)); +#elif __LINUX_ARM_ARCH__>= 7 || \ + !defined(CONFIG_ARM_HAS_GROUP_RELOCS) || \ + (defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) + cur = __current; +#else + asm(LOAD_SYM_ARMV6(%0, __current) : "=r"(cur)); #endif return cur; } #define current get_current() -#else -#include -#endif /* CONFIG_CURRENT_POINTER_IN_TPIDRURO */ #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index b8102a6ddf16..d68101655b74 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h @@ -61,6 +61,9 @@ typedef struct user_fp elf_fpregset_t; #define R_ARM_MOVT_ABS 44 #define R_ARM_MOVW_PREL_NC 45 #define R_ARM_MOVT_PREL 46 +#define R_ARM_ALU_PC_G0_NC 57 +#define R_ARM_ALU_PC_G1_NC 59 +#define R_ARM_LDR_PC_G2 63 #define R_ARM_THM_CALL 10 #define R_ARM_THM_JUMP24 30 diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S deleted file mode 100644 index dfc6bfa43012..000000000000 --- a/arch/arm/include/asm/entry-macro-multi.S +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#include - -/* - * Interrupt handling. Preserves r7, r8, r9 - */ - .macro arch_irq_handler_default - get_irqnr_preamble r6, lr -1: get_irqnr_and_base r0, r2, r6, lr - movne r1, sp - @ - @ routine called with r0 = irq number, r1 = struct pt_regs * - @ - badrne lr, 1b - bne asm_do_IRQ - -#ifdef CONFIG_SMP - /* - * XXX - * - * this macro assumes that irqstat (r2) and base (r6) are - * preserved from get_irqnr_and_base above - */ - ALT_SMP(test_for_ipi r0, r2, r6, lr) - ALT_UP_B(9997f) - movne r1, sp - badrne lr, 1b - bne do_IPI -#endif -9997: - .endm - - .macro arch_irq_handler, symbol_name - .align 5 - .global \symbol_name -\symbol_name: - mov r8, lr - arch_irq_handler_default - ret r8 - .endm diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h index a4dbac07e4ef..7e9251ca29fe 100644 --- a/arch/arm/include/asm/ftrace.h +++ b/arch/arm/include/asm/ftrace.h @@ -2,6 +2,8 @@ #ifndef _ASM_ARM_FTRACE #define _ASM_ARM_FTRACE +#define HAVE_FUNCTION_GRAPH_FP_TEST + #ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS #define ARCH_SUPPORTS_FTRACE_OPS 1 #endif @@ -48,7 +50,7 @@ void *return_address(unsigned int); static inline void *return_address(unsigned int level) { - return NULL; + return NULL; } #endif diff --git a/arch/arm/include/asm/hardware/entry-macro-iomd.S b/arch/arm/include/asm/hardware/entry-macro-iomd.S deleted file mode 100644 index f7692731e514..000000000000 --- a/arch/arm/include/asm/hardware/entry-macro-iomd.S +++ /dev/null @@ -1,131 +0,0 @@ -/* - * arch/arm/include/asm/hardware/entry-macro-iomd.S - * - * Low-level IRQ helper macros for IOC/IOMD based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -/* IOC / IOMD based hardware */ -#include - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldrb \irqstat, [\base, #IOMD_IRQREQB] @ get high priority first - ldr \tmp, =irq_prio_h - teq \irqstat, #0 -#ifdef IOMD_BASE - ldrbeq \irqstat, [\base, #IOMD_DMAREQ] @ get dma - addeq \tmp, \tmp, #256 @ irq_prio_h table size - teqeq \irqstat, #0 - bne 2406f -#endif - ldrbeq \irqstat, [\base, #IOMD_IRQREQA] @ get low priority - addeq \tmp, \tmp, #256 @ irq_prio_d table size - teqeq \irqstat, #0 -#ifdef IOMD_IRQREQC - ldrbeq \irqstat, [\base, #IOMD_IRQREQC] - addeq \tmp, \tmp, #256 @ irq_prio_l table size - teqeq \irqstat, #0 -#endif -#ifdef IOMD_IRQREQD - ldrbeq \irqstat, [\base, #IOMD_IRQREQD] - addeq \tmp, \tmp, #256 @ irq_prio_lc table size - teqeq \irqstat, #0 -#endif -2406: ldrbne \irqnr, [\tmp, \irqstat] @ get IRQ number - .endm - -/* - * Interrupt table (incorporates priority). Please note that we - * rely on the order of these tables (see above code). - */ - .align 5 -irq_prio_h: .byte 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 - .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10 -#ifdef IOMD_BASE -irq_prio_d: .byte 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 - .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16 -#endif -irq_prio_l: .byte 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 - .byte 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 - .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 - .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 - .byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3 - .byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3 - .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 - .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 - .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 - .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 - .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 - .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 - .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 - .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 - .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 - .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7 -#ifdef IOMD_IRQREQC -irq_prio_lc: .byte 24,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27 - .byte 28,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27 - .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29 - .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29 - .byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27 - .byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27 - .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29 - .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29 - .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 - .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 - .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 - .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 - .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 - .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 - .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 - .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31 -#endif -#ifdef IOMD_IRQREQD -irq_prio_ld: .byte 40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43 - .byte 44,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43 - .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45 - .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45 - .byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43 - .byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43 - .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45 - .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45 - .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 - .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 - .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 - .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 - .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 - .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 - .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 - .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47 -#endif - diff --git a/arch/arm/include/asm/insn.h b/arch/arm/include/asm/insn.h index 5475cbf9fb6b..faf3d1c28368 100644 --- a/arch/arm/include/asm/insn.h +++ b/arch/arm/include/asm/insn.h @@ -2,6 +2,23 @@ #ifndef __ASM_ARM_INSN_H #define __ASM_ARM_INSN_H +#include + +/* + * Avoid a literal load by emitting a sequence of ADD/LDR instructions with the + * appropriate relocations. The combined sequence has a range of -/+ 256 MiB, + * which should be sufficient for the core kernel as well as modules loaded + * into the module region. (Not supported by LLD before release 14) + */ +#define LOAD_SYM_ARMV6(reg, sym) \ + " .globl " #sym " \n\t" \ + " .reloc 10f, R_ARM_ALU_PC_G0_NC, " #sym " \n\t" \ + " .reloc 11f, R_ARM_ALU_PC_G1_NC, " #sym " \n\t" \ + " .reloc 12f, R_ARM_LDR_PC_G2, " #sym " \n\t" \ + "10: sub " #reg ", pc, #8 \n\t" \ + "11: sub " #reg ", " #reg ", #4 \n\t" \ + "12: ldr " #reg ", [" #reg ", #0] \n\t" + static inline unsigned long arm_gen_nop(void) { diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h index 1cbcc462b07e..a7c2337b0c7d 100644 --- a/arch/arm/include/asm/irq.h +++ b/arch/arm/include/asm/irq.h @@ -26,7 +26,6 @@ struct irqaction; struct pt_regs; -extern void asm_do_IRQ(unsigned int, struct pt_regs *); void handle_IRQ(unsigned int, struct pt_regs *); void init_IRQ(void); diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h index eec0c0bda766..9349e7a82c9c 100644 --- a/arch/arm/include/asm/mach/arch.h +++ b/arch/arm/include/asm/mach/arch.h @@ -56,9 +56,7 @@ struct machine_desc { void (*init_time)(void); void (*init_machine)(void); void (*init_late)(void); -#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER void (*handle_irq)(struct pt_regs *); -#endif void (*restart)(enum reboot_mode, const char *); }; diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h index 1592a4264488..e049723840d3 100644 --- a/arch/arm/include/asm/mmu.h +++ b/arch/arm/include/asm/mmu.h @@ -10,7 +10,7 @@ typedef struct { #else int switch_pending; #endif - unsigned int vmalloc_seq; + atomic_t vmalloc_seq; unsigned long sigpage; #ifdef CONFIG_VDSO unsigned long vdso; diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h index 84e58956fcab..db2cb06aa8cf 100644 --- a/arch/arm/include/asm/mmu_context.h +++ b/arch/arm/include/asm/mmu_context.h @@ -23,6 +23,16 @@ void __check_vmalloc_seq(struct mm_struct *mm); +#ifdef CONFIG_MMU +static inline void check_vmalloc_seq(struct mm_struct *mm) +{ + if (!IS_ENABLED(CONFIG_ARM_LPAE) && + unlikely(atomic_read(&mm->context.vmalloc_seq) != + atomic_read(&init_mm.context.vmalloc_seq))) + __check_vmalloc_seq(mm); +} +#endif + #ifdef CONFIG_CPU_HAS_ASID void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); @@ -52,8 +62,7 @@ static inline void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm, static inline void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk) { - if (unlikely(mm->context.vmalloc_seq != init_mm.context.vmalloc_seq)) - __check_vmalloc_seq(mm); + check_vmalloc_seq(mm); if (irqs_disabled()) /* @@ -129,6 +138,15 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next, #endif } +#ifdef CONFIG_VMAP_STACK +static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) +{ + if (mm != &init_mm) + check_vmalloc_seq(mm); +} +#define enter_lazy_tlb enter_lazy_tlb +#endif + #include #endif diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index 11b058a72a5b..5fcc8a600e36 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h @@ -147,6 +147,9 @@ extern void copy_page(void *to, const void *from); #include #else #include +#ifdef CONFIG_VMAP_STACK +#define ARCH_PAGE_TABLE_SYNC_MASK PGTBL_PMD_MODIFIED +#endif #endif #endif /* CONFIG_MMU */ diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h index e2fcb3cfd3de..7545c87c251f 100644 --- a/arch/arm/include/asm/percpu.h +++ b/arch/arm/include/asm/percpu.h @@ -5,20 +5,27 @@ #ifndef _ASM_ARM_PERCPU_H_ #define _ASM_ARM_PERCPU_H_ +#include + register unsigned long current_stack_pointer asm ("sp"); /* * Same as asm-generic/percpu.h, except that we store the per cpu offset * in the TPIDRPRW. TPIDRPRW only exists on V6K and V7 */ -#if defined(CONFIG_SMP) && !defined(CONFIG_CPU_V6) +#ifdef CONFIG_SMP static inline void set_my_cpu_offset(unsigned long off) { + extern unsigned int smp_on_up; + + if (IS_ENABLED(CONFIG_CPU_V6) && !smp_on_up) + return; + /* Set TPIDRPRW */ asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory"); } -static inline unsigned long __my_cpu_offset(void) +static __always_inline unsigned long __my_cpu_offset(void) { unsigned long off; @@ -27,8 +34,28 @@ static inline unsigned long __my_cpu_offset(void) * We want to allow caching the value, so avoid using volatile and * instead use a fake stack read to hazard against barrier(). */ - asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) - : "Q" (*(const unsigned long *)current_stack_pointer)); + asm("0: mrc p15, 0, %0, c13, c0, 4 \n\t" +#ifdef CONFIG_CPU_V6 + "1: \n\t" + " .subsection 1 \n\t" +#if defined(CONFIG_ARM_HAS_GROUP_RELOCS) && \ + !(defined(MODULE) && defined(CONFIG_ARM_MODULE_PLTS)) + "2: " LOAD_SYM_ARMV6(%0, __per_cpu_offset) " \n\t" + " b 1b \n\t" +#else + "2: ldr %0, 3f \n\t" + " ldr %0, [%0] \n\t" + " b 1b \n\t" + "3: .long __per_cpu_offset \n\t" +#endif + " .previous \n\t" + " .pushsection \".alt.smp.init\", \"a\" \n\t" + " .long 0b - . \n\t" + " b . + (2b - 0b) \n\t" + " .popsection \n\t" +#endif + : "=r" (off) + : "Q" (*(const unsigned long *)current_stack_pointer)); return off; } diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index f16cbbd5cda4..7c1c90d9f582 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h @@ -24,11 +24,6 @@ struct seq_file; */ extern void show_ipi_list(struct seq_file *, int); -/* - * Called from assembly code, this handles an IPI. - */ -asmlinkage void do_IPI(int ipinr, struct pt_regs *regs); - /* * Called from C code, this handles an IPI. */ diff --git a/arch/arm/include/asm/stacktrace.h b/arch/arm/include/asm/stacktrace.h index 8f54f9ad8a9b..3e78f921b8b2 100644 --- a/arch/arm/include/asm/stacktrace.h +++ b/arch/arm/include/asm/stacktrace.h @@ -14,6 +14,9 @@ struct stackframe { unsigned long sp; unsigned long lr; unsigned long pc; + + /* address of the LR value on the stack */ + unsigned long *lr_addr; #ifdef CONFIG_KRETPROBES struct llist_node *kr_cur; struct task_struct *tsk; @@ -36,5 +39,7 @@ void arm_get_current_stackframe(struct pt_regs *regs, struct stackframe *frame) extern int unwind_frame(struct stackframe *frame); extern void walk_stackframe(struct stackframe *frame, int (*fn)(struct stackframe *, void *), void *data); +extern void dump_mem(const char *lvl, const char *str, unsigned long bottom, + unsigned long top); #endif /* __ASM_STACKTRACE_H */ diff --git a/arch/arm/include/asm/switch_to.h b/arch/arm/include/asm/switch_to.h index 61e4a3c4ca6e..9372348516ce 100644 --- a/arch/arm/include/asm/switch_to.h +++ b/arch/arm/include/asm/switch_to.h @@ -3,6 +3,7 @@ #define __ASM_ARM_SWITCH_TO_H #include +#include /* * For v7 SMP cores running a preemptible kernel we may be pre-empted @@ -26,7 +27,7 @@ extern struct task_struct *__switch_to(struct task_struct *, struct thread_info #define switch_to(prev,next,last) \ do { \ __complete_pending_tlbi(); \ - if (IS_ENABLED(CONFIG_CURRENT_POINTER_IN_TPIDRURO)) \ + if (IS_ENABLED(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || is_smp()) \ __this_cpu_write(__entry_task, next); \ last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \ } while (0) diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 164e15f26485..aecc403b2880 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -25,6 +25,14 @@ #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) #define THREAD_START_SP (THREAD_SIZE - 8) +#ifdef CONFIG_VMAP_STACK +#define THREAD_ALIGN (2 * THREAD_SIZE) +#else +#define THREAD_ALIGN THREAD_SIZE +#endif + +#define OVERFLOW_STACK_SIZE SZ_4K + #ifndef __ASSEMBLY__ struct task_struct; @@ -54,9 +62,6 @@ struct cpu_context_save { struct thread_info { unsigned long flags; /* low level flags */ int preempt_count; /* 0 => preemptable, <0 => bug */ -#ifndef CONFIG_THREAD_INFO_IN_TASK - struct task_struct *task; /* main task structure */ -#endif __u32 cpu; /* cpu */ __u32 cpu_domain; /* cpu domain */ struct cpu_context_save cpu_context; /* cpu context */ @@ -72,39 +77,15 @@ struct thread_info { #define INIT_THREAD_INFO(tsk) \ { \ - INIT_THREAD_INFO_TASK(tsk) \ .flags = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ } -#ifdef CONFIG_THREAD_INFO_IN_TASK -#define INIT_THREAD_INFO_TASK(tsk) - static inline struct task_struct *thread_task(struct thread_info* ti) { return (struct task_struct *)ti; } -#else -#define INIT_THREAD_INFO_TASK(tsk) .task = &(tsk), - -static inline struct task_struct *thread_task(struct thread_info* ti) -{ - return ti->task; -} - -/* - * how to get the thread information struct from C - */ -static inline struct thread_info *current_thread_info(void) __attribute_const__; - -static inline struct thread_info *current_thread_info(void) -{ - return (struct thread_info *) - (current_stack_pointer & ~(THREAD_SIZE - 1)); -} -#endif - #define thread_saved_pc(tsk) \ ((unsigned long)(task_thread_info(tsk)->cpu_context.pc)) #define thread_saved_sp(tsk) \ diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h index c3296499176c..3dcd0f71a0da 100644 --- a/arch/arm/include/asm/tls.h +++ b/arch/arm/include/asm/tls.h @@ -18,21 +18,32 @@ .endm .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2 - ldr \tmp1, =elf_hwcap - ldr \tmp1, [\tmp1, #0] +#ifdef CONFIG_SMP +ALT_SMP(nop) +ALT_UP_B(.L0_\@) + .subsection 1 +#endif +.L0_\@: + ldr_va \tmp1, elf_hwcap mov \tmp2, #0xffff0fff tst \tmp1, #HWCAP_TLS @ hardware TLS available? streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0 - mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register - mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register - mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register - strne \tmp2, [\base, #TI_TP_VALUE + 4] @ save it + beq .L2_\@ + mcr p15, 0, \tp, c13, c0, 3 @ yes, set TLS register +#ifdef CONFIG_SMP + b .L1_\@ + .previous +#endif +.L1_\@: switch_tls_v6k \base, \tp, \tpuser, \tmp1, \tmp2 +.L2_\@: .endm .macro switch_tls_software, base, tp, tpuser, tmp1, tmp2 mov \tmp1, #0xffff0fff str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0 .endm +#else +#include #endif #ifdef CONFIG_TLS_REG_EMUL @@ -43,7 +54,7 @@ #elif defined(CONFIG_CPU_V6) #define tls_emu 0 #define has_tls_reg (elf_hwcap & HWCAP_TLS) -#define defer_tls_reg_update 0 +#define defer_tls_reg_update is_smp() #define switch_tls switch_tls_v6 #elif defined(CONFIG_CPU_32v6K) #define tls_emu 0 @@ -81,11 +92,11 @@ static inline void set_tls(unsigned long val) */ barrier(); - if (!tls_emu && !defer_tls_reg_update) { - if (has_tls_reg) { + if (!tls_emu) { + if (has_tls_reg && !defer_tls_reg_update) { asm("mcr p15, 0, %0, c13, c0, 3" : : "r" (val)); - } else { + } else if (!has_tls_reg) { #ifdef CONFIG_KUSER_HELPERS /* * User space must never try to access this diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index 32dbfd81f42a..2fcbec9c306c 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -55,21 +55,6 @@ extern int __put_user_bad(void); #ifdef CONFIG_MMU -/* - * We use 33-bit arithmetic here. Success returns zero, failure returns - * addr_limit. We take advantage that addr_limit will be zero for KERNEL_DS, - * so this will always return success in that case. - */ -#define __range_ok(addr, size) ({ \ - unsigned long flag, roksum; \ - __chk_user_ptr(addr); \ - __asm__(".syntax unified\n" \ - "adds %1, %2, %3; sbcscc %1, %1, %0; movcc %0, #0" \ - : "=&r" (flag), "=&r" (roksum) \ - : "r" (addr), "Ir" (size), "0" (TASK_SIZE) \ - : "cc"); \ - flag; }) - /* * This is a type: either unsigned long, if the argument fits into * that type, or otherwise unsigned long long. @@ -241,15 +226,12 @@ extern int __put_user_8(void *, unsigned long long); #else /* CONFIG_MMU */ -#define __addr_ok(addr) ((void)(addr), 1) -#define __range_ok(addr, size) ((void)(addr), 0) - #define get_user(x, p) __get_user(x, p) #define __put_user_check __put_user_nocheck #endif /* CONFIG_MMU */ -#define access_ok(addr, size) (__range_ok(addr, size) == 0) +#include #ifdef CONFIG_CPU_SPECTRE /* @@ -476,8 +458,6 @@ do { \ : "r" (x), "i" (-EFAULT) \ : "cc") -#define HAVE_GET_KERNEL_NOFAULT - #define __get_kernel_nofault(dst, src, type, err_label) \ do { \ const type *__pk_ptr = (src); \ diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h index 2cb00d15831b..4512f7e1918f 100644 --- a/arch/arm/include/asm/v7m.h +++ b/arch/arm/include/asm/v7m.h @@ -13,6 +13,7 @@ #define V7M_SCB_ICSR_PENDSVSET (1 << 28) #define V7M_SCB_ICSR_PENDSVCLR (1 << 27) #define V7M_SCB_ICSR_RETTOBASE (1 << 11) +#define V7M_SCB_ICSR_VECTACTIVE 0x000001ff #define V7M_SCB_VTOR 0x08 @@ -38,7 +39,7 @@ #define V7M_SCB_SHCSR_MEMFAULTENA (1 << 16) #define V7M_xPSR_FRAMEPTRALIGN 0x00000200 -#define V7M_xPSR_EXCEPTIONNO 0x000001ff +#define V7M_xPSR_EXCEPTIONNO V7M_SCB_ICSR_VECTACTIVE /* * When branching to an address that has bits [31:28] == 0xf an exception return diff --git a/arch/arm/include/uapi/asm/signal.h b/arch/arm/include/uapi/asm/signal.h index c9a3ea1d8d41..9e2178420db2 100644 --- a/arch/arm/include/uapi/asm/signal.h +++ b/arch/arm/include/uapi/asm/signal.h @@ -93,7 +93,7 @@ struct sigaction { typedef struct sigaltstack { void __user *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 6ef3b535b7bf..553866751e1a 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -10,6 +10,7 @@ ifdef CONFIG_FUNCTION_TRACER CFLAGS_REMOVE_ftrace.o = -pg CFLAGS_REMOVE_insn.o = -pg CFLAGS_REMOVE_patch.o = -pg +CFLAGS_REMOVE_unwind.o = -pg endif CFLAGS_REMOVE_return_address.o = -pg diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 645845e4982a..2c8d76fd7c66 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -43,9 +43,6 @@ int main(void) BLANK(); DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); -#ifndef CONFIG_THREAD_INFO_IN_TASK - DEFINE(TI_TASK, offsetof(struct thread_info, task)); -#endif DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); DEFINE(TI_CPU_DOMAIN, offsetof(struct thread_info, cpu_domain)); DEFINE(TI_CPU_SAVE, offsetof(struct thread_info, cpu_context)); diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index ee3f7a599181..06508698abb8 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -19,9 +19,6 @@ #include #include #include -#ifndef CONFIG_GENERIC_IRQ_MULTI_HANDLER -#include -#endif #include #include #include @@ -30,19 +27,35 @@ #include #include "entry-header.S" -#include #include /* * Interrupt handling. */ - .macro irq_handler -#ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER - mov r0, sp - bl generic_handle_arch_irq -#else - arch_irq_handler_default + .macro irq_handler, from_user:req + mov r1, sp + ldr_this_cpu r2, irq_stack_ptr, r2, r3 + .if \from_user == 0 + @ + @ If we took the interrupt while running in the kernel, we may already + @ be using the IRQ stack, so revert to the original value in that case. + @ + subs r3, r2, r1 @ SP above bottom of IRQ stack? + rsbscs r3, r3, #THREAD_SIZE @ ... and below the top? +#ifdef CONFIG_VMAP_STACK + ldr_va r3, high_memory, cc @ End of the linear region + cmpcc r3, r1 @ Stack pointer was below it? #endif + bcc 0f @ If not, switch to the IRQ stack + mov r0, r1 + bl generic_handle_arch_irq + b 1f +0: + .endif + + mov_l r0, generic_handle_arch_irq + bl call_with_stack +1: .endm .macro pabt_helper @@ -140,27 +153,35 @@ ENDPROC(__und_invalid) #define SPFIX(code...) #endif - .macro svc_entry, stack_hole=0, trace=1, uaccess=1 + .macro svc_entry, stack_hole=0, trace=1, uaccess=1, overflow_check=1 UNWIND(.fnstart ) - UNWIND(.save {r0 - pc} ) - sub sp, sp, #(SVC_REGS_SIZE + \stack_hole - 4) + sub sp, sp, #(SVC_REGS_SIZE + \stack_hole) + THUMB( add sp, r1 ) @ get SP in a GPR without + THUMB( sub r1, sp, r1 ) @ using a temp register + + .if \overflow_check + UNWIND(.save {r0 - pc} ) + do_overflow_check (SVC_REGS_SIZE + \stack_hole) + .endif + #ifdef CONFIG_THUMB2_KERNEL - SPFIX( str r0, [sp] ) @ temporarily saved - SPFIX( mov r0, sp ) - SPFIX( tst r0, #4 ) @ test original stack alignment - SPFIX( ldr r0, [sp] ) @ restored + tst r1, #4 @ test stack pointer alignment + sub r1, sp, r1 @ restore original R1 + sub sp, r1 @ restore original SP #else SPFIX( tst sp, #4 ) #endif - SPFIX( subeq sp, sp, #4 ) - stmia sp, {r1 - r12} + SPFIX( subne sp, sp, #4 ) + + ARM( stmib sp, {r1 - r12} ) + THUMB( stmia sp, {r0 - r12} ) @ No STMIB in Thumb-2 ldmia r0, {r3 - r5} - add r7, sp, #S_SP - 4 @ here for interlock avoidance + add r7, sp, #S_SP @ here for interlock avoidance mov r6, #-1 @ "" "" "" "" - add r2, sp, #(SVC_REGS_SIZE + \stack_hole - 4) - SPFIX( addeq r2, r2, #4 ) - str r3, [sp, #-4]! @ save the "real" r0 copied + add r2, sp, #(SVC_REGS_SIZE + \stack_hole) + SPFIX( addne r2, r2, #4 ) + str r3, [sp] @ save the "real" r0 copied @ from the exception stack mov r3, lr @@ -199,7 +220,7 @@ ENDPROC(__dabt_svc) .align 5 __irq_svc: svc_entry - irq_handler + irq_handler from_user=0 #ifdef CONFIG_PREEMPTION ldr r8, [tsk, #TI_PREEMPT] @ get preempt count @@ -426,7 +447,7 @@ ENDPROC(__dabt_usr) __irq_usr: usr_entry kuser_cmpxchg_check - irq_handler + irq_handler from_user=1 get_thread_info tsk mov why, #0 b ret_to_user_from_irq @@ -752,16 +773,17 @@ ENTRY(__switch_to) ldr r6, [r2, #TI_CPU_DOMAIN] #endif switch_tls r1, r4, r5, r3, r7 -#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) - ldr r7, [r2, #TI_TASK] +#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) && \ + !defined(CONFIG_STACKPROTECTOR_PER_TASK) ldr r8, =__stack_chk_guard .if (TSK_STACK_CANARY > IMM12_MASK) - add r7, r7, #TSK_STACK_CANARY & ~IMM12_MASK + add r9, r2, #TSK_STACK_CANARY & ~IMM12_MASK + ldr r9, [r9, #TSK_STACK_CANARY & IMM12_MASK] + .else + ldr r9, [r2, #TSK_STACK_CANARY & IMM12_MASK] .endif - ldr r7, [r7, #TSK_STACK_CANARY & IMM12_MASK] -#elif defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) - mov r7, r2 @ Preserve 'next' #endif + mov r7, r2 @ Preserve 'next' #ifdef CONFIG_CPU_USE_DOMAINS mcr p15, 0, r6, c3, c0, 0 @ Set domain register #endif @@ -770,19 +792,102 @@ ENTRY(__switch_to) ldr r0, =thread_notify_head mov r1, #THREAD_NOTIFY_SWITCH bl atomic_notifier_call_chain -#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) - str r7, [r8] +#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) && \ + !defined(CONFIG_STACKPROTECTOR_PER_TASK) + str r9, [r8] #endif - THUMB( mov ip, r4 ) mov r0, r5 - set_current r7 - ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously - THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously - THUMB( ldr sp, [ip], #4 ) - THUMB( ldr pc, [ip] ) +#if !defined(CONFIG_THUMB2_KERNEL) && !defined(CONFIG_VMAP_STACK) + set_current r7, r8 + ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously +#else + mov r1, r7 + ldmia r4, {r4 - sl, fp, ip, lr} @ Load all regs saved previously +#ifdef CONFIG_VMAP_STACK + @ + @ Do a dummy read from the new stack while running from the old one so + @ that we can rely on do_translation_fault() to fix up any stale PMD + @ entries covering the vmalloc region. + @ + ldr r2, [ip] +#endif + + @ When CONFIG_THREAD_INFO_IN_TASK=n, the update of SP itself is what + @ effectuates the task switch, as that is what causes the observable + @ values of current and current_thread_info to change. When + @ CONFIG_THREAD_INFO_IN_TASK=y, setting current (and therefore + @ current_thread_info) is done explicitly, and the update of SP just + @ switches us to another stack, with few other side effects. In order + @ to prevent this distinction from causing any inconsistencies, let's + @ keep the 'set_current' call as close as we can to the update of SP. + set_current r1, r2 + mov sp, ip + ret lr +#endif UNWIND(.fnend ) ENDPROC(__switch_to) +#ifdef CONFIG_VMAP_STACK + .text + .align 2 +__bad_stack: + @ + @ We've just detected an overflow. We need to load the address of this + @ CPU's overflow stack into the stack pointer register. We have only one + @ scratch register so let's use a sequence of ADDs including one + @ involving the PC, and decorate them with PC-relative group + @ relocations. As these are ARM only, switch to ARM mode first. + @ + @ We enter here with IP clobbered and its value stashed on the mode + @ stack. + @ +THUMB( bx pc ) +THUMB( nop ) +THUMB( .arm ) + ldr_this_cpu_armv6 ip, overflow_stack_ptr + + str sp, [ip, #-4]! @ Preserve original SP value + mov sp, ip @ Switch to overflow stack + pop {ip} @ Original SP in IP + +#if defined(CONFIG_UNWINDER_FRAME_POINTER) && defined(CONFIG_CC_IS_GCC) + mov ip, ip @ mov expected by unwinder + push {fp, ip, lr, pc} @ GCC flavor frame record +#else + str ip, [sp, #-8]! @ store original SP + push {fpreg, lr} @ Clang flavor frame record +#endif +UNWIND( ldr ip, [r0, #4] ) @ load exception LR +UNWIND( str ip, [sp, #12] ) @ store in the frame record + ldr ip, [r0, #12] @ reload IP + + @ Store the original GPRs to the new stack. + svc_entry uaccess=0, overflow_check=0 + +UNWIND( .save {sp, pc} ) +UNWIND( .save {fpreg, lr} ) +UNWIND( .setfp fpreg, sp ) + + ldr fpreg, [sp, #S_SP] @ Add our frame record + @ to the linked list +#if defined(CONFIG_UNWINDER_FRAME_POINTER) && defined(CONFIG_CC_IS_GCC) + ldr r1, [fp, #4] @ reload SP at entry + add fp, fp, #12 +#else + ldr r1, [fpreg, #8] +#endif + str r1, [sp, #S_SP] @ store in pt_regs + + @ Stash the regs for handle_bad_stack + mov r0, sp + + @ Time to die + bl handle_bad_stack + nop +UNWIND( .fnend ) +ENDPROC(__bad_stack) +#endif + __INIT /* diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index dbc1913ee30b..90d40f4d56cf 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -16,12 +16,14 @@ .equ NR_syscalls, __NR_syscalls -#ifdef CONFIG_NEED_RET_TO_USER -#include -#else - .macro arch_ret_to_user, tmp1, tmp2 - .endm + .macro arch_ret_to_user, tmp +#ifdef CONFIG_ARCH_IOP32X + mrc p15, 0, \tmp, c15, c1, 0 + tst \tmp, #(1 << 6) + bicne \tmp, \tmp, #(1 << 6) + mcrne p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access #endif + .endm #include "entry-header.S" @@ -55,7 +57,7 @@ __ret_fast_syscall: /* perform architecture specific actions before user return */ - arch_ret_to_user r1, lr + arch_ret_to_user r1 restore_user_regs fast = 1, offset = S_OFF UNWIND(.fnend ) @@ -128,7 +130,7 @@ no_work_pending: asm_trace_hardirqs_on save = 0 /* perform architecture specific actions before user return */ - arch_ret_to_user r1, lr + arch_ret_to_user r1 ct_user_enter save = 0 restore_user_regs fast = 0, offset = 0 diff --git a/arch/arm/kernel/entry-ftrace.S b/arch/arm/kernel/entry-ftrace.S index a74289ebc803..3e7bcaca5e07 100644 --- a/arch/arm/kernel/entry-ftrace.S +++ b/arch/arm/kernel/entry-ftrace.S @@ -22,12 +22,9 @@ * mcount can be thought of as a function called in the middle of a subroutine * call. As such, it needs to be transparent for both the caller and the * callee: the original lr needs to be restored when leaving mcount, and no - * registers should be clobbered. (In the __gnu_mcount_nc implementation, we - * clobber the ip register. This is OK because the ARM calling convention - * allows it to be clobbered in subroutines and doesn't use it to hold - * parameters.) + * registers should be clobbered. * - * When using dynamic ftrace, we patch out the mcount call by a "pop {lr}" + * When using dynamic ftrace, we patch out the mcount call by a "add sp, #4" * instead of the __gnu_mcount_nc call (see arch/arm/kernel/ftrace.c). */ @@ -38,23 +35,20 @@ .macro __mcount suffix mcount_enter - ldr r0, =ftrace_trace_function - ldr r2, [r0] - adr r0, .Lftrace_stub + ldr_va r2, ftrace_trace_function + badr r0, .Lftrace_stub cmp r0, r2 bne 1f #ifdef CONFIG_FUNCTION_GRAPH_TRACER - ldr r1, =ftrace_graph_return - ldr r2, [r1] - cmp r0, r2 - bne ftrace_graph_caller\suffix + ldr_va r2, ftrace_graph_return + cmp r0, r2 + bne ftrace_graph_caller\suffix - ldr r1, =ftrace_graph_entry - ldr r2, [r1] - ldr r0, =ftrace_graph_entry_stub - cmp r0, r2 - bne ftrace_graph_caller\suffix + ldr_va r2, ftrace_graph_entry + mov_l r0, ftrace_graph_entry_stub + cmp r0, r2 + bne ftrace_graph_caller\suffix #endif mcount_exit @@ -70,29 +64,27 @@ .macro __ftrace_regs_caller - sub sp, sp, #8 @ space for PC and CPSR OLD_R0, + str lr, [sp, #-8]! @ store LR as PC and make space for CPSR/OLD_R0, @ OLD_R0 will overwrite previous LR - add ip, sp, #12 @ move in IP the value of SP as it was - @ before the push {lr} of the mcount mechanism - - str lr, [sp, #0] @ store LR instead of PC - - ldr lr, [sp, #8] @ get previous LR + ldr lr, [sp, #8] @ get previous LR str r0, [sp, #8] @ write r0 as OLD_R0 over previous LR - stmdb sp!, {ip, lr} - stmdb sp!, {r0-r11, lr} + str lr, [sp, #-4]! @ store previous LR as LR + + add lr, sp, #16 @ move in LR the value of SP as it was + @ before the push {lr} of the mcount mechanism + + push {r0-r11, ip, lr} @ stack content at this point: @ 0 4 48 52 56 60 64 68 72 - @ R0 | R1 | ... | LR | SP + 4 | previous LR | LR | PSR | OLD_R0 | + @ R0 | R1 | ... | IP | SP + 4 | previous LR | LR | PSR | OLD_R0 | - mov r3, sp @ struct pt_regs* + mov r3, sp @ struct pt_regs* - ldr r2, =function_trace_op - ldr r2, [r2] @ pointer to the current + ldr_va r2, function_trace_op @ pointer to the current @ function tracing op ldr r1, [sp, #S_LR] @ lr of instrumented func @@ -108,35 +100,37 @@ ftrace_regs_call: #ifdef CONFIG_FUNCTION_GRAPH_TRACER .globl ftrace_graph_regs_call ftrace_graph_regs_call: - mov r0, r0 +ARM( mov r0, r0 ) +THUMB( nop.w ) #endif @ pop saved regs - ldmia sp!, {r0-r12} @ restore r0 through r12 - ldr ip, [sp, #8] @ restore PC - ldr lr, [sp, #4] @ restore LR - ldr sp, [sp, #0] @ restore SP - mov pc, ip @ return + pop {r0-r11, ip, lr} @ restore r0 through r12 + ldr lr, [sp], #4 @ restore LR + ldr pc, [sp], #12 .endm #ifdef CONFIG_FUNCTION_GRAPH_TRACER .macro __ftrace_graph_regs_caller - sub r0, fp, #4 @ lr of instrumented routine (parent) +#ifdef CONFIG_UNWINDER_FRAME_POINTER + sub r0, fp, #4 @ lr of instrumented routine (parent) +#else + add r0, sp, #S_LR +#endif @ called from __ftrace_regs_caller - ldr r1, [sp, #S_PC] @ instrumented routine (func) + ldr r1, [sp, #S_PC] @ instrumented routine (func) mcount_adjust_addr r1, r1 - mov r2, fp @ frame pointer + mov r2, fpreg @ frame pointer + add r3, sp, #PT_REGS_SIZE bl prepare_ftrace_return @ pop registers saved in ftrace_regs_caller - ldmia sp!, {r0-r12} @ restore r0 through r12 - ldr ip, [sp, #8] @ restore PC - ldr lr, [sp, #4] @ restore LR - ldr sp, [sp, #0] @ restore SP - mov pc, ip @ return + pop {r0-r11, ip, lr} @ restore r0 through r12 + ldr lr, [sp], #4 @ restore LR + ldr pc, [sp], #12 .endm #endif @@ -149,8 +143,7 @@ ftrace_graph_regs_call: mcount_adjust_addr r0, lr @ instrumented function #ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS - ldr r2, =function_trace_op - ldr r2, [r2] @ pointer to the current + ldr_va r2, function_trace_op @ pointer to the current @ function tracing op mov r3, #0 @ regs is NULL #endif @@ -162,14 +155,19 @@ ftrace_call\suffix: #ifdef CONFIG_FUNCTION_GRAPH_TRACER .globl ftrace_graph_call\suffix ftrace_graph_call\suffix: - mov r0, r0 +ARM( mov r0, r0 ) +THUMB( nop.w ) #endif mcount_exit .endm .macro __ftrace_graph_caller +#ifdef CONFIG_UNWINDER_FRAME_POINTER sub r0, fp, #4 @ &lr of instrumented routine (&parent) +#else + add r0, sp, #20 +#endif #ifdef CONFIG_DYNAMIC_FTRACE @ called from __ftrace_caller, saved in mcount_enter ldr r1, [sp, #16] @ instrumented routine (func) @@ -178,7 +176,8 @@ ftrace_graph_call\suffix: @ called from __mcount, untouched in lr mcount_adjust_addr r1, lr @ instrumented routine (func) #endif - mov r2, fp @ frame pointer + mov r2, fpreg @ frame pointer + add r3, sp, #24 bl prepare_ftrace_return mcount_exit .endm @@ -202,16 +201,17 @@ ftrace_graph_call\suffix: .endm .macro mcount_exit - ldmia sp!, {r0-r3, ip, lr} - ret ip + ldmia sp!, {r0-r3} + ldr lr, [sp, #4] + ldr pc, [sp], #8 .endm ENTRY(__gnu_mcount_nc) UNWIND(.fnstart) #ifdef CONFIG_DYNAMIC_FTRACE - mov ip, lr - ldmia sp!, {lr} - ret ip + push {lr} + ldr lr, [sp, #4] + ldr pc, [sp], #8 #else __mcount #endif @@ -256,17 +256,33 @@ ENDPROC(ftrace_graph_regs_caller) .purgem mcount_exit #ifdef CONFIG_FUNCTION_GRAPH_TRACER - .globl return_to_handler -return_to_handler: +ENTRY(return_to_handler) stmdb sp!, {r0-r3} - mov r0, fp @ frame pointer + add r0, sp, #16 @ sp at exit of instrumented routine bl ftrace_return_to_handler mov lr, r0 @ r0 has real ret addr ldmia sp!, {r0-r3} ret lr +ENDPROC(return_to_handler) #endif ENTRY(ftrace_stub) .Lftrace_stub: ret lr ENDPROC(ftrace_stub) + +#ifdef CONFIG_DYNAMIC_FTRACE + + __INIT + + .macro init_tramp, dst:req +ENTRY(\dst\()_from_init) + ldr pc, =\dst +ENDPROC(\dst\()_from_init) + .endm + + init_tramp ftrace_caller +#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS + init_tramp ftrace_regs_caller +#endif +#endif diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S index ae24dd54e9ef..9a1dc142f782 100644 --- a/arch/arm/kernel/entry-header.S +++ b/arch/arm/kernel/entry-header.S @@ -292,12 +292,18 @@ .macro restore_user_regs, fast = 0, offset = 0 -#if defined(CONFIG_CPU_32v6K) && !defined(CONFIG_CPU_V6) +#if defined(CONFIG_CPU_32v6K) && \ + (!defined(CONFIG_CPU_V6) || defined(CONFIG_SMP)) +#ifdef CONFIG_CPU_V6 +ALT_SMP(nop) +ALT_UP_B(.L1_\@) +#endif @ The TLS register update is deferred until return to user space so we @ can use it for other things while running in the kernel - get_thread_info r1 + mrc p15, 0, r1, c13, c0, 3 @ get current_thread_info pointer ldr r1, [r1, #TI_TP_VALUE] mcr p15, 0, r1, c13, c0, 3 @ set TLS register +.L1_\@: #endif uaccess_enable r1, isb=0 @@ -423,3 +429,40 @@ scno .req r7 @ syscall number tbl .req r8 @ syscall table pointer why .req r8 @ Linux syscall (!= 0) tsk .req r9 @ current thread_info + + .macro do_overflow_check, frame_size:req +#ifdef CONFIG_VMAP_STACK + @ + @ Test whether the SP has overflowed. Task and IRQ stacks are aligned + @ so that SP & BIT(THREAD_SIZE_ORDER + PAGE_SHIFT) should always be + @ zero. + @ +ARM( tst sp, #1 << (THREAD_SIZE_ORDER + PAGE_SHIFT) ) +THUMB( tst r1, #1 << (THREAD_SIZE_ORDER + PAGE_SHIFT) ) +THUMB( it ne ) + bne .Lstack_overflow_check\@ + + .pushsection .text +.Lstack_overflow_check\@: + @ + @ The stack pointer is not pointing to a valid vmap'ed stack, but it + @ may be pointing into the linear map instead, which may happen if we + @ are already running from the overflow stack. We cannot detect overflow + @ in such cases so just carry on. + @ + str ip, [r0, #12] @ Stash IP on the mode stack + ldr_va ip, high_memory @ Start of VMALLOC space +ARM( cmp sp, ip ) @ SP in vmalloc space? +THUMB( cmp r1, ip ) +THUMB( itt lo ) + ldrlo ip, [r0, #12] @ Restore IP + blo .Lout\@ @ Carry on + +THUMB( sub r1, sp, r1 ) @ Restore original R1 +THUMB( sub sp, r1 ) @ Restore original SP + add sp, sp, #\frame_size @ Undo svc_entry's SP change + b __bad_stack @ Handle VMAP stack overflow + .popsection +.Lout\@: +#endif + .endm diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S index 7bde93c10962..de8a60363c85 100644 --- a/arch/arm/kernel/entry-v7m.S +++ b/arch/arm/kernel/entry-v7m.S @@ -39,16 +39,25 @@ __irq_entry: @ @ Invoke the IRQ handler @ - mrs r0, ipsr - ldr r1, =V7M_xPSR_EXCEPTIONNO - and r0, r1 - sub r0, #16 - mov r1, sp - stmdb sp!, {lr} - @ routine called with r0 = irq number, r1 = struct pt_regs * - bl nvic_handle_irq + mov r0, sp + ldr_this_cpu sp, irq_stack_ptr, r1, r2 + + @ + @ If we took the interrupt while running in the kernel, we may already + @ be using the IRQ stack, so revert to the original value in that case. + @ + subs r2, sp, r0 @ SP above bottom of IRQ stack? + rsbscs r2, r2, #THREAD_SIZE @ ... and below the top? + movcs sp, r0 + + push {r0, lr} @ preserve LR and original SP + + @ routine called with r0 = struct pt_regs * + bl generic_handle_arch_irq + + pop {r0, lr} + mov sp, r0 - pop {lr} @ @ Check for any pending work if returning to user @ @@ -101,15 +110,17 @@ ENTRY(__switch_to) str sp, [ip], #4 str lr, [ip], #4 mov r5, r0 + mov r6, r2 @ Preserve 'next' add r4, r2, #TI_CPU_SAVE ldr r0, =thread_notify_head mov r1, #THREAD_NOTIFY_SWITCH bl atomic_notifier_call_chain - mov ip, r4 mov r0, r5 - ldmia ip!, {r4 - r11} @ Load all regs saved previously - ldr sp, [ip] - ldr pc, [ip, #4]! + mov r1, r6 + ldmia r4, {r4 - r12, lr} @ Load all regs saved previously + set_current r1, r2 + mov sp, ip + bx lr .fnend ENDPROC(__switch_to) diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c index a006585e1c09..83cc068586bc 100644 --- a/arch/arm/kernel/ftrace.c +++ b/arch/arm/kernel/ftrace.c @@ -22,12 +22,24 @@ #include #include #include +#include #include +/* + * The compiler emitted profiling hook consists of + * + * PUSH {LR} + * BL __gnu_mcount_nc + * + * To turn this combined sequence into a NOP, we need to restore the value of + * SP before the PUSH. Let's use an ADD rather than a POP into LR, as LR is not + * modified anyway, and reloading LR from memory is highly likely to be less + * efficient. + */ #ifdef CONFIG_THUMB2_KERNEL -#define NOP 0xf85deb04 /* pop.w {lr} */ +#define NOP 0xf10d0d04 /* add.w sp, sp, #4 */ #else -#define NOP 0xe8bd4000 /* pop {lr} */ +#define NOP 0xe28dd004 /* add sp, sp, #4 */ #endif #ifdef CONFIG_DYNAMIC_FTRACE @@ -51,9 +63,20 @@ static unsigned long ftrace_nop_replace(struct dyn_ftrace *rec) return NOP; } -static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr) +void ftrace_caller_from_init(void); +void ftrace_regs_caller_from_init(void); + +static unsigned long __ref adjust_address(struct dyn_ftrace *rec, + unsigned long addr) { - return addr; + if (!IS_ENABLED(CONFIG_DYNAMIC_FTRACE) || + system_state >= SYSTEM_FREEING_INITMEM || + likely(!is_kernel_inittext(rec->ip))) + return addr; + if (!IS_ENABLED(CONFIG_DYNAMIC_FTRACE_WITH_REGS) || + addr == (unsigned long)&ftrace_caller) + return (unsigned long)&ftrace_caller_from_init; + return (unsigned long)&ftrace_regs_caller_from_init; } int ftrace_arch_code_modify_prepare(void) @@ -189,15 +212,23 @@ int ftrace_make_nop(struct module *mod, #endif new = ftrace_nop_replace(rec); - ret = ftrace_modify_code(ip, old, new, true); + /* + * Locations in .init.text may call __gnu_mcount_mc via a linker + * emitted veneer if they are too far away from its implementation, and + * so validation may fail spuriously in such cases. Let's work around + * this by omitting those from validation. + */ + ret = ftrace_modify_code(ip, old, new, !is_kernel_inittext(ip)); return ret; } #endif /* CONFIG_DYNAMIC_FTRACE */ #ifdef CONFIG_FUNCTION_GRAPH_TRACER +asmlinkage void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, - unsigned long frame_pointer) + unsigned long frame_pointer, + unsigned long stack_pointer) { unsigned long return_hooker = (unsigned long) &return_to_handler; unsigned long old; @@ -205,6 +236,23 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, if (unlikely(atomic_read(¤t->tracing_graph_pause))) return; + if (IS_ENABLED(CONFIG_UNWINDER_FRAME_POINTER)) { + /* FP points one word below parent's top of stack */ + frame_pointer += 4; + } else { + struct stackframe frame = { + .fp = frame_pointer, + .sp = stack_pointer, + .lr = self_addr, + .pc = self_addr, + }; + if (unwind_frame(&frame) < 0) + return; + if (frame.lr != self_addr) + parent = frame.lr_addr; + frame_pointer = frame.sp; + } + old = *parent; *parent = return_hooker; @@ -225,7 +273,7 @@ static int __ftrace_modify_caller(unsigned long *callsite, unsigned long caller_fn = (unsigned long) func; unsigned long pc = (unsigned long) callsite; unsigned long branch = arm_gen_branch(pc, caller_fn); - unsigned long nop = 0xe1a00000; /* mov r0, r0 */ + unsigned long nop = arm_gen_nop(); unsigned long old = enable ? nop : branch; unsigned long new = enable ? branch : nop; diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S index da18e0a17dc2..42cae73fcc19 100644 --- a/arch/arm/kernel/head-common.S +++ b/arch/arm/kernel/head-common.S @@ -105,10 +105,8 @@ __mmap_switched: mov r1, #0 bl __memset @ clear .bss -#ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO adr_l r0, init_task @ get swapper task_struct - set_current r0 -#endif + set_current r0, r1 ldmia r4, {r0, r1, r2, r3} str r9, [r0] @ Save processor ID diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index c04dd94630c7..500612d3da2e 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -424,6 +424,13 @@ ENDPROC(secondary_startup) ENDPROC(secondary_startup_arm) ENTRY(__secondary_switched) +#if defined(CONFIG_VMAP_STACK) && !defined(CONFIG_ARM_LPAE) + @ Before using the vmap'ed stack, we have to switch to swapper_pg_dir + @ as the ID map does not cover the vmalloc region. + mrc p15, 0, ip, c2, c0, 1 @ read TTBR1 + mcr p15, 0, ip, c2, c0, 0 @ set TTBR0 + instr_sync +#endif adr_l r7, secondary_data + 12 @ get secondary_data.stack ldr sp, [r7] ldr r0, [r7, #4] @ get secondary_data.task diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index b79975bd988c..5c6f8d11a3ce 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c @@ -36,13 +36,53 @@ #include #include #include +#include #include #include #include #include +#include "reboot.h" + unsigned long irq_err_count; +#ifdef CONFIG_IRQSTACKS + +asmlinkage DEFINE_PER_CPU_READ_MOSTLY(u8 *, irq_stack_ptr); + +static void __init init_irq_stacks(void) +{ + u8 *stack; + int cpu; + + for_each_possible_cpu(cpu) { + if (!IS_ENABLED(CONFIG_VMAP_STACK)) + stack = (u8 *)__get_free_pages(GFP_KERNEL, + THREAD_SIZE_ORDER); + else + stack = __vmalloc_node(THREAD_SIZE, THREAD_ALIGN, + THREADINFO_GFP, NUMA_NO_NODE, + __builtin_return_address(0)); + + if (WARN_ON(!stack)) + break; + per_cpu(irq_stack_ptr, cpu) = &stack[THREAD_SIZE]; + } +} + +static void ____do_softirq(void *arg) +{ + __do_softirq(); +} + +void do_softirq_own_stack(void) +{ + call_with_stack(____do_softirq, NULL, + __this_cpu_read(irq_stack_ptr)); +} + +#endif + int arch_show_interrupts(struct seq_file *p, int prec) { #ifdef CONFIG_FIQ @@ -80,27 +120,14 @@ void handle_IRQ(unsigned int irq, struct pt_regs *regs) ack_bad_irq(irq); } -/* - * asm_do_IRQ is the interface to be used from assembly code. - */ -asmlinkage void __exception_irq_entry -asm_do_IRQ(unsigned int irq, struct pt_regs *regs) -{ - struct pt_regs *old_regs; - - irq_enter(); - old_regs = set_irq_regs(regs); - - handle_IRQ(irq, regs); - - set_irq_regs(old_regs); - irq_exit(); -} - void __init init_IRQ(void) { int ret; +#ifdef CONFIG_IRQSTACKS + init_irq_stacks(); +#endif + if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq) irqchip_init(); else diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index beac45e89ba6..549abcedf795 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -68,6 +68,44 @@ bool module_exit_section(const char *name) strstarts(name, ".ARM.exidx.exit"); } +#ifdef CONFIG_ARM_HAS_GROUP_RELOCS +/* + * This implements the partitioning algorithm for group relocations as + * documented in the ARM AArch32 ELF psABI (IHI 0044). + * + * A single PC-relative symbol reference is divided in up to 3 add or subtract + * operations, where the final one could be incorporated into a load/store + * instruction with immediate offset. E.g., + * + * ADD Rd, PC, #... or ADD Rd, PC, #... + * ADD Rd, Rd, #... ADD Rd, Rd, #... + * LDR Rd, [Rd, #...] ADD Rd, Rd, #... + * + * The latter has a guaranteed range of only 16 MiB (3x8 == 24 bits), so it is + * of limited use in the kernel. However, the ADD/ADD/LDR combo has a range of + * -/+ 256 MiB, (2x8 + 12 == 28 bits), which means it has sufficient range for + * any in-kernel symbol reference (unless module PLTs are being used). + * + * The main advantage of this approach over the typical pattern using a literal + * load is that literal loads may miss in the D-cache, and generally lead to + * lower cache efficiency for variables that are referenced often from many + * different places in the code. + */ +static u32 get_group_rem(u32 group, u32 *offset) +{ + u32 val = *offset; + u32 shift; + do { + shift = val ? (31 - __fls(val)) & ~1 : 32; + *offset = val; + if (!val) + break; + val &= 0xffffff >> shift; + } while (group--); + return shift; +} +#endif + int apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, unsigned int relindex, struct module *module) @@ -82,6 +120,9 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, unsigned long loc; Elf32_Sym *sym; const char *symname; +#ifdef CONFIG_ARM_HAS_GROUP_RELOCS + u32 shift, group = 1; +#endif s32 offset; u32 tmp; #ifdef CONFIG_THUMB2_KERNEL @@ -212,6 +253,55 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, *(u32 *)loc = __opcode_to_mem_arm(tmp); break; +#ifdef CONFIG_ARM_HAS_GROUP_RELOCS + case R_ARM_ALU_PC_G0_NC: + group = 0; + fallthrough; + case R_ARM_ALU_PC_G1_NC: + tmp = __mem_to_opcode_arm(*(u32 *)loc); + offset = ror32(tmp & 0xff, (tmp & 0xf00) >> 7); + if (tmp & BIT(22)) + offset = -offset; + offset += sym->st_value - loc; + if (offset < 0) { + offset = -offset; + tmp = (tmp & ~BIT(23)) | BIT(22); // SUB opcode + } else { + tmp = (tmp & ~BIT(22)) | BIT(23); // ADD opcode + } + + shift = get_group_rem(group, &offset); + if (shift < 24) { + offset >>= 24 - shift; + offset |= (shift + 8) << 7; + } + *(u32 *)loc = __opcode_to_mem_arm((tmp & ~0xfff) | offset); + break; + + case R_ARM_LDR_PC_G2: + tmp = __mem_to_opcode_arm(*(u32 *)loc); + offset = tmp & 0xfff; + if (~tmp & BIT(23)) // U bit cleared? + offset = -offset; + offset += sym->st_value - loc; + if (offset < 0) { + offset = -offset; + tmp &= ~BIT(23); // clear U bit + } else { + tmp |= BIT(23); // set U bit + } + get_group_rem(2, &offset); + + if (offset > 0xfff) { + pr_err("%s: section %u reloc %u sym '%s': relocation %u out of range (%#lx -> %#x)\n", + module->name, relindex, i, symname, + ELF32_R_TYPE(rel->r_info), loc, + sym->st_value); + return -ENOEXEC; + } + *(u32 *)loc = __opcode_to_mem_arm((tmp & ~0xfff) | offset); + break; +#endif #ifdef CONFIG_THUMB2_KERNEL case R_ARM_THM_CALL: case R_ARM_THM_JUMP24: diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index d47159f3791c..0617af11377f 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -36,7 +36,7 @@ #include "signal.h" -#ifdef CONFIG_CURRENT_POINTER_IN_TPIDRURO +#if defined(CONFIG_CURRENT_POINTER_IN_TPIDRURO) || defined(CONFIG_SMP) DEFINE_PER_CPU(struct task_struct *, __entry_task); #endif @@ -46,6 +46,11 @@ unsigned long __stack_chk_guard __read_mostly; EXPORT_SYMBOL(__stack_chk_guard); #endif +#ifndef CONFIG_CURRENT_POINTER_IN_TPIDRURO +asmlinkage struct task_struct *__current; +EXPORT_SYMBOL(__current); +#endif + static const char *processor_modes[] __maybe_unused = { "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" , "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26", diff --git a/arch/arm/kernel/return_address.c b/arch/arm/kernel/return_address.c index 00c11579406c..8aac1e10b117 100644 --- a/arch/arm/kernel/return_address.c +++ b/arch/arm/kernel/return_address.c @@ -41,7 +41,8 @@ void *return_address(unsigned int level) frame.fp = (unsigned long)__builtin_frame_address(0); frame.sp = current_stack_pointer; frame.lr = (unsigned long)__builtin_return_address(0); - frame.pc = (unsigned long)return_address; +here: + frame.pc = (unsigned long)&&here; #ifdef CONFIG_KRETPROBES frame.kr_cur = NULL; frame.tsk = current; diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 284a80c0b6e1..039feb7cd590 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -141,10 +141,10 @@ EXPORT_SYMBOL(outer_cache); int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN; struct stack { - u32 irq[3]; - u32 abt[3]; - u32 und[3]; - u32 fiq[3]; + u32 irq[4]; + u32 abt[4]; + u32 und[4]; + u32 fiq[4]; } ____cacheline_aligned; #ifndef CONFIG_CPU_V7M diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S index 43077e11dafd..a86a1d4f3461 100644 --- a/arch/arm/kernel/sleep.S +++ b/arch/arm/kernel/sleep.S @@ -67,6 +67,12 @@ ENTRY(__cpu_suspend) ldr r4, =cpu_suspend_size #endif mov r5, sp @ current virtual SP +#ifdef CONFIG_VMAP_STACK + @ Run the suspend code from the overflow stack so we don't have to rely + @ on vmalloc-to-phys conversions anywhere in the arch suspend code. + @ The original SP value captured in R5 will be restored on the way out. + ldr_this_cpu sp, overflow_stack_ptr, r6, r7 +#endif add r4, r4, #12 @ Space for pgd, virt sp, phys resume fn sub sp, sp, r4 @ allocate CPU state on stack ldr r3, =sleep_save_sp @@ -113,6 +119,13 @@ ENTRY(cpu_resume_mmu) ENDPROC(cpu_resume_mmu) .popsection cpu_resume_after_mmu: +#if defined(CONFIG_VMAP_STACK) && !defined(CONFIG_ARM_LPAE) + @ Before using the vmap'ed stack, we have to switch to swapper_pg_dir + @ as the ID map does not cover the vmalloc region. + mrc p15, 0, ip, c2, c0, 1 @ read TTBR1 + mcr p15, 0, ip, c2, c0, 0 @ set TTBR0 + instr_sync +#endif bl cpu_init @ restore the und/abt/irq banked regs mov r0, #0 @ return zero on success ldmfd sp!, {r4 - r11, pc} diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index a2fa7a484b00..462866459d55 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -404,6 +404,12 @@ static void smp_store_cpu_info(unsigned int cpuid) check_cpu_icache_size(cpuid); } +static void set_current(struct task_struct *cur) +{ + /* Set TPIDRURO */ + asm("mcr p15, 0, %0, c13, c0, 3" :: "r"(cur) : "memory"); +} + /* * This is the secondary CPU boot entry. We're using this CPUs * idle thread stack, but a set of temporary page tables. @@ -632,11 +638,6 @@ static void ipi_complete(unsigned int cpu) /* * Main handler for inter-processor interrupts */ -asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) -{ - handle_IPI(ipinr, regs); -} - static void do_handle_IPI(int ipinr) { unsigned int cpu = smp_processor_id(); diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c index 75e905508f27..b5efecb3d730 100644 --- a/arch/arm/kernel/stacktrace.c +++ b/arch/arm/kernel/stacktrace.c @@ -160,7 +160,8 @@ static noinline void __save_stack_trace(struct task_struct *tsk, frame.fp = (unsigned long)__builtin_frame_address(0); frame.sp = current_stack_pointer; frame.lr = (unsigned long)__builtin_return_address(0); - frame.pc = (unsigned long)__save_stack_trace; +here: + frame.pc = (unsigned long)&&here; } #ifdef CONFIG_KRETPROBES frame.kr_cur = NULL; diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c index 6166ba38bf99..b74bfcf94fb1 100644 --- a/arch/arm/kernel/swp_emulate.c +++ b/arch/arm/kernel/swp_emulate.c @@ -195,7 +195,7 @@ static int swp_handler(struct pt_regs *regs, unsigned int instr) destreg, EXTRACT_REG_NUM(instr, RT2_OFFSET), data); /* Check access in reasonable access range for both SWP and SWPB */ - if (!access_ok((address & ~3), 4)) { + if (!access_ok((void __user *)(address & ~3), 4)) { pr_debug("SWP{B} emulation: access to %p not allowed!\n", (void *)address); res = -EFAULT; diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index cae4a748811f..9283dc65be31 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -61,13 +62,24 @@ static int __init user_debug_setup(char *str) __setup("user_debug=", user_debug_setup); #endif -static void dump_mem(const char *, const char *, unsigned long, unsigned long); - void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame, const char *loglvl) { unsigned long end = frame + 4 + sizeof(struct pt_regs); + if (IS_ENABLED(CONFIG_UNWINDER_FRAME_POINTER) && + IS_ENABLED(CONFIG_CC_IS_GCC) && + end > ALIGN(frame, THREAD_SIZE)) { + /* + * If we are walking past the end of the stack, it may be due + * to the fact that we are on an IRQ or overflow stack. In this + * case, we can load the address of the other stack from the + * frame record. + */ + frame = ((unsigned long *)frame)[-2] - 4; + end = frame + 4 + sizeof(struct pt_regs); + } + #ifndef CONFIG_KALLSYMS printk("%sFunction entered at [<%08lx>] from [<%08lx>]\n", loglvl, where, from); @@ -111,7 +123,8 @@ void dump_backtrace_stm(u32 *stack, u32 instruction, const char *loglvl) static int verify_stack(unsigned long sp) { if (sp < PAGE_OFFSET || - (sp > (unsigned long)high_memory && high_memory != NULL)) + (!IS_ENABLED(CONFIG_VMAP_STACK) && + sp > (unsigned long)high_memory && high_memory != NULL)) return -EFAULT; return 0; @@ -121,8 +134,8 @@ static int verify_stack(unsigned long sp) /* * Dump out the contents of some memory nicely... */ -static void dump_mem(const char *lvl, const char *str, unsigned long bottom, - unsigned long top) +void dump_mem(const char *lvl, const char *str, unsigned long bottom, + unsigned long top) { unsigned long first; int i; @@ -281,7 +294,8 @@ static int __die(const char *str, int err, struct pt_regs *regs) if (!user_mode(regs) || in_interrupt()) { dump_mem(KERN_EMERG, "Stack: ", regs->ARM_sp, - THREAD_SIZE + (unsigned long)task_stack_page(tsk)); + ALIGN(regs->ARM_sp - THREAD_SIZE, THREAD_ALIGN) + + THREAD_SIZE); dump_backtrace(regs, tsk, KERN_EMERG); dump_instr(KERN_EMERG, regs); } @@ -577,7 +591,7 @@ do_cache_op(unsigned long start, unsigned long end, int flags) if (end < start || flags) return -EINVAL; - if (!access_ok(start, end - start)) + if (!access_ok((void __user *)start, end - start)) return -EFAULT; return __do_cache_op(start, end); @@ -880,3 +894,70 @@ void __init early_trap_init(void *vectors_base) */ } #endif + +#ifdef CONFIG_VMAP_STACK + +DECLARE_PER_CPU(u8 *, irq_stack_ptr); + +asmlinkage DEFINE_PER_CPU(u8 *, overflow_stack_ptr); + +static int __init allocate_overflow_stacks(void) +{ + u8 *stack; + int cpu; + + for_each_possible_cpu(cpu) { + stack = (u8 *)__get_free_page(GFP_KERNEL); + if (WARN_ON(!stack)) + return -ENOMEM; + per_cpu(overflow_stack_ptr, cpu) = &stack[OVERFLOW_STACK_SIZE]; + } + return 0; +} +early_initcall(allocate_overflow_stacks); + +asmlinkage void handle_bad_stack(struct pt_regs *regs) +{ + unsigned long tsk_stk = (unsigned long)current->stack; +#ifdef CONFIG_IRQSTACKS + unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); +#endif + unsigned long ovf_stk = (unsigned long)this_cpu_read(overflow_stack_ptr); + + console_verbose(); + pr_emerg("Insufficient stack space to handle exception!"); + + pr_emerg("Task stack: [0x%08lx..0x%08lx]\n", + tsk_stk, tsk_stk + THREAD_SIZE); +#ifdef CONFIG_IRQSTACKS + pr_emerg("IRQ stack: [0x%08lx..0x%08lx]\n", + irq_stk - THREAD_SIZE, irq_stk); +#endif + pr_emerg("Overflow stack: [0x%08lx..0x%08lx]\n", + ovf_stk - OVERFLOW_STACK_SIZE, ovf_stk); + + die("kernel stack overflow", regs, 0); +} + +#ifndef CONFIG_ARM_LPAE +/* + * Normally, we rely on the logic in do_translation_fault() to update stale PMD + * entries covering the vmalloc space in a task's page tables when it first + * accesses the region in question. Unfortunately, this is not sufficient when + * the task stack resides in the vmalloc region, as do_translation_fault() is a + * C function that needs a stack to run. + * + * So we need to ensure that these PMD entries are up to date *before* the MM + * switch. As we already have some logic in the MM switch path that takes care + * of this, let's trigger it by bumping the counter every time the core vmalloc + * code modifies a PMD entry in the vmalloc region. Use release semantics on + * the store so that other CPUs observing the counter's new value are + * guaranteed to see the updated page table entries as well. + */ +void arch_sync_kernel_mappings(unsigned long start, unsigned long end) +{ + if (start < VMALLOC_END && end > VMALLOC_START) + atomic_inc_return_release(&init_mm.context.vmalloc_seq); +} +#endif +#endif diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c index 59fdf257bf8b..a37ea6c772cd 100644 --- a/arch/arm/kernel/unwind.c +++ b/arch/arm/kernel/unwind.c @@ -33,6 +33,8 @@ #include #include +#include "reboot.h" + /* Dummy functions to avoid linker complaints */ void __aeabi_unwind_cpp_pr0(void) { @@ -53,6 +55,7 @@ struct unwind_ctrl_block { unsigned long vrs[16]; /* virtual register set */ const unsigned long *insn; /* pointer to the current instructions word */ unsigned long sp_high; /* highest value of sp allowed */ + unsigned long *lr_addr; /* address of LR value on the stack */ /* * 1 : check for stack overflow for each register pop. * 0 : save overhead if there is plenty of stack remaining. @@ -237,6 +240,8 @@ static int unwind_pop_register(struct unwind_ctrl_block *ctrl, * from being tracked by KASAN. */ ctrl->vrs[reg] = READ_ONCE_NOCHECK(*(*vsp)); + if (reg == 14) + ctrl->lr_addr = *vsp; (*vsp)++; return URC_OK; } @@ -256,8 +261,9 @@ static int unwind_exec_pop_subset_r4_to_r13(struct unwind_ctrl_block *ctrl, mask >>= 1; reg++; } - if (!load_sp) + if (!load_sp) { ctrl->vrs[SP] = (unsigned long)vsp; + } return URC_OK; } @@ -313,9 +319,9 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) if ((insn & 0xc0) == 0x00) ctrl->vrs[SP] += ((insn & 0x3f) << 2) + 4; - else if ((insn & 0xc0) == 0x40) + else if ((insn & 0xc0) == 0x40) { ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4; - else if ((insn & 0xf0) == 0x80) { + } else if ((insn & 0xf0) == 0x80) { unsigned long mask; insn = (insn << 8) | unwind_get_byte(ctrl); @@ -330,9 +336,9 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) if (ret) goto error; } else if ((insn & 0xf0) == 0x90 && - (insn & 0x0d) != 0x0d) + (insn & 0x0d) != 0x0d) { ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f]; - else if ((insn & 0xf0) == 0xa0) { + } else if ((insn & 0xf0) == 0xa0) { ret = unwind_exec_pop_r4_to_rN(ctrl, insn); if (ret) goto error; @@ -375,23 +381,22 @@ error: */ int unwind_frame(struct stackframe *frame) { - unsigned long low; const struct unwind_idx *idx; struct unwind_ctrl_block ctrl; + unsigned long sp_low; /* store the highest address on the stack to avoid crossing it*/ - low = frame->sp; - ctrl.sp_high = ALIGN(low, THREAD_SIZE); + sp_low = frame->sp; + ctrl.sp_high = ALIGN(sp_low - THREAD_SIZE, THREAD_ALIGN) + + THREAD_SIZE; pr_debug("%s(pc = %08lx lr = %08lx sp = %08lx)\n", __func__, frame->pc, frame->lr, frame->sp); - if (!kernel_text_address(frame->pc)) - return -URC_FAILURE; - idx = unwind_find_idx(frame->pc); if (!idx) { - pr_warn("unwind: Index not found %08lx\n", frame->pc); + if (frame->pc && kernel_text_address(frame->pc)) + pr_warn("unwind: Index not found %08lx\n", frame->pc); return -URC_FAILURE; } @@ -403,7 +408,20 @@ int unwind_frame(struct stackframe *frame) if (idx->insn == 1) /* can't unwind */ return -URC_FAILURE; - else if ((idx->insn & 0x80000000) == 0) + else if (frame->pc == prel31_to_addr(&idx->addr_offset)) { + /* + * Unwinding is tricky when we're halfway through the prologue, + * since the stack frame that the unwinder expects may not be + * fully set up yet. However, one thing we do know for sure is + * that if we are unwinding from the very first instruction of + * a function, we are still effectively in the stack frame of + * the caller, and the unwind info has no relevance yet. + */ + if (frame->pc == frame->lr) + return -URC_FAILURE; + frame->pc = frame->lr; + return URC_OK; + } else if ((idx->insn & 0x80000000) == 0) /* prel31 to the unwind table */ ctrl.insn = (unsigned long *)prel31_to_addr(&idx->insn); else if ((idx->insn & 0xff000000) == 0x80000000) @@ -430,6 +448,16 @@ int unwind_frame(struct stackframe *frame) ctrl.check_each_pop = 0; + if (prel31_to_addr(&idx->addr_offset) == (u32)&call_with_stack) { + /* + * call_with_stack() is the only place where we permit SP to + * jump from one stack to another, and since we know it is + * guaranteed to happen, set up the SP bounds accordingly. + */ + sp_low = frame->fp; + ctrl.sp_high = ALIGN(frame->fp, THREAD_SIZE); + } + while (ctrl.entries > 0) { int urc; if ((ctrl.sp_high - ctrl.vrs[SP]) < sizeof(ctrl.vrs)) @@ -437,7 +465,7 @@ int unwind_frame(struct stackframe *frame) urc = unwind_exec_insn(&ctrl); if (urc < 0) return urc; - if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= ctrl.sp_high) + if (ctrl.vrs[SP] < sp_low || ctrl.vrs[SP] > ctrl.sp_high) return -URC_FAILURE; } @@ -452,6 +480,7 @@ int unwind_frame(struct stackframe *frame) frame->sp = ctrl.vrs[SP]; frame->lr = ctrl.vrs[LR]; frame->pc = ctrl.vrs[PC]; + frame->lr_addr = ctrl.lr_addr; return URC_OK; } @@ -475,7 +504,12 @@ void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk, frame.fp = (unsigned long)__builtin_frame_address(0); frame.sp = current_stack_pointer; frame.lr = (unsigned long)__builtin_return_address(0); - frame.pc = (unsigned long)unwind_backtrace; + /* We are saving the stack and execution state at this + * point, so we should ensure that frame.pc is within + * this block of code. + */ +here: + frame.pc = (unsigned long)&&here; } else { /* task blocked in __switch_to */ frame.fp = thread_saved_fp(tsk); diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index f02d617e3359..aa12b65a7fd6 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -138,12 +138,12 @@ SECTIONS #ifdef CONFIG_STRICT_KERNEL_RWX . = ALIGN(1< #include +#include /* * void call_with_stack(void (*fn)(void *), void *arg, void *sp) * * Change the stack to that pointed at by sp, then invoke fn(arg) with * the new stack. + * + * The sequence below follows the APCS frame convention for frame pointer + * unwinding, and implements the unwinder annotations needed by the EABI + * unwinder. */ -ENTRY(call_with_stack) - str sp, [r2, #-4]! - str lr, [r2, #-4]! +ENTRY(call_with_stack) +#if defined(CONFIG_UNWINDER_FRAME_POINTER) && defined(CONFIG_CC_IS_GCC) + mov ip, sp + push {fp, ip, lr, pc} + sub fp, ip, #4 +#else +UNWIND( .fnstart ) +UNWIND( .save {fpreg, lr} ) + push {fpreg, lr} +UNWIND( .setfp fpreg, sp ) + mov fpreg, sp +#endif mov sp, r2 mov r2, r0 mov r0, r1 - badr lr, 1f - ret r2 + bl_r r2 -1: ldr lr, [sp] - ldr sp, [sp, #4] - ret lr +#if defined(CONFIG_UNWINDER_FRAME_POINTER) && defined(CONFIG_CC_IS_GCC) + ldmdb fp, {fp, sp, pc} +#else + mov sp, fpreg + pop {fpreg, pc} +UNWIND( .fnend ) +#endif ENDPROC(call_with_stack) diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S index 480a20766137..270de7debd0f 100644 --- a/arch/arm/lib/copy_from_user.S +++ b/arch/arm/lib/copy_from_user.S @@ -91,18 +91,15 @@ strb\cond \reg, [\ptr], #1 .endm - .macro enter reg1 reg2 + .macro enter regs:vararg mov r3, #0 - stmdb sp!, {r0, r2, r3, \reg1, \reg2} +UNWIND( .save {r0, r2, r3, \regs} ) + stmdb sp!, {r0, r2, r3, \regs} .endm - .macro usave reg1 reg2 - UNWIND( .save {r0, r2, r3, \reg1, \reg2} ) - .endm - - .macro exit reg1 reg2 + .macro exit regs:vararg add sp, sp, #8 - ldmfd sp!, {r0, \reg1, \reg2} + ldmfd sp!, {r0, \regs} .endm .text diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S index 810a805d36dc..8fbafb074fe9 100644 --- a/arch/arm/lib/copy_template.S +++ b/arch/arm/lib/copy_template.S @@ -69,13 +69,10 @@ * than one 32bit instruction in Thumb-2) */ - UNWIND( .fnstart ) - enter r4, lr - UNWIND( .fnend ) - - UNWIND( .fnstart ) - usave r4, lr @ in first stmdb block + enter r4, UNWIND(fpreg,) lr + UNWIND( .setfp fpreg, sp ) + UNWIND( mov fpreg, sp ) subs r2, r2, #4 blt 8f @@ -86,12 +83,7 @@ bne 10f 1: subs r2, r2, #(28) - stmfd sp!, {r5 - r8} - UNWIND( .fnend ) - - UNWIND( .fnstart ) - usave r4, lr - UNWIND( .save {r5 - r8} ) @ in second stmfd block + stmfd sp!, {r5, r6, r8, r9} blt 5f CALGN( ands ip, r0, #31 ) @@ -110,9 +102,9 @@ PLD( pld [r1, #92] ) 3: PLD( pld [r1, #124] ) -4: ldr8w r1, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f +4: ldr8w r1, r3, r4, r5, r6, r8, r9, ip, lr, abort=20f subs r2, r2, #32 - str8w r0, r3, r4, r5, r6, r7, r8, ip, lr, abort=20f + str8w r0, r3, r4, r5, r6, r8, r9, ip, lr, abort=20f bge 3b PLD( cmn r2, #96 ) PLD( bge 4b ) @@ -132,8 +124,8 @@ ldr1w r1, r4, abort=20f ldr1w r1, r5, abort=20f ldr1w r1, r6, abort=20f - ldr1w r1, r7, abort=20f ldr1w r1, r8, abort=20f + ldr1w r1, r9, abort=20f ldr1w r1, lr, abort=20f #if LDR1W_SHIFT < STR1W_SHIFT @@ -150,17 +142,14 @@ str1w r0, r4, abort=20f str1w r0, r5, abort=20f str1w r0, r6, abort=20f - str1w r0, r7, abort=20f str1w r0, r8, abort=20f + str1w r0, r9, abort=20f str1w r0, lr, abort=20f CALGN( bcs 2b ) -7: ldmfd sp!, {r5 - r8} - UNWIND( .fnend ) @ end of second stmfd block +7: ldmfd sp!, {r5, r6, r8, r9} - UNWIND( .fnstart ) - usave r4, lr @ still in first stmdb block 8: movs r2, r2, lsl #31 ldr1b r1, r3, ne, abort=21f ldr1b r1, r4, cs, abort=21f @@ -169,7 +158,7 @@ str1b r0, r4, cs, abort=21f str1b r0, ip, cs, abort=21f - exit r4, pc + exit r4, UNWIND(fpreg,) pc 9: rsb ip, ip, #4 cmp ip, #2 @@ -189,13 +178,10 @@ ldr1w r1, lr, abort=21f beq 17f bgt 18f - UNWIND( .fnend ) .macro forward_copy_shift pull push - UNWIND( .fnstart ) - usave r4, lr @ still in first stmdb block subs r2, r2, #28 blt 14f @@ -205,12 +191,8 @@ CALGN( subcc r2, r2, ip ) CALGN( bcc 15f ) -11: stmfd sp!, {r5 - r9} - UNWIND( .fnend ) +11: stmfd sp!, {r5, r6, r8 - r10} - UNWIND( .fnstart ) - usave r4, lr - UNWIND( .save {r5 - r9} ) @ in new second stmfd block PLD( pld [r1, #0] ) PLD( subs r2, r2, #96 ) PLD( pld [r1, #28] ) @@ -219,35 +201,32 @@ PLD( pld [r1, #92] ) 12: PLD( pld [r1, #124] ) -13: ldr4w r1, r4, r5, r6, r7, abort=19f +13: ldr4w r1, r4, r5, r6, r8, abort=19f mov r3, lr, lspull #\pull subs r2, r2, #32 - ldr4w r1, r8, r9, ip, lr, abort=19f + ldr4w r1, r9, r10, ip, lr, abort=19f orr r3, r3, r4, lspush #\push mov r4, r4, lspull #\pull orr r4, r4, r5, lspush #\push mov r5, r5, lspull #\pull orr r5, r5, r6, lspush #\push mov r6, r6, lspull #\pull - orr r6, r6, r7, lspush #\push - mov r7, r7, lspull #\pull - orr r7, r7, r8, lspush #\push + orr r6, r6, r8, lspush #\push mov r8, r8, lspull #\pull orr r8, r8, r9, lspush #\push mov r9, r9, lspull #\pull - orr r9, r9, ip, lspush #\push + orr r9, r9, r10, lspush #\push + mov r10, r10, lspull #\pull + orr r10, r10, ip, lspush #\push mov ip, ip, lspull #\pull orr ip, ip, lr, lspush #\push - str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, abort=19f + str8w r0, r3, r4, r5, r6, r8, r9, r10, ip, abort=19f bge 12b PLD( cmn r2, #96 ) PLD( bge 13b ) - ldmfd sp!, {r5 - r9} - UNWIND( .fnend ) @ end of the second stmfd block + ldmfd sp!, {r5, r6, r8 - r10} - UNWIND( .fnstart ) - usave r4, lr @ still in first stmdb block 14: ands ip, r2, #28 beq 16f @@ -262,7 +241,6 @@ 16: sub r1, r1, #(\push / 8) b 8b - UNWIND( .fnend ) .endm @@ -273,6 +251,7 @@ 18: forward_copy_shift pull=24 push=8 + UNWIND( .fnend ) /* * Abort preamble and completion macros. @@ -282,13 +261,13 @@ */ .macro copy_abort_preamble -19: ldmfd sp!, {r5 - r9} +19: ldmfd sp!, {r5, r6, r8 - r10} b 21f -20: ldmfd sp!, {r5 - r8} +20: ldmfd sp!, {r5, r6, r8, r9} 21: .endm .macro copy_abort_end - ldmfd sp!, {r4, pc} + ldmfd sp!, {r4, UNWIND(fpreg,) pc} .endm diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S index 842ea5ede485..fac49e57cc0b 100644 --- a/arch/arm/lib/copy_to_user.S +++ b/arch/arm/lib/copy_to_user.S @@ -90,18 +90,15 @@ strusr \reg, \ptr, 1, \cond, abort=\abort .endm - .macro enter reg1 reg2 + .macro enter regs:vararg mov r3, #0 - stmdb sp!, {r0, r2, r3, \reg1, \reg2} +UNWIND( .save {r0, r2, r3, \regs} ) + stmdb sp!, {r0, r2, r3, \regs} .endm - .macro usave reg1 reg2 - UNWIND( .save {r0, r2, r3, \reg1, \reg2} ) - .endm - - .macro exit reg1 reg2 + .macro exit regs:vararg add sp, sp, #8 - ldmfd sp!, {r0, \reg1, \reg2} + ldmfd sp!, {r0, \regs} .endm .text diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S index e4caf48c089f..90f2b645aa0d 100644 --- a/arch/arm/lib/memcpy.S +++ b/arch/arm/lib/memcpy.S @@ -42,16 +42,13 @@ strb\cond \reg, [\ptr], #1 .endm - .macro enter reg1 reg2 - stmdb sp!, {r0, \reg1, \reg2} + .macro enter regs:vararg +UNWIND( .save {r0, \regs} ) + stmdb sp!, {r0, \regs} .endm - .macro usave reg1 reg2 - UNWIND( .save {r0, \reg1, \reg2} ) - .endm - - .macro exit reg1 reg2 - ldmfd sp!, {r0, \reg1, \reg2} + .macro exit regs:vararg + ldmfd sp!, {r0, \regs} .endm .text diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S index 6fecc12a1f51..6410554039fd 100644 --- a/arch/arm/lib/memmove.S +++ b/arch/arm/lib/memmove.S @@ -31,12 +31,13 @@ WEAK(memmove) subs ip, r0, r1 cmphi r2, ip bls __memcpy - - stmfd sp!, {r0, r4, lr} UNWIND( .fnend ) UNWIND( .fnstart ) - UNWIND( .save {r0, r4, lr} ) @ in first stmfd block + UNWIND( .save {r0, r4, fpreg, lr} ) + stmfd sp!, {r0, r4, UNWIND(fpreg,) lr} + UNWIND( .setfp fpreg, sp ) + UNWIND( mov fpreg, sp ) add r1, r1, r2 add r0, r0, r2 subs r2, r2, #4 @@ -48,12 +49,7 @@ WEAK(memmove) bne 10f 1: subs r2, r2, #(28) - stmfd sp!, {r5 - r8} - UNWIND( .fnend ) - - UNWIND( .fnstart ) - UNWIND( .save {r0, r4, lr} ) - UNWIND( .save {r5 - r8} ) @ in second stmfd block + stmfd sp!, {r5, r6, r8, r9} blt 5f CALGN( ands ip, r0, #31 ) @@ -72,9 +68,9 @@ WEAK(memmove) PLD( pld [r1, #-96] ) 3: PLD( pld [r1, #-128] ) -4: ldmdb r1!, {r3, r4, r5, r6, r7, r8, ip, lr} +4: ldmdb r1!, {r3, r4, r5, r6, r8, r9, ip, lr} subs r2, r2, #32 - stmdb r0!, {r3, r4, r5, r6, r7, r8, ip, lr} + stmdb r0!, {r3, r4, r5, r6, r8, r9, ip, lr} bge 3b PLD( cmn r2, #96 ) PLD( bge 4b ) @@ -88,8 +84,8 @@ WEAK(memmove) W(ldr) r4, [r1, #-4]! W(ldr) r5, [r1, #-4]! W(ldr) r6, [r1, #-4]! - W(ldr) r7, [r1, #-4]! W(ldr) r8, [r1, #-4]! + W(ldr) r9, [r1, #-4]! W(ldr) lr, [r1, #-4]! add pc, pc, ip @@ -99,17 +95,13 @@ WEAK(memmove) W(str) r4, [r0, #-4]! W(str) r5, [r0, #-4]! W(str) r6, [r0, #-4]! - W(str) r7, [r0, #-4]! W(str) r8, [r0, #-4]! + W(str) r9, [r0, #-4]! W(str) lr, [r0, #-4]! CALGN( bcs 2b ) -7: ldmfd sp!, {r5 - r8} - UNWIND( .fnend ) @ end of second stmfd block - - UNWIND( .fnstart ) - UNWIND( .save {r0, r4, lr} ) @ still in first stmfd block +7: ldmfd sp!, {r5, r6, r8, r9} 8: movs r2, r2, lsl #31 ldrbne r3, [r1, #-1]! @@ -118,7 +110,7 @@ WEAK(memmove) strbne r3, [r0, #-1]! strbcs r4, [r0, #-1]! strbcs ip, [r0, #-1] - ldmfd sp!, {r0, r4, pc} + ldmfd sp!, {r0, r4, UNWIND(fpreg,) pc} 9: cmp ip, #2 ldrbgt r3, [r1, #-1]! @@ -137,13 +129,10 @@ WEAK(memmove) ldr r3, [r1, #0] beq 17f blt 18f - UNWIND( .fnend ) .macro backward_copy_shift push pull - UNWIND( .fnstart ) - UNWIND( .save {r0, r4, lr} ) @ still in first stmfd block subs r2, r2, #28 blt 14f @@ -152,12 +141,7 @@ WEAK(memmove) CALGN( subcc r2, r2, ip ) CALGN( bcc 15f ) -11: stmfd sp!, {r5 - r9} - UNWIND( .fnend ) - - UNWIND( .fnstart ) - UNWIND( .save {r0, r4, lr} ) - UNWIND( .save {r5 - r9} ) @ in new second stmfd block +11: stmfd sp!, {r5, r6, r8 - r10} PLD( pld [r1, #-4] ) PLD( subs r2, r2, #96 ) @@ -167,35 +151,31 @@ WEAK(memmove) PLD( pld [r1, #-96] ) 12: PLD( pld [r1, #-128] ) -13: ldmdb r1!, {r7, r8, r9, ip} +13: ldmdb r1!, {r8, r9, r10, ip} mov lr, r3, lspush #\push subs r2, r2, #32 ldmdb r1!, {r3, r4, r5, r6} orr lr, lr, ip, lspull #\pull mov ip, ip, lspush #\push - orr ip, ip, r9, lspull #\pull + orr ip, ip, r10, lspull #\pull + mov r10, r10, lspush #\push + orr r10, r10, r9, lspull #\pull mov r9, r9, lspush #\push orr r9, r9, r8, lspull #\pull mov r8, r8, lspush #\push - orr r8, r8, r7, lspull #\pull - mov r7, r7, lspush #\push - orr r7, r7, r6, lspull #\pull + orr r8, r8, r6, lspull #\pull mov r6, r6, lspush #\push orr r6, r6, r5, lspull #\pull mov r5, r5, lspush #\push orr r5, r5, r4, lspull #\pull mov r4, r4, lspush #\push orr r4, r4, r3, lspull #\pull - stmdb r0!, {r4 - r9, ip, lr} + stmdb r0!, {r4 - r6, r8 - r10, ip, lr} bge 12b PLD( cmn r2, #96 ) PLD( bge 13b ) - ldmfd sp!, {r5 - r9} - UNWIND( .fnend ) @ end of the second stmfd block - - UNWIND( .fnstart ) - UNWIND( .save {r0, r4, lr} ) @ still in first stmfd block + ldmfd sp!, {r5, r6, r8 - r10} 14: ands ip, r2, #28 beq 16f @@ -211,7 +191,6 @@ WEAK(memmove) 16: add r1, r1, #(\pull / 8) b 8b - UNWIND( .fnend ) .endm @@ -222,5 +201,6 @@ WEAK(memmove) 18: backward_copy_shift push=24 pull=8 + UNWIND( .fnend ) ENDPROC(memmove) ENDPROC(__memmove) diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index 9817cb258c1a..d71ab61430b2 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -28,16 +28,16 @@ UNWIND( .fnstart ) mov r3, r1 7: cmp r2, #16 blt 4f +UNWIND( .fnend ) #if ! CALGN(1)+0 /* * We need 2 extra registers for this loop - use r8 and the LR */ - stmfd sp!, {r8, lr} -UNWIND( .fnend ) UNWIND( .fnstart ) UNWIND( .save {r8, lr} ) + stmfd sp!, {r8, lr} mov r8, r1 mov lr, r3 @@ -66,10 +66,9 @@ UNWIND( .fnend ) * whole cache lines at once. */ - stmfd sp!, {r4-r8, lr} -UNWIND( .fnend ) UNWIND( .fnstart ) UNWIND( .save {r4-r8, lr} ) + stmfd sp!, {r4-r8, lr} mov r4, r1 mov r5, r3 mov r6, r1 diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c index 106f83a5ea6d..c30b689bec2e 100644 --- a/arch/arm/lib/uaccess_with_memcpy.c +++ b/arch/arm/lib/uaccess_with_memcpy.c @@ -92,11 +92,6 @@ __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) unsigned long ua_flags; int atomic; - if (uaccess_kernel()) { - memcpy((void *)to, from, n); - return 0; - } - /* the mmap semaphore is taken only if not in an atomic context */ atomic = faulthandler_disabled(); @@ -165,11 +160,6 @@ __clear_user_memset(void __user *addr, unsigned long n) { unsigned long ua_flags; - if (uaccess_kernel()) { - memset((void *)addr, 0, n); - return 0; - } - mmap_read_lock(current->mm); while (n) { pte_t *pte; diff --git a/arch/nds32/kernel/vdso/.gitignore b/arch/arm/mach-airoha/Makefile similarity index 66% rename from arch/nds32/kernel/vdso/.gitignore rename to arch/arm/mach-airoha/Makefile index 652e31d82582..a5857d0d02eb 100644 --- a/arch/nds32/kernel/vdso/.gitignore +++ b/arch/arm/mach-airoha/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -vdso.lds +obj-y += airoha.o diff --git a/arch/arm/mach-airoha/airoha.c b/arch/arm/mach-airoha/airoha.c new file mode 100644 index 000000000000..ea23b5abb478 --- /dev/null +++ b/arch/arm/mach-airoha/airoha.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Device Tree support for Airoha SoCs + * + * Copyright (c) 2022 Felix Fietkau + */ +#include + +static const char * const airoha_board_dt_compat[] = { + "airoha,en7523", + NULL, +}; + +DT_MACHINE_START(MEDIATEK_DT, "Airoha Cortex-A53 (Device Tree)") + .dt_compat = airoha_board_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 02f6b108fd5d..279810381256 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -63,6 +63,7 @@ config SOC_SAMA7G5 select HAVE_AT91_GENERATED_CLK select HAVE_AT91_SAM9X60_PLL select HAVE_AT91_UTMI + select PM_OPP select SOC_SAMA7 help Select this if you are using one of Microchip's SAMA7G5 family SoC. diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index dd6f4ce3f766..0fd609e26615 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -605,6 +605,30 @@ static void at91sam9_sdram_standby(void) at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); } +static void sama7g5_standby(void) +{ + int pwrtmg, ratio; + + pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL); + ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO); + + /* + * Place RAM into self-refresh after a maximum idle clocks. The maximum + * idle clocks is configured by bootloader in + * UDDRC_PWRMGT.SELFREF_TO_X32. + */ + writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN, + soc_pm.data.ramc[0] + UDDRC_PWRCTL); + /* Divide CPU clock by 16. */ + writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO); + + cpu_do_idle(); + + /* Restore previous configuration. */ + writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO); + writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL); +} + struct ramc_info { void (*idle)(void); unsigned int memctrl; @@ -615,6 +639,7 @@ static const struct ramc_info ramc_infos[] __initconst = { { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC}, { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR}, + { .idle = sama7g5_standby, }, }; static const struct of_device_id ramc_ids[] __initconst = { @@ -622,7 +647,7 @@ static const struct of_device_id ramc_ids[] __initconst = { { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] }, { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] }, { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] }, - { .compatible = "microchip,sama7g5-uddrc", }, + { .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], }, { /*sentinel*/ } }; diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S index fdb4f63ecde4..abe4ced33eda 100644 --- a/arch/arm/mach-at91/pm_suspend.S +++ b/arch/arm/mach-at91/pm_suspend.S @@ -159,7 +159,7 @@ sr_ena_1: /* Switch to self-refresh. */ ldr tmp1, [r2, #UDDRC_PWRCTL] - orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW + orr tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW str tmp1, [r2, #UDDRC_PWRCTL] sr_ena_2: @@ -276,7 +276,7 @@ sr_dis_5: /* Trigger self-refresh exit. */ ldr tmp1, [r2, #UDDRC_PWRCTL] - bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW + bic tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW str tmp1, [r2, #UDDRC_PWRCTL] sr_dis_6: diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index bd3f82788ebc..8db655c3e321 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -185,7 +185,6 @@ config ARCH_BCM_53573 config ARCH_BCM_63XX bool "Broadcom BCM63xx DSL SoC" depends on ARCH_MULTI_V7 - depends on MMU select ARCH_HAS_RESET_CONTROLLER select ARM_ERRATA_754322 select ARM_ERRATA_764369 if SMP diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile index 7baa8c9427d5..b2394ddb0558 100644 --- a/arch/arm/mach-bcm/Makefile +++ b/arch/arm/mach-bcm/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o # Support for secure monitor traps obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o +CFLAGS_REMOVE_bcm_kona_smc.o += $(CC_FLAGS_FTRACE) # BCM2835 ifeq ($(CONFIG_ARCH_BCM2835),y) diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c index 31ccbcee2627..d36f6b8269c2 100644 --- a/arch/arm/mach-dove/irq.c +++ b/arch/arm/mach-dove/irq.c @@ -73,12 +73,12 @@ void __init dove_init_irq(void) /* * Initialize gpiolib for GPIOs 0-71. */ - orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, + orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, IRQ_DOVE_GPIO_START, gpio0_irqs); - orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, + orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 32, gpio1_irqs); - orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0, + orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 64, gpio2_irqs); } diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 2eaf2dbb8e81..2da5b60b59e2 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -60,8 +60,10 @@ static int exynos_cpu_boot(int cpu) /* * Exynos3250 doesn't need to send smc command for secondary CPU boot * because Exynos3250 removes WFE in secure mode. + * + * On Exynos5 devices the call is ignored by trustzone firmware. */ - if (soc_is_exynos3250()) + if (!soc_is_exynos4210() && !soc_is_exynos4412()) return 0; /* diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index cd861c57d5ad..fd0dbeb93357 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -35,7 +35,6 @@ static bool secure_firmware __ro_after_init; */ #define exynos_v7_exit_coherency_flush(level) \ asm volatile( \ - "stmfd sp!, {fp, ip}\n\t"\ "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" \ "bic r0, r0, #"__stringify(CR_C)"\n\t" \ "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \ @@ -50,11 +49,10 @@ static bool secure_firmware __ro_after_init; "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" \ "isb\n\t" \ "dsb\n\t" \ - "ldmfd sp!, {fp, ip}" \ : \ : "Ir" (pmu_base_addr + S5P_INFORM0) \ - : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ - "r9", "r10", "lr", "memory") + : "r0", "r1", "r2", "r3", "r4", "r5", "r6", \ + "r9", "r10", "ip", "lr", "memory") static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) { diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index eee095f0e2f6..322495df271d 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -27,6 +27,91 @@ #include "common.h" +#include +#include +#include + +static int dc21285_get_irq(void) +{ + void __iomem *irqstatus = (void __iomem *)CSR_IRQ_STATUS; + u32 mask = readl(irqstatus); + + if (mask & IRQ_MASK_SDRAMPARITY) + return IRQ_SDRAMPARITY; + + if (mask & IRQ_MASK_UART_RX) + return IRQ_CONRX; + + if (mask & IRQ_MASK_DMA1) + return IRQ_DMA1; + + if (mask & IRQ_MASK_DMA2) + return IRQ_DMA2; + + if (mask & IRQ_MASK_IN0) + return IRQ_IN0; + + if (mask & IRQ_MASK_IN1) + return IRQ_IN1; + + if (mask & IRQ_MASK_IN2) + return IRQ_IN2; + + if (mask & IRQ_MASK_IN3) + return IRQ_IN3; + + if (mask & IRQ_MASK_PCI) + return IRQ_PCI; + + if (mask & IRQ_MASK_DOORBELLHOST) + return IRQ_DOORBELLHOST; + + if (mask & IRQ_MASK_I2OINPOST) + return IRQ_I2OINPOST; + + if (mask & IRQ_MASK_TIMER1) + return IRQ_TIMER1; + + if (mask & IRQ_MASK_TIMER2) + return IRQ_TIMER2; + + if (mask & IRQ_MASK_TIMER3) + return IRQ_TIMER3; + + if (mask & IRQ_MASK_UART_TX) + return IRQ_CONTX; + + if (mask & IRQ_MASK_PCI_ABORT) + return IRQ_PCI_ABORT; + + if (mask & IRQ_MASK_PCI_SERR) + return IRQ_PCI_SERR; + + if (mask & IRQ_MASK_DISCARD_TIMER) + return IRQ_DISCARD_TIMER; + + if (mask & IRQ_MASK_PCI_DPERR) + return IRQ_PCI_DPERR; + + if (mask & IRQ_MASK_PCI_PERR) + return IRQ_PCI_PERR; + + return 0; +} + +static void dc21285_handle_irq(struct pt_regs *regs) +{ + int irq; + do { + irq = dc21285_get_irq(); + if (!irq) + break; + + generic_handle_irq(irq); + } while (1); +} + + unsigned int mem_fclk_21285 = 50000000; EXPORT_SYMBOL(mem_fclk_21285); @@ -108,6 +193,8 @@ static void __init __fb_init_irq(void) void __init footbridge_init_irq(void) { + set_handle_irq(dc21285_handle_irq); + __fb_init_irq(); if (!footbridge_cfn_mode()) diff --git a/arch/arm/mach-footbridge/include/mach/entry-macro.S b/arch/arm/mach-footbridge/include/mach/entry-macro.S deleted file mode 100644 index dabbd5c54a78..000000000000 --- a/arch/arm/mach-footbridge/include/mach/entry-macro.S +++ /dev/null @@ -1,107 +0,0 @@ -/* - * arch/arm/mach-footbridge/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for footbridge-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include -#include -#include - - .equ dc21285_high, ARMCSR_BASE & 0xff000000 - .equ dc21285_low, ARMCSR_BASE & 0x00ffffff - - .macro get_irqnr_preamble, base, tmp - mov \base, #dc21285_high - .if dc21285_low - orr \base, \base, #dc21285_low - .endif - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - ldr \irqstat, [\base, #0x180] @ get interrupts - - mov \irqnr, #IRQ_SDRAMPARITY - tst \irqstat, #IRQ_MASK_SDRAMPARITY - bne 1001f - - tst \irqstat, #IRQ_MASK_UART_RX - movne \irqnr, #IRQ_CONRX - bne 1001f - - tst \irqstat, #IRQ_MASK_DMA1 - movne \irqnr, #IRQ_DMA1 - bne 1001f - - tst \irqstat, #IRQ_MASK_DMA2 - movne \irqnr, #IRQ_DMA2 - bne 1001f - - tst \irqstat, #IRQ_MASK_IN0 - movne \irqnr, #IRQ_IN0 - bne 1001f - - tst \irqstat, #IRQ_MASK_IN1 - movne \irqnr, #IRQ_IN1 - bne 1001f - - tst \irqstat, #IRQ_MASK_IN2 - movne \irqnr, #IRQ_IN2 - bne 1001f - - tst \irqstat, #IRQ_MASK_IN3 - movne \irqnr, #IRQ_IN3 - bne 1001f - - tst \irqstat, #IRQ_MASK_PCI - movne \irqnr, #IRQ_PCI - bne 1001f - - tst \irqstat, #IRQ_MASK_DOORBELLHOST - movne \irqnr, #IRQ_DOORBELLHOST - bne 1001f - - tst \irqstat, #IRQ_MASK_I2OINPOST - movne \irqnr, #IRQ_I2OINPOST - bne 1001f - - tst \irqstat, #IRQ_MASK_TIMER1 - movne \irqnr, #IRQ_TIMER1 - bne 1001f - - tst \irqstat, #IRQ_MASK_TIMER2 - movne \irqnr, #IRQ_TIMER2 - bne 1001f - - tst \irqstat, #IRQ_MASK_TIMER3 - movne \irqnr, #IRQ_TIMER3 - bne 1001f - - tst \irqstat, #IRQ_MASK_UART_TX - movne \irqnr, #IRQ_CONTX - bne 1001f - - tst \irqstat, #IRQ_MASK_PCI_ABORT - movne \irqnr, #IRQ_PCI_ABORT - bne 1001f - - tst \irqstat, #IRQ_MASK_PCI_SERR - movne \irqnr, #IRQ_PCI_SERR - bne 1001f - - tst \irqstat, #IRQ_MASK_DISCARD_TIMER - movne \irqnr, #IRQ_DISCARD_TIMER - bne 1001f - - tst \irqstat, #IRQ_MASK_PCI_DPERR - movne \irqnr, #IRQ_PCI_DPERR - bne 1001f - - tst \irqstat, #IRQ_MASK_PCI_PERR - movne \irqnr, #IRQ_PCI_PERR -1001: - .endm - diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h index ecaf6e7388d9..985ad3a95671 100644 --- a/arch/arm/mach-footbridge/include/mach/hardware.h +++ b/arch/arm/mach-footbridge/include/mach/hardware.h @@ -21,32 +21,26 @@ * 0xf0000000 0x80000000 16MB ISA memory */ -#ifdef CONFIG_MMU -#define MMU_IO(a, b) (a) -#else -#define MMU_IO(a, b) (b) -#endif - #define XBUS_SIZE 0x00100000 -#define XBUS_BASE MMU_IO(0xff800000, 0x40000000) +#define XBUS_BASE 0xff800000 #define ARMCSR_SIZE 0x00100000 -#define ARMCSR_BASE MMU_IO(0xfe000000, 0x42000000) +#define ARMCSR_BASE 0xfe000000 #define WFLUSH_SIZE 0x00100000 -#define WFLUSH_BASE MMU_IO(0xfd000000, 0x78000000) +#define WFLUSH_BASE 0xfd000000 #define PCIIACK_SIZE 0x00100000 -#define PCIIACK_BASE MMU_IO(0xfc000000, 0x79000000) +#define PCIIACK_BASE 0xfc000000 #define PCICFG1_SIZE 0x01000000 -#define PCICFG1_BASE MMU_IO(0xfb000000, 0x7a000000) +#define PCICFG1_BASE 0xfb000000 #define PCICFG0_SIZE 0x01000000 -#define PCICFG0_BASE MMU_IO(0xfa000000, 0x7b000000) +#define PCICFG0_BASE 0xfa000000 #define PCIMEM_SIZE 0x01000000 -#define PCIMEM_BASE MMU_IO(0xf0000000, 0x80000000) +#define PCIMEM_BASE 0xf0000000 #define XBUS_CS2 0x40012000 diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h deleted file mode 100644 index 4e18b921373f..000000000000 --- a/arch/arm/mach-footbridge/include/mach/io.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-footbridge/include/mach/io.h - * - * Copyright (C) 1997-1999 Russell King - * - * Modifications: - * 06-12-1997 RMK Created. - * 07-04-1999 RMK Major cleanup - */ -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -/* - * Translation of various i/o addresses to host addresses for !CONFIG_MMU - */ -#define PCIO_BASE 0x7c000000 -#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) - -#endif diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index f296bac467c8..c5a59158722b 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -227,6 +227,13 @@ config SOC_IMX7ULP help This enables support for Freescale i.MX7 Ultra Low Power processor. +config SOC_IMXRT + bool "i.MXRT support" + depends on ARM_SINGLE_ARMV7M + select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M + help + This enables support for Freescale i.MXRT Crossover processor. + config SOC_VF610 bool "Vybrid Family VF610 support" select ARM_GIC if ARCH_MULTI_V7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index d5291ed9186a..6fb3965b9ae6 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -63,6 +63,8 @@ obj-$(CONFIG_SOC_IMX50) += mach-imx50.o obj-$(CONFIG_SOC_IMX51) += mach-imx51.o obj-$(CONFIG_SOC_IMX53) += mach-imx53.o +obj-$(CONFIG_SOC_IMXRT) += mach-imxrt.o + obj-$(CONFIG_SOC_VF610) += mach-vf610.o obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o diff --git a/arch/arm/mach-imx/mach-imxrt.c b/arch/arm/mach-imx/mach-imxrt.c new file mode 100644 index 000000000000..2063a3059c84 --- /dev/null +++ b/arch/arm/mach-imx/mach-imxrt.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti + */ + +#include +#include +#include + +static const char *const imxrt_compat[] __initconst = { + "fsl,imxrt1050", + NULL +}; + +DT_MACHINE_START(IMXRTDT, "IMXRT (Device Tree Support)") + .dt_compat = imxrt_compat, + .restart = armv7m_restart, +MACHINE_END diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index 63a0ca82659a..d61ea616cf8e 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -42,24 +42,12 @@ config INTEGRATOR_IMPD1 allows ARM(R) Ltd PrimeCells to be developed and evaluated. The IM-PD1 can be found on the Integrator/PP2 platform. -config INTEGRATOR_CM7TDMI - bool "Integrator/CM7TDMI core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V4 && !MMU - select CPU_ARM7TDMI - config INTEGRATOR_CM720T bool "Integrator/CM720T core module" depends on ARCH_INTEGRATOR_AP depends on ARCH_MULTI_V4T select CPU_ARM720T -config INTEGRATOR_CM740T - bool "Integrator/CM740T core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V4T && !MMU - select CPU_ARM740T - config INTEGRATOR_CM920T bool "Integrator/CM920T core module" depends on ARCH_INTEGRATOR_AP @@ -78,23 +66,6 @@ config INTEGRATOR_CM926EJS depends on ARCH_MULTI_V5 select CPU_ARM926T -config INTEGRATOR_CM940T - bool "Integrator/CM940T core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V4T && !MMU - select CPU_ARM940T - -config INTEGRATOR_CM946ES - bool "Integrator/CM946E-S core module" - depends on ARCH_INTEGRATOR_AP - depends on ARCH_MULTI_V5 && !MMU - select CPU_ARM946E - -config INTEGRATOR_CM966ES - bool "Integrator/CM966E-S core module" - depends on ARCH_INTEGRATOR_AP - depends on BROKEN # no kernel support - config INTEGRATOR_CM10200E_REV0 bool "Integrator/CM10200E rev.0 core module" depends on ARCH_INTEGRATOR_AP && n @@ -127,7 +98,7 @@ config INTEGRATOR_CM1136JFS config ARCH_INTEGRATOR_CP bool "Support Integrator/CP platform" - depends on (!MMU || ARCH_MULTI_V5 || ARCH_MULTI_V6) + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 select ARM_TIMER_SP804 select SERIAL_AMBA_PL011 if TTY select SERIAL_AMBA_PL011_CONSOLE if TTY @@ -135,12 +106,6 @@ config ARCH_INTEGRATOR_CP help Include support for the ARM(R) Integrator CP platform. -config INTEGRATOR_CT7T - bool "Integrator/CT7TD (ARM7TDMI) core tile" - depends on ARCH_INTEGRATOR_CP - depends on ARCH_MULTI_V4T && !MMU - select CPU_ARM7TDMI - config INTEGRATOR_CT926 bool "Integrator/CT926 (ARM926EJ-S) core tile" depends on ARCH_INTEGRATOR_CP diff --git a/arch/arm/mach-integrator/hardware.h b/arch/arm/mach-integrator/hardware.h index 4d6ade3dd4ee..81ce09e3ad45 100644 --- a/arch/arm/mach-integrator/hardware.h +++ b/arch/arm/mach-integrator/hardware.h @@ -16,12 +16,7 @@ #define IO_START INTEGRATOR_HDR_BASE // PA of IO /* macro to get at IO space when running virtually */ -#ifdef CONFIG_MMU #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE) -#else -#define IO_ADDRESS(x) (x) -#endif - #define __io_address(n) ((void __iomem *)IO_ADDRESS(n)) /* diff --git a/arch/arm/mach-iop32x/cp6.c b/arch/arm/mach-iop32x/cp6.c index ec74b07fb7e3..2882674a1c39 100644 --- a/arch/arm/mach-iop32x/cp6.c +++ b/arch/arm/mach-iop32x/cp6.c @@ -7,7 +7,7 @@ #include #include -static int cp6_trap(struct pt_regs *regs, unsigned int instr) +void iop_enable_cp6(void) { u32 temp; @@ -16,7 +16,15 @@ static int cp6_trap(struct pt_regs *regs, unsigned int instr) "mrc p15, 0, %0, c15, c1, 0\n\t" "orr %0, %0, #(1 << 6)\n\t" "mcr p15, 0, %0, c15, c1, 0\n\t" + "mrc p15, 0, %0, c15, c1, 0\n\t" + "mov %0, %0\n\t" + "sub pc, pc, #4 @ cp_wait\n\t" : "=r"(temp)); +} + +static int cp6_trap(struct pt_regs *regs, unsigned int instr) +{ + iop_enable_cp6(); return 0; } diff --git a/arch/arm/mach-iop32x/include/mach/entry-macro.S b/arch/arm/mach-iop32x/include/mach/entry-macro.S deleted file mode 100644 index 8e6766d4621e..000000000000 --- a/arch/arm/mach-iop32x/include/mach/entry-macro.S +++ /dev/null @@ -1,31 +0,0 @@ -/* - * arch/arm/mach-iop32x/include/mach/entry-macro.S - * - * Low-level IRQ helper macros for IOP32x-based platforms - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - .macro get_irqnr_preamble, base, tmp - mrc p15, 0, \tmp, c15, c1, 0 - orr \tmp, \tmp, #(1 << 6) - mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access - mrc p15, 0, \tmp, c15, c1, 0 - mov \tmp, \tmp - sub pc, pc, #4 @ cp_wait - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC - cmp \irqstat, #0 - clzne \irqnr, \irqstat - rsbne \irqnr, \irqnr, #31 - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - mrc p15, 0, \tmp1, c15, c1, 0 - ands \tmp2, \tmp1, #(1 << 6) - bicne \tmp1, \tmp1, #(1 << 6) - mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access - .endm diff --git a/arch/arm/mach-iop32x/include/mach/irqs.h b/arch/arm/mach-iop32x/include/mach/irqs.h index c4e78df428e8..e09ae5f48aec 100644 --- a/arch/arm/mach-iop32x/include/mach/irqs.h +++ b/arch/arm/mach-iop32x/include/mach/irqs.h @@ -9,6 +9,6 @@ #ifndef __IRQS_H #define __IRQS_H -#define NR_IRQS 32 +#define NR_IRQS 33 #endif diff --git a/arch/arm/mach-iop32x/iop3xx.h b/arch/arm/mach-iop32x/iop3xx.h index 46b4b34a4ad2..a6ec7ebadb35 100644 --- a/arch/arm/mach-iop32x/iop3xx.h +++ b/arch/arm/mach-iop32x/iop3xx.h @@ -225,6 +225,7 @@ extern int iop3xx_get_init_atu(void); #include void iop3xx_map_io(void); +void iop_enable_cp6(void); void iop_init_cp6_handler(void); void iop_init_time(unsigned long tickrate); void iop3xx_restart(enum reboot_mode, const char *); diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c index 2d48bf1398c1..6dca7e97d81f 100644 --- a/arch/arm/mach-iop32x/irq.c +++ b/arch/arm/mach-iop32x/irq.c @@ -29,17 +29,26 @@ static void intstr_write(u32 val) asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); } +static u32 iintsrc_read(void) +{ + int irq; + + asm volatile("mrc p6, 0, %0, c8, c0, 0" : "=r" (irq)); + + return irq; +} + static void iop32x_irq_mask(struct irq_data *d) { - iop32x_mask &= ~(1 << d->irq); + iop32x_mask &= ~(1 << (d->irq - 1)); intctl_write(iop32x_mask); } static void iop32x_irq_unmask(struct irq_data *d) { - iop32x_mask |= 1 << d->irq; + iop32x_mask |= 1 << (d->irq - 1); intctl_write(iop32x_mask); } @@ -50,11 +59,25 @@ struct irq_chip ext_chip = { .irq_unmask = iop32x_irq_unmask, }; +static void iop_handle_irq(struct pt_regs *regs) +{ + u32 mask; + + iop_enable_cp6(); + + do { + mask = iintsrc_read(); + if (mask) + generic_handle_irq(fls(mask)); + } while (mask); +} + void __init iop32x_init_irq(void) { int i; iop_init_cp6_handler(); + set_handle_irq(iop_handle_irq); intctl_write(0); intstr_write(0); @@ -65,7 +88,7 @@ void __init iop32x_init_irq(void) machine_is_em7210()) *IOP3XX_PCIIRSR = 0x0f; - for (i = 0; i < NR_IRQS; i++) { + for (i = 1; i < NR_IRQS; i++) { irq_set_chip_and_handler(i, &ext_chip, handle_level_irq); irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); } diff --git a/arch/arm/mach-iop32x/irqs.h b/arch/arm/mach-iop32x/irqs.h index 69858e4e905d..e1dfc8b4e7d7 100644 --- a/arch/arm/mach-iop32x/irqs.h +++ b/arch/arm/mach-iop32x/irqs.h @@ -7,36 +7,40 @@ #ifndef __IOP32X_IRQS_H #define __IOP32X_IRQS_H +/* Interrupts in Linux start at 1, hardware starts at 0 */ + +#define IOP_IRQ(x) ((x) + 1) + /* * IOP80321 chipset interrupts */ -#define IRQ_IOP32X_DMA0_EOT 0 -#define IRQ_IOP32X_DMA0_EOC 1 -#define IRQ_IOP32X_DMA1_EOT 2 -#define IRQ_IOP32X_DMA1_EOC 3 -#define IRQ_IOP32X_AA_EOT 6 -#define IRQ_IOP32X_AA_EOC 7 -#define IRQ_IOP32X_CORE_PMON 8 -#define IRQ_IOP32X_TIMER0 9 -#define IRQ_IOP32X_TIMER1 10 -#define IRQ_IOP32X_I2C_0 11 -#define IRQ_IOP32X_I2C_1 12 -#define IRQ_IOP32X_MESSAGING 13 -#define IRQ_IOP32X_ATU_BIST 14 -#define IRQ_IOP32X_PERFMON 15 -#define IRQ_IOP32X_CORE_PMU 16 -#define IRQ_IOP32X_BIU_ERR 17 -#define IRQ_IOP32X_ATU_ERR 18 -#define IRQ_IOP32X_MCU_ERR 19 -#define IRQ_IOP32X_DMA0_ERR 20 -#define IRQ_IOP32X_DMA1_ERR 21 -#define IRQ_IOP32X_AA_ERR 23 -#define IRQ_IOP32X_MSG_ERR 24 -#define IRQ_IOP32X_SSP 25 -#define IRQ_IOP32X_XINT0 27 -#define IRQ_IOP32X_XINT1 28 -#define IRQ_IOP32X_XINT2 29 -#define IRQ_IOP32X_XINT3 30 -#define IRQ_IOP32X_HPI 31 +#define IRQ_IOP32X_DMA0_EOT IOP_IRQ(0) +#define IRQ_IOP32X_DMA0_EOC IOP_IRQ(1) +#define IRQ_IOP32X_DMA1_EOT IOP_IRQ(2) +#define IRQ_IOP32X_DMA1_EOC IOP_IRQ(3) +#define IRQ_IOP32X_AA_EOT IOP_IRQ(6) +#define IRQ_IOP32X_AA_EOC IOP_IRQ(7) +#define IRQ_IOP32X_CORE_PMON IOP_IRQ(8) +#define IRQ_IOP32X_TIMER0 IOP_IRQ(9) +#define IRQ_IOP32X_TIMER1 IOP_IRQ(10) +#define IRQ_IOP32X_I2C_0 IOP_IRQ(11) +#define IRQ_IOP32X_I2C_1 IOP_IRQ(12) +#define IRQ_IOP32X_MESSAGING IOP_IRQ(13) +#define IRQ_IOP32X_ATU_BIST IOP_IRQ(14) +#define IRQ_IOP32X_PERFMON IOP_IRQ(15) +#define IRQ_IOP32X_CORE_PMU IOP_IRQ(16) +#define IRQ_IOP32X_BIU_ERR IOP_IRQ(17) +#define IRQ_IOP32X_ATU_ERR IOP_IRQ(18) +#define IRQ_IOP32X_MCU_ERR IOP_IRQ(19) +#define IRQ_IOP32X_DMA0_ERR IOP_IRQ(20) +#define IRQ_IOP32X_DMA1_ERR IOP_IRQ(21) +#define IRQ_IOP32X_AA_ERR IOP_IRQ(23) +#define IRQ_IOP32X_MSG_ERR IOP_IRQ(24) +#define IRQ_IOP32X_SSP IOP_IRQ(25) +#define IRQ_IOP32X_XINT0 IOP_IRQ(27) +#define IRQ_IOP32X_XINT1 IOP_IRQ(28) +#define IRQ_IOP32X_XINT2 IOP_IRQ(29) +#define IRQ_IOP32X_XINT3 IOP_IRQ(30) +#define IRQ_IOP32X_HPI IOP_IRQ(31) #endif diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig index 4c787b4be62b..f41ba3f42fc8 100644 --- a/arch/arm/mach-ixp4xx/Kconfig +++ b/arch/arm/mach-ixp4xx/Kconfig @@ -17,63 +17,6 @@ config MACH_IXP4XX_OF help Say 'Y' here to support Device Tree-based IXP4xx platforms. -config MACH_GATEWAY7001 - bool "Gateway 7001" - depends on IXP4XX_PCI_LEGACY - help - Say 'Y' here if you want your kernel to support Gateway's - 7001 Access Point. For more information on this platform, - see http://openwrt.org - -config MACH_GORAMO_MLR - bool "GORAMO Multi Link Router" - depends on IXP4XX_PCI_LEGACY - help - Say 'Y' here if you want your kernel to support GORAMO - MultiLink router. - -config ARCH_PRPMC1100 - bool "PrPMC1100" - help - Say 'Y' here if you want your kernel to support the Motorola - PrPCM1100 Processor Mezanine Module. For more information on - this platform, see . - -comment "IXP4xx Options" - -config IXP4XX_PCI_LEGACY - bool "IXP4xx legacy PCI driver support" - depends on PCI - help - Selects legacy PCI driver. - Not recommended for new development. - -config IXP4XX_INDIRECT_PCI - bool "Use indirect PCI memory access" - depends on IXP4XX_PCI_LEGACY - help - IXP4xx provides two methods of accessing PCI memory space: - - 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). - To access PCI via this space, we simply ioremap() the BAR - into the kernel and we can use the standard read[bwl]/write[bwl] - macros. This is the preferred method due to speed but it - limits the system to just 64MB of PCI memory. This can be - problematic if using video cards and other memory-heavy devices. - - 2) If > 64MB of memory space is required, the IXP4xx can be - configured to use indirect registers to access the whole PCI - memory space. This currently allows for up to 1 GB (0x10000000 - to 0x4FFFFFFF) of memory on the bus. The disadvantage of this - is that every PCI access requires three local register accesses - plus a spinlock, but in some cases the performance hit is - acceptable. In addition, you cannot mmap() PCI devices in this - case due to the indirect nature of the PCI window. - - By default, the direct method is used. Choose this option if you - need to use the indirect method instead. If you don't know - what you need, leave this option unselected. - endmenu endif diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile index b241094c9649..3d1c9d854c7f 100644 --- a/arch/arm/mach-ixp4xx/Makefile +++ b/arch/arm/mach-ixp4xx/Makefile @@ -1,19 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# - -obj-pci-y := -obj-pci-n := - -# Device tree platform -obj-pci-$(CONFIG_MACH_IXP4XX_OF) += ixp4xx-of.o - -obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o - -obj-y += common.o - -obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o -obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o - -obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o +obj-y += ixp4xx-of.o diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c deleted file mode 100644 index 893c19c254e3..000000000000 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ /dev/null @@ -1,451 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-ixp4xx/common-pci.c - * - * IXP4XX PCI routines for all platforms - * - * Maintainer: Deepak Saxena - * - * Copyright (C) 2002 Intel Corporation. - * Copyright (C) 2003 Greg Ungerer - * Copyright (C) 2003-2004 MontaVista Software, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - - -/* - * IXP4xx PCI read function is dependent on whether we are - * running A0 or B0 (AppleGate) silicon. - */ -int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); - -/* - * Base address for PCI register region - */ -unsigned long ixp4xx_pci_reg_base = 0; - -/* - * PCI cfg an I/O routines are done by programming a - * command/byte enable register, and then read/writing - * the data from a data register. We need to ensure - * these transactions are atomic or we will end up - * with corrupt data on the bus or in a driver. - */ -static DEFINE_RAW_SPINLOCK(ixp4xx_pci_lock); - -/* - * Read from PCI config space - */ -static void crp_read(u32 ad_cbe, u32 *data) -{ - unsigned long flags; - raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); - *PCI_CRP_AD_CBE = ad_cbe; - *data = *PCI_CRP_RDATA; - raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); -} - -/* - * Write to PCI config space - */ -static void crp_write(u32 ad_cbe, u32 data) -{ - unsigned long flags; - raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); - *PCI_CRP_AD_CBE = CRP_AD_CBE_WRITE | ad_cbe; - *PCI_CRP_WDATA = data; - raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); -} - -static inline int check_master_abort(void) -{ - /* check Master Abort bit after access */ - unsigned long isr = *PCI_ISR; - - if (isr & PCI_ISR_PFE) { - /* make sure the Master Abort bit is reset */ - *PCI_ISR = PCI_ISR_PFE; - pr_debug("%s failed\n", __func__); - return 1; - } - - return 0; -} - -int ixp4xx_pci_read_errata(u32 addr, u32 cmd, u32* data) -{ - unsigned long flags; - int retval = 0; - int i; - - raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); - - *PCI_NP_AD = addr; - - /* - * PCI workaround - only works if NP PCI space reads have - * no side effects!!! Read 8 times. last one will be good. - */ - for (i = 0; i < 8; i++) { - *PCI_NP_CBE = cmd; - *data = *PCI_NP_RDATA; - *data = *PCI_NP_RDATA; - } - - if(check_master_abort()) - retval = 1; - - raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); - return retval; -} - -int ixp4xx_pci_read_no_errata(u32 addr, u32 cmd, u32* data) -{ - unsigned long flags; - int retval = 0; - - raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); - - *PCI_NP_AD = addr; - - /* set up and execute the read */ - *PCI_NP_CBE = cmd; - - /* the result of the read is now in NP_RDATA */ - *data = *PCI_NP_RDATA; - - if(check_master_abort()) - retval = 1; - - raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); - return retval; -} - -int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data) -{ - unsigned long flags; - int retval = 0; - - raw_spin_lock_irqsave(&ixp4xx_pci_lock, flags); - - *PCI_NP_AD = addr; - - /* set up the write */ - *PCI_NP_CBE = cmd; - - /* execute the write by writing to NP_WDATA */ - *PCI_NP_WDATA = data; - - if(check_master_abort()) - retval = 1; - - raw_spin_unlock_irqrestore(&ixp4xx_pci_lock, flags); - return retval; -} - -static u32 ixp4xx_config_addr(u8 bus_num, u16 devfn, int where) -{ - u32 addr; - if (!bus_num) { - /* type 0 */ - addr = BIT(32-PCI_SLOT(devfn)) | ((PCI_FUNC(devfn)) << 8) | - (where & ~3); - } else { - /* type 1 */ - addr = (bus_num << 16) | ((PCI_SLOT(devfn)) << 11) | - ((PCI_FUNC(devfn)) << 8) | (where & ~3) | 1; - } - return addr; -} - -/* - * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes. - * 0 and 3 are not valid indexes... - */ -static u32 bytemask[] = { - /*0*/ 0, - /*1*/ 0xff, - /*2*/ 0xffff, - /*3*/ 0, - /*4*/ 0xffffffff, -}; - -static u32 local_byte_lane_enable_bits(u32 n, int size) -{ - if (size == 1) - return (0xf & ~BIT(n)) << CRP_AD_CBE_BESL; - if (size == 2) - return (0xf & ~(BIT(n) | BIT(n+1))) << CRP_AD_CBE_BESL; - if (size == 4) - return 0; - return 0xffffffff; -} - -static int local_read_config(int where, int size, u32 *value) -{ - u32 n, data; - pr_debug("local_read_config from %d size %d\n", where, size); - n = where % 4; - crp_read(where & ~3, &data); - *value = (data >> (8*n)) & bytemask[size]; - pr_debug("local_read_config read %#x\n", *value); - return PCIBIOS_SUCCESSFUL; -} - -static int local_write_config(int where, int size, u32 value) -{ - u32 n, byte_enables, data; - pr_debug("local_write_config %#x to %d size %d\n", value, where, size); - n = where % 4; - byte_enables = local_byte_lane_enable_bits(n, size); - if (byte_enables == 0xffffffff) - return PCIBIOS_BAD_REGISTER_NUMBER; - data = value << (8*n); - crp_write((where & ~3) | byte_enables, data); - return PCIBIOS_SUCCESSFUL; -} - -static u32 byte_lane_enable_bits(u32 n, int size) -{ - if (size == 1) - return (0xf & ~BIT(n)) << 4; - if (size == 2) - return (0xf & ~(BIT(n) | BIT(n+1))) << 4; - if (size == 4) - return 0; - return 0xffffffff; -} - -static int ixp4xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value) -{ - u32 n, byte_enables, addr, data; - u8 bus_num = bus->number; - - pr_debug("read_config from %d size %d dev %d:%d:%d\n", where, size, - bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - *value = 0xffffffff; - n = where % 4; - byte_enables = byte_lane_enable_bits(n, size); - if (byte_enables == 0xffffffff) - return PCIBIOS_BAD_REGISTER_NUMBER; - - addr = ixp4xx_config_addr(bus_num, devfn, where); - if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_CONFIGREAD, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - *value = (data >> (8*n)) & bytemask[size]; - pr_debug("read_config_byte read %#x\n", *value); - return PCIBIOS_SUCCESSFUL; -} - -static int ixp4xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value) -{ - u32 n, byte_enables, addr, data; - u8 bus_num = bus->number; - - pr_debug("write_config_byte %#x to %d size %d dev %d:%d:%d\n", value, where, - size, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn)); - - n = where % 4; - byte_enables = byte_lane_enable_bits(n, size); - if (byte_enables == 0xffffffff) - return PCIBIOS_BAD_REGISTER_NUMBER; - - addr = ixp4xx_config_addr(bus_num, devfn, where); - data = value << (8*n); - if (ixp4xx_pci_write(addr, byte_enables | NP_CMD_CONFIGWRITE, data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops ixp4xx_ops = { - .read = ixp4xx_pci_read_config, - .write = ixp4xx_pci_write_config, -}; - -/* - * PCI abort handler - */ -static int abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - u32 isr, status; - - isr = *PCI_ISR; - local_read_config(PCI_STATUS, 2, &status); - pr_debug("PCI: abort_handler addr = %#lx, isr = %#x, " - "status = %#x\n", addr, isr, status); - - /* make sure the Master Abort bit is reset */ - *PCI_ISR = PCI_ISR_PFE; - status |= PCI_STATUS_REC_MASTER_ABORT; - local_write_config(PCI_STATUS, 2, status); - - /* - * If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - return 0; -} - -void __init ixp4xx_pci_preinit(void) -{ - unsigned long cpuid = read_cpuid_id(); - -#ifdef CONFIG_IXP4XX_INDIRECT_PCI - pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */ -#else - pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */ -#endif - /* - * Determine which PCI read method to use. - * Rev 0 IXP425 requires workaround. - */ - if (!(cpuid & 0xf) && cpu_is_ixp42x()) { - printk("PCI: IXP42x A0 silicon detected - " - "PCI Non-Prefetch Workaround Enabled\n"); - ixp4xx_pci_read = ixp4xx_pci_read_errata; - } else - ixp4xx_pci_read = ixp4xx_pci_read_no_errata; - - - /* hook in our fault handler for PCI errors */ - hook_fault_code(16+6, abort_handler, SIGBUS, 0, - "imprecise external abort"); - - pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); - - /* - * We use identity AHB->PCI address translation - * in the 0x48000000 to 0x4bffffff address space - */ - *PCI_PCIMEMBASE = 0x48494A4B; - - /* - * We also use identity PCI->AHB address translation - * in 4 16MB BARs that begin at the physical memory start - */ - *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + - ((PHYS_OFFSET & 0xFF000000) >> 8) + - ((PHYS_OFFSET & 0xFF000000) >> 16) + - ((PHYS_OFFSET & 0xFF000000) >> 24) + - 0x00010203; - - if (*PCI_CSR & PCI_CSR_HOST) { - printk("PCI: IXP4xx is host\n"); - - pr_debug("setup BARs in controller\n"); - - /* - * We configure the PCI inbound memory windows to be - * 1:1 mapped to SDRAM - */ - local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET); - local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M); - local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M); - local_write_config(PCI_BASE_ADDRESS_3, 4, - PHYS_OFFSET + SZ_32M + SZ_16M); - - /* - * Enable CSR window at 64 MiB to allow PCI masters - * to continue prefetching past 64 MiB boundary. - */ - local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M); - - /* - * Enable the IO window to be way up high, at 0xfffffc00 - */ - local_write_config(PCI_BASE_ADDRESS_5, 4, 0xfffffc01); - local_write_config(0x40, 4, 0x000080FF); /* No TRDY time limit */ - } else { - printk("PCI: IXP4xx is target - No bus scan performed\n"); - } - - printk("PCI: IXP4xx Using %s access for memory space\n", -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - "direct" -#else - "indirect" -#endif - ); - - pr_debug("clear error bits in ISR\n"); - *PCI_ISR = PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE; - - /* - * Set Initialize Complete in PCI Control Register: allow IXP4XX to - * respond to PCI configuration cycles. Specify that the AHB bus is - * operating in big endian mode. Set up byte lane swapping between - * little-endian PCI and the big-endian AHB bus - */ -#ifdef __ARMEB__ - *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS; -#else - *PCI_CSR = PCI_CSR_IC | PCI_CSR_ABE; -#endif - - pr_debug("DONE\n"); -} - -int ixp4xx_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - - if (nr >= 1) - return 0; - - res = kcalloc(2, sizeof(*res), GFP_KERNEL); - if (res == NULL) { - /* - * If we're out of memory this early, something is wrong, - * so we might as well catch it here. - */ - panic("PCI: unable to allocate resources?\n"); - } - - local_write_config(PCI_COMMAND, 2, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - - res[0].name = "PCI I/O Space"; - res[0].start = 0x00000000; - res[0].end = 0x0000ffff; - res[0].flags = IORESOURCE_IO; - - res[1].name = "PCI Memory Space"; - res[1].start = PCIBIOS_MIN_MEM; - res[1].end = PCIBIOS_MAX_MEM; - res[1].flags = IORESOURCE_MEM; - - request_resource(&ioport_resource, &res[0]); - request_resource(&iomem_resource, &res[1]); - - pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); - pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); - - return 1; -} - -EXPORT_SYMBOL(ixp4xx_pci_read); -EXPORT_SYMBOL(ixp4xx_pci_write); diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c deleted file mode 100644 index cdc720f54daa..000000000000 --- a/arch/arm/mach-ixp4xx/common.c +++ /dev/null @@ -1,448 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/common.c - * - * Generic code shared across all IXP4XX platforms - * - * Maintainer: Deepak Saxena - * - * Copyright 2002 (c) Intel Corporation - * Copyright 2003-2004 (c) MontaVista, Software, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "irqs.h" - -u32 ixp4xx_read_feature_bits(void) -{ - u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); - - if (cpu_is_ixp42x_rev_a0()) - return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | - IXP4XX_FEATURE_AES); - if (cpu_is_ixp42x()) - return val & IXP42X_FEATURE_MASK; - if (cpu_is_ixp43x()) - return val & IXP43X_FEATURE_MASK; - return val & IXP46X_FEATURE_MASK; -} -EXPORT_SYMBOL(ixp4xx_read_feature_bits); - -void ixp4xx_write_feature_bits(u32 value) -{ - __raw_writel(~value, IXP4XX_EXP_CFG2); -} -EXPORT_SYMBOL(ixp4xx_write_feature_bits); - -#define IXP4XX_TIMER_FREQ 66666000 - -/************************************************************************* - * IXP4xx chipset I/O mapping - *************************************************************************/ -static struct map_desc ixp4xx_io_desc[] __initdata = { - { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ - .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT, - .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), - .length = IXP4XX_PERIPHERAL_REGION_SIZE, - .type = MT_DEVICE - }, { /* Expansion Bus Config Registers */ - .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT, - .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), - .length = IXP4XX_EXP_CFG_REGION_SIZE, - .type = MT_DEVICE - }, { /* PCI Registers */ - .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT, - .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), - .length = IXP4XX_PCI_CFG_REGION_SIZE, - .type = MT_DEVICE - }, -}; - -void __init ixp4xx_map_io(void) -{ - iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc)); -} - -void __init ixp4xx_init_irq(void) -{ - /* - * ixp4xx does not implement the XScale PWRMODE register - * so it must not call cpu_do_idle(). - */ - cpu_idle_poll_ctrl(true); - - ixp4xx_irq_init(IXP4XX_INTC_BASE_PHYS, - (cpu_is_ixp46x() || cpu_is_ixp43x())); -} - -void __init ixp4xx_timer_init(void) -{ - return ixp4xx_timer_setup(IXP4XX_TIMER_BASE_PHYS, - IRQ_IXP4XX_TIMER1, - IXP4XX_TIMER_FREQ); -} - -static struct pxa2xx_udc_mach_info ixp4xx_udc_info; - -void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info) -{ - memcpy(&ixp4xx_udc_info, info, sizeof *info); -} - -static struct resource ixp4xx_udc_resources[] = { - [0] = { - .start = 0xc800b000, - .end = 0xc800bfff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IXP4XX_USB, - .end = IRQ_IXP4XX_USB, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource ixp4xx_gpio_resource[] = { - { - .start = IXP4XX_GPIO_BASE_PHYS, - .end = IXP4XX_GPIO_BASE_PHYS + 0xfff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device ixp4xx_gpio_device = { - .name = "ixp4xx-gpio", - .id = -1, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = ixp4xx_gpio_resource, - .num_resources = ARRAY_SIZE(ixp4xx_gpio_resource), -}; - -/* - * USB device controller. The IXP4xx uses the same controller as PXA25X, - * so we just use the same device. - */ -static struct platform_device ixp4xx_udc_device = { - .name = "pxa25x-udc", - .id = -1, - .num_resources = 2, - .resource = ixp4xx_udc_resources, - .dev = { - .platform_data = &ixp4xx_udc_info, - }, -}; - -static struct resource ixp4xx_npe_resources[] = { - { - .start = IXP4XX_NPEA_BASE_PHYS, - .end = IXP4XX_NPEA_BASE_PHYS + 0xfff, - .flags = IORESOURCE_MEM, - }, - { - .start = IXP4XX_NPEB_BASE_PHYS, - .end = IXP4XX_NPEB_BASE_PHYS + 0xfff, - .flags = IORESOURCE_MEM, - }, - { - .start = IXP4XX_NPEC_BASE_PHYS, - .end = IXP4XX_NPEC_BASE_PHYS + 0xfff, - .flags = IORESOURCE_MEM, - }, - -}; - -static struct platform_device ixp4xx_npe_device = { - .name = "ixp4xx-npe", - .id = -1, - .num_resources = ARRAY_SIZE(ixp4xx_npe_resources), - .resource = ixp4xx_npe_resources, -}; - -static struct resource ixp4xx_qmgr_resources[] = { - { - .start = IXP4XX_QMGR_BASE_PHYS, - .end = IXP4XX_QMGR_BASE_PHYS + 0x3fff, - .flags = IORESOURCE_MEM, - }, - { - .start = IRQ_IXP4XX_QM1, - .end = IRQ_IXP4XX_QM1, - .flags = IORESOURCE_IRQ, - }, - { - .start = IRQ_IXP4XX_QM2, - .end = IRQ_IXP4XX_QM2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device ixp4xx_qmgr_device = { - .name = "ixp4xx-qmgr", - .id = -1, - .num_resources = ARRAY_SIZE(ixp4xx_qmgr_resources), - .resource = ixp4xx_qmgr_resources, -}; - -static struct platform_device *ixp4xx_devices[] __initdata = { - &ixp4xx_npe_device, - &ixp4xx_qmgr_device, - &ixp4xx_gpio_device, - &ixp4xx_udc_device, -}; - -static struct resource ixp46x_i2c_resources[] = { - [0] = { - .start = 0xc8011000, - .end = 0xc801101c, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IXP4XX_I2C, - .end = IRQ_IXP4XX_I2C, - .flags = IORESOURCE_IRQ - } -}; - -/* A single 32-bit register on IXP46x */ -#define IXP4XX_HWRANDOM_BASE_PHYS 0x70002100 - -static struct resource ixp46x_hwrandom_resource[] = { - { - .start = IXP4XX_HWRANDOM_BASE_PHYS, - .end = IXP4XX_HWRANDOM_BASE_PHYS + 0x3, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device ixp46x_hwrandom_device = { - .name = "ixp4xx-hwrandom", - .id = -1, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = ixp46x_hwrandom_resource, - .num_resources = ARRAY_SIZE(ixp46x_hwrandom_resource), -}; - -/* - * I2C controller. The IXP46x uses the same block as the IOP3xx, so - * we just use the same device name. - */ -static struct platform_device ixp46x_i2c_controller = { - .name = "IOP3xx-I2C", - .id = 0, - .num_resources = 2, - .resource = ixp46x_i2c_resources -}; - -static struct resource ixp46x_ptp_resources[] = { - DEFINE_RES_MEM(IXP4XX_TIMESYNC_BASE_PHYS, SZ_4K), - DEFINE_RES_IRQ_NAMED(IRQ_IXP4XX_GPIO8, "master"), - DEFINE_RES_IRQ_NAMED(IRQ_IXP4XX_GPIO7, "slave"), -}; - -static struct platform_device ixp46x_ptp = { - .name = "ptp-ixp46x", - .id = -1, - .resource = ixp46x_ptp_resources, - .num_resources = ARRAY_SIZE(ixp46x_ptp_resources), -}; - -static struct platform_device *ixp46x_devices[] __initdata = { - &ixp46x_hwrandom_device, - &ixp46x_i2c_controller, - &ixp46x_ptp, -}; - -unsigned long ixp4xx_exp_bus_size; -EXPORT_SYMBOL(ixp4xx_exp_bus_size); - -static struct platform_device_info ixp_dev_info __initdata = { - .name = "ixp4xx_crypto", - .id = 0, - .dma_mask = DMA_BIT_MASK(32), -}; - -static int __init ixp_crypto_register(void) -{ - struct platform_device *pdev; - - if (!(~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH | - IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) { - printk(KERN_ERR "ixp_crypto: No HW crypto available\n"); - return -ENODEV; - } - - pdev = platform_device_register_full(&ixp_dev_info); - if (IS_ERR(pdev)) - return PTR_ERR(pdev); - - return 0; -} - -void __init ixp4xx_sys_init(void) -{ - ixp4xx_exp_bus_size = SZ_16M; - - platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices)); - - if (IS_ENABLED(CONFIG_CRYPTO_DEV_IXP4XX)) - ixp_crypto_register(); - - if (cpu_is_ixp46x()) { - int region; - - platform_add_devices(ixp46x_devices, - ARRAY_SIZE(ixp46x_devices)); - - for (region = 0; region < 7; region++) { - if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) { - ixp4xx_exp_bus_size = SZ_32M; - break; - } - } - } - - printk("IXP4xx: Using %luMiB expansion bus window size\n", - ixp4xx_exp_bus_size >> 20); -} - -unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ; -EXPORT_SYMBOL(ixp4xx_timer_freq); - -void ixp4xx_restart(enum reboot_mode mode, const char *cmd) -{ - if (mode == REBOOT_SOFT) { - /* Jump into ROM at address 0 */ - soft_restart(0); - } else { - /* Use on-chip reset capability */ - - /* set the "key" register to enable access to - * "timer" and "enable" registers - */ - *IXP4XX_OSWK = IXP4XX_WDT_KEY; - - /* write 0 to the timer register for an immediate reset */ - *IXP4XX_OSWT = 0; - - *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE; - } -} - -#ifdef CONFIG_PCI -static int ixp4xx_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) -{ - return (dma_addr + size) > SZ_64M; -} - -static int ixp4xx_platform_notify_remove(struct device *dev) -{ - if (dev_is_pci(dev)) - dmabounce_unregister_dev(dev); - - return 0; -} -#endif - -/* - * Setup DMA mask to 64MB on PCI devices and 4 GB on all other things. - */ -static int ixp4xx_platform_notify(struct device *dev) -{ - dev->dma_mask = &dev->coherent_dma_mask; - -#ifdef CONFIG_PCI - if (dev_is_pci(dev)) { - dev->coherent_dma_mask = DMA_BIT_MASK(28); /* 64 MB */ - dmabounce_register_dev(dev, 2048, 4096, ixp4xx_needs_bounce); - return 0; - } -#endif - - dev->coherent_dma_mask = DMA_BIT_MASK(32); - return 0; -} - -int dma_set_coherent_mask(struct device *dev, u64 mask) -{ - if (dev_is_pci(dev)) - mask &= DMA_BIT_MASK(28); /* 64 MB */ - - if ((mask & DMA_BIT_MASK(28)) == DMA_BIT_MASK(28)) { - dev->coherent_dma_mask = mask; - return 0; - } - - return -EIO; /* device wanted sub-64MB mask */ -} -EXPORT_SYMBOL(dma_set_coherent_mask); - -#ifdef CONFIG_IXP4XX_INDIRECT_PCI -/* - * In the case of using indirect PCI, we simply return the actual PCI - * address and our read/write implementation use that to drive the - * access registers. If something outside of PCI is ioremap'd, we - * fallback to the default. - */ - -static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size, - unsigned int mtype, void *caller) -{ - if (!is_pci_memory(addr)) - return __arm_ioremap_caller(addr, size, mtype, caller); - - return (void __iomem *)addr; -} - -static void ixp4xx_iounmap(volatile void __iomem *addr) -{ - if (!is_pci_memory((__force u32)addr)) - __iounmap(addr); -} -#endif - -void __init ixp4xx_init_early(void) -{ - platform_notify = ixp4xx_platform_notify; -#ifdef CONFIG_PCI - platform_notify_remove = ixp4xx_platform_notify_remove; -#endif -#ifdef CONFIG_IXP4XX_INDIRECT_PCI - arch_ioremap_caller = ixp4xx_ioremap_caller; - arch_iounmap = ixp4xx_iounmap; -#endif -} diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c deleted file mode 100644 index 3c3ee9dad6d8..000000000000 --- a/arch/arm/mach-ixp4xx/gateway7001-pci.c +++ /dev/null @@ -1,61 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arch/mach-ixp4xx/gateway7001-pci.c - * - * PCI setup routines for Gateway 7001 - * - * Copyright (C) 2007 Imre Kaloz - * - * based on coyote-pci.c: - * Copyright (C) 2002 Jungo Software Technologies. - * Copyright (C) 2003 MontaVista Softwrae, Inc. - * - * Maintainer: Imre Kaloz - */ - -#include -#include -#include -#include - -#include -#include - -#include - -#include "irqs.h" - -void __init gateway7001_pci_preinit(void) -{ - irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); - - ixp4xx_pci_preinit(); -} - -static int __init gateway7001_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - if (slot == 1) - return IRQ_IXP4XX_GPIO11; - else if (slot == 2) - return IRQ_IXP4XX_GPIO10; - else return -1; -} - -struct hw_pci gateway7001_pci __initdata = { - .nr_controllers = 1, - .ops = &ixp4xx_ops, - .preinit = gateway7001_pci_preinit, - .setup = ixp4xx_setup, - .map_irq = gateway7001_map_irq, -}; - -int __init gateway7001_pci_init(void) -{ - if (machine_is_gateway7001()) - pci_common_init(&gateway7001_pci); - return 0; -} - -subsys_initcall(gateway7001_pci_init); diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c deleted file mode 100644 index 678e7dfff0e5..000000000000 --- a/arch/arm/mach-ixp4xx/gateway7001-setup.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * arch/arm/mach-ixp4xx/gateway7001-setup.c - * - * Board setup for the Gateway 7001 board - * - * Copyright (C) 2007 Imre Kaloz - * - * based on coyote-setup.c: - * Copyright (C) 2003-2005 MontaVista Software, Inc. - * - * Author: Imre Kaloz - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "irqs.h" - -static struct flash_platform_data gateway7001_flash_data = { - .map_name = "cfi_probe", - .width = 2, -}; - -static struct resource gateway7001_flash_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device gateway7001_flash = { - .name = "IXP4XX-Flash", - .id = 0, - .dev = { - .platform_data = &gateway7001_flash_data, - }, - .num_resources = 1, - .resource = &gateway7001_flash_resource, -}; - -static struct resource gateway7001_uart_resource = { - .start = IXP4XX_UART2_BASE_PHYS, - .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, - .flags = IORESOURCE_MEM, -}; - -static struct plat_serial8250_port gateway7001_uart_data[] = { - { - .mapbase = IXP4XX_UART2_BASE_PHYS, - .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET, - .irq = IRQ_IXP4XX_UART2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = IXP4XX_UART_XTAL, - }, - { }, -}; - -static struct platform_device gateway7001_uart = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = gateway7001_uart_data, - }, - .num_resources = 1, - .resource = &gateway7001_uart_resource, -}; - -static struct platform_device *gateway7001_devices[] __initdata = { - &gateway7001_flash, - &gateway7001_uart -}; - -static void __init gateway7001_init(void) -{ - ixp4xx_sys_init(); - - gateway7001_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); - gateway7001_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1; - - *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; - *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0; - - platform_add_devices(gateway7001_devices, ARRAY_SIZE(gateway7001_devices)); -} - -#ifdef CONFIG_MACH_GATEWAY7001 -MACHINE_START(GATEWAY7001, "Gateway 7001 AP") - /* Maintainer: Imre Kaloz */ - .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, - .init_irq = ixp4xx_init_irq, - .init_time = ixp4xx_timer_init, - .atag_offset = 0x100, - .init_machine = gateway7001_init, -#if defined(CONFIG_PCI) - .dma_zone_size = SZ_64M, -#endif - .restart = ixp4xx_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c deleted file mode 100644 index 07b50dfcc489..000000000000 --- a/arch/arm/mach-ixp4xx/goramo_mlr.c +++ /dev/null @@ -1,532 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Goramo MultiLink router platform code - * Copyright (C) 2006-2009 Krzysztof Halasa - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "irqs.h" - -#define SLOT_ETHA 0x0B /* IDSEL = AD21 */ -#define SLOT_ETHB 0x0C /* IDSEL = AD20 */ -#define SLOT_MPCI 0x0D /* IDSEL = AD19 */ -#define SLOT_NEC 0x0E /* IDSEL = AD18 */ - -/* GPIO lines */ -#define GPIO_SCL 0 -#define GPIO_SDA 1 -#define GPIO_STR 2 -#define GPIO_IRQ_NEC 3 -#define GPIO_IRQ_ETHA 4 -#define GPIO_IRQ_ETHB 5 -#define GPIO_HSS0_DCD_N 6 -#define GPIO_HSS1_DCD_N 7 -#define GPIO_UART0_DCD 8 -#define GPIO_UART1_DCD 9 -#define GPIO_HSS0_CTS_N 10 -#define GPIO_HSS1_CTS_N 11 -#define GPIO_IRQ_MPCI 12 -#define GPIO_HSS1_RTS_N 13 -#define GPIO_HSS0_RTS_N 14 -/* GPIO15 is not connected */ - -/* Control outputs from 74HC4094 */ -#define CONTROL_HSS0_CLK_INT 0 -#define CONTROL_HSS1_CLK_INT 1 -#define CONTROL_HSS0_DTR_N 2 -#define CONTROL_HSS1_DTR_N 3 -#define CONTROL_EXT 4 -#define CONTROL_AUTO_RESET 5 -#define CONTROL_PCI_RESET_N 6 -#define CONTROL_EEPROM_WC_N 7 - -/* offsets from start of flash ROM = 0x50000000 */ -#define CFG_ETH0_ADDRESS 0x40 /* 6 bytes */ -#define CFG_ETH1_ADDRESS 0x46 /* 6 bytes */ -#define CFG_REV 0x4C /* u32 */ -#define CFG_SDRAM_SIZE 0x50 /* u32 */ -#define CFG_SDRAM_CONF 0x54 /* u32 */ -#define CFG_SDRAM_MODE 0x58 /* u32 */ -#define CFG_SDRAM_REFRESH 0x5C /* u32 */ - -#define CFG_HW_BITS 0x60 /* u32 */ -#define CFG_HW_USB_PORTS 0x00000007 /* 0 = no NEC chip, 1-5 = ports # */ -#define CFG_HW_HAS_PCI_SLOT 0x00000008 -#define CFG_HW_HAS_ETH0 0x00000010 -#define CFG_HW_HAS_ETH1 0x00000020 -#define CFG_HW_HAS_HSS0 0x00000040 -#define CFG_HW_HAS_HSS1 0x00000080 -#define CFG_HW_HAS_UART0 0x00000100 -#define CFG_HW_HAS_UART1 0x00000200 -#define CFG_HW_HAS_EEPROM 0x00000400 - -#define FLASH_CMD_READ_ARRAY 0xFF -#define FLASH_CMD_READ_ID 0x90 -#define FLASH_SER_OFF 0x102 /* 0x81 in 16-bit mode */ - -static u32 hw_bits = 0xFFFFFFFD; /* assume all hardware present */; -static u8 control_value; - -/* - * FIXME: this is reimplementing I2C bit-bangining. Move this - * over to using driver/i2c/busses/i2c-gpio.c like all other boards - * and register proper I2C device(s) on the bus for this. (See - * other IXP4xx boards for examples.) - */ -static void set_scl(u8 value) -{ - gpio_set_value(GPIO_SCL, !!value); - udelay(3); -} - -static void set_sda(u8 value) -{ - gpio_set_value(GPIO_SDA, !!value); - udelay(3); -} - -static void set_str(u8 value) -{ - gpio_set_value(GPIO_STR, !!value); - udelay(3); -} - -static inline void set_control(int line, int value) -{ - if (value) - control_value |= (1 << line); - else - control_value &= ~(1 << line); -} - - -static void output_control(void) -{ - int i; - - gpio_direction_output(GPIO_SCL, 1); - gpio_direction_output(GPIO_SDA, 1); - - for (i = 0; i < 8; i++) { - set_scl(0); - set_sda(control_value & (0x80 >> i)); /* MSB first */ - set_scl(1); /* active edge */ - } - - set_str(1); - set_str(0); - - set_scl(0); - set_sda(1); /* Be ready for START */ - set_scl(1); -} - - -static void (*set_carrier_cb_tab[2])(void *pdev, int carrier); - -static int hss_set_clock(int port, unsigned int clock_type) -{ - int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT; - - switch (clock_type) { - case CLOCK_DEFAULT: - case CLOCK_EXT: - set_control(ctrl_int, 0); - output_control(); - return CLOCK_EXT; - - case CLOCK_INT: - set_control(ctrl_int, 1); - output_control(); - return CLOCK_INT; - - default: - return -EINVAL; - } -} - -static irqreturn_t hss_dcd_irq(int irq, void *pdev) -{ - int port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N)); - int i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N); - set_carrier_cb_tab[port](pdev, !i); - return IRQ_HANDLED; -} - - -static int hss_open(int port, void *pdev, - void (*set_carrier_cb)(void *pdev, int carrier)) -{ - int i, irq; - - if (!port) - irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N); - else - irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N); - - i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N); - set_carrier_cb(pdev, !i); - - set_carrier_cb_tab[!!port] = set_carrier_cb; - - if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) { - printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n", - irq, i); - return i; - } - - set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0); - output_control(); - gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0); - return 0; -} - -static void hss_close(int port, void *pdev) -{ - free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) : - IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev); - set_carrier_cb_tab[!!port] = NULL; /* catch bugs */ - - set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1); - output_control(); - gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1); -} - - -/* Flash memory */ -static struct flash_platform_data flash_data = { - .map_name = "cfi_probe", - .width = 2, -}; - -static struct resource flash_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device device_flash = { - .name = "IXP4XX-Flash", - .id = 0, - .dev = { .platform_data = &flash_data }, - .num_resources = 1, - .resource = &flash_resource, -}; - -/* IXP425 2 UART ports */ -static struct resource uart_resources[] = { - { - .start = IXP4XX_UART1_BASE_PHYS, - .end = IXP4XX_UART1_BASE_PHYS + 0x0fff, - .flags = IORESOURCE_MEM, - }, - { - .start = IXP4XX_UART2_BASE_PHYS, - .end = IXP4XX_UART2_BASE_PHYS + 0x0fff, - .flags = IORESOURCE_MEM, - } -}; - -static struct plat_serial8250_port uart_data[] = { - { - .mapbase = IXP4XX_UART1_BASE_PHYS, - .membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT + - REG_OFFSET, - .irq = IRQ_IXP4XX_UART1, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = IXP4XX_UART_XTAL, - }, - { - .mapbase = IXP4XX_UART2_BASE_PHYS, - .membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT + - REG_OFFSET, - .irq = IRQ_IXP4XX_UART2, - .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 2, - .uartclk = IXP4XX_UART_XTAL, - }, - { }, -}; - -static struct platform_device device_uarts = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev.platform_data = uart_data, - .num_resources = 2, - .resource = uart_resources, -}; - - -/* Built-in 10/100 Ethernet MAC interfaces */ -static struct resource eth_npeb_resources[] = { - { - .start = IXP4XX_EthB_BASE_PHYS, - .end = IXP4XX_EthB_BASE_PHYS + 0x0fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource eth_npec_resources[] = { - { - .start = IXP4XX_EthC_BASE_PHYS, - .end = IXP4XX_EthC_BASE_PHYS + 0x0fff, - .flags = IORESOURCE_MEM, - }, -}; - -static struct eth_plat_info eth_plat[] = { - { - .phy = 0, - .rxq = 3, - .txreadyq = 32, - }, { - .phy = 1, - .rxq = 4, - .txreadyq = 33, - } -}; - -static struct platform_device device_eth_tab[] = { - { - .name = "ixp4xx_eth", - .id = IXP4XX_ETH_NPEB, - .dev.platform_data = eth_plat, - .num_resources = ARRAY_SIZE(eth_npeb_resources), - .resource = eth_npeb_resources, - }, { - .name = "ixp4xx_eth", - .id = IXP4XX_ETH_NPEC, - .dev.platform_data = eth_plat + 1, - .num_resources = ARRAY_SIZE(eth_npec_resources), - .resource = eth_npec_resources, - } -}; - - -/* IXP425 2 synchronous serial ports */ -static struct hss_plat_info hss_plat[] = { - { - .set_clock = hss_set_clock, - .open = hss_open, - .close = hss_close, - .txreadyq = 34, - }, { - .set_clock = hss_set_clock, - .open = hss_open, - .close = hss_close, - .txreadyq = 35, - } -}; - -static struct platform_device device_hss_tab[] = { - { - .name = "ixp4xx_hss", - .id = 0, - .dev.platform_data = hss_plat, - }, { - .name = "ixp4xx_hss", - .id = 1, - .dev.platform_data = hss_plat + 1, - } -}; - - -static struct platform_device *device_tab[7] __initdata = { - &device_flash, /* index 0 */ -}; - -static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr) -{ -#ifdef __ARMEB__ - return __raw_readb(flash + addr); -#else - return __raw_readb(flash + (addr ^ 3)); -#endif -} - -static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr) -{ -#ifdef __ARMEB__ - return __raw_readw(flash + addr); -#else - return __raw_readw(flash + (addr ^ 2)); -#endif -} - -static void __init gmlr_init(void) -{ - u8 __iomem *flash; - int i, devices = 1; /* flash */ - - ixp4xx_sys_init(); - - if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL) - printk(KERN_ERR "goramo-mlr: unable to access system" - " configuration data\n"); - else { - system_rev = __raw_readl(flash + CFG_REV); - hw_bits = __raw_readl(flash + CFG_HW_BITS); - - for (i = 0; i < ETH_ALEN; i++) { - eth_plat[0].hwaddr[i] = - flash_readb(flash, CFG_ETH0_ADDRESS + i); - eth_plat[1].hwaddr[i] = - flash_readb(flash, CFG_ETH1_ADDRESS + i); - } - - __raw_writew(FLASH_CMD_READ_ID, flash); - system_serial_high = flash_readw(flash, FLASH_SER_OFF); - system_serial_high <<= 16; - system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2); - system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4); - system_serial_low <<= 16; - system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6); - __raw_writew(FLASH_CMD_READ_ARRAY, flash); - - iounmap(flash); - } - - switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) { - case CFG_HW_HAS_UART0: - memset(&uart_data[1], 0, sizeof(uart_data[1])); - device_uarts.num_resources = 1; - break; - - case CFG_HW_HAS_UART1: - device_uarts.dev.platform_data = &uart_data[1]; - device_uarts.resource = &uart_resources[1]; - device_uarts.num_resources = 1; - break; - } - if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) - device_tab[devices++] = &device_uarts; /* max index 1 */ - - if (hw_bits & CFG_HW_HAS_ETH0) - device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */ - if (hw_bits & CFG_HW_HAS_ETH1) - device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */ - - if (hw_bits & CFG_HW_HAS_HSS0) - device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */ - if (hw_bits & CFG_HW_HAS_HSS1) - device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */ - - hss_plat[0].timer_freq = ixp4xx_timer_freq; - hss_plat[1].timer_freq = ixp4xx_timer_freq; - - gpio_request(GPIO_SCL, "SCL/clock"); - gpio_request(GPIO_SDA, "SDA/data"); - gpio_request(GPIO_STR, "strobe"); - gpio_request(GPIO_HSS0_RTS_N, "HSS0 RTS"); - gpio_request(GPIO_HSS1_RTS_N, "HSS1 RTS"); - gpio_request(GPIO_HSS0_DCD_N, "HSS0 DCD"); - gpio_request(GPIO_HSS1_DCD_N, "HSS1 DCD"); - - gpio_direction_output(GPIO_SCL, 1); - gpio_direction_output(GPIO_SDA, 1); - gpio_direction_output(GPIO_STR, 0); - gpio_direction_output(GPIO_HSS0_RTS_N, 1); - gpio_direction_output(GPIO_HSS1_RTS_N, 1); - gpio_direction_input(GPIO_HSS0_DCD_N); - gpio_direction_input(GPIO_HSS1_DCD_N); - irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); - irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); - - set_control(CONTROL_HSS0_DTR_N, 1); - set_control(CONTROL_HSS1_DTR_N, 1); - set_control(CONTROL_EEPROM_WC_N, 1); - set_control(CONTROL_PCI_RESET_N, 1); - output_control(); - - msleep(1); /* Wait for PCI devices to initialize */ - - flash_resource.start = IXP4XX_EXP_BUS_BASE(0); - flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1; - - platform_add_devices(device_tab, devices); -} - - -#ifdef CONFIG_PCI -static void __init gmlr_pci_preinit(void) -{ - irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); - irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); - ixp4xx_pci_preinit(); -} - -static void __init gmlr_pci_postinit(void) -{ - if ((hw_bits & CFG_HW_USB_PORTS) >= 2 && - (hw_bits & CFG_HW_USB_PORTS) < 5) { - /* need to adjust number of USB ports on NEC chip */ - u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0; - if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) { - value &= ~7; - value |= (hw_bits & CFG_HW_USB_PORTS); - ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value); - } - } -} - -static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - switch(slot) { - case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA); - case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB); - case SLOT_NEC: return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC); - default: return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI); - } -} - -static struct hw_pci gmlr_hw_pci __initdata = { - .nr_controllers = 1, - .ops = &ixp4xx_ops, - .preinit = gmlr_pci_preinit, - .postinit = gmlr_pci_postinit, - .setup = ixp4xx_setup, - .map_irq = gmlr_map_irq, -}; - -static int __init gmlr_pci_init(void) -{ - if (machine_is_goramo_mlr() && - (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT))) - pci_common_init(&gmlr_hw_pci); - return 0; -} - -subsys_initcall(gmlr_pci_init); -#endif /* CONFIG_PCI */ - - -MACHINE_START(GORAMO_MLR, "MultiLink") - /* Maintainer: Krzysztof Halasa */ - .map_io = ixp4xx_map_io, - .init_early = ixp4xx_init_early, - .init_irq = ixp4xx_init_irq, - .init_time = ixp4xx_timer_init, - .atag_offset = 0x100, - .init_machine = gmlr_init, -#if defined(CONFIG_PCI) - .dma_zone_size = SZ_64M, -#endif - .restart = ixp4xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h deleted file mode 100644 index b2b7301ce503..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/hardware.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ixp4xx/include/mach/hardware.h - * - * Copyright (C) 2002 Intel Corporation. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - */ - -/* - * Hardware definitions for IXP4xx based systems - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#define __ASM_ARCH_HARDWARE_H__ - -#ifdef CONFIG_IXP4XX_INDIRECT_PCI -#define PCIBIOS_MAX_MEM 0x4FFFFFFF -#else -#define PCIBIOS_MAX_MEM 0x4BFFFFFF -#endif - -/* Register locations and bits */ -#include "ixp4xx-regs.h" - -#ifndef __ASSEMBLER__ -#include -#endif - -/* Platform helper functions and definitions */ -#include "platform.h" - -#endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h deleted file mode 100644 index 014cf6dcaf8b..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ /dev/null @@ -1,545 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ixp4xx/include/mach/io.h - * - * Author: Deepak Saxena - * - * Copyright (C) 2002-2005 MontaVista Software, Inc. - */ - -#ifndef __ASM_ARM_ARCH_IO_H -#define __ASM_ARM_ARCH_IO_H - -#include - -#include - -extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); -extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); - - -/* - * IXP4xx provides two methods of accessing PCI memory space: - * - * 1) A direct mapped window from 0x48000000 to 0x4BFFFFFF (64MB). - * To access PCI via this space, we simply ioremap() the BAR - * into the kernel and we can use the standard read[bwl]/write[bwl] - * macros. This is the preffered method due to speed but it - * limits the system to just 64MB of PCI memory. This can be - * problematic if using video cards and other memory-heavy targets. - * - * 2) If > 64MB of memory space is required, the IXP4xx can use indirect - * registers to access the whole 4 GB of PCI memory space (as we do below - * for I/O transactions). This allows currently for up to 1 GB (0x10000000 - * to 0x4FFFFFFF) of memory on the bus. The disadvantage of this is that - * every PCI access requires three local register accesses plus a spinlock, - * but in some cases the performance hit is acceptable. In addition, you - * cannot mmap() PCI devices in this case. - */ -#ifdef CONFIG_IXP4XX_INDIRECT_PCI - -/* - * In the case of using indirect PCI, we simply return the actual PCI - * address and our read/write implementation use that to drive the - * access registers. If something outside of PCI is ioremap'd, we - * fallback to the default. - */ - -extern unsigned long pcibios_min_mem; -static inline int is_pci_memory(u32 addr) -{ - return (addr >= pcibios_min_mem) && (addr <= 0x4FFFFFFF); -} - -#define writeb(v, p) __indirect_writeb(v, p) -#define writew(v, p) __indirect_writew(v, p) -#define writel(v, p) __indirect_writel(v, p) - -#define writeb_relaxed(v, p) __indirect_writeb(v, p) -#define writew_relaxed(v, p) __indirect_writew(v, p) -#define writel_relaxed(v, p) __indirect_writel(v, p) - -#define writesb(p, v, l) __indirect_writesb(p, v, l) -#define writesw(p, v, l) __indirect_writesw(p, v, l) -#define writesl(p, v, l) __indirect_writesl(p, v, l) - -#define readb(p) __indirect_readb(p) -#define readw(p) __indirect_readw(p) -#define readl(p) __indirect_readl(p) - -#define readb_relaxed(p) __indirect_readb(p) -#define readw_relaxed(p) __indirect_readw(p) -#define readl_relaxed(p) __indirect_readl(p) - -#define readsb(p, v, l) __indirect_readsb(p, v, l) -#define readsw(p, v, l) __indirect_readsw(p, v, l) -#define readsl(p, v, l) __indirect_readsl(p, v, l) - -static inline void __indirect_writeb(u8 value, volatile void __iomem *p) -{ - u32 addr = (u32)p; - u32 n, byte_enables, data; - - if (!is_pci_memory(addr)) { - __raw_writeb(value, p); - return; - } - - n = addr % 4; - byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; - data = value << (8*n); - ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); -} - -static inline void __indirect_writesb(volatile void __iomem *bus_addr, - const void *p, int count) -{ - const u8 *vaddr = p; - - while (count--) - writeb(*vaddr++, bus_addr); -} - -static inline void __indirect_writew(u16 value, volatile void __iomem *p) -{ - u32 addr = (u32)p; - u32 n, byte_enables, data; - - if (!is_pci_memory(addr)) { - __raw_writew(value, p); - return; - } - - n = addr % 4; - byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; - data = value << (8*n); - ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data); -} - -static inline void __indirect_writesw(volatile void __iomem *bus_addr, - const void *p, int count) -{ - const u16 *vaddr = p; - - while (count--) - writew(*vaddr++, bus_addr); -} - -static inline void __indirect_writel(u32 value, volatile void __iomem *p) -{ - u32 addr = (__force u32)p; - - if (!is_pci_memory(addr)) { - __raw_writel(value, p); - return; - } - - ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value); -} - -static inline void __indirect_writesl(volatile void __iomem *bus_addr, - const void *p, int count) -{ - const u32 *vaddr = p; - while (count--) - writel(*vaddr++, bus_addr); -} - -static inline u8 __indirect_readb(const volatile void __iomem *p) -{ - u32 addr = (u32)p; - u32 n, byte_enables, data; - - if (!is_pci_memory(addr)) - return __raw_readb(p); - - n = addr % 4; - byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; - if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) - return 0xff; - - return data >> (8*n); -} - -static inline void __indirect_readsb(const volatile void __iomem *bus_addr, - void *p, u32 count) -{ - u8 *vaddr = p; - - while (count--) - *vaddr++ = readb(bus_addr); -} - -static inline u16 __indirect_readw(const volatile void __iomem *p) -{ - u32 addr = (u32)p; - u32 n, byte_enables, data; - - if (!is_pci_memory(addr)) - return __raw_readw(p); - - n = addr % 4; - byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; - if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data)) - return 0xffff; - - return data>>(8*n); -} - -static inline void __indirect_readsw(const volatile void __iomem *bus_addr, - void *p, u32 count) -{ - u16 *vaddr = p; - - while (count--) - *vaddr++ = readw(bus_addr); -} - -static inline u32 __indirect_readl(const volatile void __iomem *p) -{ - u32 addr = (__force u32)p; - u32 data; - - if (!is_pci_memory(addr)) - return __raw_readl(p); - - if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data)) - return 0xffffffff; - - return data; -} - -static inline void __indirect_readsl(const volatile void __iomem *bus_addr, - void *p, u32 count) -{ - u32 *vaddr = p; - - while (count--) - *vaddr++ = readl(bus_addr); -} - - -/* - * We can use the built-in functions b/c they end up calling writeb/readb - */ -#define memset_io(c,v,l) _memset_io((c),(v),(l)) -#define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l)) -#define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l)) - -#endif /* CONFIG_IXP4XX_INDIRECT_PCI */ - -#ifndef CONFIG_PCI - -#define __io(v) __typesafe_io(v) - -#else - -/* - * IXP4xx does not have a transparent cpu -> PCI I/O translation - * window. Instead, it has a set of registers that must be tweaked - * with the proper byte lanes, command types, and address for the - * transaction. This means that we need to override the default - * I/O functions. - */ - -#define outb outb -static inline void outb(u8 value, u32 addr) -{ - u32 n, byte_enables, data; - n = addr % 4; - byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; - data = value << (8*n); - ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); -} - -#define outsb outsb -static inline void outsb(u32 io_addr, const void *p, u32 count) -{ - const u8 *vaddr = p; - - while (count--) - outb(*vaddr++, io_addr); -} - -#define outw outw -static inline void outw(u16 value, u32 addr) -{ - u32 n, byte_enables, data; - n = addr % 4; - byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; - data = value << (8*n); - ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data); -} - -#define outsw outsw -static inline void outsw(u32 io_addr, const void *p, u32 count) -{ - const u16 *vaddr = p; - while (count--) - outw(cpu_to_le16(*vaddr++), io_addr); -} - -#define outl outl -static inline void outl(u32 value, u32 addr) -{ - ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value); -} - -#define outsl outsl -static inline void outsl(u32 io_addr, const void *p, u32 count) -{ - const u32 *vaddr = p; - while (count--) - outl(cpu_to_le32(*vaddr++), io_addr); -} - -#define inb inb -static inline u8 inb(u32 addr) -{ - u32 n, byte_enables, data; - n = addr % 4; - byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL; - if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) - return 0xff; - - return data >> (8*n); -} - -#define insb insb -static inline void insb(u32 io_addr, void *p, u32 count) -{ - u8 *vaddr = p; - while (count--) - *vaddr++ = inb(io_addr); -} - -#define inw inw -static inline u16 inw(u32 addr) -{ - u32 n, byte_enables, data; - n = addr % 4; - byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL; - if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data)) - return 0xffff; - - return data>>(8*n); -} - -#define insw insw -static inline void insw(u32 io_addr, void *p, u32 count) -{ - u16 *vaddr = p; - while (count--) - *vaddr++ = le16_to_cpu(inw(io_addr)); -} - -#define inl inl -static inline u32 inl(u32 addr) -{ - u32 data; - if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data)) - return 0xffffffff; - - return data; -} - -#define insl insl -static inline void insl(u32 io_addr, void *p, u32 count) -{ - u32 *vaddr = p; - while (count--) - *vaddr++ = le32_to_cpu(inl(io_addr)); -} - -#define PIO_OFFSET 0x10000UL -#define PIO_MASK 0x0ffffUL - -#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ - ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) - -#define ioread8(p) ioread8(p) -static inline u8 ioread8(const void __iomem *addr) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - return (unsigned int)inb(port & PIO_MASK); - else -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - return (unsigned int)__raw_readb(addr); -#else - return (unsigned int)__indirect_readb(addr); -#endif -} - -#define ioread8_rep(p, v, c) ioread8_rep(p, v, c) -static inline void ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - insb(port & PIO_MASK, vaddr, count); - else -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_readsb(addr, vaddr, count); -#else - __indirect_readsb(addr, vaddr, count); -#endif -} - -#define ioread16(p) ioread16(p) -static inline u16 ioread16(const void __iomem *addr) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - return (unsigned int)inw(port & PIO_MASK); - else -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - return le16_to_cpu((__force __le16)__raw_readw(addr)); -#else - return (unsigned int)__indirect_readw(addr); -#endif -} - -#define ioread16_rep(p, v, c) ioread16_rep(p, v, c) -static inline void ioread16_rep(const void __iomem *addr, void *vaddr, - u32 count) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - insw(port & PIO_MASK, vaddr, count); - else -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_readsw(addr, vaddr, count); -#else - __indirect_readsw(addr, vaddr, count); -#endif -} - -#define ioread32(p) ioread32(p) -static inline u32 ioread32(const void __iomem *addr) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - return (unsigned int)inl(port & PIO_MASK); - else { -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - return le32_to_cpu((__force __le32)__raw_readl(addr)); -#else - return (unsigned int)__indirect_readl(addr); -#endif - } -} - -#define ioread32_rep(p, v, c) ioread32_rep(p, v, c) -static inline void ioread32_rep(const void __iomem *addr, void *vaddr, - u32 count) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - insl(port & PIO_MASK, vaddr, count); - else -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_readsl(addr, vaddr, count); -#else - __indirect_readsl(addr, vaddr, count); -#endif -} - -#define iowrite8(v, p) iowrite8(v, p) -static inline void iowrite8(u8 value, void __iomem *addr) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - outb(value, port & PIO_MASK); - else -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writeb(value, addr); -#else - __indirect_writeb(value, addr); -#endif -} - -#define iowrite8_rep(p, v, c) iowrite8_rep(p, v, c) -static inline void iowrite8_rep(void __iomem *addr, const void *vaddr, - u32 count) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - outsb(port & PIO_MASK, vaddr, count); - else -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writesb(addr, vaddr, count); -#else - __indirect_writesb(addr, vaddr, count); -#endif -} - -#define iowrite16(v, p) iowrite16(v, p) -static inline void iowrite16(u16 value, void __iomem *addr) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - outw(value, port & PIO_MASK); - else -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writew(cpu_to_le16(value), addr); -#else - __indirect_writew(value, addr); -#endif -} - -#define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c) -static inline void iowrite16_rep(void __iomem *addr, const void *vaddr, - u32 count) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - outsw(port & PIO_MASK, vaddr, count); - else -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writesw(addr, vaddr, count); -#else - __indirect_writesw(addr, vaddr, count); -#endif -} - -#define iowrite32(v, p) iowrite32(v, p) -static inline void iowrite32(u32 value, void __iomem *addr) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - outl(value, port & PIO_MASK); - else -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writel((u32 __force)cpu_to_le32(value), addr); -#else - __indirect_writel(value, addr); -#endif -} - -#define iowrite32_rep(p, v, c) iowrite32_rep(p, v, c) -static inline void iowrite32_rep(void __iomem *addr, const void *vaddr, - u32 count) -{ - unsigned long port = (unsigned long __force)addr; - if (__is_io_address(port)) - outsl(port & PIO_MASK, vaddr, count); - else -#ifndef CONFIG_IXP4XX_INDIRECT_PCI - __raw_writesl(addr, vaddr, count); -#else - __indirect_writesl(addr, vaddr, count); -#endif -} - -#define ioport_map(port, nr) ioport_map(port, nr) -static inline void __iomem *ioport_map(unsigned long port, unsigned int nr) -{ - return ((void __iomem*)((port) + PIO_OFFSET)); -} -#define ioport_unmap(addr) ioport_unmap(addr) -static inline void ioport_unmap(void __iomem *addr) -{ -} -#endif /* CONFIG_PCI */ - -#endif /* __ASM_ARM_ARCH_IO_H */ diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h deleted file mode 100644 index 74e63d4531aa..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +++ /dev/null @@ -1,303 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h - * - * Register definitions for IXP4xx chipset. This file contains - * register location and bit definitions only. Platform specific - * definitions and helper function declarations are in platform.h - * and machine-name.h. - * - * Copyright (C) 2002 Intel Corporation. - * Copyright (C) 2003-2004 MontaVista Software, Inc. - */ - -#ifndef _ASM_ARM_IXP4XX_H_ -#define _ASM_ARM_IXP4XX_H_ - -/* - * IXP4xx Linux Memory Map: - * - * Phy Size Virt Description - * ========================================================================= - * - * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM - * - * 0x48000000 0x04000000 ioremap'd PCI Memory Space - * - * 0x50000000 0x10000000 ioremap'd EXP BUS - * - * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals - * - * 0xC0000000 0x00001000 0xFEF13000 PCI CFG - * - * 0xC4000000 0x00001000 0xFEF14000 EXP CFG - * - * 0x60000000 0x00004000 0xFEF15000 QMgr - */ - -/* - * Queue Manager - */ -#define IXP4XX_QMGR_BASE_PHYS 0x60000000 - -/* - * Peripheral space, including debug UART. Must be section-aligned so that - * it can be used with the low-level debug code. - */ -#define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 -#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEC00000) -#define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 - -/* - * PCI Config registers - */ -#define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 -#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEC13000) -#define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 - -/* - * Expansion BUS Configuration registers - */ -#define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 -#define IXP4XX_EXP_CFG_BASE_VIRT 0xFEC14000 -#define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 - -#define IXP4XX_EXP_CS0_OFFSET 0x00 -#define IXP4XX_EXP_CS1_OFFSET 0x04 -#define IXP4XX_EXP_CS2_OFFSET 0x08 -#define IXP4XX_EXP_CS3_OFFSET 0x0C -#define IXP4XX_EXP_CS4_OFFSET 0x10 -#define IXP4XX_EXP_CS5_OFFSET 0x14 -#define IXP4XX_EXP_CS6_OFFSET 0x18 -#define IXP4XX_EXP_CS7_OFFSET 0x1C -#define IXP4XX_EXP_CFG0_OFFSET 0x20 -#define IXP4XX_EXP_CFG1_OFFSET 0x24 -#define IXP4XX_EXP_CFG2_OFFSET 0x28 -#define IXP4XX_EXP_CFG3_OFFSET 0x2C - -/* - * Expansion Bus Controller registers. - */ -#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) - -#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) -#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) -#define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) -#define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET) -#define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET) -#define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET) -#define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET) -#define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET) - -#define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) -#define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) -#define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) -#define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET) - - -/* - * Peripheral Space Register Region Base Addresses - */ -#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000) -#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000) -#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000) -#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) -#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) -#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) -#define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000) -#define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000) -#define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000) -#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) -#define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) -#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) -/* ixp46X only */ -#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000) -#define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000) -#define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000) -#define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000) -#define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000) -#define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000) -#define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000) - - -/* The UART is explicitly put in the beginning of fixmap */ -#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) -#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) -#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) -#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) -#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) -#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) -#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) -#define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) -#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) -/* ixp46X only */ -#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000) -#define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000) -#define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000) -#define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000) -#define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000) -#define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000) -#define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000) - -/* - * Constants to make it easy to access Timer Control/Status registers - */ -#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */ -#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ -#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ -#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ -#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ -#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */ -#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */ -#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */ -#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */ - -/* - * Operating System Timer Register Definitions. - */ - -#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x))) - -#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET) -#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET) -#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET) -#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET) -#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET) -#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET) -#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET) -#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET) -#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET) - -/* - * Timer register values and bit definitions - */ -#define IXP4XX_OST_ENABLE 0x00000001 -#define IXP4XX_OST_ONE_SHOT 0x00000002 -/* Low order bits of reload value ignored */ -#define IXP4XX_OST_RELOAD_MASK 0x00000003 -#define IXP4XX_OST_DISABLED 0x00000000 -#define IXP4XX_OSST_TIMER_1_PEND 0x00000001 -#define IXP4XX_OSST_TIMER_2_PEND 0x00000002 -#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004 -#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008 -#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010 - -#define IXP4XX_WDT_KEY 0x0000482E - -#define IXP4XX_WDT_RESET_ENABLE 0x00000001 -#define IXP4XX_WDT_IRQ_ENABLE 0x00000002 -#define IXP4XX_WDT_COUNT_ENABLE 0x00000004 - - -/* - * Constants to make it easy to access PCI Control/Status registers - */ -#define PCI_NP_AD_OFFSET 0x00 -#define PCI_NP_CBE_OFFSET 0x04 -#define PCI_NP_WDATA_OFFSET 0x08 -#define PCI_NP_RDATA_OFFSET 0x0c -#define PCI_CRP_AD_CBE_OFFSET 0x10 -#define PCI_CRP_WDATA_OFFSET 0x14 -#define PCI_CRP_RDATA_OFFSET 0x18 -#define PCI_CSR_OFFSET 0x1c -#define PCI_ISR_OFFSET 0x20 -#define PCI_INTEN_OFFSET 0x24 -#define PCI_DMACTRL_OFFSET 0x28 -#define PCI_AHBMEMBASE_OFFSET 0x2c -#define PCI_AHBIOBASE_OFFSET 0x30 -#define PCI_PCIMEMBASE_OFFSET 0x34 -#define PCI_AHBDOORBELL_OFFSET 0x38 -#define PCI_PCIDOORBELL_OFFSET 0x3C -#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 -#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 -#define PCI_ATPDMA0_LENADDR_OFFSET 0x48 -#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C -#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 -#define PCI_ATPDMA1_LENADDR_OFFSET 0x54 - -/* - * PCI Control/Status Registers - */ -#define _IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) - -#define PCI_NP_AD _IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET) -#define PCI_NP_CBE _IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET) -#define PCI_NP_WDATA _IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET) -#define PCI_NP_RDATA _IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET) -#define PCI_CRP_AD_CBE _IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) -#define PCI_CRP_WDATA _IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET) -#define PCI_CRP_RDATA _IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET) -#define PCI_CSR _IXP4XX_PCI_CSR(PCI_CSR_OFFSET) -#define PCI_ISR _IXP4XX_PCI_CSR(PCI_ISR_OFFSET) -#define PCI_INTEN _IXP4XX_PCI_CSR(PCI_INTEN_OFFSET) -#define PCI_DMACTRL _IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET) -#define PCI_AHBMEMBASE _IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET) -#define PCI_AHBIOBASE _IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET) -#define PCI_PCIMEMBASE _IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET) -#define PCI_AHBDOORBELL _IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET) -#define PCI_PCIDOORBELL _IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET) -#define PCI_ATPDMA0_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) -#define PCI_ATPDMA0_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) -#define PCI_ATPDMA0_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) -#define PCI_ATPDMA1_AHBADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) -#define PCI_ATPDMA1_PCIADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) -#define PCI_ATPDMA1_LENADDR _IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) - -/* - * PCI register values and bit definitions - */ - -/* CSR bit definitions */ -#define PCI_CSR_HOST 0x00000001 -#define PCI_CSR_ARBEN 0x00000002 -#define PCI_CSR_ADS 0x00000004 -#define PCI_CSR_PDS 0x00000008 -#define PCI_CSR_ABE 0x00000010 -#define PCI_CSR_DBT 0x00000020 -#define PCI_CSR_ASE 0x00000100 -#define PCI_CSR_IC 0x00008000 - -/* ISR (Interrupt status) Register bit definitions */ -#define PCI_ISR_PSE 0x00000001 -#define PCI_ISR_PFE 0x00000002 -#define PCI_ISR_PPE 0x00000004 -#define PCI_ISR_AHBE 0x00000008 -#define PCI_ISR_APDC 0x00000010 -#define PCI_ISR_PADC 0x00000020 -#define PCI_ISR_ADB 0x00000040 -#define PCI_ISR_PDB 0x00000080 - -/* INTEN (Interrupt Enable) Register bit definitions */ -#define PCI_INTEN_PSE 0x00000001 -#define PCI_INTEN_PFE 0x00000002 -#define PCI_INTEN_PPE 0x00000004 -#define PCI_INTEN_AHBE 0x00000008 -#define PCI_INTEN_APDC 0x00000010 -#define PCI_INTEN_PADC 0x00000020 -#define PCI_INTEN_ADB 0x00000040 -#define PCI_INTEN_PDB 0x00000080 - -/* - * Shift value for byte enable on NP cmd/byte enable register - */ -#define IXP4XX_PCI_NP_CBE_BESL 4 - -/* - * PCI commands supported by NP access unit - */ -#define NP_CMD_IOREAD 0x2 -#define NP_CMD_IOWRITE 0x3 -#define NP_CMD_CONFIGREAD 0xa -#define NP_CMD_CONFIGWRITE 0xb -#define NP_CMD_MEMREAD 0x6 -#define NP_CMD_MEMWRITE 0x7 - -/* - * Constants for CRP access into local config space - */ -#define CRP_AD_CBE_BESL 20 -#define CRP_AD_CBE_WRITE 0x00010000 - -#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ - -#endif diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h deleted file mode 100644 index d8b4df96db08..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/platform.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/mach-ixp4xx/include/mach/platform.h - * - * Constants and functions that are useful to IXP4xx platform-specific code - * and device drivers. - * - * Copyright (C) 2004 MontaVista Software, Inc. - */ - -#ifndef __ASM_ARCH_HARDWARE_H__ -#error "Do not include this directly, instead #include " -#endif - -#ifndef __ASSEMBLY__ - -#include -#include - -#include - -#ifndef __ARMEB__ -#define REG_OFFSET 0 -#else -#define REG_OFFSET 3 -#endif - -/* - * Expansion bus memory regions - */ -#define IXP4XX_EXP_BUS_BASE_PHYS (0x50000000) - -/* - * The expansion bus on the IXP4xx can be configured for either 16 or - * 32MB windows and the CS offset for each region changes based on the - * current configuration. This means that we cannot simply hardcode - * each offset. ixp4xx_sys_init() looks at the expansion bus configuration - * as setup by the bootloader to determine our window size. - */ -extern unsigned long ixp4xx_exp_bus_size; - -#define IXP4XX_EXP_BUS_BASE(region)\ - (IXP4XX_EXP_BUS_BASE_PHYS + ((region) * ixp4xx_exp_bus_size)) - -#define IXP4XX_EXP_BUS_END(region)\ - (IXP4XX_EXP_BUS_BASE(region) + ixp4xx_exp_bus_size - 1) - -/* Those macros can be used to adjust timing and configure - * other features for each region. - */ - -#define IXP4XX_EXP_BUS_RECOVERY_T(x) (((x) & 0x0f) << 16) -#define IXP4XX_EXP_BUS_HOLD_T(x) (((x) & 0x03) << 20) -#define IXP4XX_EXP_BUS_STROBE_T(x) (((x) & 0x0f) << 22) -#define IXP4XX_EXP_BUS_SETUP_T(x) (((x) & 0x03) << 26) -#define IXP4XX_EXP_BUS_ADDR_T(x) (((x) & 0x03) << 28) -#define IXP4XX_EXP_BUS_SIZE(x) (((x) & 0x0f) << 10) -#define IXP4XX_EXP_BUS_CYCLES(x) (((x) & 0x03) << 14) - -#define IXP4XX_EXP_BUS_CS_EN (1L << 31) -#define IXP4XX_EXP_BUS_BYTE_RD16 (1L << 6) -#define IXP4XX_EXP_BUS_HRDY_POL (1L << 5) -#define IXP4XX_EXP_BUS_MUX_EN (1L << 4) -#define IXP4XX_EXP_BUS_SPLT_EN (1L << 3) -#define IXP4XX_EXP_BUS_WR_EN (1L << 1) -#define IXP4XX_EXP_BUS_BYTE_EN (1L << 0) - -#define IXP4XX_EXP_BUS_CYCLES_INTEL 0x00 -#define IXP4XX_EXP_BUS_CYCLES_MOTOROLA 0x01 -#define IXP4XX_EXP_BUS_CYCLES_HPI 0x02 - -#define IXP4XX_FLASH_WRITABLE (0x2) -#define IXP4XX_FLASH_DEFAULT (0xbcd23c40) -#define IXP4XX_FLASH_WRITE (0xbcd23c42) - -/* - * Clock Speed Definitions. - */ -#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66MHzi APB BUS */ -#define IXP4XX_UART_XTAL 14745600 - -/* - * Frequency of clock used for primary clocksource - */ -extern unsigned long ixp4xx_timer_freq; - -/* - * Functions used by platform-level setup code - */ -extern void ixp4xx_map_io(void); -extern void ixp4xx_init_early(void); -extern void ixp4xx_init_irq(void); -extern void ixp4xx_sys_init(void); -extern void ixp4xx_timer_init(void); -extern void ixp4xx_restart(enum reboot_mode, const char *); -extern void ixp4xx_pci_preinit(void); -struct pci_sys_data; -extern int ixp4xx_setup(int nr, struct pci_sys_data *sys); -extern struct pci_ops ixp4xx_ops; - -#endif // __ASSEMBLY__ - diff --git a/arch/arm/mach-ixp4xx/include/mach/udc.h b/arch/arm/mach-ixp4xx/include/mach/udc.h deleted file mode 100644 index 7bd8b96c8843..000000000000 --- a/arch/arm/mach-ixp4xx/include/mach/udc.h +++ /dev/null @@ -1,8 +0,0 @@ -/* - * arch/arm/mach-ixp4xx/include/mach/udc.h - * - */ -#include - -extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info); - diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h index 9e08b270cfc7..09e7663e6a55 100644 --- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h +++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h @@ -9,10 +9,12 @@ #ifndef _ARCH_UNCOMPRESS_H_ #define _ARCH_UNCOMPRESS_H_ -#include "ixp4xx-regs.h" #include #include +#define IXP4XX_UART1_BASE_PHYS 0xc8000000 +#define IXP4XX_UART2_BASE_PHYS 0xc8001000 + #define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE) volatile u32* uart_base; diff --git a/arch/arm/mach-ixp4xx/irqs.h b/arch/arm/mach-ixp4xx/irqs.h deleted file mode 100644 index a3e8d6408c56..000000000000 --- a/arch/arm/mach-ixp4xx/irqs.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * arch/arm/mach-ixp4xx/include/mach/irqs.h - * - * IRQ definitions for IXP4XX based systems - * - * Copyright (C) 2002 Intel Corporation. - * Copyright (C) 2003 MontaVista Software, Inc. - */ - -#ifndef _ARCH_IXP4XX_IRQS_H_ -#define _ARCH_IXP4XX_IRQS_H_ - -#define IRQ_IXP4XX_BASE 16 - -#define IRQ_IXP4XX_NPEA (IRQ_IXP4XX_BASE + 0) -#define IRQ_IXP4XX_NPEB (IRQ_IXP4XX_BASE + 1) -#define IRQ_IXP4XX_NPEC (IRQ_IXP4XX_BASE + 2) -#define IRQ_IXP4XX_QM1 (IRQ_IXP4XX_BASE + 3) -#define IRQ_IXP4XX_QM2 (IRQ_IXP4XX_BASE + 4) -#define IRQ_IXP4XX_TIMER1 (IRQ_IXP4XX_BASE + 5) -#define IRQ_IXP4XX_GPIO0 (IRQ_IXP4XX_BASE + 6) -#define IRQ_IXP4XX_GPIO1 (IRQ_IXP4XX_BASE + 7) -#define IRQ_IXP4XX_PCI_INT (IRQ_IXP4XX_BASE + 8) -#define IRQ_IXP4XX_PCI_DMA1 (IRQ_IXP4XX_BASE + 9) -#define IRQ_IXP4XX_PCI_DMA2 (IRQ_IXP4XX_BASE + 10) -#define IRQ_IXP4XX_TIMER2 (IRQ_IXP4XX_BASE + 11) -#define IRQ_IXP4XX_USB (IRQ_IXP4XX_BASE + 12) -#define IRQ_IXP4XX_UART2 (IRQ_IXP4XX_BASE + 13) -#define IRQ_IXP4XX_TIMESTAMP (IRQ_IXP4XX_BASE + 14) -#define IRQ_IXP4XX_UART1 (IRQ_IXP4XX_BASE + 15) -#define IRQ_IXP4XX_WDOG (IRQ_IXP4XX_BASE + 16) -#define IRQ_IXP4XX_AHB_PMU (IRQ_IXP4XX_BASE + 17) -#define IRQ_IXP4XX_XSCALE_PMU (IRQ_IXP4XX_BASE + 18) -#define IRQ_IXP4XX_GPIO2 (IRQ_IXP4XX_BASE + 19) -#define IRQ_IXP4XX_GPIO3 (IRQ_IXP4XX_BASE + 20) -#define IRQ_IXP4XX_GPIO4 (IRQ_IXP4XX_BASE + 21) -#define IRQ_IXP4XX_GPIO5 (IRQ_IXP4XX_BASE + 22) -#define IRQ_IXP4XX_GPIO6 (IRQ_IXP4XX_BASE + 23) -#define IRQ_IXP4XX_GPIO7 (IRQ_IXP4XX_BASE + 24) -#define IRQ_IXP4XX_GPIO8 (IRQ_IXP4XX_BASE + 25) -#define IRQ_IXP4XX_GPIO9 (IRQ_IXP4XX_BASE + 26) -#define IRQ_IXP4XX_GPIO10 (IRQ_IXP4XX_BASE + 27) -#define IRQ_IXP4XX_GPIO11 (IRQ_IXP4XX_BASE + 28) -#define IRQ_IXP4XX_GPIO12 (IRQ_IXP4XX_BASE + 29) -#define IRQ_IXP4XX_SW_INT1 (IRQ_IXP4XX_BASE + 30) -#define IRQ_IXP4XX_SW_INT2 (IRQ_IXP4XX_BASE + 31) -#define IRQ_IXP4XX_USB_HOST (IRQ_IXP4XX_BASE + 32) -#define IRQ_IXP4XX_I2C (IRQ_IXP4XX_BASE + 33) -#define IRQ_IXP4XX_SSP (IRQ_IXP4XX_BASE + 34) -#define IRQ_IXP4XX_TSYNC (IRQ_IXP4XX_BASE + 35) -#define IRQ_IXP4XX_EAU_DONE (IRQ_IXP4XX_BASE + 36) -#define IRQ_IXP4XX_SHA_DONE (IRQ_IXP4XX_BASE + 37) -#define IRQ_IXP4XX_SWCP_PE (IRQ_IXP4XX_BASE + 58) -#define IRQ_IXP4XX_QM_PE (IRQ_IXP4XX_BASE + 60) -#define IRQ_IXP4XX_MCU_ECC (IRQ_IXP4XX_BASE + 61) -#define IRQ_IXP4XX_EXP_PE (IRQ_IXP4XX_BASE + 62) - -#define _IXP4XX_GPIO_IRQ(n) (IRQ_IXP4XX_GPIO ## n) -#define IXP4XX_GPIO_IRQ(n) _IXP4XX_GPIO_IRQ(n) - -#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU) - -#endif diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c index 6794e2db1ad5..ecc46c31004f 100644 --- a/arch/arm/mach-mmp/sram.c +++ b/arch/arm/mach-mmp/sram.c @@ -72,6 +72,8 @@ static int sram_probe(struct platform_device *pdev) if (!info) return -ENOMEM; + platform_set_drvdata(pdev, info); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { dev_err(&pdev->dev, "no memory resource defined\n"); @@ -107,8 +109,6 @@ static int sram_probe(struct platform_device *pdev) list_add(&info->node, &sram_bank_list); mutex_unlock(&sram_lock); - platform_set_drvdata(pdev, info); - dev_info(&pdev->dev, "initialized\n"); return 0; @@ -127,17 +127,19 @@ static int sram_remove(struct platform_device *pdev) struct sram_bank_info *info; info = platform_get_drvdata(pdev); - if (info == NULL) - return -ENODEV; - mutex_lock(&sram_lock); - list_del(&info->node); - mutex_unlock(&sram_lock); + if (info->sram_size) { + mutex_lock(&sram_lock); + list_del(&info->node); + mutex_unlock(&sram_lock); + + gen_pool_destroy(info->gpool); + iounmap(info->sram_virt); + kfree(info->pool_name); + } - gen_pool_destroy(info->gpool); - iounmap(info->sram_virt); - kfree(info->pool_name); kfree(info); + return 0; } diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig index 0bf4d312bcfd..5dbea7b485af 100644 --- a/arch/arm/mach-mstar/Kconfig +++ b/arch/arm/mach-mstar/Kconfig @@ -1,6 +1,7 @@ menuconfig ARCH_MSTARV7 bool "MStar/Sigmastar Armv7 SoC Support" depends on ARCH_MULTI_V7 + select ARM_ERRATA_814220 select ARM_GIC select ARM_HEAVY_MB select HAVE_ARM_ARCH_TIMER diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c index 788569e960e1..0b5f055ca1c3 100644 --- a/arch/arm/mach-mv78xx0/irq.c +++ b/arch/arm/mach-mv78xx0/irq.c @@ -67,7 +67,6 @@ void __init mv78xx0_init_irq(void) * registers for core #1 are at an offset of 0x18 from those of * core #0.) */ - orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, - mv78xx0_core_index() ? 0x18 : 0, + orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0, IRQ_MV78XX0_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig index b3d161e8e2fb..6ef1b167619b 100644 --- a/arch/arm/mach-nspire/Kconfig +++ b/arch/arm/mach-nspire/Kconfig @@ -2,7 +2,6 @@ config ARCH_NSPIRE bool "TI-NSPIRE based" depends on ARCH_MULTI_V4_V5 - depends on MMU select CPU_ARM926T select GENERIC_IRQ_CHIP select ARM_AMBA diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index e94a61901ffd..c77f3b4e287b 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only menuconfig ARCH_ORION5X bool "Marvell Orion" - depends on MMU && ARCH_MULTI_V5 + depends on ARCH_MULTI_V5 select CPU_FEROCEON select GPIOLIB select MVEBU_MBUS diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index ac4af2283bef..1ae775d02d90 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -49,6 +49,6 @@ void __init orion5x_init_irq(void) /* * Initialize gpiolib for GPIOs 0-31. */ - orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0, + orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START, gpio0_irqs); } diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index f7520a6cc7d4..57f0be4065c1 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -153,16 +153,6 @@ config GUMSTIX_AM300EPD endchoice -config MACH_INTELMOTE2 - bool "Intel Mote 2 Platform" - select IWMMXT - select PXA27x - -config MACH_STARGATE2 - bool "Intel Stargate 2 Platform" - select IWMMXT - select PXA27x - config MACH_XCEP bool "Iskratel Electronics XCEP" select MTD diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 177abe584dd5..68730ceb8b7c 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -45,8 +45,6 @@ obj-$(CONFIG_MACH_CAPC7117) += capc7117.o mxm8x10.o obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o -obj-$(CONFIG_MACH_INTELMOTE2) += stargate2.o -obj-$(CONFIG_MACH_STARGATE2) += stargate2.o obj-$(CONFIG_MACH_XCEP) += xcep.o obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index c36306064eee..1ed629e38ce6 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h @@ -58,9 +58,8 @@ static inline void arch_decomp_setup(void) uart_shift = 2; uart_is_pxa = 1; - if (machine_is_littleton() || machine_is_intelmote2() - || machine_is_csb726() || machine_is_stargate2() - || machine_is_cm_x300() || machine_is_balloon3()) + if (machine_is_littleton() || machine_is_csb726() || + machine_is_cm_x300() || machine_is_balloon3()) uart_base = STUART_BASE; if (machine_is_arcom_zeus()) { diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c deleted file mode 100644 index b43e2f4536a5..000000000000 --- a/arch/arm/mach-pxa/stargate2.c +++ /dev/null @@ -1,1046 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-pxa/stargate2.c - * - * Author: Ed C. Epp - * Created: Nov 05, 2002 - * Copyright: Intel Corp. - * - * Modified 2009: Jonathan Cameron - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "pxa27x.h" -#include -#include "udc.h" -#include "pxa27x-udc.h" -#include - -#include -#include -#include - -#include "devices.h" -#include "generic.h" - -#define STARGATE_NR_IRQS (IRQ_BOARD_START + 8) - -/* Bluetooth */ -#define SG2_BT_RESET 81 - -/* SD */ -#define SG2_GPIO_nSD_DETECT 90 -#define SG2_SD_POWER_ENABLE 89 - -static unsigned long sg2_im2_unified_pin_config[] __initdata = { - /* Device Identification for wakeup*/ - GPIO102_GPIO, - /* DA9030 */ - GPIO1_GPIO, - - /* MMC */ - GPIO32_MMC_CLK, - GPIO112_MMC_CMD, - GPIO92_MMC_DAT_0, - GPIO109_MMC_DAT_1, - GPIO110_MMC_DAT_2, - GPIO111_MMC_DAT_3, - - /* 802.15.4 radio - driver out of mainline */ - GPIO22_GPIO, /* CC_RSTN */ - GPIO114_GPIO, /* CC_FIFO */ - GPIO116_GPIO, /* CC_CCA */ - GPIO0_GPIO, /* CC_FIFOP */ - GPIO16_GPIO, /* CCSFD */ - GPIO115_GPIO, /* Power enable */ - - /* I2C */ - GPIO117_I2C_SCL, - GPIO118_I2C_SDA, - - /* SSP 3 - 802.15.4 radio */ - GPIO39_GPIO, /* Chip Select */ - GPIO34_SSP3_SCLK, - GPIO35_SSP3_TXD, - GPIO41_SSP3_RXD, - - /* SSP 2 to daughter boards */ - GPIO11_SSP2_RXD, - GPIO38_SSP2_TXD, - GPIO36_SSP2_SCLK, - GPIO37_GPIO, /* chip select */ - - /* SSP 1 - to daughter boards */ - GPIO24_GPIO, /* Chip Select */ - GPIO23_SSP1_SCLK, - GPIO25_SSP1_TXD, - GPIO26_SSP1_RXD, - - /* BTUART Basic Connector*/ - GPIO42_BTUART_RXD, - GPIO43_BTUART_TXD, - GPIO44_BTUART_CTS, - GPIO45_BTUART_RTS, - - /* STUART - IM2 via debug board not sure on SG2*/ - GPIO46_STUART_RXD, - GPIO47_STUART_TXD, - - /* Basic sensor board */ - GPIO96_GPIO, /* accelerometer interrupt */ - GPIO99_GPIO, /* ADC interrupt */ - - /* SHT15 */ - GPIO100_GPIO, - GPIO98_GPIO, - - /* Basic sensor board */ - GPIO96_GPIO, /* accelerometer interrupt */ - GPIO99_GPIO, /* ADC interrupt */ - - /* Connector pins specified as gpios */ - GPIO94_GPIO, /* large basic connector pin 14 */ - GPIO10_GPIO, /* large basic connector pin 23 */ -}; - -static struct gpiod_lookup_table sht15_gpiod_table = { - .dev_id = "sht15", - .table = { - /* FIXME: should this have |GPIO_OPEN_DRAIN set? */ - GPIO_LOOKUP("gpio-pxa", 100, "data", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-pxa", 98, "clk", GPIO_ACTIVE_HIGH), - }, -}; - -static struct platform_device sht15 = { - .name = "sht15", - .id = -1, -}; - -static struct regulator_consumer_supply stargate2_sensor_3_con[] = { - REGULATOR_SUPPLY("vcc", "sht15"), -}; - -enum stargate2_ldos{ - vcc_vref, - vcc_cc2420, - /* a mote connector? */ - vcc_mica, - /* the CSR bluecore chip */ - vcc_bt, - /* The two voltages available to sensor boards */ - vcc_sensor_1_8, - vcc_sensor_3, - /* directly connected to the pxa27x */ - vcc_sram_ext, - vcc_pxa_pll, - vcc_pxa_usim, /* Reference voltage for certain gpios */ - vcc_pxa_mem, - vcc_pxa_flash, - vcc_pxa_core, /*Dc-Dc buck not yet supported */ - vcc_lcd, - vcc_bb, - vcc_bbio, /*not sure!*/ - vcc_io, /* cc2420 802.15.4 radio and pxa vcc_io ?*/ -}; - -/* The values of the various regulator constraints are obviously dependent - * on exactly what is wired to each ldo. Unfortunately this information is - * not generally available. More information has been requested from Xbow. - */ -static struct regulator_init_data stargate2_ldo_init_data[] = { - [vcc_bbio] = { - .constraints = { /* board default 1.8V */ - .name = "vcc_bbio", - .min_uV = 1800000, - .max_uV = 1800000, - }, - }, - [vcc_bb] = { - .constraints = { /* board default 2.8V */ - .name = "vcc_bb", - .min_uV = 2700000, - .max_uV = 3000000, - }, - }, - [vcc_pxa_flash] = { - .constraints = {/* default is 1.8V */ - .name = "vcc_pxa_flash", - .min_uV = 1800000, - .max_uV = 1800000, - }, - }, - [vcc_cc2420] = { /* also vcc_io */ - .constraints = { - /* board default is 2.8V */ - .name = "vcc_cc2420", - .min_uV = 2700000, - .max_uV = 3300000, - }, - }, - [vcc_vref] = { /* Reference for what? */ - .constraints = { /* default 1.8V */ - .name = "vcc_vref", - .min_uV = 1800000, - .max_uV = 1800000, - }, - }, - [vcc_sram_ext] = { - .constraints = { /* default 2.8V */ - .name = "vcc_sram_ext", - .min_uV = 2800000, - .max_uV = 2800000, - }, - }, - [vcc_mica] = { - .constraints = { /* default 2.8V */ - .name = "vcc_mica", - .min_uV = 2800000, - .max_uV = 2800000, - }, - }, - [vcc_bt] = { - .constraints = { /* default 2.8V */ - .name = "vcc_bt", - .min_uV = 2800000, - .max_uV = 2800000, - }, - }, - [vcc_lcd] = { - .constraints = { /* default 2.8V */ - .name = "vcc_lcd", - .min_uV = 2700000, - .max_uV = 3300000, - }, - }, - [vcc_io] = { /* Same or higher than everything - * bar vccbat and vccusb */ - .constraints = { /* default 2.8V */ - .name = "vcc_io", - .min_uV = 2692000, - .max_uV = 3300000, - }, - }, - [vcc_sensor_1_8] = { - .constraints = { /* default 1.8V */ - .name = "vcc_sensor_1_8", - .min_uV = 1800000, - .max_uV = 1800000, - }, - }, - [vcc_sensor_3] = { /* curiously default 2.8V */ - .constraints = { - .name = "vcc_sensor_3", - .min_uV = 2800000, - .max_uV = 3000000, - }, - .num_consumer_supplies = ARRAY_SIZE(stargate2_sensor_3_con), - .consumer_supplies = stargate2_sensor_3_con, - }, - [vcc_pxa_pll] = { /* 1.17V - 1.43V, default 1.3V*/ - .constraints = { - .name = "vcc_pxa_pll", - .min_uV = 1170000, - .max_uV = 1430000, - }, - }, - [vcc_pxa_usim] = { - .constraints = { /* default 1.8V */ - .name = "vcc_pxa_usim", - .min_uV = 1710000, - .max_uV = 2160000, - }, - }, - [vcc_pxa_mem] = { - .constraints = { /* default 1.8V */ - .name = "vcc_pxa_mem", - .min_uV = 1800000, - .max_uV = 1800000, - }, - }, -}; - -static struct mtd_partition stargate2flash_partitions[] = { - { - .name = "Bootloader", - .size = 0x00040000, - .offset = 0, - .mask_flags = 0, - }, { - .name = "Kernel", - .size = 0x00200000, - .offset = 0x00040000, - .mask_flags = 0 - }, { - .name = "Filesystem", - .size = 0x01DC0000, - .offset = 0x00240000, - .mask_flags = 0 - }, -}; - -static struct resource flash_resources = { - .start = PXA_CS0_PHYS, - .end = PXA_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct flash_platform_data stargate2_flash_data = { - .map_name = "cfi_probe", - .parts = stargate2flash_partitions, - .nr_parts = ARRAY_SIZE(stargate2flash_partitions), - .name = "PXA27xOnChipROM", - .width = 2, -}; - -static struct platform_device stargate2_flash_device = { - .name = "pxa2xx-flash", - .id = 0, - .dev = { - .platform_data = &stargate2_flash_data, - }, - .resource = &flash_resources, - .num_resources = 1, -}; - -static struct pxa2xx_spi_controller pxa_ssp_master_0_info = { - .num_chipselect = 1, -}; - -static struct pxa2xx_spi_controller pxa_ssp_master_1_info = { - .num_chipselect = 1, -}; - -static struct pxa2xx_spi_controller pxa_ssp_master_2_info = { - .num_chipselect = 1, -}; - -static struct gpiod_lookup_table pxa_ssp1_gpio_table = { - .dev_id = "pxa2xx-spi.1", - .table = { - GPIO_LOOKUP_IDX("gpio-pxa", 24, "cs", 0, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct gpiod_lookup_table pxa_ssp3_gpio_table = { - .dev_id = "pxa2xx-spi.3", - .table = { - GPIO_LOOKUP_IDX("gpio-pxa", 39, "cs", 0, GPIO_ACTIVE_LOW), - { }, - }, -}; - -/* An upcoming kernel change will scrap SFRM usage so these - * drivers have been moved to use GPIOs */ -static struct pxa2xx_spi_chip staccel_chip_info = { - .tx_threshold = 8, - .rx_threshold = 8, - .dma_burst_size = 8, - .timeout = 235, -}; - -static struct pxa2xx_spi_chip cc2420_info = { - .tx_threshold = 8, - .rx_threshold = 8, - .dma_burst_size = 8, - .timeout = 235, -}; - -static struct spi_board_info spi_board_info[] __initdata = { - { - .modalias = "lis3l02dq", - .max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */ - .bus_num = 1, - .chip_select = 0, - .controller_data = &staccel_chip_info, - .irq = PXA_GPIO_TO_IRQ(96), - }, { - .modalias = "cc2420", - .max_speed_hz = 6500000, - .bus_num = 3, - .chip_select = 0, - .controller_data = &cc2420_info, - }, -}; - -static void sg2_udc_command(int cmd) -{ - switch (cmd) { - case PXA2XX_UDC_CMD_CONNECT: - UP2OCR |= UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE; - break; - case PXA2XX_UDC_CMD_DISCONNECT: - UP2OCR &= ~(UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE); - break; - } -} - -static struct i2c_pxa_platform_data i2c_pwr_pdata = { - .fast_mode = 1, -}; - -static struct i2c_pxa_platform_data i2c_pdata = { - .fast_mode = 1, -}; - -static void __init imote2_stargate2_init(void) -{ - - pxa2xx_mfp_config(ARRAY_AND_SIZE(sg2_im2_unified_pin_config)); - - pxa_set_ffuart_info(NULL); - pxa_set_btuart_info(NULL); - pxa_set_stuart_info(NULL); - - gpiod_add_lookup_table(&pxa_ssp1_gpio_table); - gpiod_add_lookup_table(&pxa_ssp3_gpio_table); - pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info); - pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info); - pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info); - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); - - - pxa27x_set_i2c_power_info(&i2c_pwr_pdata); - pxa_set_i2c_info(&i2c_pdata); -} - -#ifdef CONFIG_MACH_INTELMOTE2 -/* As the the imote2 doesn't currently have a conventional SD slot - * there is no option to hotplug cards, making all this rather simple - */ -static int imote2_mci_get_ro(struct device *dev) -{ - return 0; -} - -/* Rather simple case as hotplugging not possible */ -static struct pxamci_platform_data imote2_mci_platform_data = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* default anyway */ - .get_ro = imote2_mci_get_ro, -}; - -static struct gpio_led imote2_led_pins[] = { - { - .name = "imote2:red", - .gpio = 103, - .active_low = 1, - }, { - .name = "imote2:green", - .gpio = 104, - .active_low = 1, - }, { - .name = "imote2:blue", - .gpio = 105, - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data imote2_led_data = { - .num_leds = ARRAY_SIZE(imote2_led_pins), - .leds = imote2_led_pins, -}; - -static struct platform_device imote2_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &imote2_led_data, - }, -}; - -static struct da903x_subdev_info imote2_da9030_subdevs[] = { - { - .name = "da903x-regulator", - .id = DA9030_ID_LDO2, - .platform_data = &stargate2_ldo_init_data[vcc_bbio], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO3, - .platform_data = &stargate2_ldo_init_data[vcc_bb], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO4, - .platform_data = &stargate2_ldo_init_data[vcc_pxa_flash], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO5, - .platform_data = &stargate2_ldo_init_data[vcc_cc2420], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO6, - .platform_data = &stargate2_ldo_init_data[vcc_vref], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO7, - .platform_data = &stargate2_ldo_init_data[vcc_sram_ext], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO8, - .platform_data = &stargate2_ldo_init_data[vcc_mica], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO9, - .platform_data = &stargate2_ldo_init_data[vcc_bt], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO10, - .platform_data = &stargate2_ldo_init_data[vcc_sensor_1_8], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO11, - .platform_data = &stargate2_ldo_init_data[vcc_sensor_3], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO12, - .platform_data = &stargate2_ldo_init_data[vcc_lcd], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO15, - .platform_data = &stargate2_ldo_init_data[vcc_pxa_pll], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO17, - .platform_data = &stargate2_ldo_init_data[vcc_pxa_usim], - }, { - .name = "da903x-regulator", /*pxa vcc i/o and cc2420 vcc i/o */ - .id = DA9030_ID_LDO18, - .platform_data = &stargate2_ldo_init_data[vcc_io], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO19, - .platform_data = &stargate2_ldo_init_data[vcc_pxa_mem], - }, -}; - -static struct da903x_platform_data imote2_da9030_pdata = { - .num_subdevs = ARRAY_SIZE(imote2_da9030_subdevs), - .subdevs = imote2_da9030_subdevs, -}; - -static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = { - { - .type = "da9030", - .addr = 0x49, - .platform_data = &imote2_da9030_pdata, - .irq = PXA_GPIO_TO_IRQ(1), - }, -}; - -static struct i2c_board_info __initdata imote2_i2c_board_info[] = { - { /* UCAM sensor board */ - .type = "max1239", - .addr = 0x35, - }, { /* ITS400 Sensor board only */ - .type = "max1363", - .addr = 0x34, - /* Through a nand gate - Also beware, on V2 sensor board the - * pull up resistors are missing. - */ - .irq = PXA_GPIO_TO_IRQ(99), - }, { /* ITS400 Sensor board only */ - .type = "tsl2561", - .addr = 0x49, - /* Through a nand gate - Also beware, on V2 sensor board the - * pull up resistors are missing. - */ - .irq = PXA_GPIO_TO_IRQ(99), - }, { /* ITS400 Sensor board only */ - .type = "tmp175", - .addr = 0x4A, - .irq = PXA_GPIO_TO_IRQ(96), - }, { /* IMB400 Multimedia board */ - .type = "wm8940", - .addr = 0x1A, - }, -}; - -static unsigned long imote2_pin_config[] __initdata = { - - /* Button */ - GPIO91_GPIO, - - /* LEDS */ - GPIO103_GPIO, /* red led */ - GPIO104_GPIO, /* green led */ - GPIO105_GPIO, /* blue led */ -}; - -static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = { - .udc_command = sg2_udc_command, -}; - -static struct platform_device imote2_audio_device = { - .name = "imote2-audio", - .id = -1, -}; - -static struct platform_device *imote2_devices[] = { - &stargate2_flash_device, - &imote2_leds, - &sht15, - &imote2_audio_device, -}; - -static void __init imote2_init(void) -{ - pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config)); - - imote2_stargate2_init(); - - gpiod_add_lookup_table(&sht15_gpiod_table); - platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices)); - - i2c_register_board_info(0, imote2_i2c_board_info, - ARRAY_SIZE(imote2_i2c_board_info)); - i2c_register_board_info(1, imote2_pwr_i2c_board_info, - ARRAY_SIZE(imote2_pwr_i2c_board_info)); - - pxa_set_mci_info(&imote2_mci_platform_data); - pxa_set_udc_info(&imote2_udc_info); -} -#endif - -#ifdef CONFIG_MACH_STARGATE2 - -static unsigned long stargate2_pin_config[] __initdata = { - - GPIO15_nCS_1, /* SRAM */ - /* SMC91x */ - GPIO80_nCS_4, - GPIO40_GPIO, /*cable detect?*/ - - /* Button */ - GPIO91_GPIO | WAKEUP_ON_LEVEL_HIGH, - - /* Compact Flash */ - GPIO79_PSKTSEL, - GPIO48_nPOE, - GPIO49_nPWE, - GPIO50_nPIOR, - GPIO51_nPIOW, - GPIO85_nPCE_1, - GPIO54_nPCE_2, - GPIO55_nPREG, - GPIO56_nPWAIT, - GPIO57_nIOIS16, - GPIO120_GPIO, /* Buff ctrl */ - GPIO108_GPIO, /* Power ctrl */ - GPIO82_GPIO, /* Reset */ - GPIO53_GPIO, /* SG2_S0_GPIO_DETECT */ - - /* MMC not shared with imote2 */ - GPIO90_GPIO, /* nSD detect */ - GPIO89_GPIO, /* SD_POWER_ENABLE */ - - /* Bluetooth */ - GPIO81_GPIO, /* reset */ -}; - -static struct resource smc91x_resources[] = { - [0] = { - .name = "smc91x-regs", - .start = (PXA_CS4_PHYS + 0x300), - .end = (PXA_CS4_PHYS + 0xfffff), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = PXA_GPIO_TO_IRQ(40), - .end = PXA_GPIO_TO_IRQ(40), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - } -}; - -static struct smc91x_platdata stargate2_smc91x_info = { - .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT - | SMC91X_NOWAIT | SMC91X_USE_DMA, - .pxa_u16_align4 = true, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = -1, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, - .dev = { - .platform_data = &stargate2_smc91x_info, - }, -}; - - -/* - * The card detect interrupt isn't debounced so we delay it by 250ms - * to give the card a chance to fully insert / eject. - */ -static int stargate2_mci_init(struct device *dev, - irq_handler_t stargate2_detect_int, - void *data) -{ - int err; - - err = gpio_request(SG2_SD_POWER_ENABLE, "SG2_sd_power_enable"); - if (err) { - printk(KERN_ERR "Can't get the gpio for SD power control"); - goto return_err; - } - gpio_direction_output(SG2_SD_POWER_ENABLE, 0); - - err = gpio_request(SG2_GPIO_nSD_DETECT, "SG2_sd_detect"); - if (err) { - printk(KERN_ERR "Can't get the sd detect gpio"); - goto free_power_en; - } - gpio_direction_input(SG2_GPIO_nSD_DETECT); - - err = request_irq(PXA_GPIO_TO_IRQ(SG2_GPIO_nSD_DETECT), - stargate2_detect_int, - IRQ_TYPE_EDGE_BOTH, - "MMC card detect", - data); - if (err) { - printk(KERN_ERR "can't request MMC card detect IRQ\n"); - goto free_nsd_detect; - } - return 0; - - free_nsd_detect: - gpio_free(SG2_GPIO_nSD_DETECT); - free_power_en: - gpio_free(SG2_SD_POWER_ENABLE); - return_err: - return err; -} - -/** - * stargate2_mci_setpower() - set state of mmc power supply - * - * Very simple control. Either it is on or off and is controlled by - * a gpio pin */ -static int stargate2_mci_setpower(struct device *dev, unsigned int vdd) -{ - gpio_set_value(SG2_SD_POWER_ENABLE, !!vdd); - return 0; -} - -static void stargate2_mci_exit(struct device *dev, void *data) -{ - free_irq(PXA_GPIO_TO_IRQ(SG2_GPIO_nSD_DETECT), data); - gpio_free(SG2_SD_POWER_ENABLE); - gpio_free(SG2_GPIO_nSD_DETECT); -} - -static struct pxamci_platform_data stargate2_mci_platform_data = { - .detect_delay_ms = 250, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .init = stargate2_mci_init, - .setpower = stargate2_mci_setpower, - .exit = stargate2_mci_exit, -}; - - -/* - * SRAM - The Stargate 2 has 32MB of SRAM. - * - * Here it is made available as an MTD. This will then - * typically have a cifs filesystem created on it to provide - * fast temporary storage. - */ -static struct resource sram_resources = { - .start = PXA_CS1_PHYS, - .end = PXA_CS1_PHYS + SZ_32M-1, - .flags = IORESOURCE_MEM, -}; - -static struct platdata_mtd_ram stargate2_sram_pdata = { - .mapname = "Stargate2 SRAM", - .bankwidth = 2, -}; - -static struct platform_device stargate2_sram = { - .name = "mtd-ram", - .id = 0, - .resource = &sram_resources, - .num_resources = 1, - .dev = { - .platform_data = &stargate2_sram_pdata, - }, -}; - -static struct pcf857x_platform_data platform_data_pcf857x = { - .gpio_base = 128, - .n_latch = 0, - .setup = NULL, - .teardown = NULL, - .context = NULL, -}; - -static const struct property_entry pca9500_eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 4), - { } -}; - -static const struct software_node pca9500_eeprom_node = { - .properties = pca9500_eeprom_properties, -}; - -/** - * stargate2_reset_bluetooth() reset the bluecore to ensure consistent state - **/ -static int stargate2_reset_bluetooth(void) -{ - int err; - err = gpio_request(SG2_BT_RESET, "SG2_BT_RESET"); - if (err) { - printk(KERN_ERR "Could not get gpio for bluetooth reset\n"); - return err; - } - gpio_direction_output(SG2_BT_RESET, 1); - mdelay(5); - /* now reset it - 5 msec minimum */ - gpio_set_value(SG2_BT_RESET, 0); - mdelay(10); - gpio_set_value(SG2_BT_RESET, 1); - gpio_free(SG2_BT_RESET); - return 0; -} - -static struct led_info stargate2_leds[] = { - { - .name = "sg2:red", - .flags = DA9030_LED_RATE_ON, - }, { - .name = "sg2:blue", - .flags = DA9030_LED_RATE_ON, - }, { - .name = "sg2:green", - .flags = DA9030_LED_RATE_ON, - }, -}; - -static struct da903x_subdev_info stargate2_da9030_subdevs[] = { - { - .name = "da903x-led", - .id = DA9030_ID_LED_2, - .platform_data = &stargate2_leds[0], - }, { - .name = "da903x-led", - .id = DA9030_ID_LED_3, - .platform_data = &stargate2_leds[2], - }, { - .name = "da903x-led", - .id = DA9030_ID_LED_4, - .platform_data = &stargate2_leds[1], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO2, - .platform_data = &stargate2_ldo_init_data[vcc_bbio], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO3, - .platform_data = &stargate2_ldo_init_data[vcc_bb], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO4, - .platform_data = &stargate2_ldo_init_data[vcc_pxa_flash], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO5, - .platform_data = &stargate2_ldo_init_data[vcc_cc2420], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO6, - .platform_data = &stargate2_ldo_init_data[vcc_vref], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO7, - .platform_data = &stargate2_ldo_init_data[vcc_sram_ext], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO8, - .platform_data = &stargate2_ldo_init_data[vcc_mica], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO9, - .platform_data = &stargate2_ldo_init_data[vcc_bt], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO10, - .platform_data = &stargate2_ldo_init_data[vcc_sensor_1_8], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO11, - .platform_data = &stargate2_ldo_init_data[vcc_sensor_3], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO12, - .platform_data = &stargate2_ldo_init_data[vcc_lcd], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO15, - .platform_data = &stargate2_ldo_init_data[vcc_pxa_pll], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO17, - .platform_data = &stargate2_ldo_init_data[vcc_pxa_usim], - }, { - .name = "da903x-regulator", /*pxa vcc i/o and cc2420 vcc i/o */ - .id = DA9030_ID_LDO18, - .platform_data = &stargate2_ldo_init_data[vcc_io], - }, { - .name = "da903x-regulator", - .id = DA9030_ID_LDO19, - .platform_data = &stargate2_ldo_init_data[vcc_pxa_mem], - }, -}; - -static struct da903x_platform_data stargate2_da9030_pdata = { - .num_subdevs = ARRAY_SIZE(stargate2_da9030_subdevs), - .subdevs = stargate2_da9030_subdevs, -}; - -static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = { - { - .type = "da9030", - .addr = 0x49, - .platform_data = &stargate2_da9030_pdata, - .irq = PXA_GPIO_TO_IRQ(1), - }, -}; - -static struct i2c_board_info __initdata stargate2_i2c_board_info[] = { - /* Techically this a pca9500 - but it's compatible with the 8574 - * for gpio expansion and the 24c02 for eeprom access. - */ - { - .type = "pcf8574", - .addr = 0x27, - .platform_data = &platform_data_pcf857x, - }, { - .type = "24c02", - .addr = 0x57, - .swnode = &pca9500_eeprom_node, - }, { - .type = "max1238", - .addr = 0x35, - }, { /* ITS400 Sensor board only */ - .type = "max1363", - .addr = 0x34, - /* Through a nand gate - Also beware, on V2 sensor board the - * pull up resistors are missing. - */ - .irq = PXA_GPIO_TO_IRQ(99), - }, { /* ITS400 Sensor board only */ - .type = "tsl2561", - .addr = 0x49, - /* Through a nand gate - Also beware, on V2 sensor board the - * pull up resistors are missing. - */ - .irq = PXA_GPIO_TO_IRQ(99), - }, { /* ITS400 Sensor board only */ - .type = "tmp175", - .addr = 0x4A, - .irq = PXA_GPIO_TO_IRQ(96), - }, -}; - -/* Board doesn't support cable detection - so always lie and say - * something is there. - */ -static int sg2_udc_detect(void) -{ - return 1; -} - -static struct pxa2xx_udc_mach_info stargate2_udc_info __initdata = { - .udc_is_connected = sg2_udc_detect, - .udc_command = sg2_udc_command, -}; - -static struct platform_device *stargate2_devices[] = { - &stargate2_flash_device, - &stargate2_sram, - &smc91x_device, - &sht15, -}; - -static void __init stargate2_init(void) -{ - /* This is probably a board specific hack as this must be set - prior to connecting the MFP stuff up. */ - __raw_writel(__raw_readl(MECR) & ~MECR_NOS, MECR); - - pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config)); - - imote2_stargate2_init(); - - gpiod_add_lookup_table(&sht15_gpiod_table); - platform_add_devices(ARRAY_AND_SIZE(stargate2_devices)); - - i2c_register_board_info(0, ARRAY_AND_SIZE(stargate2_i2c_board_info)); - i2c_register_board_info(1, stargate2_pwr_i2c_board_info, - ARRAY_SIZE(stargate2_pwr_i2c_board_info)); - - pxa_set_mci_info(&stargate2_mci_platform_data); - - pxa_set_udc_info(&stargate2_udc_info); - - stargate2_reset_bluetooth(); -} -#endif - -#ifdef CONFIG_MACH_INTELMOTE2 -MACHINE_START(INTELMOTE2, "IMOTE 2") - .map_io = pxa27x_map_io, - .nr_irqs = PXA_NR_IRQS, - .init_irq = pxa27x_init_irq, - .handle_irq = pxa27x_handle_irq, - .init_time = pxa_timer_init, - .init_machine = imote2_init, - .atag_offset = 0x100, - .restart = pxa_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_STARGATE2 -MACHINE_START(STARGATE2, "Stargate 2") - .map_io = pxa27x_map_io, - .nr_irqs = STARGATE_NR_IRQS, - .init_irq = pxa27x_init_irq, - .handle_irq = pxa27x_handle_irq, - .init_time = pxa_timer_init, - .init_machine = stargate2_init, - .atag_offset = 0x100, - .restart = pxa_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c index 58a4228455ce..65a0d5ce2bb3 100644 --- a/arch/arm/mach-qcom/platsmp.c +++ b/arch/arm/mach-qcom/platsmp.c @@ -357,8 +357,7 @@ static void __init qcom_smp_prepare_cpus(unsigned int max_cpus) { int cpu; - if (qcom_scm_set_cold_boot_addr(secondary_startup_arm, - cpu_present_mask)) { + if (qcom_scm_set_cold_boot_addr(secondary_startup_arm)) { for_each_present_cpu(cpu) { if (cpu == smp_processor_id()) continue; diff --git a/arch/arm/mach-rpc/fiq.S b/arch/arm/mach-rpc/fiq.S index 0de83e9b0b39..087bdf4bc093 100644 --- a/arch/arm/mach-rpc/fiq.S +++ b/arch/arm/mach-rpc/fiq.S @@ -2,10 +2,11 @@ #include #include #include -#include + + .equ ioc_base_high, IOC_BASE & 0xff000000 + .equ ioc_base_low, IOC_BASE & 0x00ff0000 .text - .global rpc_default_fiq_end ENTRY(rpc_default_fiq_start) mov r12, #ioc_base_high diff --git a/arch/arm/mach-rpc/include/mach/entry-macro.S b/arch/arm/mach-rpc/include/mach/entry-macro.S deleted file mode 100644 index a6d1a9f4bb79..000000000000 --- a/arch/arm/mach-rpc/include/mach/entry-macro.S +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#include -#include - - .equ ioc_base_high, IOC_BASE & 0xff000000 - .equ ioc_base_low, IOC_BASE & 0x00ff0000 - - .macro get_irqnr_preamble, base, tmp - mov \base, #ioc_base_high @ point at IOC - .if ioc_base_low - orr \base, \base, #ioc_base_low - .endif - .endm diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c index 803aeb126f0e..dc29384b6ef8 100644 --- a/arch/arm/mach-rpc/irq.c +++ b/arch/arm/mach-rpc/irq.c @@ -14,6 +14,99 @@ #define CLR 0x04 #define MASK 0x08 +static const u8 irq_prio_h[256] = { + 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10, + 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10, + 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10, + 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10, + 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10, + 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10, + 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10, + 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10, + 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10, + 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10, + 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10, + 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10, + 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10, + 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10, + 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10, + 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10, +}; + +static const u8 irq_prio_d[256] = { + 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, + 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16, +}; + +static const u8 irq_prio_l[256] = { + 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, + 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, + 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, + 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, + 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3, + 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3, + 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, + 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, +}; + +static int iomd_get_irq_nr(void) +{ + int irq; + u8 reg; + + /* get highest priority first */ + reg = readb(IOC_BASE + IOMD_IRQREQB); + irq = irq_prio_h[reg]; + if (irq) + return irq; + + /* get DMA */ + reg = readb(IOC_BASE + IOMD_DMAREQ); + irq = irq_prio_d[reg]; + if (irq) + return irq; + + /* get low priority */ + reg = readb(IOC_BASE + IOMD_IRQREQA); + irq = irq_prio_l[reg]; + if (irq) + return irq; + return 0; +} + +static void iomd_handle_irq(struct pt_regs *regs) +{ + int irq; + + do { + irq = iomd_get_irq_nr(); + if (irq) + generic_handle_irq(irq); + } while (irq); +} + static void __iomem *iomd_get_base(struct irq_data *d) { void *cd = irq_data_get_irq_chip_data(d); @@ -82,6 +175,8 @@ void __init rpc_init_irq(void) set_fiq_handler(&rpc_default_fiq_start, &rpc_default_fiq_end - &rpc_default_fiq_start); + set_handle_irq(iomd_handle_irq); + for (irq = 0; irq < NR_IRQS; irq++) { clr = IRQ_NOREQUEST; set = 0; diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index 3683d6f10973..50909c4b95b2 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 menuconfig ARCH_RENESAS bool "Renesas ARM SoCs" - depends on ARCH_MULTI_V7 && MMU + depends on ARCH_MULTI_V7 select ARM_GIC select GPIOLIB select NO_IOPORT_MAP diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c index 74d1ca2a529a..b38391e9d8bf 100644 --- a/arch/arm/mach-spear/spear13xx.c +++ b/arch/arm/mach-spear/spear13xx.c @@ -29,7 +29,7 @@ void __init spear13xx_l2x0_init(void) /* * 512KB (64KB/way), 8-way associativity, parity supported * - * FIXME: 9th bit, of Auxillary Controller register must be set + * FIXME: 9th bit, of Auxiliary Controller register must be set * for some spear13xx devices for stable L2 operation. * * Enable Early BRESP, L2 prefetch for Instruction and Data, diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 24ed7f4a87a4..c18def269137 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 menuconfig ARCH_U8500 bool "ST-Ericsson U8500 Series" - depends on ARCH_MULTI_V7 && MMU + depends on ARCH_MULTI_V7 select AB8500_CORE select ABX500_CORE select ARM_AMBA diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 9724c16e9076..d30ee26ccc87 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -386,6 +386,7 @@ config CPU_V6 select CPU_PABRT_V6 select CPU_THUMB_CAPABLE select CPU_TLB_V6 if MMU + select SMP_ON_UP if SMP # ARMv6k config CPU_V6K diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 830bbfb26ca5..7c9499b728c4 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -90,7 +90,7 @@ ENDPROC(v7_flush_icache_all) * * Flush the D-cache up to the Level of Unification Inner Shareable * - * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) + * Corrupted registers: r0-r6, r9-r10 */ ENTRY(v7_flush_dcache_louis) @@ -117,7 +117,7 @@ ENDPROC(v7_flush_dcache_louis) * * Flush the whole D-cache. * - * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) + * Corrupted registers: r0-r6, r9-r10 * * - mm - mm_struct describing address space */ @@ -149,22 +149,22 @@ flush_levels: movw r4, #0x3ff ands r4, r4, r1, lsr #3 @ find maximum number on the way size clz r5, r4 @ find bit position of way size increment - movw r7, #0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the index size + movw r6, #0x7fff + and r1, r6, r1, lsr #13 @ extract max number of the index size + mov r6, #1 + movne r4, r4, lsl r5 @ # of ways shifted into bits [31:...] + movne r6, r6, lsl r5 @ 1 shifted left by same amount loop1: - mov r9, r7 @ create working copy of max index + mov r9, r1 @ create working copy of max index loop2: - ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11 - THUMB( lsl r6, r4, r5 ) - THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 - ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11 - THUMB( lsl r6, r9, r2 ) - THUMB( orr r11, r11, r6 ) @ factor index number into r11 - mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + mov r5, r9, lsl r2 @ factor set number into r5 + orr r5, r5, r4 @ factor way number into r5 + orr r5, r5, r10 @ factor cache level into r5 + mcr p15, 0, r5, c7, c14, 2 @ clean & invalidate by set/way subs r9, r9, #1 @ decrement the index bge loop2 - subs r4, r4, #1 @ decrement the way - bge loop1 + subs r4, r4, r6 @ decrement the way + bcs loop1 skip: add r10, r10, #2 @ increment cache number cmp r3, r10 @@ -192,14 +192,12 @@ ENDPROC(v7_flush_dcache_all) * */ ENTRY(v7_flush_kern_cache_all) - ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) - THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) + stmfd sp!, {r4-r6, r9-r10, lr} bl v7_flush_dcache_all mov r0, #0 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate - ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) - THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) + ldmfd sp!, {r4-r6, r9-r10, lr} ret lr ENDPROC(v7_flush_kern_cache_all) @@ -210,14 +208,12 @@ ENDPROC(v7_flush_kern_cache_all) * Invalidate the I-cache to the point of unification. */ ENTRY(v7_flush_kern_cache_louis) - ARM( stmfd sp!, {r4-r5, r7, r9-r11, lr} ) - THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) + stmfd sp!, {r4-r6, r9-r10, lr} bl v7_flush_dcache_louis mov r0, #0 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate - ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) - THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) + ldmfd sp!, {r4-r6, r9-r10, lr} ret lr ENDPROC(v7_flush_kern_cache_louis) diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c index 48091870db89..4204ffa2d104 100644 --- a/arch/arm/mm/context.c +++ b/arch/arm/mm/context.c @@ -240,8 +240,7 @@ void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk) unsigned int cpu = smp_processor_id(); u64 asid; - if (unlikely(mm->context.vmalloc_seq != init_mm.context.vmalloc_seq)) - __check_vmalloc_seq(mm); + check_vmalloc_seq(mm); /* * We cannot update the pgd and the ASID atomicly with classic diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 197f8eb3a775..aa08bcb72db9 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -117,16 +117,21 @@ EXPORT_SYMBOL(ioremap_page); void __check_vmalloc_seq(struct mm_struct *mm) { - unsigned int seq; + int seq; do { - seq = init_mm.context.vmalloc_seq; + seq = atomic_read(&init_mm.context.vmalloc_seq); memcpy(pgd_offset(mm, VMALLOC_START), pgd_offset_k(VMALLOC_START), sizeof(pgd_t) * (pgd_index(VMALLOC_END) - pgd_index(VMALLOC_START))); - mm->context.vmalloc_seq = seq; - } while (seq != init_mm.context.vmalloc_seq); + /* + * Use a store-release so that other CPUs that observe the + * counter's new value are guaranteed to see the results of the + * memcpy as well. + */ + atomic_set_release(&mm->context.vmalloc_seq, seq); + } while (seq != atomic_read(&init_mm.context.vmalloc_seq)); } #if !defined(CONFIG_SMP) && !defined(CONFIG_ARM_LPAE) @@ -157,7 +162,7 @@ static void unmap_area_sections(unsigned long virt, unsigned long size) * Note: this is still racy on SMP machines. */ pmd_clear(pmdp); - init_mm.context.vmalloc_seq++; + atomic_inc_return_release(&init_mm.context.vmalloc_seq); /* * Free the page table, if there was one. @@ -174,8 +179,7 @@ static void unmap_area_sections(unsigned long virt, unsigned long size) * Ensure that the active_mm is up to date - we want to * catch any use-after-iounmap cases. */ - if (current->active_mm->context.vmalloc_seq != init_mm.context.vmalloc_seq) - __check_vmalloc_seq(current->active_mm); + check_vmalloc_seq(current->active_mm); flush_tlb_kernel_range(virt, end); } diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 734f0be4f14a..3ef9ecdd6343 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c @@ -516,8 +516,7 @@ static void orion_gpio_mask_irq(struct irq_data *d) irq_gc_unlock(gc); } -void __init orion_gpio_init(struct device_node *np, - int gpio_base, int ngpio, +void __init orion_gpio_init(int gpio_base, int ngpio, void __iomem *base, int mask_offset, int secondary_irq_base, int irqs[4]) @@ -545,9 +544,6 @@ void __init orion_gpio_init(struct device_node *np, ochip->chip.base = gpio_base; ochip->chip.ngpio = ngpio; ochip->chip.can_sleep = 0; -#ifdef CONFIG_OF - ochip->chip.of_node = np; -#endif ochip->chip.dbg_show = orion_gpio_dbg_show; spin_lock_init(&ochip->lock); @@ -605,7 +601,7 @@ void __init orion_gpio_init(struct device_node *np, IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); /* Setup irq domain on top of the generic chip. */ - ochip->domain = irq_domain_add_legacy(np, + ochip->domain = irq_domain_add_legacy(NULL, ochip->chip.ngpio, ochip->secondary_irq_base, ochip->secondary_irq_base, diff --git a/arch/arm/plat-orion/include/plat/orion-gpio.h b/arch/arm/plat-orion/include/plat/orion-gpio.h index e856b073a9c8..25a2963e0e0f 100644 --- a/arch/arm/plat-orion/include/plat/orion-gpio.h +++ b/arch/arm/plat-orion/include/plat/orion-gpio.h @@ -30,8 +30,7 @@ int orion_gpio_led_blink_set(struct gpio_desc *desc, int state, void orion_gpio_set_valid(unsigned pin, int mode); /* Initialize gpiolib. */ -void __init orion_gpio_init(struct device_node *np, - int gpio_base, int ngpio, +void __init orion_gpio_init(int gpio_base, int ngpio, void __iomem *base, int mask_offset, int secondary_irq_base, int irq[4]); diff --git a/arch/arm/probes/kprobes/actions-common.c b/arch/arm/probes/kprobes/actions-common.c index 836aebe596cd..79171344dbeb 100644 --- a/arch/arm/probes/kprobes/actions-common.c +++ b/arch/arm/probes/kprobes/actions-common.c @@ -84,7 +84,8 @@ emulate_generic_r0_12_noflags(probes_opcode_t insn, register void *rfn asm("lr") = asi->insn_fn; __asm__ __volatile__ ( - "stmdb sp!, {%[regs], r11} \n\t" +ARM( "stmdb sp!, {%[regs], r11} \n\t" ) +THUMB( "stmdb sp!, {%[regs], r7} \n\t" ) "ldmia %[regs], {r0-r12} \n\t" #if __LINUX_ARM_ARCH__ >= 6 "blx %[fn] \n\t" @@ -96,10 +97,11 @@ emulate_generic_r0_12_noflags(probes_opcode_t insn, #endif "ldr lr, [sp], #4 \n\t" /* lr = regs */ "stmia lr, {r0-r12} \n\t" - "ldr r11, [sp], #4 \n\t" +ARM( "ldr r11, [sp], #4 \n\t" ) +THUMB( "ldr r7, [sp], #4 \n\t" ) : [regs] "=r" (rregs), [fn] "=r" (rfn) : "0" (rregs), "1" (rfn) - : "r0", "r2", "r3", "r4", "r5", "r6", "r7", + : "r0", "r2", "r3", "r4", "r5", "r6", ARM("r7") THUMB("r11"), "r8", "r9", "r10", "r12", "memory", "cc" ); } diff --git a/arch/arm/probes/kprobes/actions-thumb.c b/arch/arm/probes/kprobes/actions-thumb.c index 7884fcb81c26..51624fc263fc 100644 --- a/arch/arm/probes/kprobes/actions-thumb.c +++ b/arch/arm/probes/kprobes/actions-thumb.c @@ -447,14 +447,16 @@ t16_emulate_loregs(probes_opcode_t insn, __asm__ __volatile__ ( "msr cpsr_fs, %[oldcpsr] \n\t" + "mov r11, r7 \n\t" "ldmia %[regs], {r0-r7} \n\t" "blx %[fn] \n\t" "stmia %[regs], {r0-r7} \n\t" + "mov r7, r11 \n\t" "mrs %[newcpsr], cpsr \n\t" : [newcpsr] "=r" (newcpsr) : [oldcpsr] "r" (oldcpsr), [regs] "r" (regs), [fn] "r" (asi->insn_fn) - : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r11", "lr", "memory", "cc" ); @@ -524,14 +526,16 @@ t16_emulate_push(probes_opcode_t insn, struct arch_probes_insn *asi, struct pt_regs *regs) { __asm__ __volatile__ ( + "mov r11, r7 \n\t" "ldr r9, [%[regs], #13*4] \n\t" "ldr r8, [%[regs], #14*4] \n\t" "ldmia %[regs], {r0-r7} \n\t" "blx %[fn] \n\t" "str r9, [%[regs], #13*4] \n\t" + "mov r7, r11 \n\t" : : [regs] "r" (regs), [fn] "r" (asi->insn_fn) - : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", + : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r8", "r9", "r11", "lr", "memory", "cc" ); } @@ -558,14 +562,16 @@ t16_emulate_pop_nopc(probes_opcode_t insn, struct arch_probes_insn *asi, struct pt_regs *regs) { __asm__ __volatile__ ( + "mov r11, r7 \n\t" "ldr r9, [%[regs], #13*4] \n\t" "ldmia %[regs], {r0-r7} \n\t" "blx %[fn] \n\t" "stmia %[regs], {r0-r7} \n\t" "str r9, [%[regs], #13*4] \n\t" + "mov r7, r11 \n\t" : : [regs] "r" (regs), [fn] "r" (asi->insn_fn) - : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9", + : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r9", "r11", "lr", "memory", "cc" ); } @@ -577,14 +583,16 @@ t16_emulate_pop_pc(probes_opcode_t insn, register unsigned long pc asm("r8"); __asm__ __volatile__ ( + "mov r11, r7 \n\t" "ldr r9, [%[regs], #13*4] \n\t" "ldmia %[regs], {r0-r7} \n\t" "blx %[fn] \n\t" "stmia %[regs], {r0-r7} \n\t" "str r9, [%[regs], #13*4] \n\t" + "mov r7, r11 \n\t" : "=r" (pc) : [regs] "r" (regs), [fn] "r" (asi->insn_fn) - : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r9", + : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r9", "r11", "lr", "memory", "cc" ); diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 21697449d762..30b123cde02c 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -268,6 +268,12 @@ config ARCH_TEGRA help This enables support for the NVIDIA Tegra SoC family. +config ARCH_TESLA_FSD + bool "ARMv8 based Tesla platform" + depends on ARCH_EXYNOS + help + Support for ARMv8 based Tesla platforms. + config ARCH_SPRD bool "Spreadtrum SoC platform" help diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 639e01a4d855..1ba04e31a438 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -27,6 +27,7 @@ subdir-y += rockchip subdir-y += socionext subdir-y += sprd subdir-y += synaptics +subdir-y += tesla subdir-y += ti subdir-y += toshiba subdir-y += xilinx diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 3ec301bd08a9..884bda106399 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -77,6 +77,16 @@ method = "smc"; }; + /* Local timer */ + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + interrupt-parent = <&intc>; + }; + intc: interrupt-controller@fffc1000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; @@ -286,7 +296,7 @@ status = "disabled"; }; - mmc: dwmmc0@ff808000 { + mmc: mmc@ff808000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-dw-mshc"; @@ -323,7 +333,7 @@ reg = <0xffe00000 0x100000>; }; - pdma: pdma@ffda0000 { + pdma: dma-controller@ffda0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffda0000 0x1000>; interrupts = <0 81 4>, @@ -406,15 +416,6 @@ reg = <0xffd12000 0x228>; }; - /* Local timer */ - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - timer0: timer0@ffc03000 { compatible = "snps,dw-apb-timer"; interrupts = <0 113 4>; @@ -484,6 +485,7 @@ resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; clocks = <&clkmgr STRATIX10_USB_CLK>; + clock-names = "otg"; iommus = <&smmu 6>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 46e558ab7729..5159cd5771dc 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -7,6 +7,7 @@ / { model = "SoCFPGA Stratix 10 SoCDK"; + compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10"; aliases { serial0 = &uart0; @@ -43,7 +44,7 @@ reg = <0 0 0 0>; }; - ref_033v: 033-v-ref { + ref_033v: regulator-v-ref { compatible = "regulator-fixed"; regulator-name = "0.33V"; regulator-min-microvolt = <330000>; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index bbc3db42d6e8..0ab676c639a1 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -7,6 +7,7 @@ / { model = "SoCFPGA Stratix 10 SoCDK"; + compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10"; aliases { serial0 = &uart0; @@ -43,7 +44,7 @@ reg = <0 0 0 0>; }; - ref_033v: 033-v-ref { + ref_033v: regulator-v-ref { compatible = "regulator-fixed"; regulator-name = "0.33V"; regulator-min-microvolt = <330000>; diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 5148cd9e5146..0eec18678311 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-vero4k-plus.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb @@ -51,9 +52,15 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-h96-max.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index f84d4b489e0b..45947c1031c4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -845,6 +845,22 @@ }; }; + pwm_f_z_pins: pwm-f-z { + mux { + groups = "pwm_f_z"; + function = "pwm_f"; + bias-disable; + }; + }; + + pwm_f_a_pins: pwm-f-a { + mux { + groups = "pwm_f_a"; + function = "pwm_f"; + bias-disable; + }; + }; + pwm_f_x_pins: pwm-f-x { mux { groups = "pwm_f_x"; @@ -1887,6 +1903,33 @@ }; }; + uart_ao_b_2_3_pins: uart-ao-b-2-3 { + mux { + groups = "uart_ao_b_tx_2", + "uart_ao_b_rx_3"; + function = "uart_ao_b"; + bias-disable; + }; + }; + + uart_ao_b_8_9_pins: uart-ao-b-8-9 { + mux { + groups = "uart_ao_b_tx_8", + "uart_ao_b_rx_9"; + function = "uart_ao_b"; + bias-disable; + }; + }; + + uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts { + mux { + groups = "uart_ao_b_cts", + "uart_ao_b_rts"; + function = "uart_ao_b"; + bias-disable; + }; + }; + pwm_a_e_pins: pwm-a-e { mux { groups = "pwm_a_e"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts new file mode 100644 index 000000000000..4b0ff707e21b --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-vero4k-plus.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Author: Christian Hewitt + */ + +/dts-v1/; + +#include "meson-gxl-s905d.dtsi" +#include "meson-gx-p23x-q20x.dtsi" +#include +#include + +/ { + compatible = "osmc,vero4k-plus", "amlogic,s905d", "amlogic,meson-gxl"; + model = "OSMC Vero 4K Plus"; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <20>; + + button@0 { + label = "power"; + linux,code = ; + gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-standby { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_LOW>; + default-state = "off"; + panic-indicator; + }; + }; +}; + +ðmac { + pinctrl-0 = <ð_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; + + amlogic,tx-delay-ns = <0>; +}; + +&external_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + pinctrl-0 = <ð_phy_irq_pin>; + pinctrl-names = "default"; + + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + + interrupt-parent = <&gpio_intc>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pinctrl_periphs { + /* Ensure the phy irq pin is properly configured as input */ + eth_phy_irq_pin: eth-phy-irq { + mux { + groups = "GPIOZ_15"; + function = "gpio_periphs"; + bias-disable; + output-disable; + }; + }; +}; + +&sd_emmc_a { + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + }; +}; + +&usb { + dr_mode = "host"; +}; + +&usb2_phy0 { + /* HDMI_5V also supplies the USB VBUS */ + phy-supply = <&hdmi_5v>; +}; + +&usb2_phy0 { + /* HDMI_5V also supplies the USB VBUS */ + phy-supply = <&hdmi_5v>; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts new file mode 100644 index 000000000000..8ffbcb2b1ac5 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "meson-s4.dtsi" + +/ { + model = "Amlogic Meson S4 AQ222 Development Board"; + compatible = "amlogic,aq222", "amlogic,s4"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_B; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + +}; + +&uart_B { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi new file mode 100644 index 000000000000..bf9ae1e1016b --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + */ + +#include +#include + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35","arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; + interrupts = ; + }; + + apb4: apb4@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_B: serial@7a000 { + compatible = "amlogic,meson-s4-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x7a000 0x0 0x18>; + interrupts = ; + status = "disabled"; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts new file mode 100644 index 000000000000..d1debccdc1c2 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-sm1-ac2xx.dtsi" +#include + +/ { + compatible = "cyx,a95xf3-air-gbit", "amlogic,sm1"; + model = "Shenzhen CYX Industrial Co., Ltd A95XF3-AIR"; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "A95XF3-AIR"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; + + rx-internal-delay-ps = <800>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts new file mode 100644 index 000000000000..c94f2870b78b --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-sm1-ac2xx.dtsi" +#include + +/ { + compatible = "cyx,a95xf3-air", "amlogic,sm1"; + model = "Shenzhen CYX Industrial Co., Ltd A95XF3-AIR"; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "A95XF3-AIR"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi new file mode 100644 index 000000000000..46a34731f7e2 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-ac2xx.dtsi @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + * + * AC200/AC202 = S905D3 + * AC213/AC214 = S905X3 + * + */ + +#include "meson-sm1.dtsi" +#include +#include +#include + +/ { + aliases { + serial0 = &uart_AO; + ethernet0 = ðmac; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>; + }; + + cvbs-connector { + compatible = "composite-video-connector"; + + port { + cvbs_connector_in: endpoint { + remote-endpoint = <&cvbs_vdac_out>; + }; + }; + }; + + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_tx_tmds_out>; + }; + }; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + ao_5v: regulator-ao_5v { + compatible = "regulator-fixed"; + regulator-name = "AO_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + dc_in: regulator-dc_in { + compatible = "regulator-fixed"; + regulator-name = "DC_IN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + emmc_1v8: regulator-emmc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "EMMC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vddao_3v3: regulator-vddao_3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDAO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_in>; + regulator-always-on; + }; + + vddcpu: regulator-vddcpu { + compatible = "pwm-regulator"; + + regulator-name = "VDDCPU"; + regulator-min-microvolt = <690000>; + regulator-max-microvolt = <1050000>; + + vin-supply = <&dc_in>; + + pwms = <&pwm_AO_cd 1 1500 0>; + pwm-dutycycle-range = <100 0>; + + regulator-boot-on; + regulator-always-on; + }; + + vddio_ao1v8: regulator-vddio_ao1v8 { + compatible = "regulator-fixed"; + regulator-name = "VDDIO_AO1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; + clocks = <&wifi32k>; + clock-names = "ext_clock"; + }; + + wifi32k: wifi32k { + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */ + }; +}; + +&cec_AO { + pinctrl-0 = <&cec_ao_a_h_pins>; + pinctrl-names = "default"; + status = "disabled"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cecb_AO { + pinctrl-0 = <&cec_ao_b_h_pins>; + pinctrl-names = "default"; + status = "okay"; + hdmi-phandle = <&hdmi_tx>; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU_CLK>; + clock-latency = <50000>; +}; + +&cpu1 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU1_CLK>; + clock-latency = <50000>; +}; + +&cpu2 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU2_CLK>; + clock-latency = <50000>; +}; + +&cpu3 { + cpu-supply = <&vddcpu>; + operating-points-v2 = <&cpu_opp_table>; + clocks = <&clkc CLKID_CPU3_CLK>; + clock-latency = <50000>; +}; + +&cvbs_vdac_port { + cvbs_vdac_out: endpoint { + remote-endpoint = <&cvbs_connector_in>; + }; +}; + +&hdmi_tx { + status = "okay"; + pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>; + pinctrl-names = "default"; +}; + +&hdmi_tx_tmds_port { + hdmi_tx_tmds_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; +}; + +&ir { + status = "okay"; + pinctrl-0 = <&remote_input_ao_pins>; + pinctrl-names = "default"; +}; + +&pwm_AO_ab { + status = "okay"; + pinctrl-0 = <&pwm_ao_a_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + +&pwm_AO_cd { + pinctrl-0 = <&pwm_ao_d_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin1"; + status = "okay"; +}; + +&pwm_ef { + status = "okay"; + pinctrl-0 = <&pwm_e_pins>; + pinctrl-names = "default"; + clocks = <&xtal>; + clock-names = "clkin0"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vddio_ao1v8>; +}; + +/* SDIO */ +&sd_emmc_a { + status = "okay"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + #address-cells = <1>; + #size-cells = <0>; + + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr104; + max-frequency = <200000000>; + + non-removable; + disable-wp; + + /* WiFi firmware requires power to be kept while in suspend */ + keep-power-in-suspend; + + mmc-pwrseq = <&sdio_pwrseq>; + + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddio_ao1v8>; +}; + +/* SD Card */ +&sd_emmc_b { + status = "okay"; + pinctrl-0 = <&sdcard_c_pins>; + pinctrl-1 = <&sdcard_clk_gate_c_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <4>; + cap-sd-highspeed; + /* CRC errors are observed at 50MHz */ + max-frequency = <35000000>; + disable-wp; + + cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&vddao_3v3>; +}; + +/* eMMC */ +&sd_emmc_c { + status = "okay"; + pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>; + pinctrl-1 = <&emmc_clk_gate_pins>; + pinctrl-names = "default", "clk-gate"; + + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <200000000>; + non-removable; + disable-wp; + + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vddao_3v3>; + vqmmc-supply = <&emmc_1v8>; +}; + +&uart_AO { + status = "okay"; + pinctrl-0 = <&uart_ao_a_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + dr_mode = "otg"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts new file mode 100644 index 000000000000..0f6660e68e72 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-sm1-ac2xx.dtsi" +#include + +/ { + compatible = "haochuangyi,h96-max", "amlogic,sm1"; + model = "Shenzhen Haochuangyi Technology Co., Ltd H96 Max"; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "H96-MAX"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; + + rx-internal-delay-ps = <800>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; + +&uart_A { + status = "okay"; + + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts new file mode 100644 index 000000000000..7e1a74046ba5 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-sm1-ac2xx.dtsi" +#include + +/ { + compatible = "amediatech,x96-air-gbit", "amlogic,sm1"; + model = "Shenzhen Amediatech Technology Co., Ltd X96 Air"; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "X96-AIR"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +ðmac { + status = "okay"; + + pinctrl-0 = <ð_pins>, <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii-txid"; + phy-handle = <&external_phy>; + + rx-internal-delay-ps = <800>; +}; + +&ext_mdio { + external_phy: ethernet-phy@0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + max-speed = <1000>; + + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&gpio GPIOZ_15 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; + + interrupt-parent = <&gpio_intc>; + /* MAC_INTR on GPIOZ_14 */ + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&ir { + linux,rc-map-name = "rc-x96max"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts new file mode 100644 index 000000000000..cd93d798f2a3 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre SAS. All rights reserved. + * Copyright (c) 2020 Christian Hewitt + */ + +/dts-v1/; + +#include "meson-sm1-ac2xx.dtsi" +#include + +/ { + compatible = "amediatech,x96-air", "amlogic,sm1"; + model = "Shenzhen Amediatech Technology Co., Ltd X96 Air"; + + sound { + compatible = "amlogic,axg-sound-card"; + model = "X96-AIR"; + audio-aux-devs = <&tdmout_b>; + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT"; + + assigned-clocks = <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + status = "okay"; + + dai-link-0 { + sound-dai = <&frddr_a>; + }; + + dai-link-1 { + sound-dai = <&frddr_b>; + }; + + dai-link-2 { + sound-dai = <&frddr_c>; + }; + + /* 8ch hdmi interface */ + dai-link-3 { + sound-dai = <&tdmif_b>; + dai-format = "i2s"; + dai-tdm-slot-tx-mask-0 = <1 1>; + dai-tdm-slot-tx-mask-1 = <1 1>; + dai-tdm-slot-tx-mask-2 = <1 1>; + dai-tdm-slot-tx-mask-3 = <1 1>; + mclk-fs = <256>; + + codec { + sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* hdmi glue */ + dai-link-4 { + sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>; + + codec { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&arb { + status = "okay"; +}; + +&clkc_audio { + status = "okay"; +}; + +ðmac { + status = "okay"; + phy-handle = <&internal_ephy>; + phy-mode = "rmii"; +}; + +&frddr_a { + status = "okay"; +}; + +&frddr_b { + status = "okay"; +}; + +&frddr_c { + status = "okay"; +}; + +&ir { + linux,rc-map-name = "rc-beelink-gs1"; +}; + +&tdmif_b { + status = "okay"; +}; + +&tdmout_b { + status = "okay"; +}; + +&tohdmitx { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 3d8b1f4f2001..3c07a89bfd27 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -356,6 +356,33 @@ status = "disabled"; }; + spdifin: audio-controller@400 { + compatible = "amlogic,g12a-spdifin", + "amlogic,axg-spdifin"; + reg = <0x0 0x400 0x0 0x30>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFIN"; + interrupts = ; + clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, + <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; + clock-names = "pclk", "refclk"; + resets = <&clkc_audio AUD_RESET_SPDIFIN>; + status = "disabled"; + }; + + spdifout_a: audio-controller@480 { + compatible = "amlogic,g12a-spdifout", + "amlogic,axg-spdifout"; + reg = <0x0 0x480 0x0 0x50>; + #sound-dai-cells = <0>; + sound-name-prefix = "SPDIFOUT_A"; + clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, + <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; + clock-names = "pclk", "mclk"; + resets = <&clkc_audio AUD_RESET_SPDIFOUT>; + status = "disabled"; + }; + tdmout_a: audio-controller@500 { compatible = "amlogic,sm1-tdmout"; reg = <0x0 0x500 0x0 0x40>; diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 800da2e84f3f..4382b73baef5 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -2,7 +2,7 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += \ foundation-v8.dtb foundation-v8-psci.dtb \ foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb juno-r1-scmi.dtb juno-r2-scmi.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index a2635b14da30..446c8f476eec 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -671,7 +671,7 @@ dma-coherent; }; - dma@7ff00000 { + dma-controller@7ff00000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0x7ff00000 0 0x1000>; #dma-cells = <1>; diff --git a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts new file mode 100644 index 000000000000..190a0fba4ad6 --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts @@ -0,0 +1,23 @@ +#include "juno-r1.dts" +#include "juno-scmi.dtsi" + +/ { + funnel@20130000 { + power-domains = <&scmi_devpd 8>; + }; + + etf@20140000 { + power-domains = <&scmi_devpd 0>; + }; + + funnel@20150000 { + power-domains = <&scmi_devpd 0>; + }; +}; + +&A57_0 { + clocks = <&scmi_dvfs 0>; +}; +&A57_1 { + clocks = <&scmi_dvfs 0>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts new file mode 100644 index 000000000000..dbf13770084f --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts @@ -0,0 +1,23 @@ +#include "juno-r2.dts" +#include "juno-scmi.dtsi" + +/ { + funnel@20130000 { + power-domains = <&scmi_devpd 8>; + }; + + etf@20140000 { + power-domains = <&scmi_devpd 0>; + }; + + funnel@20150000 { + power-domains = <&scmi_devpd 0>; + }; +}; + +&A72_0 { + clocks = <&scmi_dvfs 0>; +}; +&A72_1 { + clocks = <&scmi_dvfs 0>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dts b/arch/arm64/boot/dts/arm/juno-scmi.dts new file mode 100644 index 000000000000..41588fa46d31 --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-scmi.dts @@ -0,0 +1,9 @@ +#include "juno.dts" +#include "juno-scmi.dtsi" + +&A57_0 { + clocks = <&scmi_dvfs 0>; +}; +&A57_1 { + clocks = <&scmi_dvfs 0>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi new file mode 100644 index 000000000000..d72dcff9bf06 --- /dev/null +++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi @@ -0,0 +1,199 @@ +/ { + etf@20010000 { + power-domains = <&scmi_devpd 8>; + }; + + tpiu@20030000 { + power-domains = <&scmi_devpd 8>; + }; + + funnel@20040000 { + power-domains = <&scmi_devpd 8>; + }; + + etr@20070000 { + power-domains = <&scmi_devpd 8>; + }; + + stm@20100000 { + power-domains = <&scmi_devpd 8>; + }; + + replicator@20120000 { + power-domains = <&scmi_devpd 8>; + }; + + funnel@220c0000 { + power-domains = <&scmi_devpd 8>; + }; + + funnel@230c0000 { + power-domains = <&scmi_devpd 8>; + }; + + hdlcd@7ff50000 { + clocks = <&scmi_clk 3>; + }; + + hdlcd@7ff60000 { + clocks = <&scmi_clk 3>; + }; + + /delete-node/ scpi; + + firmware { + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 0 0 &mailbox 0 1>; + shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 1 0 &mailbox 1 1>; + shmem = <&cpu_scp_hpri0 &cpu_scp_hpri1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_sensors0: protocol@15 { + reg = <0x15>; + #thermal-sensor-cells = <1>; + }; + }; + }; + + thermal-zones { + pmic { + thermal-sensors = <&scmi_sensors0 0>; + }; + + soc { + thermal-sensors = <&scmi_sensors0 3>; + }; + + big-cluster { + thermal-sensors = <&scmi_sensors0 21>; + }; + + little-cluster { + thermal-sensors = <&scmi_sensors0 22>; + }; + + gpu0 { + thermal-sensors = <&scmi_sensors0 23>; + }; + + gpu1 { + thermal-sensors = <&scmi_sensors0 24>; + }; + }; + +}; + +&A53_0 { + clocks = <&scmi_dvfs 1>; +}; +&A53_1 { + clocks = <&scmi_dvfs 1>; +}; +&A53_2 { + clocks = <&scmi_dvfs 1>; +}; +&A53_3 { + clocks = <&scmi_dvfs 1>; +}; + +&cpu_debug0 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug1 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug2 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug3 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug4 { + power-domains = <&scmi_devpd 8>; +}; +&cpu_debug5 { + power-domains = <&scmi_devpd 8>; +}; + +&etm0 { + power-domains = <&scmi_devpd 8>; +}; +&etm1 { + power-domains = <&scmi_devpd 8>; +}; +&etm2 { + power-domains = <&scmi_devpd 8>; +}; +&etm3 { + power-domains = <&scmi_devpd 8>; +}; +&etm4 { + power-domains = <&scmi_devpd 8>; +}; +&etm5 { + power-domains = <&scmi_devpd 8>; +}; + +&gpu { + clocks = <&scmi_dvfs 2>; + power-domains = <&scmi_devpd 9>; +}; + +&mailbox { + compatible = "arm,mhu-doorbell", "arm,primecell"; + #mbox-cells = <2>; + mbox-name = "ARM-MHU"; +}; + +&smmu_etr { + power-domains = <&scmi_devpd 8>; +}; + +&smmu_gpu { + power-domains = <&scmi_devpd 9>; +}; + +&sram { + /delete-node/ scp-sram@0; + /delete-node/ scp-sram@200; + + cpu_scp_lpri0: scp-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + cpu_scp_lpri1: scp-sram@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + + cpu_scp_hpri0: scp-sram@100 { + compatible = "arm,scmi-shmem"; + reg = <0x100 0x80>; + }; + + cpu_scp_hpri1: scp-sram@180 { + compatible = "arm,scmi-shmem"; + reg = <0x180 0x80>; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index c6882032a428..5082fcd1fea5 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -5,7 +5,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ - bcm2837-rpi-cm3-io3.dtb + bcm2837-rpi-cm3-io3.dtb \ + bcm2837-rpi-zero-2-w.dtb subdir-y += bcm4908 subdir-y += northstar2 diff --git a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts new file mode 100644 index 000000000000..307ae693e4a0 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts @@ -0,0 +1,2 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "arm/bcm2837-rpi-zero-2-w.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi index 984c737fa627..a4be040a00c0 100644 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi @@ -273,9 +273,18 @@ #size-cells = <1>; ranges = <0x00 0x00 0xff800000 0x3000>; - timer: timer@400 { - compatible = "brcm,bcm6328-timer", "syscon"; - reg = <0x400 0x3c>; + twd: timer-mfd@400 { + compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon"; + reg = <0x400 0x4c>; + ranges = <0x0 0x400 0x4c>; + + #address-cells = <1>; + #size-cells = <1>; + + watchdog@28 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x28 0x8>; + }; }; gpio0: gpio-controller@500 { @@ -287,6 +296,141 @@ gpio-controller; }; + pinctrl@560 { + compatible = "brcm,bcm4908-pinctrl"; + reg = <0x560 0x10>; + + pins_led_0_a: led_0-a-pins { + function = "led_0"; + groups = "led_0_grp_a"; + }; + + pins_led_1_a: led_1-a-pins { + function = "led_1"; + groups = "led_1_grp_a"; + }; + + pins_led_2_a: led_2-a-pins { + function = "led_2"; + groups = "led_2_grp_a"; + }; + + pins_led_3_a: led_3-a-pins { + function = "led_3"; + groups = "led_3_grp_a"; + }; + + pins_led_4_a: led_4-a-pins { + function = "led_4"; + groups = "led_4_grp_a"; + }; + + pins_led_5_a: led_5-a-pins { + function = "led_5"; + groups = "led_5_grp_a"; + }; + + pins_led_6_a: led_6-a-pins { + function = "led_6"; + groups = "led_6_grp_a"; + }; + + pins_led_7_a: led_7-a-pins { + function = "led_7"; + groups = "led_7_grp_a"; + }; + + pins_led_8_a: led_8-a-pins { + function = "led_8"; + groups = "led_8_grp_a"; + }; + + pins_led_9_a: led_9-a-pins { + function = "led_9"; + groups = "led_9_grp_a"; + }; + + pins_led_21_a: led_21-a-pins { + function = "led_21"; + groups = "led_21_grp_a"; + }; + + pins_led_22_a: led_22-a-pins { + function = "led_22"; + groups = "led_22_grp_a"; + }; + + pins_led_26_a: led_26-a-pins { + function = "led_26"; + groups = "led_26_grp_a"; + }; + + pins_led_27_a: led_27-a-pins { + function = "led_27"; + groups = "led_27_grp_a"; + }; + + pins_led_28_a: led_28-a-pins { + function = "led_28"; + groups = "led_28_grp_a"; + }; + + pins_led_29_a: led_29-a-pins { + function = "led_29"; + groups = "led_29_grp_a"; + }; + + pins_led_30_a: led_30-a-pins { + function = "led_30"; + groups = "led_30_grp_a"; + }; + + pins_hs_uart: hs_uart-pins { + function = "hs_uart"; + groups = "hs_uart_grp"; + }; + + pins_i2c_a: i2c-a-pins { + function = "i2c"; + groups = "i2c_grp_a"; + }; + + pins_i2c_b: i2c-b-pins { + function = "i2c"; + groups = "i2c_grp_b"; + }; + + pins_i2s: i2s-pins { + function = "i2s"; + groups = "i2s_grp"; + }; + + pins_nand_ctrl: nand_ctrl-pins { + function = "nand_ctrl"; + groups = "nand_ctrl_grp"; + }; + + pins_nand_data: nand_data-pins { + function = "nand_data"; + groups = "nand_data_grp"; + }; + + pins_emmc_ctrl: emmc_ctrl-pins { + function = "emmc_ctrl"; + groups = "emmc_ctrl_grp"; + }; + + pins_usb0_pwr: usb0_pwr-pins { + function = "usb0_pwr"; + groups = "usb0_pwr_grp"; + }; + + pins_usb1_pwr: usb1_pwr-pins { + function = "usb1_pwr"; + groups = "usb1_pwr_grp"; + }; + }; + uart0: serial@640 { compatible = "brcm,bcm6345-uart"; reg = <0x640 0x18>; @@ -312,6 +456,15 @@ }; }; + i2c@2100 { + compatible = "brcm,brcmper-i2c"; + reg = <0x2100 0x58>; + clock-frequency = <97500>; + pinctrl-names = "default"; + pinctrl-0 = <&pins_i2c_a>; + status = "disabled"; + }; + misc@2600 { compatible = "brcm,misc", "simple-mfd"; reg = <0x2600 0xe4>; @@ -330,7 +483,7 @@ reboot { compatible = "syscon-reboot"; - regmap = <&timer>; + regmap = <&twd>; offset = <0x34>; mask = <1>; }; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index ec19fbf928a1..12a4b1c03390 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -111,8 +111,8 @@ compatible = "silabs,si3226x"; reg = <0>; spi-max-frequency = <5000000>; - spi-cpha = <1>; - spi-cpol = <1>; + spi-cpha; + spi-cpol; pl022,hierarchy = <0>; pl022,interface = <0>; pl022,slave-tx-disable = <0>; @@ -135,8 +135,8 @@ at25,byte-len = <0x8000>; at25,addr-mode = <2>; at25,page-size = <64>; - spi-cpha = <1>; - spi-cpol = <1>; + spi-cpha; + spi-cpol; pl022,hierarchy = <0>; pl022,interface = <0>; pl022,slave-tx-disable = <0>; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 2cfeaf3b0a87..f59fa3979a04 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -276,7 +276,7 @@ mboxes = <&pdc3 0>; }; - dma0: dma@61360000 { + dma0: dma-controller@61360000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x61360000 0x1000>; interrupts = , @@ -644,7 +644,7 @@ reg = <0x66180000 0x1000>; interrupts = ; clocks = <&iprocslow>, <&iprocslow>; - clock-names = "spiclk", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -655,7 +655,7 @@ reg = <0x66190000 0x1000>; interrupts = ; clocks = <&iprocslow>, <&iprocslow>; - clock-names = "spiclk", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -687,7 +687,7 @@ }; }; - sata: ahci@663f2000 { + sata: sata@663f2000 { compatible = "brcm,iproc-ahci", "generic-ahci"; reg = <0x663f2000 0x1000>; dma-coherent; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 7b04dfe67bef..7f1b8efd0883 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -519,7 +519,7 @@ reg = <0x00180000 0x1000>; interrupts = ; clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; - clock-names = "spiclk", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -531,7 +531,7 @@ reg = <0x00190000 0x1000>; interrupts = ; clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; - clock-names = "spiclk", "apb_pclk"; + clock-names = "sspclk", "apb_pclk"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -543,7 +543,7 @@ reg = <0x00220000 0x28>; }; - dma0: dma@310000 { + dma0: dma-controller@310000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x00310000 0x1000>; interrupts = , diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index b41e86df0a84..6e4ba69268e5 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_EXYNOS) += \ - exynos5433-tm2.dtb \ - exynos5433-tm2e.dtb \ - exynos7-espresso.dtb \ + exynos5433-tm2.dtb \ + exynos5433-tm2e.dtb \ + exynos7-espresso.dtb \ + exynos7885-jackpotlte.dtb \ + exynos850-e850-96.dtb \ exynosautov9-sadk.dtb diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi index 32a6518517e5..4b46af3e164d 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi @@ -11,16 +11,25 @@ #include -#define PIN(_func, _pin, _pull, _drv) \ - _pin { \ +#define PIN(_pin, _func, _pull, _drv) \ + pin- ## _pin { \ samsung,pins = #_pin; \ samsung,pin-function = ; \ samsung,pin-pud = ; \ samsung,pin-drv = ; \ } +#define PIN_IN(_pin, _pull, _drv) \ + PIN(_pin, INPUT, _pull, _drv) + +#define PIN_OT(_pin, _pull, _drv) \ + PIN(_pin, OUTPUT, _pull, _drv) + +#define PIN_F2(_pin, _pull, _drv) \ + PIN(_pin, 2, _pull, _drv) + &pinctrl_alive { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -37,7 +46,7 @@ #interrupt-cells = <2>; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -54,7 +63,7 @@ #interrupt-cells = <2>; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -62,7 +71,7 @@ #interrupt-cells = <2>; }; - gpa3: gpa3 { + gpa3: gpa3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -70,7 +79,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -78,7 +87,7 @@ #interrupt-cells = <2>; }; - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -86,7 +95,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -94,7 +103,7 @@ #interrupt-cells = <2>; }; - gpf4: gpf4 { + gpf4: gpf4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -102,7 +111,7 @@ #interrupt-cells = <2>; }; - gpf5: gpf5 { + gpf5: gpf5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -112,7 +121,7 @@ }; &pinctrl_aud { - gpz0: gpz0 { + gpz0: gpz0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -120,7 +129,7 @@ #interrupt-cells = <2>; }; - gpz1: gpz1 { + gpz1: gpz1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -128,7 +137,7 @@ #interrupt-cells = <2>; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", "gpz0-4", "gpz0-5", "gpz0-6"; samsung,pin-function = ; @@ -136,14 +145,14 @@ samsung,pin-drv = ; }; - pcm0_bus: pcm0-bus { + pcm0_bus: pcm0-bus-pins { samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart_aud_bus: uart-aud-bus { + uart_aud_bus: uart-aud-bus-pins { samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0"; samsung,pin-function = ; samsung,pin-pud = ; @@ -152,7 +161,7 @@ }; &pinctrl_cpif { - gpv6: gpv6 { + gpv6: gpv6-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -162,7 +171,7 @@ }; &pinctrl_ese { - gpj2: gpj2 { + gpj2: gpj2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -172,7 +181,7 @@ }; &pinctrl_finger { - gpd5: gpd5 { + gpd5: gpd5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -180,14 +189,14 @@ #interrupt-cells = <2>; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c6_bus: hs-i2c6-bus { + hs_i2c6_bus: hs-i2c6-bus-pins { samsung,pins = "gpd5-3", "gpd5-2"; samsung,pin-function = ; samsung,pin-pud = ; @@ -196,7 +205,7 @@ }; &pinctrl_fsys { - gph1: gph1 { + gph1: gph1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -204,7 +213,7 @@ #interrupt-cells = <2>; }; - gpr4: gpr4 { + gpr4: gpr4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -212,7 +221,7 @@ #interrupt-cells = <2>; }; - gpr0: gpr0 { + gpr0: gpr0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -220,7 +229,7 @@ #interrupt-cells = <2>; }; - gpr1: gpr1 { + gpr1: gpr1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -228,7 +237,7 @@ #interrupt-cells = <2>; }; - gpr2: gpr2 { + gpr2: gpr2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -236,7 +245,7 @@ #interrupt-cells = <2>; }; - gpr3: gpr3 { + gpr3: gpr3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -244,139 +253,139 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpr0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpr0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_rdqs: sd0-rdqs { + sd0_rdqs: sd0-rdqs-pins { samsung,pins = "gpr0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_qrdy: sd0-qrdy { + sd0_qrdy: sd0-qrdy-pins { samsung,pins = "gpr0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpr1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpr2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpr2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpr3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus8: sd1-bus-width8 { + sd1_bus8: sd1-bus-width8-pins { samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pcie_bus: pcie_bus { + pcie_bus: pcie-bus-pins { samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpr4-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpr4-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpr4-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpr4-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_clk_output: sd2-clk-output { + sd2_clk_output: sd2-clk-output-pins { samsung,pins = "gpr4-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd_output: sd2-cmd-output { + sd2_cmd_output: sd2-cmd-output-pins { samsung,pins = "gpr4-1"; samsung,pin-function = ; samsung,pin-pud = ; @@ -385,7 +394,7 @@ }; &pinctrl_imem { - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -395,7 +404,7 @@ }; &pinctrl_nfc { - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -403,7 +412,7 @@ #interrupt-cells = <2>; }; - hs_i2c4_bus: hs-i2c4-bus { + hs_i2c4_bus: hs-i2c4-bus-pins { samsung,pins = "gpj0-1", "gpj0-0"; samsung,pin-function = ; samsung,pin-pud = ; @@ -412,7 +421,7 @@ }; &pinctrl_peric { - gpv7: gpv7 { + gpv7: gpv7-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -420,7 +429,7 @@ #interrupt-cells = <2>; }; - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -428,7 +437,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -436,7 +445,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -444,7 +453,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -452,7 +461,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -460,7 +469,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -468,7 +477,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -476,7 +485,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -484,7 +493,7 @@ #interrupt-cells = <2>; }; - gpd2: gpd2 { + gpd2: gpd2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -492,7 +501,7 @@ #interrupt-cells = <2>; }; - gpd4: gpd4 { + gpd4: gpd4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -500,7 +509,7 @@ #interrupt-cells = <2>; }; - gpd8: gpd8 { + gpd8: gpd8-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -508,7 +517,7 @@ #interrupt-cells = <2>; }; - gpd6: gpd6 { + gpd6: gpd6-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -516,7 +525,7 @@ #interrupt-cells = <2>; }; - gpd7: gpd7 { + gpd7: gpd7-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -524,7 +533,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -532,7 +541,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -540,7 +549,7 @@ #interrupt-cells = <2>; }; - gpg3: gpg3 { + gpg3: gpg3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -548,21 +557,21 @@ #interrupt-cells = <2>; }; - hs_i2c8_bus: hs-i2c8-bus { + hs_i2c8_bus: hs-i2c8-bus-pins { samsung,pins = "gpb0-1", "gpb0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c9_bus: hs-i2c9-bus { + hs_i2c9_bus: hs-i2c9-bus-pins { samsung,pins = "gpb0-3", "gpb0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", "gpd4-3", "gpd4-4"; samsung,pin-function = ; @@ -570,7 +579,7 @@ samsung,pin-drv = ; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2", "gpd4-3", "gpd4-4"; samsung,pin-function = ; @@ -578,193 +587,193 @@ samsung,pin-drv = ; }; - spdif_bus: spdif-bus { + spdif_bus: spdif-bus-pins { samsung,pins = "gpd4-3", "gpd4-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_spi_pin0: fimc-is-spi-pin0 { + fimc_is_spi_pin0: fimc-is-spi-pin0-pins { samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_spi_pin1: fimc-is-spi-pin1 { + fimc_is_spi_pin1: fimc-is-spi-pin1-pins { samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_bus: uart0-bus { + uart0_bus: uart0-bus-pins { samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - hs_i2c2_bus: hs-i2c2-bus { + hs_i2c2_bus: hs-i2c2-bus-pins { samsung,pins = "gpd0-3", "gpd0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_bus: uart2-bus { + uart2_bus: uart2-bus-pins { samsung,pins = "gpd1-5", "gpd1-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart1_bus: uart1-bus { + uart1_bus: uart1-bus-pins { samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - hs_i2c3_bus: hs-i2c3-bus { + hs_i2c3_bus: hs-i2c3-bus-pins { samsung,pins = "gpd1-3", "gpd1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c0_bus: hs-i2c0-bus { + hs_i2c0_bus: hs-i2c0-bus-pins { samsung,pins = "gpd2-1", "gpd2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c1_bus: hs-i2c1-bus { + hs_i2c1_bus: hs-i2c1-bus-pins { samsung,pins = "gpd2-3", "gpd2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd2-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c7_bus: hs-i2c7-bus { + hs_i2c7_bus: hs-i2c7-bus-pins { samsung,pins = "gpd2-7", "gpd2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c10_bus: hs-i2c10-bus { + hs_i2c10_bus: hs-i2c10-bus-pins { samsung,pins = "gpg3-1", "gpg3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c11_bus: hs-i2c11-bus { + hs_i2c11_bus: hs-i2c11-bus-pins { samsung,pins = "gpg3-3", "gpg3-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi3_bus: spi3-bus { + spi3_bus: spi3-bus-pins { samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi4_bus: spi4-bus { + spi4_bus: spi4-bus-pins { samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_uart: fimc-is-uart { + fimc_is_uart: fimc-is-uart-pins { samsung,pins = "gpc1-1", "gpc0-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch0_i2c: fimc-is-ch0_i2c { + fimc_is_ch0_i2c: fimc-is-ch0-i2c-pins { samsung,pins = "gpc2-1", "gpc2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch0_mclk: fimc-is-ch0_mclk { + fimc_is_ch0_mclk: fimc-is-ch0-mclk-pins { samsung,pins = "gpd7-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch1_i2c: fimc-is-ch1-i2c { + fimc_is_ch1_i2c: fimc-is-ch1-i2c-pins { samsung,pins = "gpc2-3", "gpc2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch1_mclk: fimc-is-ch1-mclk { + fimc_is_ch1_mclk: fimc-is-ch1-mclk-pins { samsung,pins = "gpd7-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch2_i2c: fimc-is-ch2-i2c { + fimc_is_ch2_i2c: fimc-is-ch2-i2c-pins { samsung,pins = "gpc2-5", "gpc2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - fimc_is_ch2_mclk: fimc-is-ch2-mclk { + fimc_is_ch2_mclk: fimc-is-ch2-mclk-pins { samsung,pins = "gpd7-2"; samsung,pin-function = ; samsung,pin-pud = ; @@ -773,7 +782,7 @@ }; &pinctrl_touch { - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -781,7 +790,7 @@ #interrupt-cells = <2>; }; - hs_i2c5_bus: hs-i2c5-bus { + hs_i2c5_bus: hs-i2c5-bus-pins { samsung,pins = "gpj1-1", "gpj1-0"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index cbcc01a66aab..91c9bd1b47dd 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -858,10 +858,10 @@ interrupts = <5 IRQ_TYPE_EDGE_FALLING>; reg = <0x66>; - muic: max77843-muic { + muic: extcon { compatible = "maxim,max77843-muic"; - musb_con: musb-connector { + musb_con: connector { compatible = "samsung,usb-connector-11pin", "usb-b-connector"; label = "micro-USB"; @@ -871,6 +871,17 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + /* + * TODO: The DTS this is based on does not have + * port@0 which is a required property. The ports + * look incomplete and need fixing. + * Add a disabled port just to satisfy dtschema. + */ + reg = <0>; + status = "disabled"; + }; + port@3 { reg = <3>; musb_con_to_mhl: endpoint { @@ -910,7 +921,7 @@ }; }; - haptic: max77843-haptic { + haptic: motor-driver { compatible = "maxim,max77843-haptic"; haptic-supply = <&ldo38_reg>; pwms = <&pwm 0 33670 0>; @@ -1011,80 +1022,80 @@ pinctrl-0 = <&initial_alive>; initial_alive: initial-state { - PIN(INPUT, gpa0-0, DOWN, FAST_SR1); - PIN(INPUT, gpa0-1, NONE, FAST_SR1); - PIN(INPUT, gpa0-2, DOWN, FAST_SR1); - PIN(INPUT, gpa0-3, NONE, FAST_SR1); - PIN(INPUT, gpa0-4, NONE, FAST_SR1); - PIN(INPUT, gpa0-5, DOWN, FAST_SR1); - PIN(INPUT, gpa0-6, NONE, FAST_SR1); - PIN(INPUT, gpa0-7, NONE, FAST_SR1); + PIN_IN(gpa0-0, DOWN, FAST_SR1); + PIN_IN(gpa0-1, NONE, FAST_SR1); + PIN_IN(gpa0-2, DOWN, FAST_SR1); + PIN_IN(gpa0-3, NONE, FAST_SR1); + PIN_IN(gpa0-4, NONE, FAST_SR1); + PIN_IN(gpa0-5, DOWN, FAST_SR1); + PIN_IN(gpa0-6, NONE, FAST_SR1); + PIN_IN(gpa0-7, NONE, FAST_SR1); - PIN(INPUT, gpa1-0, UP, FAST_SR1); - PIN(INPUT, gpa1-1, UP, FAST_SR1); - PIN(INPUT, gpa1-2, NONE, FAST_SR1); - PIN(INPUT, gpa1-3, DOWN, FAST_SR1); - PIN(INPUT, gpa1-4, DOWN, FAST_SR1); - PIN(INPUT, gpa1-5, NONE, FAST_SR1); - PIN(INPUT, gpa1-6, NONE, FAST_SR1); - PIN(INPUT, gpa1-7, NONE, FAST_SR1); + PIN_IN(gpa1-0, UP, FAST_SR1); + PIN_IN(gpa1-1, UP, FAST_SR1); + PIN_IN(gpa1-2, NONE, FAST_SR1); + PIN_IN(gpa1-3, DOWN, FAST_SR1); + PIN_IN(gpa1-4, DOWN, FAST_SR1); + PIN_IN(gpa1-5, NONE, FAST_SR1); + PIN_IN(gpa1-6, NONE, FAST_SR1); + PIN_IN(gpa1-7, NONE, FAST_SR1); - PIN(INPUT, gpa2-0, NONE, FAST_SR1); - PIN(INPUT, gpa2-1, NONE, FAST_SR1); - PIN(INPUT, gpa2-2, NONE, FAST_SR1); - PIN(INPUT, gpa2-3, DOWN, FAST_SR1); - PIN(INPUT, gpa2-4, NONE, FAST_SR1); - PIN(INPUT, gpa2-5, DOWN, FAST_SR1); - PIN(INPUT, gpa2-6, DOWN, FAST_SR1); - PIN(INPUT, gpa2-7, NONE, FAST_SR1); + PIN_IN(gpa2-0, NONE, FAST_SR1); + PIN_IN(gpa2-1, NONE, FAST_SR1); + PIN_IN(gpa2-2, NONE, FAST_SR1); + PIN_IN(gpa2-3, DOWN, FAST_SR1); + PIN_IN(gpa2-4, NONE, FAST_SR1); + PIN_IN(gpa2-5, DOWN, FAST_SR1); + PIN_IN(gpa2-6, DOWN, FAST_SR1); + PIN_IN(gpa2-7, NONE, FAST_SR1); - PIN(INPUT, gpa3-0, DOWN, FAST_SR1); - PIN(INPUT, gpa3-1, DOWN, FAST_SR1); - PIN(INPUT, gpa3-2, NONE, FAST_SR1); - PIN(INPUT, gpa3-3, DOWN, FAST_SR1); - PIN(INPUT, gpa3-4, NONE, FAST_SR1); - PIN(INPUT, gpa3-5, DOWN, FAST_SR1); - PIN(INPUT, gpa3-6, DOWN, FAST_SR1); - PIN(INPUT, gpa3-7, DOWN, FAST_SR1); + PIN_IN(gpa3-0, DOWN, FAST_SR1); + PIN_IN(gpa3-1, DOWN, FAST_SR1); + PIN_IN(gpa3-2, NONE, FAST_SR1); + PIN_IN(gpa3-3, DOWN, FAST_SR1); + PIN_IN(gpa3-4, NONE, FAST_SR1); + PIN_IN(gpa3-5, DOWN, FAST_SR1); + PIN_IN(gpa3-6, DOWN, FAST_SR1); + PIN_IN(gpa3-7, DOWN, FAST_SR1); - PIN(INPUT, gpf1-0, NONE, FAST_SR1); - PIN(INPUT, gpf1-1, NONE, FAST_SR1); - PIN(INPUT, gpf1-2, DOWN, FAST_SR1); - PIN(INPUT, gpf1-4, UP, FAST_SR1); - PIN(OUTPUT, gpf1-5, NONE, FAST_SR1); - PIN(INPUT, gpf1-6, DOWN, FAST_SR1); - PIN(INPUT, gpf1-7, DOWN, FAST_SR1); + PIN_IN(gpf1-0, NONE, FAST_SR1); + PIN_IN(gpf1-1, NONE, FAST_SR1); + PIN_IN(gpf1-2, DOWN, FAST_SR1); + PIN_IN(gpf1-4, UP, FAST_SR1); + PIN_OT(gpf1-5, NONE, FAST_SR1); + PIN_IN(gpf1-6, DOWN, FAST_SR1); + PIN_IN(gpf1-7, DOWN, FAST_SR1); - PIN(INPUT, gpf2-0, DOWN, FAST_SR1); - PIN(INPUT, gpf2-1, DOWN, FAST_SR1); - PIN(INPUT, gpf2-2, DOWN, FAST_SR1); - PIN(INPUT, gpf2-3, DOWN, FAST_SR1); + PIN_IN(gpf2-0, DOWN, FAST_SR1); + PIN_IN(gpf2-1, DOWN, FAST_SR1); + PIN_IN(gpf2-2, DOWN, FAST_SR1); + PIN_IN(gpf2-3, DOWN, FAST_SR1); - PIN(INPUT, gpf3-0, DOWN, FAST_SR1); - PIN(INPUT, gpf3-1, DOWN, FAST_SR1); - PIN(INPUT, gpf3-2, NONE, FAST_SR1); - PIN(INPUT, gpf3-3, DOWN, FAST_SR1); + PIN_IN(gpf3-0, DOWN, FAST_SR1); + PIN_IN(gpf3-1, DOWN, FAST_SR1); + PIN_IN(gpf3-2, NONE, FAST_SR1); + PIN_IN(gpf3-3, DOWN, FAST_SR1); - PIN(INPUT, gpf4-0, DOWN, FAST_SR1); - PIN(INPUT, gpf4-1, DOWN, FAST_SR1); - PIN(INPUT, gpf4-2, DOWN, FAST_SR1); - PIN(INPUT, gpf4-3, DOWN, FAST_SR1); - PIN(INPUT, gpf4-4, DOWN, FAST_SR1); - PIN(INPUT, gpf4-5, DOWN, FAST_SR1); - PIN(INPUT, gpf4-6, DOWN, FAST_SR1); - PIN(INPUT, gpf4-7, DOWN, FAST_SR1); + PIN_IN(gpf4-0, DOWN, FAST_SR1); + PIN_IN(gpf4-1, DOWN, FAST_SR1); + PIN_IN(gpf4-2, DOWN, FAST_SR1); + PIN_IN(gpf4-3, DOWN, FAST_SR1); + PIN_IN(gpf4-4, DOWN, FAST_SR1); + PIN_IN(gpf4-5, DOWN, FAST_SR1); + PIN_IN(gpf4-6, DOWN, FAST_SR1); + PIN_IN(gpf4-7, DOWN, FAST_SR1); - PIN(INPUT, gpf5-0, DOWN, FAST_SR1); - PIN(INPUT, gpf5-1, DOWN, FAST_SR1); - PIN(INPUT, gpf5-2, DOWN, FAST_SR1); - PIN(INPUT, gpf5-3, DOWN, FAST_SR1); - PIN(OUTPUT, gpf5-4, NONE, FAST_SR1); - PIN(INPUT, gpf5-5, DOWN, FAST_SR1); - PIN(INPUT, gpf5-6, DOWN, FAST_SR1); - PIN(INPUT, gpf5-7, DOWN, FAST_SR1); + PIN_IN(gpf5-0, DOWN, FAST_SR1); + PIN_IN(gpf5-1, DOWN, FAST_SR1); + PIN_IN(gpf5-2, DOWN, FAST_SR1); + PIN_IN(gpf5-3, DOWN, FAST_SR1); + PIN_OT(gpf5-4, NONE, FAST_SR1); + PIN_IN(gpf5-5, DOWN, FAST_SR1); + PIN_IN(gpf5-6, DOWN, FAST_SR1); + PIN_IN(gpf5-7, DOWN, FAST_SR1); }; - te_irq: te-irq { + te_irq: te-irq-pins { samsung,pins = "gpf1-3"; samsung,pin-function = <0xf>; }; @@ -1095,8 +1106,8 @@ pinctrl-0 = <&initial_cpif>; initial_cpif: initial-state { - PIN(INPUT, gpv6-0, DOWN, FAST_SR1); - PIN(INPUT, gpv6-1, DOWN, FAST_SR1); + PIN_IN(gpv6-0, DOWN, FAST_SR1); + PIN_IN(gpv6-1, DOWN, FAST_SR1); }; }; @@ -1104,13 +1115,16 @@ pinctrl-names = "default"; pinctrl-0 = <&initial_ese>; - pcie_wlanen: pcie-wlanen { - PIN(INPUT, gpj2-0, UP, FAST_SR4); + pcie_wlanen: pcie-wlanen-pins { + samsung,pins = "gpj2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; initial_ese: initial-state { - PIN(INPUT, gpj2-1, DOWN, FAST_SR1); - PIN(INPUT, gpj2-2, DOWN, FAST_SR1); + PIN_IN(gpj2-1, DOWN, FAST_SR1); + PIN_IN(gpj2-2, DOWN, FAST_SR1); }; }; @@ -1119,11 +1133,11 @@ pinctrl-0 = <&initial_fsys>; initial_fsys: initial-state { - PIN(INPUT, gpr3-0, NONE, FAST_SR1); - PIN(INPUT, gpr3-1, DOWN, FAST_SR1); - PIN(INPUT, gpr3-2, DOWN, FAST_SR1); - PIN(INPUT, gpr3-3, DOWN, FAST_SR1); - PIN(INPUT, gpr3-7, NONE, FAST_SR1); + PIN_IN(gpr3-0, NONE, FAST_SR1); + PIN_IN(gpr3-1, DOWN, FAST_SR1); + PIN_IN(gpr3-2, DOWN, FAST_SR1); + PIN_IN(gpr3-3, DOWN, FAST_SR1); + PIN_IN(gpr3-7, NONE, FAST_SR1); }; }; @@ -1132,14 +1146,14 @@ pinctrl-0 = <&initial_imem>; initial_imem: initial-state { - PIN(INPUT, gpf0-0, UP, FAST_SR1); - PIN(INPUT, gpf0-1, UP, FAST_SR1); - PIN(INPUT, gpf0-2, DOWN, FAST_SR1); - PIN(INPUT, gpf0-3, UP, FAST_SR1); - PIN(INPUT, gpf0-4, DOWN, FAST_SR1); - PIN(INPUT, gpf0-5, NONE, FAST_SR1); - PIN(INPUT, gpf0-6, DOWN, FAST_SR1); - PIN(INPUT, gpf0-7, UP, FAST_SR1); + PIN_IN(gpf0-0, UP, FAST_SR1); + PIN_IN(gpf0-1, UP, FAST_SR1); + PIN_IN(gpf0-2, DOWN, FAST_SR1); + PIN_IN(gpf0-3, UP, FAST_SR1); + PIN_IN(gpf0-4, DOWN, FAST_SR1); + PIN_IN(gpf0-5, NONE, FAST_SR1); + PIN_IN(gpf0-6, DOWN, FAST_SR1); + PIN_IN(gpf0-7, UP, FAST_SR1); }; }; @@ -1148,7 +1162,7 @@ pinctrl-0 = <&initial_nfc>; initial_nfc: initial-state { - PIN(INPUT, gpj0-2, DOWN, FAST_SR1); + PIN_IN(gpj0-2, DOWN, FAST_SR1); }; }; @@ -1157,53 +1171,53 @@ pinctrl-0 = <&initial_peric>; initial_peric: initial-state { - PIN(INPUT, gpv7-0, DOWN, FAST_SR1); - PIN(INPUT, gpv7-1, DOWN, FAST_SR1); - PIN(INPUT, gpv7-2, NONE, FAST_SR1); - PIN(INPUT, gpv7-3, DOWN, FAST_SR1); - PIN(INPUT, gpv7-4, DOWN, FAST_SR1); - PIN(INPUT, gpv7-5, DOWN, FAST_SR1); + PIN_IN(gpv7-0, DOWN, FAST_SR1); + PIN_IN(gpv7-1, DOWN, FAST_SR1); + PIN_IN(gpv7-2, NONE, FAST_SR1); + PIN_IN(gpv7-3, DOWN, FAST_SR1); + PIN_IN(gpv7-4, DOWN, FAST_SR1); + PIN_IN(gpv7-5, DOWN, FAST_SR1); - PIN(INPUT, gpb0-4, DOWN, FAST_SR1); + PIN_IN(gpb0-4, DOWN, FAST_SR1); - PIN(INPUT, gpc0-2, DOWN, FAST_SR1); - PIN(INPUT, gpc0-5, DOWN, FAST_SR1); - PIN(INPUT, gpc0-7, DOWN, FAST_SR1); + PIN_IN(gpc0-2, DOWN, FAST_SR1); + PIN_IN(gpc0-5, DOWN, FAST_SR1); + PIN_IN(gpc0-7, DOWN, FAST_SR1); - PIN(INPUT, gpc1-1, DOWN, FAST_SR1); + PIN_IN(gpc1-1, DOWN, FAST_SR1); - PIN(INPUT, gpc3-4, NONE, FAST_SR1); - PIN(INPUT, gpc3-5, NONE, FAST_SR1); - PIN(INPUT, gpc3-6, NONE, FAST_SR1); - PIN(INPUT, gpc3-7, NONE, FAST_SR1); + PIN_IN(gpc3-4, NONE, FAST_SR1); + PIN_IN(gpc3-5, NONE, FAST_SR1); + PIN_IN(gpc3-6, NONE, FAST_SR1); + PIN_IN(gpc3-7, NONE, FAST_SR1); - PIN(OUTPUT, gpg0-0, NONE, FAST_SR1); - PIN(2, gpg0-1, DOWN, FAST_SR1); + PIN_OT(gpg0-0, NONE, FAST_SR1); + PIN_F2(gpg0-1, DOWN, FAST_SR1); - PIN(INPUT, gpd2-5, DOWN, FAST_SR1); + PIN_IN(gpd2-5, DOWN, FAST_SR1); - PIN(INPUT, gpd4-0, NONE, FAST_SR1); - PIN(INPUT, gpd4-1, DOWN, FAST_SR1); - PIN(INPUT, gpd4-2, DOWN, FAST_SR1); - PIN(INPUT, gpd4-3, DOWN, FAST_SR1); - PIN(INPUT, gpd4-4, DOWN, FAST_SR1); + PIN_IN(gpd4-0, NONE, FAST_SR1); + PIN_IN(gpd4-1, DOWN, FAST_SR1); + PIN_IN(gpd4-2, DOWN, FAST_SR1); + PIN_IN(gpd4-3, DOWN, FAST_SR1); + PIN_IN(gpd4-4, DOWN, FAST_SR1); - PIN(INPUT, gpd6-3, DOWN, FAST_SR1); + PIN_IN(gpd6-3, DOWN, FAST_SR1); - PIN(INPUT, gpd8-1, UP, FAST_SR1); + PIN_IN(gpd8-1, UP, FAST_SR1); - PIN(INPUT, gpg1-0, DOWN, FAST_SR1); - PIN(INPUT, gpg1-1, DOWN, FAST_SR1); - PIN(INPUT, gpg1-2, DOWN, FAST_SR1); - PIN(INPUT, gpg1-3, DOWN, FAST_SR1); - PIN(INPUT, gpg1-4, DOWN, FAST_SR1); + PIN_IN(gpg1-0, DOWN, FAST_SR1); + PIN_IN(gpg1-1, DOWN, FAST_SR1); + PIN_IN(gpg1-2, DOWN, FAST_SR1); + PIN_IN(gpg1-3, DOWN, FAST_SR1); + PIN_IN(gpg1-4, DOWN, FAST_SR1); - PIN(INPUT, gpg2-0, DOWN, FAST_SR1); - PIN(INPUT, gpg2-1, DOWN, FAST_SR1); + PIN_IN(gpg2-0, DOWN, FAST_SR1); + PIN_IN(gpg2-1, DOWN, FAST_SR1); - PIN(INPUT, gpg3-0, DOWN, FAST_SR1); - PIN(INPUT, gpg3-1, DOWN, FAST_SR1); - PIN(INPUT, gpg3-5, DOWN, FAST_SR1); + PIN_IN(gpg3-0, DOWN, FAST_SR1); + PIN_IN(gpg3-1, DOWN, FAST_SR1); + PIN_IN(gpg3-5, DOWN, FAST_SR1); }; }; @@ -1212,7 +1226,7 @@ pinctrl-0 = <&initial_touch>; initial_touch: initial-state { - PIN(INPUT, gpj1-2, DOWN, FAST_SR1); + PIN_IN(gpj1-2, DOWN, FAST_SR1); }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index bfe4ed8a23d6..661567d2dd7a 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1858,7 +1858,7 @@ status = "disabled"; }; - pdma0: pdma@15610000 { + pdma0: dma-controller@15610000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x15610000 0x1000>; interrupts = ; @@ -1869,7 +1869,7 @@ #dma-requests = <32>; }; - pdma1: pdma@15600000 { + pdma1: dma-controller@15600000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x15600000 0x1000>; interrupts = ; @@ -1885,13 +1885,12 @@ reg = <0x11400000 0x100>, <0x11500000 0x08>; clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; clock-names = "sfr0_ctrl"; - samsung,pmu-syscon = <&pmu_system_controller>; power-domains = <&pd_aud>; #address-cells = <1>; #size-cells = <1>; ranges; - adma: adma@11420000 { + adma: dma-controller@11420000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x11420000 0x1000>; interrupts = ; diff --git a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts index 125c03f351d9..0895e818d3c1 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-espresso.dts +++ b/arch/arm64/boot/dts/exynos/exynos7-espresso.dts @@ -354,7 +354,7 @@ }; &pinctrl_alive { - pmic_irq: pmic-irq { + pmic_irq: pmic-irq-pins { samsung,pins = "gpa0-2"; samsung,pin-pud = ; samsung,pin-drv = ; @@ -393,14 +393,14 @@ }; &pinctrl_bus1 { - usb30_vbus_en: usb30-vbus-en { + usb30_vbus_en: usb30-vbus-en-pins { samsung,pins = "gph1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - usb3drd_boost_en: usb3drd-boost-en { + usb3drd_boost_en: usb3drd-boost-en-pins { samsung,pins = "gpf4-1"; samsung,pin-function = ; samsung,pin-pud = ; @@ -412,6 +412,11 @@ status = "okay"; }; +&usbdrd { + vdd10-supply = <&ldo4_reg>; + vdd33-supply = <&ldo6_reg>; +}; + &usbdrd_phy { vbus-supply = <&usb30_vbus_reg>; vbus-boost-supply = <&usb3drd_boost_5v>; diff --git a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi index 472dd649aa7e..be9b971f3697 100644 --- a/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi @@ -12,7 +12,7 @@ #include &pinctrl_alive { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -29,7 +29,7 @@ ; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -46,7 +46,7 @@ ; }; - gpa2: gpa2 { + gpa2: gpa2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -54,7 +54,7 @@ #interrupt-cells = <2>; }; - gpa3: gpa3 { + gpa3: gpa3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -64,7 +64,7 @@ }; &pinctrl_bus0 { - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -72,7 +72,7 @@ #interrupt-cells = <2>; }; - gpc0: gpc0 { + gpc0: gpc0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -80,7 +80,7 @@ #interrupt-cells = <2>; }; - gpc1: gpc1 { + gpc1: gpc1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -88,7 +88,7 @@ #interrupt-cells = <2>; }; - gpc2: gpc2 { + gpc2: gpc2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -96,7 +96,7 @@ #interrupt-cells = <2>; }; - gpc3: gpc3 { + gpc3: gpc3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -104,7 +104,7 @@ #interrupt-cells = <2>; }; - gpd0: gpd0 { + gpd0: gpd0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -112,7 +112,7 @@ #interrupt-cells = <2>; }; - gpd1: gpd1 { + gpd1: gpd1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -120,7 +120,7 @@ #interrupt-cells = <2>; }; - gpd2: gpd2 { + gpd2: gpd2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -128,7 +128,7 @@ #interrupt-cells = <2>; }; - gpd4: gpd4 { + gpd4: gpd4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -136,7 +136,7 @@ #interrupt-cells = <2>; }; - gpd5: gpd5 { + gpd5: gpd5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -144,7 +144,7 @@ #interrupt-cells = <2>; }; - gpd6: gpd6 { + gpd6: gpd6-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -152,7 +152,7 @@ #interrupt-cells = <2>; }; - gpd7: gpd7 { + gpd7: gpd7-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -160,7 +160,7 @@ #interrupt-cells = <2>; }; - gpd8: gpd8 { + gpd8: gpd8-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -168,7 +168,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -176,7 +176,7 @@ #interrupt-cells = <2>; }; - gpg3: gpg3 { + gpg3: gpg3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -184,161 +184,161 @@ #interrupt-cells = <2>; }; - hs_i2c10_bus: hs-i2c10-bus { + hs_i2c10_bus: hs-i2c10-bus-pins { samsung,pins = "gpb0-1", "gpb0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c11_bus: hs-i2c11-bus { + hs_i2c11_bus: hs-i2c11-bus-pins { samsung,pins = "gpb0-3", "gpb0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c2_bus: hs-i2c2-bus { + hs_i2c2_bus: hs-i2c2-bus-pins { samsung,pins = "gpd0-3", "gpd0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpd0-0", "gpd0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpd0-2", "gpd0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpd1-4", "gpd1-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c3_bus: hs-i2c3-bus { + hs_i2c3_bus: hs-i2c3-bus-pins { samsung,pins = "gpd1-3", "gpd1-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpd1-0", "gpd1-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpd1-2", "gpd1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c0_bus: hs-i2c0-bus { + hs_i2c0_bus: hs-i2c0-bus-pins { samsung,pins = "gpd2-1", "gpd2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c1_bus: hs-i2c1-bus { + hs_i2c1_bus: hs-i2c1-bus-pins { samsung,pins = "gpd2-3", "gpd2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c9_bus: hs-i2c9-bus { + hs_i2c9_bus: hs-i2c9-bus-pins { samsung,pins = "gpd2-7", "gpd2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpd2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpd2-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm2_out: pwm2-out { + pwm2_out: pwm2-out-pins { samsung,pins = "gpd2-6"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - pwm3_out: pwm3-out { + pwm3_out: pwm3-out-pins { samsung,pins = "gpd2-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c8_bus: hs-i2c8-bus { + hs_i2c8_bus: hs-i2c8-bus-pins { samsung,pins = "gpd5-3", "gpd5-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpd5-0", "gpd5-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi2_bus: spi2-bus { + spi2_bus: spi2-bus-pins { samsung,pins = "gpd5-0", "gpd5-1", "gpd5-2", "gpd5-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpd6-2", "gpd6-3", "gpd6-4", "gpd6-5"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpd8-0", "gpd8-1", "gpd6-0", "gpd6-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c4_bus: hs-i2c4-bus { + hs_i2c4_bus: hs-i2c4-bus-pins { samsung,pins = "gpg3-1", "gpg3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - hs_i2c5_bus: hs-i2c5-bus { + hs_i2c5_bus: hs-i2c5-bus-pins { samsung,pins = "gpg3-3", "gpg3-2"; samsung,pin-function = ; samsung,pin-pud = ; @@ -347,7 +347,7 @@ }; &pinctrl_nfc { - gpj0: gpj0 { + gpj0: gpj0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -355,7 +355,7 @@ #interrupt-cells = <2>; }; - hs_i2c6_bus: hs-i2c6-bus { + hs_i2c6_bus: hs-i2c6-bus-pins { samsung,pins = "gpj0-1", "gpj0-0"; samsung,pin-function = ; samsung,pin-pud = ; @@ -364,7 +364,7 @@ }; &pinctrl_touch { - gpj1: gpj1 { + gpj1: gpj1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -372,7 +372,7 @@ #interrupt-cells = <2>; }; - hs_i2c7_bus: hs-i2c7-bus { + hs_i2c7_bus: hs-i2c7-bus-pins { samsung,pins = "gpj1-1", "gpj1-0"; samsung,pin-function = ; samsung,pin-pud = ; @@ -381,7 +381,7 @@ }; &pinctrl_ff { - gpg4: gpg4 { + gpg4: gpg4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -389,7 +389,7 @@ #interrupt-cells = <2>; }; - spi3_bus: spi3-bus { + spi3_bus: spi3-bus-pins { samsung,pins = "gpg4-0", "gpg4-1", "gpg4-2", "gpg4-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -398,7 +398,7 @@ }; &pinctrl_ese { - gpv7: gpv7 { + gpv7: gpv7-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -406,7 +406,7 @@ #interrupt-cells = <2>; }; - spi4_bus: spi4-bus { + spi4_bus: spi4-bus-pins { samsung,pins = "gpv7-0", "gpv7-1", "gpv7-2", "gpv7-3"; samsung,pin-function = ; samsung,pin-pud = ; @@ -415,7 +415,7 @@ }; &pinctrl_fsys0 { - gpr4: gpr4 { + gpr4: gpr4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -423,35 +423,35 @@ #interrupt-cells = <2>; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpr4-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpr4-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_cd: sd2-cd { + sd2_cd: sd2-cd-pins { samsung,pins = "gpr4-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus1: sd2-bus-width1 { + sd2_bus1: sd2-bus-width1-pins { samsung,pins = "gpr4-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd2_bus4: sd2-bus-width4 { + sd2_bus4: sd2-bus-width4-pins { samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6"; samsung,pin-function = ; samsung,pin-pud = ; @@ -460,7 +460,7 @@ }; &pinctrl_fsys1 { - gpr0: gpr0 { + gpr0: gpr0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -468,7 +468,7 @@ #interrupt-cells = <2>; }; - gpr1: gpr1 { + gpr1: gpr1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -476,7 +476,7 @@ #interrupt-cells = <2>; }; - gpr2: gpr2 { + gpr2: gpr2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -484,7 +484,7 @@ #interrupt-cells = <2>; }; - gpr3: gpr3 { + gpr3: gpr3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -492,105 +492,105 @@ #interrupt-cells = <2>; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpr0-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpr0-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_ds: sd0-ds { + sd0_ds: sd0-ds-pins { samsung,pins = "gpr0-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_qrdy: sd0-qrdy { + sd0_qrdy: sd0-qrdy-pins { samsung,pins = "gpr0-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus1: sd0-bus-width1 { + sd0_bus1: sd0-bus-width1-pins { samsung,pins = "gpr1-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus4: sd0-bus-width4 { + sd0_bus4: sd0-bus-width4-pins { samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd0_bus8: sd0-bus-width8 { + sd0_bus8: sd0-bus-width8-pins { samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gpr2-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gpr2-1"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_ds: sd1-ds { + sd1_ds: sd1-ds-pins { samsung,pins = "gpr2-2"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_qrdy: sd1-qrdy { + sd1_qrdy: sd1-qrdy-pins { samsung,pins = "gpr2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_int: sd1-int { + sd1_int: sd1-int-pins { samsung,pins = "gpr2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus1: sd1-bus-width1 { + sd1_bus1: sd1-bus-width1-pins { samsung,pins = "gpr3-0"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus4: sd1-bus-width4 { + sd1_bus4: sd1-bus-width4-pins { samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - sd1_bus8: sd1-bus-width8 { + sd1_bus8: sd1-bus-width8-pins { samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7"; samsung,pin-function = ; samsung,pin-pud = ; @@ -599,7 +599,7 @@ }; &pinctrl_bus1 { - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -607,7 +607,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -615,7 +615,7 @@ #interrupt-cells = <2>; }; - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -623,7 +623,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -631,7 +631,7 @@ #interrupt-cells = <2>; }; - gpf4: gpf4 { + gpf4: gpf4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -639,7 +639,7 @@ #interrupt-cells = <2>; }; - gpf5: gpf5 { + gpf5: gpf5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -647,7 +647,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -655,7 +655,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -663,7 +663,7 @@ #interrupt-cells = <2>; }; - gph1: gph1 { + gph1: gph1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -671,7 +671,7 @@ #interrupt-cells = <2>; }; - gpv6: gpv6 { + gpv6: gpv6-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -679,21 +679,21 @@ #interrupt-cells = <2>; }; - spi5_bus: spi5-bus { + spi5_bus: spi5-bus-pins { samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - ufs_refclk_out: ufs-refclk-out { + ufs_refclk_out: ufs-refclk-out-pins { samsung,pins = "gpg2-4"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-drv = ; }; - ufs_rst_n: ufs-rst-n { + ufs_rst_n: ufs-rst-n-pins { samsung,pins = "gph1-5"; samsung,pin-function = ; samsung,pin-pud = ; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index c3efbc8add38..e38bb02a2152 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -142,7 +142,7 @@ <0x11006000 0x2000>; }; - pdma0: pdma@10e10000 { + pdma0: dma-controller@10e10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10E10000 0x1000>; interrupts = ; @@ -153,7 +153,7 @@ #dma-requests = <32>; }; - pdma1: pdma@10eb0000 { + pdma1: dma-controller@10eb0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x10EB0000 0x1000>; interrupts = ; @@ -177,10 +177,11 @@ clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, <&clock_topc DOUT_SCLK_BUS1_PLL>, <&clock_topc DOUT_SCLK_CC_PLL>, - <&clock_topc DOUT_SCLK_MFC_PLL>; + <&clock_topc DOUT_SCLK_MFC_PLL>, + <&clock_topc DOUT_SCLK_AUD_PLL>; clock-names = "fin_pll", "dout_sclk_bus0_pll", "dout_sclk_bus1_pll", "dout_sclk_cc_pll", - "dout_sclk_mfc_pll"; + "dout_sclk_mfc_pll", "dout_sclk_aud_pll"; }; clock_top1: clock-controller@105e0000 { @@ -218,12 +219,32 @@ compatible = "samsung,exynos7-clock-peric1"; reg = <0x14c80000 0xd00>; #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, + clocks = <&fin_pll>, + <&clock_top0 DOUT_ACLK_PERIC1>, <&clock_top0 CLK_SCLK_UART1>, <&clock_top0 CLK_SCLK_UART2>, - <&clock_top0 CLK_SCLK_UART3>; - clock-names = "fin_pll", "dout_aclk_peric1_66", - "sclk_uart1", "sclk_uart2", "sclk_uart3"; + <&clock_top0 CLK_SCLK_UART3>, + <&clock_top0 CLK_SCLK_SPI0>, + <&clock_top0 CLK_SCLK_SPI1>, + <&clock_top0 CLK_SCLK_SPI2>, + <&clock_top0 CLK_SCLK_SPI3>, + <&clock_top0 CLK_SCLK_SPI4>, + <&clock_top0 CLK_SCLK_I2S1>, + <&clock_top0 CLK_SCLK_PCM1>, + <&clock_top0 CLK_SCLK_SPDIF>; + clock-names = "fin_pll", + "dout_aclk_peric1_66", + "sclk_uart1", + "sclk_uart2", + "sclk_uart3", + "sclk_spi0", + "sclk_spi1", + "sclk_spi2", + "sclk_spi3", + "sclk_spi4", + "sclk_i2s1", + "sclk_pcm1", + "sclk_spdif"; }; clock_peris: clock-controller@10040000 { @@ -663,16 +684,15 @@ reg = <0x15500000 0x100>; clocks = <&clock_fsys0 ACLK_USBDRD300>, <&clock_fsys0 OSCCLK_PHY_CLKOUT_USB30_PHY>, - <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PHYCLK_USER>, + <&clock_fsys0 PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER>, <&clock_fsys0 SCLK_USBDRD300_REFCLK>; - clock-names = "phy", "ref", "phy_pipe", - "phy_utmi", "itp"; + clock-names = "phy", "ref", "phy_utmi", "phy_pipe", "itp"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <1>; }; - usbdrd3 { + usbdrd: usb { compatible = "samsung,exynos7-dwusb3"; clocks = <&clock_fsys0 ACLK_USBDRD300>, <&clock_fsys0 SCLK_USBDRD300_SUSPENDCLK>, diff --git a/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts new file mode 100644 index 000000000000..4cf9aa25f618 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Galaxy A8 2018 (jackpotlte/SM-A530F) device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * Copyright (c) 2021 Dávid Virág + */ + +/dts-v1/; +#include "exynos7885.dtsi" +#include +#include +#include + +/ { + model = "Samsung Galaxy A8 (2018)"; + compatible = "samsung,jackpotlte", "samsung,exynos7885"; + chassis-type = "handset"; + + aliases { + serial0 = &serial_0; + serial1 = &serial_1; + serial2 = &serial_2; + }; + + chosen { + stdout-path = &serial_2; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x3da00000>, + <0x0 0xc0000000 0x40000000>, + <0x8 0x80000000 0x40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_volup &key_voldown &key_power>; + + volup-key { + label = "Volume Up"; + linux,code = ; + gpios = <&gpa1 5 GPIO_ACTIVE_LOW>; + }; + + voldown-key { + label = "Volume Down"; + linux,code = ; + gpios = <&gpa1 6 GPIO_ACTIVE_LOW>; + }; + + power-key { + label = "Power"; + linux,code = ; + gpios = <&gpa1 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; +}; + +&oscclk { + clock-frequency = <26000000>; +}; + +&pinctrl_alive { + key_volup: key-volup-pins { + samsung,pins = "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_voldown: key-voldown-pins { + samsung,pins = "gpa1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_power: key-power-pins { + samsung,pins = "gpa1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&serial_2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi new file mode 100644 index 000000000000..a50c1dbd5545 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos7885-pinctrl.dtsi @@ -0,0 +1,855 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos7885 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2017 Samsung Electronics Co., Ltd. + * Copyright (c) 2021 Dávid Virág + * + * Samsung's Exynos7885 SoC pin-mux and pin-config options are listed as + * device tree nodes in this file. + */ + +#include +#include + +&pinctrl_alive { + etc0: etc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + etc1: etc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpq0: gpq0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sim1_det_gpio: sim1-det-gpio-pins { + samsung,pins = "gpa2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sim0_det_gpio: sim0-det-gpio-pins { + samsung,pins = "gpa2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + speedy_bus: speedy-bus-pins { + samsung,pins = "gpq0-2"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* UART_DEBUG */ + uart2_bus: uart2-bus-pins { + samsung,pins = "gpq0-4", "gpq0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_dispaud { + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb2: gpb2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + aud_codec_mclk: aud-codec-mclk-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_mclk_idle: aud-codec-mclk-idle-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_bus: aud-codec-bus-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_bus_idle: aud-codec-bus-idle-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_loopback_bus: aud-loopback-bus-pins { + samsung,pins = "gpb1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_loopback_bus_idle: aud-loopback-bus-idle-pins { + samsung,pins = "gpb1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_bus: aud-fm-bus-pins { + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_bus_idle: aud-fm-bus-idle-pins { + samsung,pins = "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_spk_bus: aud-spk-bus-pins { + samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_spk_bus_idle: aud-spk-bus-idle-pins { + samsung,pins = "gpb2-0", "gpb2-1", "gpb2-2", "gpb2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_fsys { + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf4: gpf4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd: sd0-cmd-pins { + samsung,pins = "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_rdqs: sd0-rdqs-pins { + samsung,pins = "gpf0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1: sd0-bus-width1-pins { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4: sd0-bus-width4-pins { + samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8: sd0-bus-width8-pins { + samsung,pins = "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk: sd1-clk-pins { + samsung,pins = "gpf3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk_fast_slew_rate_1x: sd1-clk-fast-slew-rate-1x-pins { + samsung,pins = "gpf3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk_fast_slew_rate_2x: sd1-clk-fast-slew-rate-2x-pins { + samsung,pins = "gpf3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk_fast_slew_rate_3x: sd1-clk-fast-slew-rate-3x-pins { + samsung,pins = "gpf3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_clk_fast_slew_rate_4x: sd1-clk-fast-slew-rate-4x-pins { + samsung,pins = "gpf3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_cmd: sd1-cmd-pins { + samsung,pins = "gpf3-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus1: sd1-bus-width1-pins { + samsung,pins = "gpf3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd1_bus4: sd1-bus-width4-pins { + samsung,pins = "gpf3-3", "gpf3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk: sd2-clk-pins { + samsung,pins = "gpf4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x-pins { + samsung,pins = "gpf4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x-pins { + samsung,pins = "gpf4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x-pins { + samsung,pins = "gpf4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x-pins { + samsung,pins = "gpf4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd: sd2-cmd-pins { + samsung,pins = "gpf4-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1: sd2-bus-width1-pins { + samsung,pins = "gpf4-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4: sd2-bus-width4-pins { + samsung,pins = "gpf4-3", "gpf4-4", "gpf4-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_top { + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc2: gpc2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg4: gpg4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp0: gpp0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp1: gpp1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp3: gpp3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp4: gpp4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp5: gpp5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp6: gpp6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp7: gpp7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp8: gpp8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + hs_i2c0_bus: hs-i2c0-bus-pins { + samsung,pins = "gpc1-1", "gpc1-0"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c1_bus: hs-i2c1-bus-pins { + samsung,pins = "gpc1-3", "gpc1-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + hs_i2c2_bus: hs-i2c2-bus-pins { + samsung,pins = "gpc1-5", "gpc1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + hs_i2c3_bus: hs-i2c3-bus-pins { + samsung,pins = "gpc1-7", "gpc1-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI0 UART */ + uart3_bus_single: uart3-bus-single-pins { + samsung,pins = "gpc2-3", "gpc2-2", "gpc2-1", "gpc2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI0 UART_HSI2C1 */ + uart3_bus_dual: uart3-bus-dual-pins { + samsung,pins = "gpc2-1", "gpc2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI0 HSI2C0 */ + hs_i2c4_bus: hs-i2c4-bus-pins { + samsung,pins = "gpc2-1", "gpc2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI0 HSI2C1 */ + hs_i2c5_bus: hs-i2c5-bus-pins { + samsung,pins = "gpc2-3", "gpc2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI0 SPI */ + spi2_bus: spi2-bus-pins { + samsung,pins = "gpc2-1", "gpc2-0", "gpc2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_cs: spi2-cs-pins { + samsung,pins = "gpc2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI1 UART */ + uart4_bus_single: uart4-bus-single-pins { + samsung,pins = "gpc2-7", "gpc2-6", "gpc2-5", "gpc2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI1 UART_HSI2C1*/ + uart4_bus_dual: uart4-bus-dual-pins { + samsung,pins = "gpc2-5", "gpc2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI1 HSI2C0 */ + hs_i2c6_bus: hs-i2c6-bus-pins { + samsung,pins = "gpc2-5", "gpc2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI1 HSI2C1 */ + hs_i2c7_bus: hs-i2c7-bus-pins { + samsung,pins = "gpc2-7", "gpc2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI1 SPI */ + spi3_bus: spi3-bus-pins { + samsung,pins = "gpc2-5", "gpc2-4", "gpc2-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi3_cs: spi3-cs-pins { + samsung,pins = "gpc2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + fm_lna_en: fm-lna-en-pins { + samsung,pins = "gpg0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + samsung,pin-val = <1>; + }; + + uart1_bus: uart1-bus-pins { + samsung,pins = "gpg1-3", "gpg1-2", "gpg1-1", "gpg1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2c7_bus: i2c7-bus-pins { + samsung,pins = "gpg1-5", "gpg1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + aud_dmic_on: aud-dmic-on-pins { + samsung,pins = "gpg2-1"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-val = <1>; + }; + + aud_dmic_off: aud-dmic-off-pins { + samsung,pins = "gpg2-1"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-val = <0>; + }; + + /* UART_HEALTH */ + uart0_bus: uart0-bus-pins { + samsung,pins = "gpp0-3", "gpp0-2", "gpp0-1", "gpp0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + i2c0_bus: i2c0-bus-pins { + samsung,pins = "gpp1-1", "gpp1-0"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_bus: i2c1-bus-pins { + samsung,pins = "gpp1-3", "gpp1-2"; + samsung,pin-function = ; + samsung,pin-con-pdn = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_bus: i2c2-bus-pins { + samsung,pins = "gpp2-1", "gpp2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_bus: i2c3-bus-pins { + samsung,pins = "gpp3-1", "gpp3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_bus: i2c4-bus-pins { + samsung,pins = "gpp4-1", "gpp4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c5_bus: i2c5-bus-pins { + samsung,pins = "gpp4-3", "gpp4-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c6_bus: i2c6-bus-pins { + samsung,pins = "gpp4-5", "gpp4-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* SPI_ESE */ + spi0_bus: spi0-bus-pins { + samsung,pins = "gpp5-3", "gpp5-2", "gpp5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_cs: spi0-cs-pins { + samsung,pins = "gpp5-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* SPI_FP */ + spi1_bus: spi1-bus-pins { + samsung,pins = "gpp6-3", "gpp6-2", "gpp6-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_cs: spi1-cs-pins { + samsung,pins = "gpp6-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI2 UART */ + uart5_bus_single: uart5-bus-single-pins { + samsung,pins = "gpp8-1", "gpp8-0", "gpp7-1", "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI2 UART_HSI2C1 */ + uart5_bus_dual: uart5-bus-dual-pins { + samsung,pins = "gpp7-1", "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI2 HSI2C0 */ + hs_i2c8_bus: hs-i2c8-bus-pins { + samsung,pins = "gpp7-1", "gpp7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI2 HSI2C1 */ + hs_i2c9_bus: hs-i2c9-bus-pins { + samsung,pins = "gpp8-1", "gpp8-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + samsung,pin-con-pdn = ; + samsung,pin-pud-pdn = ; + }; + + /* USI2 SPI */ + spi4_bus: spi4-bus-pins { + samsung,pins = "gpp7-1", "gpp7-0", "gpp8-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi4_cs: spi4-cs-pins { + samsung,pins = "gpp8-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi new file mode 100644 index 000000000000..3170661f5b67 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos7885 SoC device tree source + * + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * Copyright (c) 2021 Dávid Virág + */ + +#include +#include + +/ { + compatible = "samsung,exynos7885"; + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_dispaud; + pinctrl2 = &pinctrl_fsys; + pinctrl3 = &pinctrl_top; + }; + + arm-a53-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + , + , + ; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>, + <&cpu4>, + <&cpu5>; + }; + + arm-a73-pmu { + compatible = "arm,cortex-a73-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu6>, + <&cpu7>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + core4 { + cpu = <&cpu4>; + }; + core5 { + cpu = <&cpu5>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu6>; + }; + core1 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + }; + + cpu1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + }; + + cpu2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + }; + + cpu3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + }; + + cpu4: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x200>; + enable-method = "psci"; + }; + + cpu5: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x201>; + enable-method = "psci"; + }; + + cpu6: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0>; + enable-method = "psci"; + }; + + cpu7: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x1>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts = , + , + , + ; + }; + + fixed-rate-clocks { + oscclk: osc-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "oscclk"; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + chipid@10000000 { + compatible = "samsung,exynos850-chipid"; + reg = <0x10000000 0x24>; + }; + + gic: interrupt-controller@12301000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x12301000 0x1000>, + <0x12302000 0x2000>, + <0x12304000 0x2000>, + <0x12306000 0x2000>; + interrupts = ; + }; + + cmu_peri: clock-controller@10010000 { + compatible = "samsung,exynos7885-cmu-peri"; + reg = <0x10010000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_SPI0>, + <&cmu_top CLK_DOUT_PERI_SPI1>, + <&cmu_top CLK_DOUT_PERI_UART0>, + <&cmu_top CLK_DOUT_PERI_UART1>, + <&cmu_top CLK_DOUT_PERI_UART2>, + <&cmu_top CLK_DOUT_PERI_USI0>, + <&cmu_top CLK_DOUT_PERI_USI1>, + <&cmu_top CLK_DOUT_PERI_USI2>; + clock-names = "oscclk", + "dout_peri_bus", + "dout_peri_spi0", + "dout_peri_spi1", + "dout_peri_uart0", + "dout_peri_uart1", + "dout_peri_uart2", + "dout_peri_usi0", + "dout_peri_usi1", + "dout_peri_usi2"; + }; + + cmu_core: clock-controller@12000000 { + compatible = "samsung,exynos7885-cmu-core"; + reg = <0x12000000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CORE_BUS>, + <&cmu_top CLK_DOUT_CORE_CCI>, + <&cmu_top CLK_DOUT_CORE_G3D>; + clock-names = "oscclk", + "dout_core_bus", + "dout_core_cci", + "dout_core_g3d"; + }; + + cmu_top: clock-controller@12060000 { + compatible = "samsung,exynos7885-cmu-top"; + reg = <0x12060000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>; + clock-names = "oscclk"; + }; + + pinctrl_alive: pinctrl@11cb0000 { + compatible = "samsung,exynos7885-pinctrl"; + reg = <0x11cb0000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pinctrl_fsys: pinctrl@13430000 { + compatible = "samsung,exynos7885-pinctrl"; + reg = <0x13430000 0x1000>; + interrupts = ; + }; + + pinctrl_top: pinctrl@139b0000 { + compatible = "samsung,exynos7885-pinctrl"; + reg = <0x139b0000 0x1000>; + interrupts = ; + }; + + pinctrl_dispaud: pinctrl@148f0000 { + compatible = "samsung,exynos7885-pinctrl"; + reg = <0x148f0000 0x1000>; + interrupts = ; + }; + + pmu_system_controller: system-controller@11c80000 { + compatible = "samsung,exynos7-pmu", "syscon"; + reg = <0x11c80000 0x10000>; + }; + + serial_0: serial@13800000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x13800000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>, + <&cmu_peri CLK_GOUT_UART0_PCLK>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + serial_1: serial@13810000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x13810000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_bus>; + clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>, + <&cmu_peri CLK_GOUT_UART1_PCLK>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + + serial_2: serial@13820000 { + compatible = "samsung,exynos5433-uart"; + reg = <0x13820000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_bus>; + clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>, + <&cmu_peri CLK_GOUT_UART2_PCLK>; + clock-names = "uart", "clk_uart_baud0"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + + i2c_0: i2c@13830000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13830000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_1: i2c@13840000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13840000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_2: i2c@13850000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13850000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_3: i2c@13860000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_4: i2c@13870000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_5: i2c@13880000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_6: i2c@13890000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_7: i2c@11cd0000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x11cd0000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; + clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + }; +}; + +#include "exynos7885-pinctrl.dtsi" +#include "arm/exynos-syscon-restart.dtsi" diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts new file mode 100644 index 000000000000..7b5a61d22cc5 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * WinLink E850-96 board device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Device tree source file for WinLink's E850-96 board which is based on + * Samsung Exynos850 SoC. + */ + +/dts-v1/; + +#include "exynos850.dtsi" +#include +#include +#include + +/ { + model = "WinLink E850-96 board"; + compatible = "winlink,e850-96", "samsung,exynos850"; + + chosen { + stdout-path = &serial_0; + }; + + /* + * RAM: 4 GiB (eMCP): + * - 2 GiB at 0x80000000 + * - 2 GiB at 0x880000000 + * + * 0xbab00000..0xbfffffff: secure memory (85 MiB). + */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x3ab00000>, + <0x0 0xc0000000 0x40000000>, + <0x8 0x80000000 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_voldown_pins &key_volup_pins>; + + volume-down-key { + label = "Volume Down"; + linux,code = ; + gpios = <&gpa1 0 GPIO_ACTIVE_LOW>; + }; + + volume-up-key { + label = "Volume Up"; + linux,code = ; + gpios = <&gpa0 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + /* HEART_BEAT_LED */ + user_led1: led-1 { + label = "yellow:user1"; + gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + + /* eMMC_LED */ + user_led2: led-2 { + label = "yellow:user2"; + gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>; + color = ; + linux,default-trigger = "mmc0"; + }; + + /* SD_LED */ + user_led3: led-3 { + label = "white:user3"; + gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_SD; + linux,default-trigger = "mmc2"; + }; + + /* WIFI_LED */ + wlan_active_led: led-4 { + label = "yellow:wlan"; + gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + /* BLUETOOTH_LED */ + bt_active_led: led-5 { + label = "blue:bt"; + gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_BLUETOOTH; + linux,default-trigger = "hci0rx"; + default-state = "off"; + }; + }; + + /* + * RTC clock (XrtcXTI); external, must be 32.768 kHz. + * + * TODO: Remove this once RTC clock is implemented properly as part of + * PMIC driver. + */ + rtcclk: clock-rtcclk { + compatible = "fixed-clock"; + clock-output-names = "rtcclk"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; +}; + +&cmu_hsi { + clocks = <&oscclk>, <&rtcclk>, + <&cmu_top CLK_DOUT_HSI_BUS>, + <&cmu_top CLK_DOUT_HSI_MMC_CARD>, + <&cmu_top CLK_DOUT_HSI_USB20DRD>; + clock-names = "oscclk", "rtcclk", "dout_hsi_bus", + "dout_hsi_mmc_card", "dout_hsi_usb20drd"; +}; + +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + mmc-hs400-enhanced-strobe; + card-detect-delay = <200>; + clock-frequency = <800000000>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + samsung,dw-mshc-hs400-timing = <0 2>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins + &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>; +}; + +&oscclk { + clock-frequency = <26000000>; +}; + +&pinctrl_alive { + key_voldown_pins: key-voldown-pins { + samsung,pins = "gpa1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_volup_pins: key-volup-pins { + samsung,pins = "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>; + clock-names = "rtc", "rtc_src"; +}; + +&serial_0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&usi_uart { + samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; +}; + +&watchdog_cl0 { + status = "okay"; +}; + +&watchdog_cl1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi new file mode 100644 index 000000000000..f43e4a206282 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source + * + * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include +#include + +&pinctrl_alive { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa3: gpa3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa4: gpa4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + gpq0: gpq0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ + i2c5_pins: i2c5-pins { + samsung,pins = "gpa3-5", "gpa3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* I2C6 (also called MOTOR_I2C in TRM) */ + i2c6_pins: i2c6-pins { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: UART_DEBUG_0 pins */ + uart0_pins: uart0-pins { + samsung,pins = "gpq0-0", "gpq0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI: UART_DEBUG_1 pins */ + uart1_pins: uart1-pins { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_cmgp { + gpm0: gpm0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm1: gpm1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm2: gpm2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm3: gpm3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm4: gpm4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm5: gpm5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm6: gpm6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm7: gpm7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + /* USI_CMGP0: HSI2C function */ + hsi2c3_pins: hsi2c3-pins { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */ + uart1_single_pins: uart1-single-pins { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */ + uart1_dual_pins: uart1-dual-pins { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: SPI function */ + spi1_pins: spi1-pins { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI_CMGP1: HSI2C function */ + hsi2c4_pins: hsi2c4-pins { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */ + uart2_single_pins: uart2-single-pins { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */ + uart2_dual_pins: uart2-dual-pins { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: SPI function */ + spi2_pins: spi2-pins { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_aud { + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + aud_codec_mclk_pins: aud-codec-mclk-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_pins: aud-i2s0-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_idle_pins: aud-i2s0-idle-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_pins: aud-i2s1-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_idle_pins: aud-i2s1-idle-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_pins: aud-fm-pins { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_idle_pins: aud-fm-idle-pins { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_hsi { + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd2_clk_pins: sd2-clk-pins { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd_pins: sd2-cmd-pins { + samsung,pins = "gpf2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1_pins: sd2-bus1-pins { + samsung,pins = "gpf2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4_pins: sd2-bus4-pins { + samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_pdn_pins: sd2-pdn-pins { + samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_core { + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk_pins: sd0-clk-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd_pins: sd0-cmd-pins { + samsung,pins = "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_rdqs_pins: sd0-rdqs-pins { + samsung,pins = "gpf0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_nreset_pins: sd0-nreset-pins { + samsung,pins = "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1_pins: sd0-bus1-pins { + samsung,pins = "gpf1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4_pins: sd0-bus4-pins { + samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8_pins: sd0-bus8-pins { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_peri { + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp0: gpp0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp1: gpp1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sensor_mclk0_in_pins: sensor-mclk0-in-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk0_out_pins: sensor-mclk0-out-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk0_fn_pins: sensor-mclk0-fn-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk1_in_pins: sensor-mclk1-in-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk1_out_pins: sensor-mclk1-out-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk1_fn_pins: sensor-mclk1-fn-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk2_in_pins: sensor-mclk2-in-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk2_out_pins: sensor-mclk2-out-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk2_fn_pins: sensor-mclk2-fn-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: HSI2C0 */ + hsi2c0_pins: hsi2c0-pins { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: HSI2C1 */ + hsi2c1_pins: hsi2c1-pins { + samsung,pins = "gpc1-2", "gpc1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: HSI2C2 */ + hsi2c2_pins: hsi2c2-pins { + samsung,pins = "gpc1-4", "gpc1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: SPI */ + spi0_pins: spi0-pins { + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_pins: i2c0-pins { + samsung,pins = "gpp0-0", "gpp0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_pins: i2c1-pins { + samsung,pins = "gpp0-2", "gpp0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_pins: i2c2-pins { + samsung,pins = "gpp0-4", "gpp0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_pins: i2c3-pins { + samsung,pins = "gpp1-0", "gpp1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_pins: i2c4-pins { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + xclkout_pins: xclkout-pins { + samsung,pins = "gpq0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi new file mode 100644 index 000000000000..d1700e96fee2 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -0,0 +1,701 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos850 SoC device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung Exynos850 SoC device nodes are listed in this file. + * Exynos850 based board files can include this file and provide + * values for board specific bindings. + */ + +#include +#include +#include + +/ { + /* Also known under engineering name Exynos3830 */ + compatible = "samsung,exynos850"; + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_cmgp; + pinctrl2 = &pinctrl_aud; + pinctrl3 = &pinctrl_hsi; + pinctrl4 = &pinctrl_core; + pinctrl5 = &pinctrl_peri; + mmc0 = &mmc_0; + serial0 = &serial_0; + serial1 = &serial_1; + serial2 = &serial_2; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &hsi2c_0; + i2c8 = &hsi2c_1; + i2c9 = &hsi2c_2; + i2c10 = &hsi2c_3; + i2c11 = &hsi2c_4; + }; + + arm-pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* Main system clock (XTCXO); external, must be 26 MHz */ + oscclk: clock-oscclk { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x1>; + enable-method = "psci"; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x2>; + enable-method = "psci"; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x3>; + enable-method = "psci"; + }; + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + }; + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x101>; + enable-method = "psci"; + }; + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x102>; + enable-method = "psci"; + }; + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x103>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts = + , + , + , + ; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + chipid@10000000 { + compatible = "samsung,exynos850-chipid"; + reg = <0x10000000 0x100>; + }; + + timer@10040000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10040000 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + }; + + gic: interrupt-controller@12a01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0x12a01000 0x1000>, + <0x12a02000 0x2000>, + <0x12a04000 0x2000>, + <0x12a06000 0x2000>; + interrupt-controller; + interrupts = ; + }; + + pmu_system_controller: system-controller@11860000 { + compatible = "samsung,exynos850-pmu", "syscon"; + reg = <0x11860000 0x10000>; + clocks = <&cmu_apm CLK_GOUT_PMU_ALIVE_PCLK>; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ + mask = <0x2>; /* SWRESET_SYSTEM */ + value = <0x2>; /* reset value */ + }; + }; + + watchdog_cl0: watchdog@10050000 { + compatible = "samsung,exynos850-wdt"; + reg = <0x10050000 0x100>; + interrupts = ; + clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <0>; + status = "disabled"; + }; + + watchdog_cl1: watchdog@10060000 { + compatible = "samsung,exynos850-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <1>; + status = "disabled"; + }; + + cmu_peri: clock-controller@10030000 { + compatible = "samsung,exynos850-cmu-peri"; + reg = <0x10030000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_UART>, + <&cmu_top CLK_DOUT_PERI_IP>; + clock-names = "oscclk", "dout_peri_bus", + "dout_peri_uart", "dout_peri_ip"; + }; + + cmu_apm: clock-controller@11800000 { + compatible = "samsung,exynos850-cmu-apm"; + reg = <0x11800000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; + clock-names = "oscclk", "dout_clkcmu_apm_bus"; + }; + + cmu_cmgp: clock-controller@11c00000 { + compatible = "samsung,exynos850-cmu-cmgp"; + reg = <0x11c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; + clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; + }; + + cmu_core: clock-controller@12000000 { + compatible = "samsung,exynos850-cmu-core"; + reg = <0x12000000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, + <&cmu_top CLK_DOUT_CORE_CCI>, + <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, + <&cmu_top CLK_DOUT_CORE_SSS>; + clock-names = "oscclk", "dout_core_bus", + "dout_core_cci", "dout_core_mmc_embd", + "dout_core_sss"; + }; + + cmu_top: clock-controller@120e0000 { + compatible = "samsung,exynos850-cmu-top"; + reg = <0x120e0000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>; + clock-names = "oscclk"; + }; + + cmu_dpu: clock-controller@13000000 { + compatible = "samsung,exynos850-cmu-dpu"; + reg = <0x13000000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; + clock-names = "oscclk", "dout_dpu"; + }; + + cmu_hsi: clock-controller@13400000 { + compatible = "samsung,exynos850-cmu-hsi"; + reg = <0x13400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_HSI_BUS>, + <&cmu_top CLK_DOUT_HSI_MMC_CARD>, + <&cmu_top CLK_DOUT_HSI_USB20DRD>; + clock-names = "oscclk", "dout_hsi_bus", + "dout_hsi_mmc_card", "dout_hsi_usb20drd"; + }; + + pinctrl_alive: pinctrl@11850000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11850000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos850-wakeup-eint"; + }; + }; + + pinctrl_cmgp: pinctrl@11c30000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11c30000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos850-wakeup-eint"; + }; + }; + + pinctrl_core: pinctrl@12070000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x12070000 0x1000>; + interrupts = ; + }; + + pinctrl_hsi: pinctrl@13430000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x13430000 0x1000>; + interrupts = ; + }; + + pinctrl_peri: pinctrl@139b0000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x139b0000 0x1000>; + interrupts = ; + }; + + pinctrl_aud: pinctrl@14a60000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x14a60000 0x1000>; + }; + + rtc: rtc@11a30000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x11a30000 0x100>; + interrupts = , + ; + clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; + clock-names = "rtc"; + status = "disabled"; + }; + + mmc_0: mmc@12100000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + reg = <0x12100000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, + <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + i2c_0: i2c@13830000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13830000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_1: i2c@13840000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13840000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_2: i2c@13850000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13850000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_3: i2c@13860000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_4: i2c@13870000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ + i2c_5: i2c@13880000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + /* I2C_6 (also called MOTOR_I2C in TRM) */ + i2c_6: i2c@13890000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + sysreg_peri: syscon@10020000 { + compatible = "samsung,exynos850-sysreg", "syscon"; + reg = <0x10020000 0x10000>; + clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; + }; + + sysreg_cmgp: syscon@11c20000 { + compatible = "samsung,exynos850-sysreg", "syscon"; + reg = <0x11c20000 0x10000>; + clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; + }; + + usi_uart: usi@138200c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138200c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1010>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, + <&cmu_peri CLK_GOUT_UART_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_0: serial@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x13820000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, + <&cmu_peri CLK_GOUT_UART_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + + usi_hsi2c_0: usi@138a00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138a00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1020>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_0: i2c@138a0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138a0000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c0_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_hsi2c_1: usi@138b00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138b00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1030>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_1: i2c@138b0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138b0000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c1_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_hsi2c_2: usi@138c00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138c00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1040>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_2: i2c@138c0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138c0000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c2_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_spi_0: usi@139400c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x139400c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1050>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, + <&cmu_peri CLK_GOUT_SPI0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + }; + + usi_cmgp0: usi@11d000c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x11d000c0 0x20>; + samsung,sysreg = <&sysreg_cmgp 0x2000>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_3: i2c@11d00000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x11d00000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c3_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + + serial_1: serial@11d00000 { + compatible = "samsung,exynos850-uart"; + reg = <0x11d00000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_single_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + + usi_cmgp1: usi@11d200c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x11d200c0 0x20>; + samsung,sysreg = <&sysreg_cmgp 0x2010>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_4: i2c@11d20000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x11d20000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c4_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + + serial_2: serial@11d20000 { + compatible = "samsung,exynos850-uart"; + reg = <0x11d20000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_single_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + }; +}; + +#include "exynos850-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi index 2407b03b5404..ef0349d1c3d0 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi @@ -11,7 +11,7 @@ #include &pinctrl_alive { - gpa0: gpa0 { + gpa0: gpa0-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -27,7 +27,7 @@ ; }; - gpa1: gpa1 { + gpa1: gpa1-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -47,7 +47,7 @@ samsung,pin-function = ; }; - gpq0: gpq0 { + gpq0: gpq0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -69,7 +69,7 @@ }; &pinctrl_aud { - gpb0: gpb0 { + gpb0: gpb0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -77,7 +77,7 @@ #interrupt-cells = <2>; }; - gpb1: gpb1 { + gpb1: gpb1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -85,7 +85,7 @@ #interrupt-cells = <2>; }; - gpb2: gpb2 { + gpb2: gpb2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -93,7 +93,7 @@ #interrupt-cells = <2>; }; - gpb3: gpb3 { + gpb3: gpb3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -199,7 +199,7 @@ }; &pinctrl_fsys0 { - gpf0: gpf0 { + gpf0: gpf0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -207,7 +207,7 @@ #interrupt-cells = <2>; }; - gpf1: gpf1 { + gpf1: gpf1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -355,7 +355,7 @@ }; &pinctrl_fsys1 { - gpf8: gpf8 { + gpf8: gpf8-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -393,7 +393,7 @@ }; &pinctrl_fsys2 { - gpf2: gpf2 { + gpf2: gpf2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -401,7 +401,7 @@ #interrupt-cells = <2>; }; - gpf3: gpf3 { + gpf3: gpf3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -409,7 +409,7 @@ #interrupt-cells = <2>; }; - gpf4: gpf4 { + gpf4: gpf4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -417,7 +417,7 @@ #interrupt-cells = <2>; }; - gpf5: gpf5 { + gpf5: gpf5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -425,7 +425,7 @@ #interrupt-cells = <2>; }; - gpf6: gpf6 { + gpf6: gpf6-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -499,7 +499,7 @@ }; &pinctrl_peric0 { - gpp0: gpp0 { + gpp0: gpp0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -507,7 +507,7 @@ #interrupt-cells = <2>; }; - gpp1: gpp1 { + gpp1: gpp1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -515,7 +515,7 @@ #interrupt-cells = <2>; }; - gpp2: gpp2 { + gpp2: gpp2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -523,7 +523,7 @@ #interrupt-cells = <2>; }; - gpg0: gpg0 { + gpg0: gpg0-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -833,7 +833,7 @@ }; &pinctrl_peric1 { - gpp3: gpp3 { + gpp3: gpp3-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -841,7 +841,7 @@ #interrupt-cells = <2>; }; - gpp4: gpp4 { + gpp4: gpp4-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -849,7 +849,7 @@ #interrupt-cells = <2>; }; - gpp5: gpp5 { + gpp5: gpp5-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -857,7 +857,7 @@ #interrupt-cells = <2>; }; - gpg1: gpg1 { + gpg1: gpg1-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -865,7 +865,7 @@ #interrupt-cells = <2>; }; - gpg2: gpg2 { + gpg2: gpg2-gpio-bank { gpio-controller; #gpio-cells = <2>; @@ -873,7 +873,7 @@ #interrupt-cells = <2>; }; - gpg3: gpg3 { + gpg3: gpg3-gpio-bank { gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index de8fcb82eaec..807d500d6022 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -208,7 +208,7 @@ reg = <0x10450000 0x1000>; wakeup-interrupt-controller { - compatible = "samsung,exynos7-wakeup-eint"; + compatible = "samsung,exynosautov9-wakeup-eint"; }; }; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 6d8f0a532587..7f51b537df40 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -1,14 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -# required for overlay support -DTC_FLAGS_fsl-ls1028a-qds := -@ -DTC_FLAGS_fsl-ls1028a-qds-13bb := -@ -DTC_FLAGS_fsl-ls1028a-qds-65bb := -@ -DTC_FLAGS_fsl-ls1028a-qds-7777 := -@ -DTC_FLAGS_fsl-ls1028a-qds-85bb := -@ -DTC_FLAGS_fsl-ls1028a-qds-899b := -@ -DTC_FLAGS_fsl-ls1028a-qds-9999 := -@ - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb @@ -21,12 +12,6 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb -dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb @@ -49,9 +34,24 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb +fsl-ls1028a-qds-13bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-13bb.dtbo +fsl-ls1028a-qds-65bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-65bb.dtbo +fsl-ls1028a-qds-7777-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-7777.dtbo +fsl-ls1028a-qds-85bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-85bb.dtbo +fsl-ls1028a-qds-899b-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-899b.dtbo +fsl-ls1028a-qds-9999-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-9999.dtbo + +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb -dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb @@ -63,6 +63,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb @@ -94,6 +99,24 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb +imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo +imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo +imx8mm-venice-gw72xx-0x-rs422-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs422.dtbo +imx8mm-venice-gw72xx-0x-rs485-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs485.dtbo +imx8mm-venice-gw73xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo +imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo +imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo +imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo + +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs422.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs485.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-imx219.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb + dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts index f748a2c12a70..f826392c23fa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts @@ -12,102 +12,80 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - slot1_sgmii: ethernet-phy@2 { - /* AQR112 */ - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - }; - }; - - fragment@1 { - target = <&enetc_port0>; - - __overlay__ { - phy-handle = <&slot1_sgmii>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - status = "okay"; - }; - }; - - fragment@2 { - target = <&mdio_slot2>; - - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on AQR412 */ - slot2_qxgmii0: ethernet-phy@0 { - reg = <0x0>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot2_qxgmii1: ethernet-phy@1 { - reg = <0x1>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot2_qxgmii2: ethernet-phy@2 { - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot2_qxgmii3: ethernet-phy@3 { - reg = <0x3>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - }; - }; - - fragment@3 { - target = <&mscc_felix_ports>; - - __overlay__ { - port@0 { - status = "okay"; - phy-handle = <&slot2_qxgmii0>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; - - port@1 { - status = "okay"; - phy-handle = <&slot2_qxgmii1>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot2_qxgmii2>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; - - port@3 { - status = "okay"; - phy-handle = <&slot2_qxgmii3>; - phy-mode = "usxgmii"; - managed = "in-band-status"; - }; - }; - }; - - fragment@4 { - target = <&mscc_felix>; - - __overlay__ { - status = "okay"; - }; + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; }; }; + +&enetc_port0 { + phy-handle = <&slot1_sgmii>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&mdio_slot2 { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on AQR412 */ + slot2_qxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot2_qxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; +}; + +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot2_qxgmii0>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qxgmii1>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qxgmii2>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qxgmii3>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + }; +}; + +&mscc_felix { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts index 8ffb707a1576..40d34c8384a5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts @@ -11,98 +11,76 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - slot1_sgmii: ethernet-phy@2 { - /* AQR112 */ - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - }; - }; - - fragment@1 { - target = <&enetc_port0>; - - __overlay__ { - phy-handle = <&slot1_sgmii>; - phy-mode = "2500base-x"; - managed = "in-band-status"; - status = "okay"; - }; - }; - - fragment@2 { - target = <&mdio_slot2>; - - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on VSC8514 */ - slot2_qsgmii0: ethernet-phy@8 { - reg = <0x8>; - }; - - slot2_qsgmii1: ethernet-phy@9 { - reg = <0x9>; - }; - - slot2_qsgmii2: ethernet-phy@a { - reg = <0xa>; - }; - - slot2_qsgmii3: ethernet-phy@b { - reg = <0xb>; - }; - }; - }; - - fragment@3 { - target = <&mscc_felix_ports>; - - __overlay__ { - port@0 { - status = "okay"; - phy-handle = <&slot2_qsgmii0>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@1 { - status = "okay"; - phy-handle = <&slot2_qsgmii1>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot2_qsgmii2>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@3 { - status = "okay"; - phy-handle = <&slot2_qsgmii3>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - }; - }; - - fragment@4 { - target = <&mscc_felix>; - - __overlay__ { - status = "okay"; - }; + slot1_sgmii: ethernet-phy@2 { + /* AQR112 */ + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; }; }; + +&enetc_port0 { + phy-handle = <&slot1_sgmii>; + phy-mode = "2500base-x"; + managed = "in-band-status"; + status = "okay"; +}; + +&mdio_slot2 { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; +}; + +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; +}; + +&mscc_felix { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts index eb6a1e674f10..1dff68d7484b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts @@ -12,71 +12,58 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on AQR412 */ - slot1_sxgmii0: ethernet-phy@0 { - reg = <0x0>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot1_sxgmii1: ethernet-phy@1 { - reg = <0x1>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot1_sxgmii2: ethernet-phy@2 { - reg = <0x2>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - - slot1_sxgmii3: ethernet-phy@3 { - reg = <0x3>; - compatible = "ethernet-phy-ieee802.3-c45"; - }; - }; + /* 4 ports on AQR412 */ + slot1_sxgmii0: ethernet-phy@0 { + reg = <0x0>; + compatible = "ethernet-phy-ieee802.3-c45"; }; - fragment@1 { - target = <&mscc_felix_ports>; - - __overlay__ { - port@0 { - status = "okay"; - phy-handle = <&slot1_sxgmii0>; - phy-mode = "2500base-x"; - }; - - port@1 { - status = "okay"; - phy-handle = <&slot1_sxgmii1>; - phy-mode = "2500base-x"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot1_sxgmii2>; - phy-mode = "2500base-x"; - }; - - port@3 { - status = "okay"; - phy-handle = <&slot1_sxgmii3>; - phy-mode = "2500base-x"; - }; - }; + slot1_sxgmii1: ethernet-phy@1 { + reg = <0x1>; + compatible = "ethernet-phy-ieee802.3-c45"; }; - fragment@2 { - target = <&mscc_felix>; - __overlay__ { - status = "okay"; - }; + slot1_sxgmii2: ethernet-phy@2 { + reg = <0x2>; + compatible = "ethernet-phy-ieee802.3-c45"; + }; + + slot1_sxgmii3: ethernet-phy@3 { + reg = <0x3>; + compatible = "ethernet-phy-ieee802.3-c45"; }; }; + +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot1_sxgmii0>; + phy-mode = "2500base-x"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sxgmii1>; + phy-mode = "2500base-x"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sxgmii2>; + phy-mode = "2500base-x"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sxgmii3>; + phy-mode = "2500base-x"; + }; +}; + +&mscc_felix { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts index 8e90c3088ba1..19424d349713 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts @@ -11,97 +11,75 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - slot1_sgmii: ethernet-phy@1c { - /* 1st port on VSC8234 */ - reg = <0x1c>; - }; - }; - }; - - fragment@1 { - target = <&enetc_port0>; - - __overlay__ { - phy-handle = <&slot1_sgmii>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; - }; - }; - - fragment@2 { - target = <&mdio_slot2>; - - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - - /* 4 ports on VSC8514 */ - slot2_qsgmii0: ethernet-phy@8 { - reg = <0x8>; - }; - - slot2_qsgmii1: ethernet-phy@9 { - reg = <0x9>; - }; - - slot2_qsgmii2: ethernet-phy@a { - reg = <0xa>; - }; - - slot2_qsgmii3: ethernet-phy@b { - reg = <0xb>; - }; - }; - }; - - fragment@3 { - target = <&mscc_felix_ports>; - - __overlay__ { - port@0 { - status = "okay"; - phy-handle = <&slot2_qsgmii0>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@1 { - status = "okay"; - phy-handle = <&slot2_qsgmii1>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot2_qsgmii2>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - - port@3 { - status = "okay"; - phy-handle = <&slot2_qsgmii3>; - phy-mode = "qsgmii"; - managed = "in-band-status"; - }; - }; - }; - - fragment@4 { - target = <&mscc_felix>; - - __overlay__ { - status = "okay"; - }; + slot1_sgmii: ethernet-phy@1c { + /* 1st port on VSC8234 */ + reg = <0x1c>; }; }; + +&enetc_port0 { + phy-handle = <&slot1_sgmii>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&mdio_slot2 { + #address-cells = <1>; + #size-cells = <0>; + + /* 4 ports on VSC8514 */ + slot2_qsgmii0: ethernet-phy@8 { + reg = <0x8>; + }; + + slot2_qsgmii1: ethernet-phy@9 { + reg = <0x9>; + }; + + slot2_qsgmii2: ethernet-phy@a { + reg = <0xa>; + }; + + slot2_qsgmii3: ethernet-phy@b { + reg = <0xb>; + }; +}; + +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot2_qsgmii0>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot2_qsgmii1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot2_qsgmii2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot2_qsgmii3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + }; +}; + +&mscc_felix { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts index 5d0a094e6c44..fb85847f778f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts @@ -11,65 +11,51 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; - /* VSC8234 */ - slot1_sgmii0: ethernet-phy@1c { - reg = <0x1c>; - }; - - slot1_sgmii1: ethernet-phy@1d { - reg = <0x1d>; - }; - - slot1_sgmii2: ethernet-phy@1e { - reg = <0x1e>; - }; - - slot1_sgmii3: ethernet-phy@1f { - reg = <0x1f>; - }; - }; + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; }; - fragment@1 { - target = <&enetc_port0>; - __overlay__ { - phy-handle = <&slot1_sgmii0>; - phy-mode = "sgmii"; - managed = "in-band-status"; - status = "okay"; - }; + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; }; - fragment@2 { - target = <&mscc_felix_ports>; - __overlay__ { - port@1 { - status = "okay"; - phy-handle = <&slot1_sgmii1>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot1_sgmii2>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - }; + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; }; - fragment@3 { - target = <&mscc_felix>; - __overlay__ { - status = "okay"; - }; + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; }; }; + +&enetc_port0 { + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; +}; + +&mscc_felix_ports { + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; +}; + +&mscc_felix { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts index 1ef743c48e84..63e46fad22bd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts @@ -11,69 +11,58 @@ /dts-v1/; /plugin/; -/ { - fragment@0 { - target = <&mdio_slot1>; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; +&mdio_slot1 { + #address-cells = <1>; + #size-cells = <0>; - /* VSC8234 */ - slot1_sgmii0: ethernet-phy@1c { - reg = <0x1c>; - }; - - slot1_sgmii1: ethernet-phy@1d { - reg = <0x1d>; - }; - - slot1_sgmii2: ethernet-phy@1e { - reg = <0x1e>; - }; - - slot1_sgmii3: ethernet-phy@1f { - reg = <0x1f>; - }; - }; + /* VSC8234 */ + slot1_sgmii0: ethernet-phy@1c { + reg = <0x1c>; }; - fragment@1 { - target = <&mscc_felix_ports>; - __overlay__ { - port@0 { - status = "okay"; - phy-handle = <&slot1_sgmii0>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - - port@1 { - status = "okay"; - phy-handle = <&slot1_sgmii1>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - - port@2 { - status = "okay"; - phy-handle = <&slot1_sgmii2>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - - port@3 { - status = "okay"; - phy-handle = <&slot1_sgmii3>; - phy-mode = "sgmii"; - managed = "in-band-status"; - }; - }; + slot1_sgmii1: ethernet-phy@1d { + reg = <0x1d>; }; - fragment@2 { - target = <&mscc_felix>; - __overlay__ { - status = "okay"; - }; + slot1_sgmii2: ethernet-phy@1e { + reg = <0x1e>; + }; + + slot1_sgmii3: ethernet-phy@1f { + reg = <0x1f>; }; }; + +&mscc_felix_ports { + port@0 { + status = "okay"; + phy-handle = <&slot1_sgmii0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@1 { + status = "okay"; + phy-handle = <&slot1_sgmii1>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@2 { + status = "okay"; + phy-handle = <&slot1_sgmii2>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; + + port@3 { + status = "okay"; + phy-handle = <&slot1_sgmii3>; + phy-mode = "sgmii"; + managed = "in-band-status"; + }; +}; + +&mscc_felix { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 177bc1405f0f..19d3952dbffe 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -107,6 +107,30 @@ reg = <5>; }; }; + + mdio_slot1: mdio@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + mdio_slot2: mdio@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + mdio_slot3: mdio@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + mdio_slot4: mdio@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 5bb8c26e0825..088271d49139 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -224,6 +224,17 @@ little-endian; }; + efuse@1e80000 { + compatible = "fsl,ls1028a-sfp"; + reg = <0x0 0x1e80000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + ls1028a_uid: unique-id@1c { + reg = <0x1c 0x8>; + }; + }; + scfg: syscon@1fc0000 { compatible = "fsl,ls1028a-scfg", "syscon"; reg = <0x0 0x1fc0000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index ee4e585a9c39..6446e6df7a9a 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -141,6 +141,22 @@ lsio_subsys: bus@5d000000 { status = "disabled"; }; + lsio_mu5: mailbox@5d200000 { + reg = <0x5d200000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_5A>; + status = "disabled"; + }; + + lsio_mu6: mailbox@5d210000 { + reg = <0x5d210000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_MU_6A>; + status = "disabled"; + }; + lsio_mu13: mailbox@5d280000 { reg = <0x5d280000 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index 0da311898e01..ec3f2c177035 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -3,6 +3,8 @@ * Copyright 2020 Compass Electronics Group, LLC */ +#include + / { leds { compatible = "gpio-leds"; @@ -34,6 +36,19 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie0_refclk_gated: pcie0-refclk-gated { + compatible = "gpio-gate-clock"; + clocks = <&pcie0_refclk>; + #clock-cells = <0>; + enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>; + }; + reg_audio: regulator-audio { compatible = "regulator-fixed"; regulator-name = "3v3_aud"; @@ -64,6 +79,16 @@ startup-delay-us = <100000>; }; + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "pci_pwr_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -202,6 +227,32 @@ }; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk_gated>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk_gated>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + vpcie-supply = <®_pcie0>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -308,6 +359,12 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + >; + }; + pinctrl_sai3: sai3grp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts new file mode 100644 index 000000000000..b2e8967e9687 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (c) 2021 emtrion GmbH +// Author: Frank Erdrich +// + +/dts-v1/; + +#include "imx8mm-emcon.dtsi" +#include "imx8mm-emcon-avari.dtsi" + +/ { + model = "emtrion SoM emCON-MX8M mini on Avari"; + compatible = "emtrion,emcon-mx8mm-avari", "fsl,imx8mm"; +}; + +&lvds_backlight { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi new file mode 100644 index 000000000000..5028f232b6bd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright (C) 2021 emtrion GmbH +// Author: Frank Erdrich +// + +/ { + aliases { + boardid = &boardID; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + }; + + chosen { + stdout-path = &uart1; + }; + + reg_wall_5p0: regulator-wall5p0 { + compatible = "regulator-fixed"; + regulator-name = "Main-Supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base3p3: regulator-base3p3 { + compatible = "regulator-fixed"; + vin-supply = <®_wall_5p0>; + regulator-name = "3V3-avari"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_base1p5: regulator-base1p5 { + compatible = "regulator-fixed"; + vin-supply = <®_base3p3>; + regulator-name = "1V5-avari"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_usb_otg: regulator-otgvbus { + compatible = "regulator-fixed"; + vin-supply = <®_wall_5p0>; + regulator-name = "OTG_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + clk_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SGTL5000-Card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&ecspi1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; + + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_codec>; + VDDA-supply = <®_base3p3>; + VDDIO-supply = <®_base3p3>; + }; + + boardID: gpio@3a { + compatible = "nxp,pca8574"; + reg = <0x3a>; + gpio-controller; + #gpio-cells = <1>; + }; +}; + +&sai2 { + status = "okay"; +}; + +&uart2 { + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "disabled"; +}; + +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi new file mode 100644 index 000000000000..7c4af71baab9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +// +// Copyright 2018 NXP +// Copyright (C) 2021 emtrion GmbH +// + +/dts-v1/; + +#include "imx8mm.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + som_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + green { + label = "som:green"; + gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + red { + label = "som:red"; + gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + lvds_backlight: lvds-backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 50000 0>; + brightness-levels = < + 0 4 8 16 32 64 80 96 112 + 128 144 160 176 250 + >; + default-brightness-level = <9>; + status = "disabled"; + }; + + reg_usdhc1_vmmc: regulator-emmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "sdcard_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + pinctrl-1 = <&pinctrl_flexspi1>; + status = "okay"; + + flash0: spi-flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <40000000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + pinctrl_csi_pwn: csi-pwn-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + >; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + >; + }; + + pinctrl_ecspi1_cs: ecspi1-cs { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 + >; + }; + + pinctrl_flexspi1: flexspi1-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 + >; + }; + + pinctrl_gpio_led: gpio-led-grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_lvds: lvds-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x06 + >; + }; + + pinctrl_pcie0: pcie0-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x41 + >; + }; + + pinctrl_pmic: pmic-irq { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x41 + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 + >; + }; + + pinctrl_sai2: sai2-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + >; + }; + + pinctrl_spdif1: spdif1-grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 + MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + + /* rts and cts */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + /* no reset for sdhc2 interface */ + pinctrl_usdhc2_gpio: usdhc2-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x1c4 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + bd71847: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + rv1805: rtc@69 { + compatible = "abracon,ab1805"; + reg = <0x69>; + }; +}; + +&mu { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&sai2 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12000000>; + status = "disabled"; +}; + +&spdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif1>; + assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>, + <&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", + "rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k"; + status = "disabled"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MM_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MM_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + over-current-active-low; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "disabled"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + bus-width = <8>; + vmmc-supply = <®_usdhc1_vmmc>; + keep-power-in-suspend; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 3bac87b7e142..6d67df7692f1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -5,6 +5,7 @@ /dts-v1/; +#include #include #include "imx8mm.dtsi" @@ -30,6 +31,23 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_pcie0: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -296,6 +314,30 @@ }; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + vpcie-supply = <®_pcie0>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -413,6 +455,19 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 + MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41 + >; + }; + + pinctrl_pcie0_reg: pcie0reggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h index a003e6af3353..83c8f715cd90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h +++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h @@ -248,6 +248,7 @@ #define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 #define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0 #define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +#define MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x134 0x39C 0x000 0x2 0x0 #define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 #define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0 #define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 @@ -279,7 +280,7 @@ #define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1 #define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 -#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0 +#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53C 0x4 0x0 #define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 #define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0 @@ -486,7 +487,7 @@ #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 -#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4Fc 0x4 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2 #define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 @@ -494,7 +495,7 @@ #define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 #define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 -#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4Fc 0x4 0x3 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3 #define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts b/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts new file mode 100644 index 000000000000..9fbbbb556c0b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2020 Protonic Holland + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include +#include "imx8mm.dtsi" + +/ { + model = "Protonic PRT8MM"; + compatible = "prt,prt8mm", "fsl,imx8mm"; + + chosen { + stdout-path = &uart4; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + debug-led0 { + label = "DEBUG_LED0"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + debug-led1 { + label = "DEBUG_LED1"; + gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu"; + }; + }; + + sound-ssm2518 { + compatible = "simple-audio-card"; + simple-audio-card,name = "ssm2518-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&cpudai>; + simple-audio-card,bitclock-master = <&cpudai>; + + cpudai: simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&ssm2518>; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + ssm2518: audio-codec@34 { + compatible = "adi,ssm2518"; + reg = <0x34>; + #sound-dai-cells = <0>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + regulator-name = "0V9_CORE"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <980000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf85363"; + reg = <0x51>; + }; + + touchscreeen@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_NONE>; + irq-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + + temp-sense@70 { + compatible = "ti,tmp103"; + reg = <0x70>; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <12288000>; + fsl,sai-mclk-direction-output; + fsl,sai-asynchronous; + status = "okay"; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + dr_mode = "host"; + disable-over-current; + power-active-high; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <100000000>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpio_leds: ledsgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x00 + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x00 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c3 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 + MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; + + pinctrl_touchscreen: tsgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x80 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x000 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x000 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0d4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index 7844878788f4..286d2df01cfa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -5,6 +5,7 @@ /dts-v1/; +#include #include "imx8mm-tqma8mqml.dtsi" #include "mba8mx.dtsi" @@ -58,6 +59,24 @@ }; }; +&pcie_phy { + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + &sai3 { assigned-clocks = <&clk IMX8MM_CLK_SAI3>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index 284e62acc0b4..16ee9b5179e6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -227,6 +227,11 @@ }; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 28012279f6f6..73addc0b8e57 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { aliases { @@ -33,6 +34,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -61,6 +68,20 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -87,6 +108,28 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + /* GPS */ &uart1 { pinctrl-names = "default"; @@ -148,6 +191,12 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 + >; + }; + pinctrl_pps: ppsgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts new file mode 100644 index 000000000000..4eaf8aabcbff --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-imx219.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm"; + + reg_cam: regulator-cam { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_cam>; + compatible = "regulator-fixed"; + regulator-name = "reg_cam"; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + cam24m: cam24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "cam24m"; + }; +}; + +&csi { + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cam24m>; + VDIG-supply = <®_cam>; + + port { + /* MIPI CSI-2 bus endpoint */ + imx219_to_mipi_csi2: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&mipi_csi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + imx8mm_mipi_csi_in: endpoint { + remote-endpoint = <&imx219_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + imx8mm_mipi_csi_out: endpoint { + remote-endpoint = <&csi_in>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_reg_cam: regcamgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts new file mode 100644 index 000000000000..3ea73a6886ff --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs232-rts.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW72xx RS232 with RTS/CTS hardware flow control: + * - GPIO4_0 rs485_en needs to be driven low (in-active) + * - UART4_TX becomes RTS + * - UART4_RX becomes CTS + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_en"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts new file mode 100644 index 000000000000..c3cd9f2b0db3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs422.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW72xx RS422 (RS485 full duplex): + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven low (in-active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be low + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts new file mode 100644 index 000000000000..cc0a287226ab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rs485.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW72xx RS485 HD: + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven high (active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be pulled high + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw72xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 27afa46a253a..1e7badb2a82e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -5,9 +5,11 @@ #include #include +#include / { aliases { + ethernet1 = ð1; usb0 = &usbotg1; usb1 = &usbotg2; }; @@ -33,6 +35,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -80,6 +88,22 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "rs485_term", "mipi_gpio4", "", "", + "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", + "mipi_gpio1", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -106,6 +130,54 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + pcie@1,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + pcie@2,3 { + reg = <0x1800 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + eth1: pcie@5,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + }; +}; + /* off-board header */ &sai3 { pinctrl-names = "default"; @@ -198,6 +270,12 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 + >; + }; + pinctrl_pps: ppsgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts new file mode 100644 index 000000000000..f3ece4b7fbbd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-imx219.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; + + reg_cam: regulator-cam { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_cam>; + compatible = "regulator-fixed"; + regulator-name = "reg_cam"; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + cam24m: cam24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "cam24m"; + }; +}; + +&csi { + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cam24m>; + VDIG-supply = <®_cam>; + + port { + /* MIPI CSI-2 bus endpoint */ + imx219_to_mipi_csi2: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&mipi_csi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + imx8mm_mipi_csi_in: endpoint { + remote-endpoint = <&imx219_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + + imx8mm_mipi_csi_out: endpoint { + remote-endpoint = <&csi_in>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_reg_cam: regcamgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts new file mode 100644 index 000000000000..2fa635e1c1a8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + * + * GW73xx RS232 with RTS/CTS hardware flow control: + * - GPIO4_0 rs485_en needs to be driven low (in-active) + * - UART4_TX becomes RTS + * - UART4_RX becomes CTS + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_en"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts new file mode 100644 index 000000000000..3e6404340d52 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Gateworks Corporation + * + * GW73xx RS422 (RS485 full duplex): + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven low (in-active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be low + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts new file mode 100644 index 000000000000..2c71ab9854cb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Gateworks Corporation + * + * GW73xx RS485 HD: + * - GPIO1_0 rs485_term selects on-chip termination + * - GPIO4_0 rs485_en needs to be driven high (active) + * - GPIO4_2 rs485_hd needs to be driven high (active) + * - UART4_TX is DE for RS485 transmitter + * - RS485_EN needs to be pulled high + * - RS485_HALF needs to be pulled high + */ + +#include + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x"; +}; + +&gpio4 { + rs485_en { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_en"; + }; + + rs485_hd { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "rs485_hd"; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index a59e849c7be2..426483ec1f88 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -5,9 +5,11 @@ #include #include +#include / { aliases { + ethernet1 = ð1; usb0 = &usbotg1; usb1 = &usbotg2; }; @@ -33,6 +35,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -100,6 +108,22 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "rs485_term", "mipi_gpio4", "", "", + "", "", "pci_usb_sel", "dio0", + "", "dio1", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", + "mipi_gpio1", "", "", "pci_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -126,6 +150,54 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + pcie@1,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + pcie@2,4 { + reg = <0x2000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + eth1: pcie@6,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + }; +}; + /* off-board header */ &sai3 { pinctrl-names = "default"; @@ -241,6 +313,12 @@ >; }; + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 + >; + }; + pinctrl_pps: ppsgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 21c546c4628d..7e7231046215 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -8,6 +8,7 @@ #include #include #include +#include #include "imx8mm.dtsi" @@ -179,6 +180,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V"; @@ -286,6 +293,29 @@ }; }; +&gpio1 { + gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#", + "", "uart1_rs232#", "dig1_in", "dig1_out", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "uart3_rs232#", "uart3_rs422#", + "uart3_rs485#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "", + "", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &gpu_2d { status = "disabled"; }; @@ -644,6 +674,28 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + &pgc_gpu { status = "disabled"; }; @@ -820,6 +872,13 @@ >; }; + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index d52686f4c059..edf0c7aaaef0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -9,6 +9,7 @@ #include #include #include +#include #include "imx8mm.dtsi" @@ -17,6 +18,7 @@ compatible = "gw,imx8mm-gw7902", "fsl,imx8mm"; aliases { + ethernet1 = ð1; usb0 = &usbotg1; usb1 = &usbotg2; }; @@ -128,6 +130,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + pps { compatible = "pps-gpio"; pinctrl-names = "default"; @@ -252,6 +260,43 @@ }; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", + "uart2_en#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", + "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485", + "", "uart1_term", "uart1_half", "app_gpio2", + "mipi_gpio1", "", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "mipi_gpio4", + "mipi_gpio3", "mipi_gpio2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -547,6 +592,42 @@ status = "okay"; }; +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&clk IMX8MM_CLK_DUMMY>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + eth1: pcie@1,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + + local-mac-address = [00 00 00 00 00 00]; + }; + }; +}; + /* off-board header */ &sai3 { pinctrl-names = "default"; @@ -647,7 +728,7 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ @@ -737,6 +818,12 @@ >; }; + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts new file mode 100644 index 000000000000..1deb2ea8fcc9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -0,0 +1,836 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Gateworks Corporation + */ + +/dts-v1/; + +#include +#include +#include +#include + +#include "imx8mm.dtsi" + +/ { + model = "Gateworks Venice GW7903 i.MX8MM board"; + compatible = "gw,imx8mm-gw7903", "fsl,imx8mm"; + + aliases { + ethernet0 = &fec1; + usb0 = &usbotg1; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + user-pb { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + user-pb1x { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-erased { + label = "key_erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + eeprom-wp { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + switch-hold { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led01_red"; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led01_grn"; + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led02_red"; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-3 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led02_grn"; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-4 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led03_red"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-5 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led03_grn"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-6 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led04_red"; + gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-7 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led04_grn"; + gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-8 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led05_red"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-9 { + function = LED_FUNCTION_STATUS; + color = ; + label = "led05_grn"; + gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-a { + function = LED_FUNCTION_STATUS; + color = ; + label = "led06_red"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-b { + function = LED_FUNCTION_STATUS; + color = ; + label = "led06_grn"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + local-mac-address = [00 00 00 00 00 00]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2500>; + }; + }; +}; + +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "", + "dig1_out#", "dig1_in", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "", "", "", "", "sim1_det#", + "sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vin"; + gw,voltage-divider-ohms = <22100 1000>; + gw,voltage-offset-microvolt = <700000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_0p9"; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_soc"; + }; + + channel@8e { + gw,mode = <2>; + reg = <0x8e>; + label = "vdd_arm"; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_1p8"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_dram"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + + regulators { + /* vdd_soc: 0.805-0.900V (typ=0.8V) */ + BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + /* vdd_arm: 0.805-1.0V (typ=0.9V) */ + buck2: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ + BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_3p3 */ + BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_1p8 */ + BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_dram */ + BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + /* nvcc_snvs_1p8 */ + LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd_snvs_0p8 */ + LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdda_1p8 */ + LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + accelerometer@19 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + compatible = "st,lis2de12"; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio1>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = ; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + +&pgc_mipi { + status = "disabled"; +}; + +/* off-board RS232/RS485/RS422 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + uart-has-rtscts; + status = "okay"; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */ + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */ + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */ + MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */ + MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */ + MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */ + MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */ + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */ + MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */ + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */ + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 + MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19 + MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 + MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19 + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + >; + }; + + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140 + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi new file mode 100644 index 000000000000..aca5ae0d307d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + sound_card: sound-card { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx8mm-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Headphone Jack", "MICBIAS", + "IN1L", "Headphone Jack"; + simple-audio-card,widgets = + "Microphone", "Headphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + dailink_master: simple-audio-card,codec { + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + status = "okay"; +}; + +/* EEPROM on display adapter boards */ +&eeprom_display_adapter { + status = "okay"; +}; + +/* EEPROM on Verdin Development board */ +&eeprom_carrier_board { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi { + status = "okay"; +}; + +/* Current measurement into module VCC */ +&hwmon { + status = "okay"; +}; + +&hwmon_temp { + vs-supply = <®_1p8v>; + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + status = "okay"; + + /* Audio Codec */ + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + AVDD-supply = <®_3p3v>; + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + clock-names = "mclk"; + CPVDD-supply = <®_3p3v>; + DBVDD-supply = <®_3p3v>; + DCVDD-supply = <®_3p3v>; + MICVDD-supply = <®_3p3v>; + reg = <0x1a>; + #sound-dai-cells = <0>; + }; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm1 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm3 { + status = "okay"; +}; + +/* VERDIN I2S_1 */ +&sai2 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbotg1 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbotg2 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi new file mode 100644 index 000000000000..73cc3fafa018 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "imx8mm-verdin-dahlia.dtsi" + +/ { + sound_card: sound-card { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx8mm-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + dailink_master: simple-audio-card,codec { + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +&gpio_expander_21 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + /* Audio Codec */ + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + }; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver */ +&uart2 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; +}; + +/* Limit frequency on dev board due to long traces and bad signal integrity */ +&usdhc2 { + max-frequency = <100000000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts new file mode 100644 index 000000000000..d64ff378a152 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dahlia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-nonwifi.dtsi" +#include "imx8mm-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Dahlia Board"; + compatible = "toradex,verdin-imx8mm-nonwifi-dahlia", + "toradex,verdin-imx8mm-nonwifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts new file mode 100644 index 000000000000..6ae71ecac8de --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-nonwifi.dtsi" +#include "imx8mm-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Verdin Development Board"; + compatible = "toradex,verdin-imx8mm-nonwifi-dev", + "toradex,verdin-imx8mm-nonwifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi new file mode 100644 index 000000000000..1e0f87c7a609 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +&gpio3 { + gpio-line-names = "SODIMM_52", + "SODIMM_54", + "SODIMM_64", + "SODIMM_21", + "SODIMM_206", + "SODIMM_76", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "SODIMM_162", + "SODIMM_164", + "SODIMM_166", + "SODIMM_168", + "SODIMM_66", + "SODIMM_17", + "", + "SODIMM_156", + "SODIMM_160", + "SODIMM_244", + "", + "SODIMM_48", + "SODIMM_44", + "SODIMM_42", + "SODIMM_46"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_102", + "SODIMM_90", + "SODIMM_92", + "SODIMM_94", + "SODIMM_96", + "SODIMM_100", + "SODIMM_148", + "SODIMM_152", + "SODIMM_154", + "SODIMM_174", + "SODIMM_120", + "SODIMM_104", + "SODIMM_106", + "SODIMM_108", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "SODIMM_150", + "SODIMM_118", + "", + "SODIMM_88", + "SODIMM_149", + "SODIMM_147", + "SODIMM_36", + "SODIMM_32", + "SODIMM_30", + "SODIMM_34", + "SODIMM_38", + "SODIMM_252", + "SODIMM_133", + "SODIMM_135", + "SODIMM_129"; +}; + +&usdhc3 { + bus-width = <4>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts new file mode 100644 index 000000000000..d424c475cba1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-wifi.dtsi" +#include "imx8mm-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB on Dahlia Board"; + compatible = "toradex,verdin-imx8mm-wifi-dahlia", + "toradex,verdin-imx8mm-wifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts new file mode 100644 index 000000000000..ef952021832e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-wifi.dtsi" +#include "imx8mm-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB on Verdin Development Board"; + compatible = "toradex,verdin-imx8mm-wifi-dev", + "toradex,verdin-imx8mm-wifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi new file mode 100644 index 000000000000..3e06a6ce3406 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PDn_AW-CM276NF"; + startup-delay-us = <2000>; + }; +}; + +/* On-module Wi-Fi */ +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_52", + "SODIMM_54", + "SODIMM_64", + "SODIMM_21", + "SODIMM_206", + "SODIMM_76", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", + "SODIMM_66", + "SODIMM_17", + "", + "", + "", + "SODIMM_244", + "", + "SODIMM_48", + "SODIMM_44", + "SODIMM_42", + "SODIMM_46"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_102", + "SODIMM_90", + "SODIMM_92", + "SODIMM_94", + "SODIMM_96", + "SODIMM_100", + "", + "", + "", + "", + "SODIMM_120", + "SODIMM_104", + "SODIMM_106", + "SODIMM_108", + "SODIMM_112", + "SODIMM_114", + "SODIMM_116", + "", + "SODIMM_118", + "", + "SODIMM_88", + "SODIMM_149", + "SODIMM_147", + "SODIMM_36", + "SODIMM_32", + "SODIMM_30", + "SODIMM_34", + "SODIMM_38", + "SODIMM_252", + "SODIMM_133", + "SODIMM_135", + "SODIMM_129"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi new file mode 100644 index 000000000000..0d84d29e70f1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -0,0 +1,1264 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "dt-bindings/phy/phy-imx8-pcie.h" +#include "dt-bindings/pwm/pwm.h" +#include "imx8mm.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ + enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; + power-supply = <®_3p3v>; + /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + /* Fixed clock dedicated to SPI CAN controller */ + clk20m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + debounce-interval = <10>; + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + /* Carrier Board Supplies */ + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "+V5_SW"; + }; + + /* Non PMIC On-module Supplies */ + reg_ethphy: regulator-ethphy { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ + off-on-delay = <500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth>; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_ETH"; + startup-delay-us = <200000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB_1_EN (SODIMM 155) */ + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg1_vbus"; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB_2_EN (SODIMM 185) */ + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb_otg2_vbus"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + off-on-delay = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SD"; + startup-delay-us = <2000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Use the kernel configuration settings instead */ + /delete-node/ linux,cma; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; +}; + +/* Verdin CAN_1 (On-module) */ +&ecspi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can1: can@0 { + compatible = "microchip,mcp251xfd"; + clocks = <&clk20m>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_int>; + reg = <0>; + spi-max-frequency = <8500000>; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&fec1 { + fsl,magic-packet; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + phy-supply = <®_ethphy>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; + +/* Verdin QSPI_1 */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; +}; + +&gpio1 { + gpio-line-names = "SODIMM_216", + "SODIMM_19", + "", + "", + "", + "", + "", + "", + "SODIMM_220", + "SODIMM_222", + "", + "SODIMM_218", + "SODIMM_155", + "SODIMM_157", + "SODIMM_185", + "SODIMM_187"; +}; + +&gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_84", + "SODIMM_78", + "SODIMM_74", + "SODIMM_80", + "SODIMM_82", + "SODIMM_70", + "SODIMM_72"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_131", + "", + "SODIMM_91", + "SODIMM_16", + "SODIMM_15", + "SODIMM_208", + "SODIMM_137", + "SODIMM_139", + "SODIMM_141", + "SODIMM_143", + "SODIMM_196", + "SODIMM_200", + "SODIMM_198", + "SODIMM_202", + "", + "", + "SODIMM_55", + "SODIMM_53", + "SODIMM_95", + "SODIMM_93", + "SODIMM_14", + "SODIMM_12", + "", + "", + "", + "", + "SODIMM_210", + "SODIMM_212", + "SODIMM_151", + "SODIMM_153"; + + ctrl_sleep_moci-hog { + gpio-hog; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <1 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; + }; +}; + +/* On-module I2C */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + interrupt-parent = <&gpio1>; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x25>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + regulators { + reg_vdd_soc: BUCK1 { + nxp,dvs-run-voltage = <850000>; + nxp,dvs-standby-voltage = <800000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <800000>; + regulator-name = "+VDD_SOC"; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_arm: BUCK2 { + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <850000>; + regulator-name = "+VDD_ARM"; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_dram: BUCK3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <850000>; + regulator-name = "+VDD_GPU_VPU_DDR"; + }; + + reg_vdd_3v3: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3"; + }; + + reg_vdd_1v8: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "PWR_1V8_MOCI"; + }; + + reg_nvcc_dram: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "+VDD_DDR"; + }; + + reg_nvcc_snvs: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SNVS"; + }; + + reg_vdd_snvs: LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <800000>; + regulator-name = "+V0.8_SNVS"; + }; + + reg_vdda: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8A"; + }; + + reg_vdd_phy: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <900000>; + regulator-name = "+V0.9_MIPI"; + }; + + reg_nvcc_sd: LDO5 { + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V3.3_1.8_SD"; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Verdin I2C_1 (ADC_4 - ADC_3) */ + channel@0 { + reg = <0>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_4 - ADC_1) */ + channel@1 { + reg = <1>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_3 - ADC_1) */ + channel@2 { + reg = <2>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_2 - ADC_1) */ + channel@3 { + reg = <3>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_4 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_3 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_1 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <2>; + }; + }; + + eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + clock-frequency = <10000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "disabled"; +}; + +/* Verdin I2C_3_HDMI N/A */ + +/* Verdin I2C_4_CSI */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Verdin I2C_1 */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + gpio_expander_21: gpio-expander@21 { + compatible = "nxp,pcal6416"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x21>; + vcc-supply = <®_3p3v>; + status = "disabled"; + }; + + lvds_ti_sn65dsi83: bridge@2c { + compatible = "ti,sn65dsi83"; + /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ + /* Verdin GPIO_10_DSI (SODIMM 21) */ + enable-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>; + reg = <0x2c>; + status = "disabled"; + }; + + /* Current measurement into module VCC */ + hwmon: hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + status = "disabled"; + }; + + hdmi_lontium_lt8912: hdmi@48 { + compatible = "lontium,lt8912b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; + reg = <0x48>; + /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ + /* Verdin GPIO_10_DSI (SODIMM 21) */ + reset-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + atmel_mxt_ts: touch@4a { + compatible = "atmel,maxtouch"; + /* Verdin GPIO_9_DSI */ + /* (TOUCH_INT#, SODIMM 17, also routed to SN65dsi83 IRQ albeit currently unused) */ + interrupt-parent = <&gpio3>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; + reg = <0x4a>; + /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ + reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + /* Temperature sensor on carrier board */ + hwmon_temp: sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + status = "disabled"; + }; + + /* EEPROM on display adapter (MIPI DSI Display Adapter) */ + eeprom_display_adapter: eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + status = "disabled"; + }; + + /* EEPROM on carrier board */ + eeprom_carrier_board: eeprom@57 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x57>; + status = "disabled"; + }; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + assigned-clock-rates = <10000000>, <250000000>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + /* PCIE_1_RESET# (SODIMM 244) */ + reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; +}; + +&pcie_phy { + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; +}; + +/* Verdin PWM_3_DSI */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_1>; + #pwm-cells = <3>; +}; + +/* Verdin PWM_1 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_2>; + #pwm-cells = <3>; +}; + +/* Verdin PWM_2 */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_3>; + #pwm-cells = <3>; +}; + +/* VERDIN I2S_1 */ +&sai2 { + #sound-dai-cells = <0>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Verdin UART_1 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; +}; + +/* Verdin UART_2 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; +}; + +/* Verdin UART_4 */ +/* + * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS + */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +/* Verdin USB_1 */ +&usbotg1 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + over-current-active-low; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; +}; + +/* Verdin USB_2 */ +&usbotg2 { + dr_mode = "host"; + over-current-active-low; + samsung,picophy-dc-vol-level-adjust = <7>; + samsung,picophy-pre-emp-curr-control = <3>; + vbus-supply = <®_usb_otg2_vbus>; +}; + +&usbphynop1 { + vcc-supply = <®_vdd_3v3>; +}; + +&usbphynop2 { + vcc-supply = <®_vdd_3v3>; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + vmmc-supply = <®_usdhc2_vmmc>; +}; + +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, + <&pinctrl_gpio7>, <&pinctrl_gpio8>, + <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, + <&pinctrl_pmic_tpm_ena>; + + pinctrl_can1_int: can1intgrp { + fsl,pins = + ; /* CAN_1_SPI_INT#_1.8V */ + }; + + pinctrl_can2_int: can2intgrp { + fsl,pins = + ; /* CAN_2_SPI_INT#_1.8V */ + }; + + pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + fsl,pins = + ; /* SODIMM 256 */ + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = + , /* SODIMM 196 */ + , /* SODIMM 200 */ + , /* SODIMM 198 */ + ; /* SODIMM 202 */ + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = + , /* CAN_SPI_SCK_1.8V */ + , /* CAN_SPI_MOSI_1.8V */ + , /* CAN_SPI_MISO_1.8V */ + , /* CAN_1_SPI_CS_1.8V# */ + ; /* CAN_2_SPI_CS#_1.8V */ + }; + + pinctrl_fec1: fec1grp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_fec1_sleep: fec1-sleepgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = + , /* SODIMM 52 */ + , /* SODIMM 54 */ + , /* SODIMM 64 */ + , /* SODIMM 66 */ + , /* SODIMM 56 */ + , /* SODIMM 58 */ + , /* SODIMM 60 */ + ; /* SODIMM 62 */ + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = + ; /* SODIMM 206 */ + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = + ; /* SODIMM 208 */ + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = + ; /* SODIMM 210 */ + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = + ; /* SODIMM 212 */ + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = + ; /* SODIMM 216 */ + }; + + pinctrl_gpio6: gpio6grp { + fsl,pins = + ; /* SODIMM 218 */ + }; + + pinctrl_gpio7: gpio7grp { + fsl,pins = + ; /* SODIMM 220 */ + }; + + pinctrl_gpio8: gpio8grp { + fsl,pins = + ; /* SODIMM 222 */ + }; + + /* Verdin GPIO_9_DSI (pulled-up as active-low) */ + pinctrl_gpio_9_dsi: gpio9dsigrp { + fsl,pins = + ; /* SODIMM 17 */ + }; + + /* Verdin GPIO_10_DSI */ + pinctrl_gpio_10_dsi: gpio10dsigrp { + fsl,pins = + ; /* SODIMM 21 */ + }; + + pinctrl_gpio_hog1: gpiohog1grp { + fsl,pins = + , /* SODIMM 88 */ + , /* SODIMM 90 */ + , /* SODIMM 92 */ + , /* SODIMM 94 */ + , /* SODIMM 96 */ + , /* SODIMM 100 */ + , /* SODIMM 102 */ + , /* SODIMM 104 */ + , /* SODIMM 106 */ + , /* SODIMM 108 */ + , /* SODIMM 112 */ + , /* SODIMM 114 */ + , /* SODIMM 116 */ + , /* SODIMM 118 */ + ; /* SODIMM 120 */ + }; + + pinctrl_gpio_hog2: gpiohog2grp { + fsl,pins = + ; /* SODIMM 91 */ + }; + + pinctrl_gpio_hog3: gpiohog3grp { + fsl,pins = + , /* SODIMM 157 */ + ; /* SODIMM 187 */ + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = + ; /* SODIMM 252 */ + }; + + /* On-module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c2: i2c2grp { + fsl,pins = + , /* SODIMM 55 */ + ; /* SODIMM 53 */ + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = + , /* SODIMM 55 */ + ; /* SODIMM 53 */ + }; + + /* Verdin I2C_2_DSI */ + pinctrl_i2c3: i2c3grp { + fsl,pins = + , /* SODIMM 95 */ + ; /* SODIMM 93 */ + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = + , /* SODIMM 95 */ + ; /* SODIMM 93 */ + }; + + /* Verdin I2C_1 */ + pinctrl_i2c4: i2c4grp { + fsl,pins = + , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = + , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ + pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { + fsl,pins = + ; /* SODIMM 42 */ + }; + + /* Verdin I2S_2_D_OUT shared with SAI5 */ + pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { + fsl,pins = + ; /* SODIMM 46 */ + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = + , /* SODIMM 244 */ + /* PMIC_EN_PCIe_CLK, unused */ + ; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = + ; /* PMIC_INT# */ + }; + + /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ + pinctrl_pwm_1: pwm1grp { + fsl,pins = + ; /* SODIMM 19 */ + }; + + pinctrl_pwm_2: pwm2grp { + fsl,pins = + ; /* SODIMM 15 */ + }; + + pinctrl_pwm_3: pwm3grp { + fsl,pins = + ; /* SODIMM 16 */ + }; + + /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ + pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { + fsl,pins = + ; /* SODIMM 19 */ + }; + + pinctrl_reg_eth: regethgrp { + fsl,pins = + ; /* PMIC_EN_ETH */ + }; + + pinctrl_reg_usb1_en: regusb1engrp { + fsl,pins = + ; /* SODIMM 155 */ + }; + + pinctrl_reg_usb2_en: regusb2engrp { + fsl,pins = + ; /* SODIMM 185 */ + }; + + pinctrl_sai2: sai2grp { + fsl,pins = + , /* SODIMM 32 */ + , /* SODIMM 30 */ + , /* SODIMM 38 */ + , /* SODIMM 36 */ + ; /* SODIMM 34 */ + }; + + pinctrl_sai5: sai5grp { + fsl,pins = + , /* SODIMM 48 */ + , /* SODIMM 44 */ + , /* SODIMM 42 */ + ; /* SODIMM 46 */ + }; + + /* control signal for optional ATTPM20P or SE050 */ + pinctrl_pmic_tpm_ena: pmictpmenagrp { + fsl,pins = + ; /* PMIC_TPM_ENA */ + }; + + pinctrl_tsp: tspgrp { + fsl,pins = + , /* SODIMM 148 */ + , /* SODIMM 152 */ + , /* SODIMM 154 */ + , /* SODIMM 174 */ + ; /* SODIMM 150 */ + }; + + pinctrl_uart1: uart1grp { + fsl,pins = + , /* SODIMM 149 */ + ; /* SODIMM 147 */ + }; + + pinctrl_uart2: uart2grp { + fsl,pins = + , /* SODIMM 129 */ + , /* SODIMM 131 */ + , /* SODIMM 133 */ + ; /* SODIMM 135 */ + }; + + pinctrl_uart3: uart3grp { + fsl,pins = + , /* SODIMM 137 */ + , /* SODIMM 139 */ + , /* SODIMM 141 */ + ; /* SODIMM 143 */ + }; + + pinctrl_uart4: uart4grp { + fsl,pins = + , /* SODIMM 151 */ + ; /* SODIMM 153 */ + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = + ; /* SODIMM 84 */ + }; + + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { + fsl,pins = + ; /* SODIMM 76 */ + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = + , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + , /* SODIMM 72 */ + ; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + /* On-module Wi-Fi/BT or type specific SDHC interface */ + /* (e.g. on X52 extension slot of Verdin Development Board) */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = + ; /* PMIC_WDI */ + }; + + pinctrl_wifi_ctrl: wifictrlgrp { + fsl,pins = + , /* WIFI_WKUP_BT */ + , /* WIFI_W_WKUP_HOST */ + ; /* WIFI_WKUP_WLAN */ + }; + + pinctrl_wifi_i2s: bti2sgrp { + fsl,pins = + , /* WIFI_TX_BCLK */ + , /* WIFI_TX_DATA0 */ + , /* WIFI_TX_SYNC */ + ; /* WIFI_RX_DATA0 */ + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = + ; /* PMIC_EN_WIFI */ + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 0c7a72c51a31..1ee05677c2dd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -548,7 +548,7 @@ }; gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; + compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -1210,6 +1210,19 @@ reg = <0x32e50200 0x200>; }; + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mm-pcie-phy"; + reg = <0x32f00000 0x10000>; + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + clock-names = "ref"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; + assigned-clock-rates = <100000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; + resets = <&src IMX8MQ_RESET_PCIEPHY>; + reset-names = "pciephy"; + #phy-cells = <0>; + status = "disabled"; + }; }; dma_apbh: dma-controller@33000000 { @@ -1241,6 +1254,37 @@ status = "disabled"; }; + pcie0: pcie@33800000 { + compatible = "fsl,imx8mm-pcie"; + reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <2>; + linux,pci-domain = <0>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "apps", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + status = "disabled"; + }; + gpu_3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; @@ -1272,6 +1316,22 @@ power-domains = <&pgc_gpu>; }; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mm-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; + }; + vpu_blk_ctrl: blk-ctrl@38330000 { compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; reg = <0x38330000 0x100>; @@ -1282,6 +1342,12 @@ <&clk IMX8MM_CLK_VPU_G2_ROOT>, <&clk IMX8MM_CLK_VPU_H1_ROOT>; clock-names = "g1", "g2", "h1"; + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, + <&clk IMX8MM_CLK_VPU_G2>; + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, + <&clk IMX8MM_VPU_PLL_OUT>; + assigned-clock-rates = <600000000>, + <600000000>; #power-domain-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 236f425e1570..3c0e63d2e82d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -220,6 +220,10 @@ }; }; +&disp_blk_ctrl { + status = "disabled"; +}; + /* off-board header */ &ecspi2 { pinctrl-names = "default"; @@ -251,6 +255,47 @@ }; }; +&gpio1 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "m2_reset", "", "m2_wdis#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", "", "", "", "", + "uart2_en#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "app_gpio1", "", "uart1_rs485", + "", "uart1_term", "uart1_half", "app_gpio2", + "mipi_gpio1", "", "", ""; +}; + +&gpio5 { + gpio-line-names = "", "", "", "mipi_gpio4", + "mipi_gpio3", "mipi_gpio2", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpu { + status = "disabled"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -546,6 +591,10 @@ status = "okay"; }; +&pgc_gpumix { + status = "disabled"; +}; + /* off-board header */ &sai3 { pinctrl-names = "default"; @@ -633,7 +682,7 @@ pinctrl_hog: hoggrp { fsl,pins = < MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ - MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */ + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index b8d49d5f2668..99f0f5026674 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -4,6 +4,8 @@ */ #include +#include +#include #include #include #include @@ -640,6 +642,53 @@ interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mn-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_hsiomix: power-domain@0 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MN_CLK_USB_BUS>; + }; + + pgc_otg1: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_hsiomix>; + }; + + pgc_gpumix: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + resets = <&src IMX8MQ_RESET_GPU_RESET>; + }; + + pgc_dispmix: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + }; + + pgc_mipi: power-domain@4 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_dispmix>; + }; + }; + }; }; aips2: bus@30400000 { @@ -989,6 +1038,34 @@ #size-cells = <1>; ranges; + disp_blk_ctrl: blk-ctrl@32e28000 { + compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; + reg = <0x32e28000 0x100>; + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, + <&pgc_dispmix>, <&pgc_mipi>, + <&pgc_mipi>; + power-domain-names = "bus", "isi", + "lcdif", "mipi-dsi", + "mipi-csi"; + clocks = <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>, + <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>, + <&clk IMX8MN_CLK_CSI1_PHY_REF>, + <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; + clock-names = "disp_axi", "disp_apb", + "disp_axi_root", "disp_apb_root", + "lcdif-axi", "lcdif-apb", "lcdif-pix", + "dsi-pclk", "dsi-ref", + "csi-aclk", "csi-pclk"; + #power-domain-cells = <1>; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; @@ -999,6 +1076,7 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&pgc_otg1>; status = "disabled"; }; @@ -1038,6 +1116,32 @@ status = "disabled"; }; + gpu: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER>; + clock-names = "reg", "bus", "core", "shader"; + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, + <&clk IMX8MN_CLK_GPU_SHADER>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, + <400000000>, + <800000000>, + <400000000>, + <1200000000>; + power-domains = <&pgc_gpumix>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index 2eb943210678..4c3ac4214a2c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -294,9 +294,46 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca6416_int>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + gpio-line-names = "EXT_PWREN1", + "EXT_PWREN2", + "CAN1/I2C5_SEL", + "PDM/CAN2_SEL", + "FAN_EN", + "PWR_MEAS_IO1", + "PWR_MEAS_IO2", + "EXP_P0_7", + "EXP_P1_0", + "EXP_P1_1", + "EXP_P1_2", + "EXP_P1_3", + "EXP_P1_4", + "EXP_P1_5", + "EXP_P1_6", + "EXP_P1_7"; }; }; +/* I2C on expansion connector J22. */ +&i2c5 { + clock-frequency = <100000>; /* Lower clock speed for external bus. */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5>; + status = "disabled"; /* can1 pins conflict with i2c5 */ + + /* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions: + * LOW: CAN1 (default, pull-down) + * HIGH: I2C5 + * You need to set it to high to enable I2C5 (for example, add gpio-hog + * in pca6416 node). + */ +}; + &snvs_pwrkey { status = "okay"; }; @@ -442,12 +479,25 @@ >; }; + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3 + MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3 + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 >; }; + pinctrl_pca6416_int: pca6416_int_grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */ + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index fc178eebf8aa..79b290a002c1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -60,6 +60,7 @@ ti,tx-internal-delay = ; ti,fifo-depth = ; ti,clk-output-sel = ; + ti,min-output-impedance; enet-phy-lane-no-swap; }; }; @@ -113,6 +114,8 @@ regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; }; buck4: BUCK4 { @@ -167,14 +170,14 @@ regulator-compatible = "LDO4"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; }; ldo5: LDO5 { regulator-compatible = "LDO5"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; }; }; }; @@ -194,6 +197,8 @@ /* eMMC */ &usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; @@ -221,12 +226,12 @@ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 >; }; @@ -298,21 +303,21 @@ fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 6b840c05dd77..3f8703f3ba5b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -958,6 +958,7 @@ assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; #phy-cells = <0>; + status = "disabled"; }; usb3_1: usb@32f10108 { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index a1b7582f3ecf..99fed35168eb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -27,6 +27,17 @@ clock-frequency = <100000000>; }; + reg_pcie1: regulator-pcie { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_usdhc2_vmmc: regulator-vsd-3v3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_reg_usdhc2>; @@ -123,6 +134,7 @@ &ddrc { operating-points-v2 = <&ddrc_opp_table>; + status = "okay"; ddrc_opp_table: opp-table { compatible = "operating-points-v2"; @@ -327,6 +339,20 @@ status = "okay"; }; +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + vpcie-supply = <®_pcie1>; + vph-supply = <&vgen5_reg>; + status = "okay"; +}; + &pgc_gpu { power-supply = <&sw1a_reg>; }; @@ -482,6 +508,19 @@ >; }; + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 + MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 + >; + }; + + pinctrl_pcie1_reg: pcie1reggrp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 + >; + }; + pinctrl_qspi: qspigrp { fsl,pins = < MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 2d4a472af6a9..05c16376b4d8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -278,6 +278,7 @@ &ddrc { operating-points-v2 = <&ddrc_opp_table>; + status = "okay"; ddrc_opp_table: opp-table { compatible = "operating-points-v2"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index fa721a13de20..94a13cb500e6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -14,6 +14,30 @@ compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; chassis-type = "laptop"; + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm2 0 10000>; + power-supply = <®_main_usb>; + enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 32 64 128 160 200 255>; + default-brightness-level = <6>; + }; + + panel { + compatible = "innolux,n125hce-gn1", "simple-panel"; + power-supply = <®_main_3v3>; + backlight = <&backlight>; + no-hpd; + + port { + panel_in: endpoint { + remote-endpoint = <&edp_bridge_out>; + }; + }; + }; + pcie1_refclk: clock-pcie1-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -42,6 +66,22 @@ vin-supply = <®_main_5v>; }; + reg_main_1v8: regulator-main-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <®_main_3v3>; + }; + + reg_main_1v2: regulator-main-1v2 { + compatible = "regulator-fixed"; + regulator-name = "1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <®_main_5v>; + }; + sound { compatible = "fsl,imx-audio-wm8960"; audio-cpu = <&sai2>; @@ -61,6 +101,13 @@ }; }; +&dphy { + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <25000000>; + status = "okay"; +}; + &fec1 { status = "okay"; }; @@ -84,6 +131,67 @@ }; }; +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + clock-frequency = <400000>; + status = "okay"; + + edp_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edp_bridge>; + reg = <0x2c>; + enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; + vccio-supply = <®_main_1v8>; + vpll-supply = <®_main_1v8>; + vcca-supply = <®_main_1v2>; + vcc-supply = <®_main_1v2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + edp_bridge_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + edp_bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +}; + +&lcdif { + assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>; + /delete-property/assigned-clock-rates; + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&edp_bridge_in>; + }; + }; + }; +}; + &pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie1>; @@ -96,6 +204,13 @@ status = "okay"; }; +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + + ®_1p8v { vin-supply = <®_main_5v>; }; @@ -169,10 +284,29 @@ }; &iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3 + >; + }; + + pinctrl_edp_bridge: edpbridgegrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f - MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022 + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000022 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022 + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000022 >; }; @@ -182,6 +316,12 @@ >; }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x3 + >; + }; + pinctrl_sai2: sai2grp { fsl,pins = < MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi index 8aedcddfeab8..38ffcd145b33 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi @@ -272,10 +272,6 @@ status = "okay"; }; -&vpu { - status = "okay"; -}; - /* Attention: wdog reset forcing POR needs baseboard support */ &wdog1 { status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index e92ebb6147e6..5b3e849f554d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -737,7 +737,21 @@ pgc_vpu: power-domain@6 { #power-domain-cells = <0>; reg = ; - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, + <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, + <&clk IMX8MQ_CLK_VPU_G2>, + <&clk IMX8MQ_CLK_VPU_BUS>, + <&clk IMX8MQ_VPU_PLL_BYPASS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_VPU_PLL>; + assigned-clock-rates = <600000000>, + <600000000>, + <800000000>, + <0>; }; pgc_disp: power-domain@7 { @@ -1457,30 +1471,31 @@ status = "disabled"; }; - vpu: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>, - <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; - interrupts = , - ; - interrupt-names = "g1", "g2"; + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; + }; + + vpu_g2: video-codec@38310000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = ; + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; + }; + + vpu_blk_ctrl: blk-ctrl@38320000 { + compatible = "fsl,imx8mq-vpu-blk-ctrl"; + reg = <0x38320000 0x100>; + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; + power-domain-names = "bus", "g1", "g2"; clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - clock-names = "g1", "g2", "bus"; - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, - <&clk IMX8MQ_CLK_VPU_G2>, - <&clk IMX8MQ_CLK_VPU_BUS>, - <&clk IMX8MQ_VPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_VPU_PLL>; - assigned-clock-rates = <600000000>, <600000000>, - <800000000>, <0>; - power-domains = <&pgc_vpu>; + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + clock-names = "g1", "g2"; + #power-domain-cells = <1>; }; pcie0: pcie@33800000 { @@ -1579,6 +1594,7 @@ <&clk IMX8MQ_DRAM_PLL_OUT>, <&clk IMX8MQ_CLK_DRAM_ALT>, <&clk IMX8MQ_CLK_DRAM_APB>; + status = "disabled"; }; ddr-pmu@3d800000 { diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi index 42637a45701c..ec1639174e2e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi @@ -19,3 +19,7 @@ &usdhc2 { compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; }; + +&usdhc3 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi index 30896610c654..669aa14ce9f7 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi @@ -56,6 +56,14 @@ compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu"; }; +&lsio_mu5 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu6 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + &lsio_mu13 { compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 4a7c017b5f31..be8c76a0554c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -20,6 +20,9 @@ mmc1 = &usdhc2; mmc2 = &usdhc3; serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; }; cpus { @@ -54,7 +57,7 @@ A53_0: cpu@0 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -68,7 +71,7 @@ A53_1: cpu@1 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x1>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -82,7 +85,7 @@ A53_2: cpu@2 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x2>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -96,7 +99,7 @@ A53_3: cpu@3 { device_type = "cpu"; - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; reg = <0x0 0x3>; enable-method = "psci"; i-cache-size = <0x8000>; @@ -110,7 +113,7 @@ A72_0: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x100>; enable-method = "psci"; i-cache-size = <0xC000>; @@ -124,7 +127,7 @@ A72_1: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a72", "arm,armv8"; + compatible = "arm,cortex-a72"; reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&A72_L2>; @@ -201,6 +204,9 @@ compatible = "fsl,imx8qm-iomuxc"; }; + rtc: rtc { + compatible = "fsl,imx8qxp-sc-rtc"; + }; }; /* sorted in register address */ diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi index dc1daa8dc72f..7bae516004bf 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -5,19 +5,19 @@ */ &lpuart0 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8qxp-lpuart"; }; &lpuart1 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8qxp-lpuart"; }; &lpuart2 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8qxp-lpuart"; }; &lpuart3 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8qxp-lpuart"; }; &i2c0 { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi index 11395479ffc0..8e2152c6eb88 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -56,6 +56,14 @@ compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; }; +&lsio_mu5 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu6 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + &lsio_mu13 { compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; }; diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index ce6d5bdba0a8..c2f0f1a1566c 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -66,6 +66,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_hub_vbus: regulator-hub-vbus { compatible = "regulator-fixed"; regulator-name = "MBA8MX_HUB_VBUS"; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index f4270cf18996..c78371703e76 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -300,7 +300,7 @@ status = "disabled"; }; - mmc: dwmmc0@ff808000 { + mmc: mmc@ff808000 { #address-cells = <1>; #size-cells = <0>; compatible = "altr,socfpga-dw-mshc"; @@ -337,7 +337,7 @@ reg = <0xffe00000 0x40000>; }; - pdma: pdma@ffda0000 { + pdma: dma-controller@ffda0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffda0000 0x1000>; interrupts = , @@ -510,6 +510,7 @@ resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; clocks = <&clkmgr AGILEX_USB_CLK>; + clock-names = "otg"; iommus = <&smmu 6>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 0f7a0ba344be..26cd3c121757 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -6,6 +6,7 @@ / { model = "SoCFPGA Agilex SoCDK"; + compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex"; aliases { serial0 = &uart0; @@ -20,17 +21,17 @@ leds { compatible = "gpio-leds"; - hps0 { + led0 { label = "hps_led0"; gpios = <&portb 20 GPIO_ACTIVE_HIGH>; }; - hps1 { + led1 { label = "hps_led1"; gpios = <&portb 19 GPIO_ACTIVE_HIGH>; }; - hps2 { + led2 { label = "hps_led2"; gpios = <&portb 21 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts index 57f83481f551..51f83f96ec65 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts @@ -6,6 +6,7 @@ / { model = "SoCFPGA Agilex SoCDK"; + compatible = "intel,socfpga-agilex-socdk", "intel,socfpga-agilex"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index f3c1310dae0a..62c66e52b656 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -6,6 +6,7 @@ / { model = "eASIC N5X SoCDK"; + compatible = "intel,n5x-socdk", "intel,socfpga-agilex"; aliases { serial0 = &uart0; @@ -23,6 +24,15 @@ /* We expect the bootloader to fill in the reg */ reg = <0 0 0 0>; }; + + soc { + sdram_edac: memory-controller@f87f8000 { + compatible = "snps,ddrc-3.80a"; + reg = <0xf87f8000 0x400>; + interrupts = <0 175 4>; + status = "okay"; + }; + }; }; &clkmgr { diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 081fe7a9f605..bec97480a960 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -182,12 +182,13 @@ clocks = <&clk_bus>; clock-names = "apb_pclk"; }; - dmac0: dma@c1128000 { + dmac0: dma-controller@c1128000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xc1128000 0x1000>; interrupts = ; clocks = <&clk_bus>; clock-names = "apb_pclk"; + #dma-cells = <1>; }; gpio0: gpio@fd400000 { #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index 604bb6975337..ada3d4dc6305 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -182,12 +182,13 @@ clocks = <&clk_bus>; clock-names = "apb_pclk"; }; - dmac0: dma@c1128000 { + dmac0: dma-controller@c1128000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xc1128000 0x1000>; interrupts = ; clocks = <&clk_bus>; clock-names = "apb_pclk"; + #dma-cells = <1>; }; gpio0: gpio@fd400000 { #gpio-cells = <2>; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index fb78ef613b29..30233de58bb3 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -489,6 +489,7 @@ bus-range = <0x00 0xff>; interrupts = ; #interrupt-cells = <1>; + clocks = <&sb_periph_clk 13>; msi-parent = <&pcie0>; msi-controller; /* diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts/mediatek/mt6358.dtsi index 95145076b7e6..98f3b0e0c9f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt6358.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6358.dtsi @@ -2,6 +2,7 @@ /* * Copyright (c) 2020 MediaTek Inc. */ +#include &pwrap { pmic: mt6358 { @@ -357,5 +358,16 @@ mt6358rtc: mt6358rtc { compatible = "mediatek,mt6358-rtc"; }; + + mt6358keys: mt6358keys { + compatible = "mediatek,mt6358-keys"; + power { + linux,keycodes = ; + wakeup-source; + }; + home { + linux,keycodes = ; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index 5cd760abff51..21e420829572 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -19,7 +19,8 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@40000000 { + device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index b8da76b6ba47..694acf8f5b70 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -6,16 +6,18 @@ #include #include +#include / { interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; - system_clk: dummy40m { + clk40m: oscillator@0 { compatible = "fixed-clock"; clock-frequency = <40000000>; #clock-cells = <0>; + clock-output-names = "clkxtal"; }; cpus { @@ -98,6 +100,18 @@ interrupts = ; }; + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7986-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7986-topckgen", "syscon"; + reg = <0 0x1001B000 0 0x1000>; + #clock-cells = <1>; + }; + watchdog: watchdog@1001c000 { compatible = "mediatek,mt7986-wdt", "mediatek,mt6589-wdt"; @@ -107,6 +121,12 @@ status = "disabled"; }; + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7986-apmixedsys"; + reg = <0 0x1001E000 0 0x1000>; + #clock-cells = <1>; + }; + pio: pinctrl@1001f000 { compatible = "mediatek,mt7986a-pinctrl"; reg = <0 0x1001f000 0 0x1000>, @@ -128,11 +148,25 @@ #interrupt-cells = <2>; }; + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7986-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7986-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + trng: trng@1020f000 { compatible = "mediatek,mt7986-rng", "mediatek,mt7623-rng"; reg = <0 0x1020f000 0 0x100>; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_TRNG_CK>; clock-names = "rng"; status = "disabled"; }; @@ -142,7 +176,13 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = ; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART0_SEL>, + <&infracfg CLK_INFRA_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; status = "disabled"; }; @@ -151,7 +191,11 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = ; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART1_SEL>, + <&infracfg CLK_INFRA_UART1_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; status = "disabled"; }; @@ -160,10 +204,24 @@ "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = ; - clocks = <&system_clk>; + clocks = <&infracfg CLK_INFRA_UART2_SEL>, + <&infracfg CLK_INFRA_UART2_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; status = "disabled"; }; + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7986-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 5fb752edd754..d73467ea3641 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -19,7 +19,8 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@40000000 { + device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 00f2ddd245e1..4b08691ed39e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1594,6 +1594,18 @@ power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; }; + venc_jpg: venc_jpg@17030000 { + compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; + reg = <0 0x17030000 0 0x1000>; + interrupts = ; + mediatek,larb = <&larb4>; + iommus = <&iommu M4U_PORT_JPGENC_RDMA>, + <&iommu M4U_PORT_JPGENC_BSDMA>; + power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_JPGENC>; + clock-names = "jpgenc"; + }; + ipu_conn: syscon@19000000 { compatible = "mediatek,mt8183-ipu_conn", "syscon"; reg = <0 0x19000000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 53d790c335f9..411feb294613 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8192"; @@ -301,6 +302,212 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8192-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + power-domain@MT8192_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&infracfg CLK_INFRA_AUDIO>; + clock-names = "audio", "audio1", "audio2"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CONN { + reg = ; + clocks = <&infracfg CLK_INFRA_PMIC_CONN>; + clock-names = "conn"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG0 { + reg = ; + clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_MFG1 { + reg = ; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_MFG2 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG3 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG4 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG5 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MFG6 { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8192_POWER_DOMAIN_DISP { + reg = ; + clocks = <&topckgen CLK_TOP_DISP_SEL>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "disp", "disp-0", "disp-1", "disp-2", + "disp-3"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_IPE { + reg = ; + clocks = <&topckgen CLK_TOP_IPE_SEL>, + <&ipesys CLK_IPE_LARB19>, + <&ipesys CLK_IPE_LARB20>, + <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_GALS>; + clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", + "ipe-3"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_IMG1_SEL>, + <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_GALS>; + clock-names = "isp", "isp-0", "isp-1"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_ISP2 { + reg = ; + clocks = <&topckgen CLK_TOP_IMG2_SEL>, + <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_GALS>; + clock-names = "isp2", "isp2-0", "isp2-1"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_MDP { + reg = ; + clocks = <&topckgen CLK_TOP_MDP_SEL>, + <&mdpsys CLK_MDP_SMI0>; + clock-names = "mdp", "mdp-0"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_VENC { + reg = ; + clocks = <&topckgen CLK_TOP_VENC_SEL>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "venc", "venc-0"; + mediatek,infracfg = <&infracfg>; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_VDEC2 { + reg = ; + clocks = <&vdecsys CLK_VDEC_VDEC>, + <&vdecsys CLK_VDEC_LAT>, + <&vdecsys CLK_VDEC_LARB1>; + clock-names = "vdec2-0", "vdec2-1", + "vdec2-2"; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM { + reg = ; + clocks = <&topckgen CLK_TOP_CAM_SEL>, + <&camsys CLK_CAM_LARB13>, + <&camsys CLK_CAM_LARB14>, + <&camsys CLK_CAM_CCU_GALS>, + <&camsys CLK_CAM_CAM2MM_GALS>; + clock-names = "cam", "cam-0", "cam-1", "cam-2", + "cam-3"; + mediatek,infracfg = <&infracfg>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { + reg = ; + clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "cam_rawa-0"; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { + reg = ; + clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "cam_rawb-0"; + #power-domain-cells = <0>; + }; + + power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { + reg = ; + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; + clock-names = "cam_rawc-0"; + #power-domain-cells = <0>; + }; + }; + }; + }; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8192-wdt"; + reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; + }; + apmixedsys: syscon@1000c000 { compatible = "mediatek,mt8192-apmixedsys", "syscon"; reg = <0 0x1000c000 0 0x1000>; @@ -312,7 +519,7 @@ "mediatek,mt6765-timer"; reg = <0 0x10017000 0 0x1000>; interrupts = ; - clocks = <&clk26m>; + clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; clock-names = "clk13m"; }; @@ -327,7 +534,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; clock-names = "baud", "bus"; status = "disabled"; }; @@ -337,7 +544,7 @@ "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; clock-names = "baud", "bus"; status = "disabled"; }; @@ -355,9 +562,9 @@ #size-cells = <0>; reg = <0 0x1100a000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -369,9 +576,9 @@ #size-cells = <0>; reg = <0 0x11010000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI1>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -383,9 +590,9 @@ #size-cells = <0>; reg = <0 0x11012000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI2>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -397,9 +604,9 @@ #size-cells = <0>; reg = <0 0x11013000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI3>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -411,9 +618,9 @@ #size-cells = <0>; reg = <0 0x11018000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI4>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -425,9 +632,9 @@ #size-cells = <0>; reg = <0 0x11019000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI5>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -439,9 +646,9 @@ #size-cells = <0>; reg = <0 0x1101d000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI6>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -453,9 +660,9 @@ #size-cells = <0>; reg = <0 0x1101e000 0 0x1000>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI7>; clock-names = "parent-clk", "sel-clk", "spi-clk"; status = "disabled"; }; @@ -464,10 +671,12 @@ compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; interrupts = ; - clocks = <&clk26m>, - <&clk26m>, - <&clk26m>; + clocks = <&topckgen CLK_TOP_SFLASH_SEL>, + <&infracfg CLK_INFRA_FLASHIF_SFLASH>, + <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; clock-names = "spi", "sf", "axi"; + assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; + assigned-clock-parents = <&clk26m>; #address-cells = <1>; #size-cells = <0>; status = "disable"; @@ -484,7 +693,8 @@ reg = <0 0x11cb0000 0 0x1000>, <0 0x10217300 0 0x80>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -503,7 +713,8 @@ reg = <0 0x11d00000 0 0x1000>, <0 0x10217600 0 0x180>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -516,7 +727,8 @@ reg = <0 0x11d01000 0 0x1000>, <0 0x10217780 0 0x180>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -529,7 +741,8 @@ reg = <0 0x11d02000 0 0x1000>, <0 0x10217900 0 0x180>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -548,7 +761,8 @@ reg = <0 0x11d20000 0 0x1000>, <0 0x10217100 0 0x80>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -561,7 +775,8 @@ reg = <0 0x11d21000 0 0x1000>, <0 0x10217180 0 0x180>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -574,7 +789,8 @@ reg = <0 0x11d22000 0 0x1000>, <0 0x10217380 0 0x180>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -593,7 +809,8 @@ reg = <0 0x11e00000 0 0x1000>, <0 0x10217500 0 0x80>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -612,7 +829,8 @@ reg = <0 0x11f00000 0 0x1000>, <0 0x10217080 0 0x80>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; @@ -625,7 +843,8 @@ reg = <0 0x11f01000 0 0x1000>, <0 0x10217580 0 0x80>; interrupts = ; - clocks = <&clk26m>, <&clk26m>; + clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, + <&infracfg CLK_INFRA_AP_DMA>; clock-names = "main", "dma"; clock-div = <1>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index ea3f338fd013..bc34c9d8846a 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -1,4 +1,15 @@ # SPDX-License-Identifier: GPL-2.0 + +# Enables support for device-tree overlays +DTC_FLAGS_tegra210-p2371-2180 := -@ +DTC_FLAGS_tegra210-p3450-0000 := -@ +DTC_FLAGS_tegra186-p2771-0000 := -@ +DTC_FLAGS_tegra186-p3509-0000+p3636-0001 := -@ +DTC_FLAGS_tegra194-p2972-0000 := -@ +DTC_FLAGS_tegra194-p3509-0000+p3668-0000 := -@ +DTC_FLAGS_tegra194-p3509-0000+p3668-0001 := -@ +DTC_FLAGS_tegra234-p3737-0000+p3701-0000 := -@ + dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index c91afff1b757..e9b40f5d79ec 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -73,6 +73,48 @@ snps,rxpbl = <8>; }; + gpcdma: dma-controller@2600000 { + compatible = "nvidia,tegra186-gpcdma"; + reg = <0x0 0x2600000 0x0 0x210000>; + resets = <&bpmp TEGRA186_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + status = "okay"; + }; + aconnect@2900000 { compatible = "nvidia,tegra186-aconnect", "nvidia,tegra210-aconnect"; @@ -1938,14 +1980,14 @@ }; pmu_denver { - compatible = "nvidia,denver-pmu", "arm,armv8-pmuv3"; + compatible = "nvidia,denver-pmu"; interrupts = , ; interrupt-affinity = <&denver_0 &denver_1>; }; pmu_a57 { - compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3"; + compatible = "arm,cortex-a57-pmu"; interrupts = , , , diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 1323fa9b8301..32ce7904f44f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -1826,6 +1826,10 @@ pads { usb2 { lanes { + usb2-0 { + status = "okay"; + }; + usb2-1 { status = "okay"; }; @@ -1846,6 +1850,20 @@ }; ports { + usb2-0 { + mode = "otg"; + status = "okay"; + usb-role-switch; + connector { + compatible = "gpio-usb-b-connector", + "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-gpio = <&gpio TEGRA194_MAIN_GPIO(Z, 1) + GPIO_ACTIVE_LOW>; + }; + }; + usb2-1 { mode = "host"; status = "okay"; @@ -1874,6 +1892,13 @@ phy-names = "usb2-1", "usb2-2", "usb3-2"; }; + usb@3550000 { + status = "okay"; + + phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>; + phy-names = "usb2-0"; + }; + spi@3270000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index aaa00da5351d..751ebe5e9506 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -115,6 +115,49 @@ snps,rxpbl = <8>; }; + gpcdma: dma-controller@2600000 { + compatible = "nvidia,tegra194-gpcdma", + "nvidia,tegra186-gpcdma"; + reg = <0x2600000 0x210000>; + resets = <&bpmp TEGRA194_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + iommus = <&smmu TEGRA194_SID_GPCDMA_0>; + dma-coherent; + status = "okay"; + }; + aconnect@2900000 { compatible = "nvidia,tegra194-aconnect", "nvidia,tegra210-aconnect"; @@ -243,6 +286,10 @@ "rx19", "tx19", "rx20", "tx20"; status = "disabled"; + interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA194_SID_APE>; }; tegra_i2s1: i2s@2901000 { @@ -2839,7 +2886,7 @@ }; pmu { - compatible = "arm,armv8-pmuv3"; + compatible = "nvidia,carmel-pmu"; interrupts = , , , @@ -2876,11 +2923,6 @@ * for 8x and 11.025x sample rate streams. */ assigned-clock-rates = <258000000>; - - interconnects = <&mc TEGRA194_MEMORY_CLIENT_APEDMAR &emc>, - <&mc TEGRA194_MEMORY_CLIENT_APEDMAW &emc>; - interconnect-names = "dma-mem", "write"; - iommus = <&smmu TEGRA194_SID_APE>; }; tcu: serial { diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index efbbb878ba5a..34d6a01ee1c6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; +#include +#include + #include "tegra234-p3701-0000.dtsi" #include "tegra234-p3737-0000.dtsi" @@ -11,6 +14,1744 @@ aliases { mmc3 = "/bus@0/mmc@3460000"; serial0 = &tcu; + serial1 = &uarta; + }; + + bus@0 { + aconnect@2900000 { + status = "okay"; + + ahub@2900800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0: endpoint { + remote-endpoint = <&admaif0>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1: endpoint { + remote-endpoint = <&admaif1>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2: endpoint { + remote-endpoint = <&admaif2>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3: endpoint { + remote-endpoint = <&admaif3>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4: endpoint { + remote-endpoint = <&admaif4>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5: endpoint { + remote-endpoint = <&admaif5>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6: endpoint { + remote-endpoint = <&admaif6>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7: endpoint { + remote-endpoint = <&admaif7>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8: endpoint { + remote-endpoint = <&admaif8>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9: endpoint { + remote-endpoint = <&admaif9>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10: endpoint { + remote-endpoint = <&admaif10>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11: endpoint { + remote-endpoint = <&admaif11>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12: endpoint { + remote-endpoint = <&admaif12>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13: endpoint { + remote-endpoint = <&admaif13>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14: endpoint { + remote-endpoint = <&admaif14>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15: endpoint { + remote-endpoint = <&admaif15>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16: endpoint { + remote-endpoint = <&admaif16>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17: endpoint { + remote-endpoint = <&admaif17>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18: endpoint { + remote-endpoint = <&admaif18>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19: endpoint { + remote-endpoint = <&admaif19>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1: endpoint { + remote-endpoint = <&i2s1_cif>; + }; + }; + + xbar_i2s2_port: port@15 { + reg = <0x15>; + + xbar_i2s2: endpoint { + remote-endpoint = <&i2s2_cif>; + }; + }; + + xbar_i2s4_port: port@17 { + reg = <0x17>; + + xbar_i2s4: endpoint { + remote-endpoint = <&i2s4_cif>; + }; + }; + + xbar_i2s6_port: port@19 { + reg = <0x19>; + + xbar_i2s6: endpoint { + remote-endpoint = <&i2s6_cif>; + }; + }; + + xbar_dmic3_port: port@1c { + reg = <0x1c>; + + xbar_dmic3: endpoint { + remote-endpoint = <&dmic3_cif>; + }; + }; + + xbar_sfc1_in_port: port@20 { + reg = <0x20>; + + xbar_sfc1_in: endpoint { + remote-endpoint = <&sfc1_cif_in>; + }; + }; + + port@21 { + reg = <0x21>; + + xbar_sfc1_out: endpoint { + remote-endpoint = <&sfc1_cif_out>; + }; + }; + + xbar_sfc2_in_port: port@22 { + reg = <0x22>; + + xbar_sfc2_in: endpoint { + remote-endpoint = <&sfc2_cif_in>; + }; + }; + + port@23 { + reg = <0x23>; + + xbar_sfc2_out: endpoint { + remote-endpoint = <&sfc2_cif_out>; + }; + }; + + xbar_sfc3_in_port: port@24 { + reg = <0x24>; + + xbar_sfc3_in: endpoint { + remote-endpoint = <&sfc3_cif_in>; + }; + }; + + port@25 { + reg = <0x25>; + + xbar_sfc3_out: endpoint { + remote-endpoint = <&sfc3_cif_out>; + }; + }; + + xbar_sfc4_in_port: port@26 { + reg = <0x26>; + + xbar_sfc4_in: endpoint { + remote-endpoint = <&sfc4_cif_in>; + }; + }; + + port@27 { + reg = <0x27>; + + xbar_sfc4_out: endpoint { + remote-endpoint = <&sfc4_cif_out>; + }; + }; + + xbar_mvc1_in_port: port@28 { + reg = <0x28>; + + xbar_mvc1_in: endpoint { + remote-endpoint = <&mvc1_cif_in>; + }; + }; + + port@29 { + reg = <0x29>; + + xbar_mvc1_out: endpoint { + remote-endpoint = <&mvc1_cif_out>; + }; + }; + + xbar_mvc2_in_port: port@2a { + reg = <0x2a>; + + xbar_mvc2_in: endpoint { + remote-endpoint = <&mvc2_cif_in>; + }; + }; + + port@2b { + reg = <0x2b>; + + xbar_mvc2_out: endpoint { + remote-endpoint = <&mvc2_cif_out>; + }; + }; + + xbar_amx1_in1_port: port@2c { + reg = <0x2c>; + + xbar_amx1_in1: endpoint { + remote-endpoint = <&amx1_in1>; + }; + }; + + xbar_amx1_in2_port: port@2d { + reg = <0x2d>; + + xbar_amx1_in2: endpoint { + remote-endpoint = <&amx1_in2>; + }; + }; + + xbar_amx1_in3_port: port@2e { + reg = <0x2e>; + + xbar_amx1_in3: endpoint { + remote-endpoint = <&amx1_in3>; + }; + }; + + xbar_amx1_in4_port: port@2f { + reg = <0x2f>; + + xbar_amx1_in4: endpoint { + remote-endpoint = <&amx1_in4>; + }; + }; + + port@30 { + reg = <0x30>; + + xbar_amx1_out: endpoint { + remote-endpoint = <&amx1_out>; + }; + }; + + xbar_amx2_in1_port: port@31 { + reg = <0x31>; + + xbar_amx2_in1: endpoint { + remote-endpoint = <&amx2_in1>; + }; + }; + + xbar_amx2_in2_port: port@32 { + reg = <0x32>; + + xbar_amx2_in2: endpoint { + remote-endpoint = <&amx2_in2>; + }; + }; + + xbar_amx2_in3_port: port@33 { + reg = <0x33>; + + xbar_amx2_in3: endpoint { + remote-endpoint = <&amx2_in3>; + }; + }; + + xbar_amx2_in4_port: port@34 { + reg = <0x34>; + + xbar_amx2_in4: endpoint { + remote-endpoint = <&amx2_in4>; + }; + }; + + port@35 { + reg = <0x35>; + + xbar_amx2_out: endpoint { + remote-endpoint = <&amx2_out>; + }; + }; + + xbar_amx3_in1_port: port@36 { + reg = <0x36>; + + xbar_amx3_in1: endpoint { + remote-endpoint = <&amx3_in1>; + }; + }; + + xbar_amx3_in2_port: port@37 { + reg = <0x37>; + + xbar_amx3_in2: endpoint { + remote-endpoint = <&amx3_in2>; + }; + }; + + xbar_amx3_in3_port: port@38 { + reg = <0x38>; + + xbar_amx3_in3: endpoint { + remote-endpoint = <&amx3_in3>; + }; + }; + + xbar_amx3_in4_port: port@39 { + reg = <0x39>; + + xbar_amx3_in4: endpoint { + remote-endpoint = <&amx3_in4>; + }; + }; + + port@3a { + reg = <0x3a>; + + xbar_amx3_out: endpoint { + remote-endpoint = <&amx3_out>; + }; + }; + + xbar_amx4_in1_port: port@3b { + reg = <0x3b>; + + xbar_amx4_in1: endpoint { + remote-endpoint = <&amx4_in1>; + }; + }; + + xbar_amx4_in2_port: port@3c { + reg = <0x3c>; + + xbar_amx4_in2: endpoint { + remote-endpoint = <&amx4_in2>; + }; + }; + + xbar_amx4_in3_port: port@3d { + reg = <0x3d>; + + xbar_amx4_in3: endpoint { + remote-endpoint = <&amx4_in3>; + }; + }; + + xbar_amx4_in4_port: port@3e { + reg = <0x3e>; + + xbar_amx4_in4: endpoint { + remote-endpoint = <&amx4_in4>; + }; + }; + + port@3f { + reg = <0x3f>; + + xbar_amx4_out: endpoint { + remote-endpoint = <&amx4_out>; + }; + }; + + xbar_adx1_in_port: port@40 { + reg = <0x40>; + + xbar_adx1_in: endpoint { + remote-endpoint = <&adx1_in>; + }; + }; + + port@41 { + reg = <0x41>; + + xbar_adx1_out1: endpoint { + remote-endpoint = <&adx1_out1>; + }; + }; + + port@42 { + reg = <0x42>; + + xbar_adx1_out2: endpoint { + remote-endpoint = <&adx1_out2>; + }; + }; + + port@43 { + reg = <0x43>; + + xbar_adx1_out3: endpoint { + remote-endpoint = <&adx1_out3>; + }; + }; + + port@44 { + reg = <0x44>; + + xbar_adx1_out4: endpoint { + remote-endpoint = <&adx1_out4>; + }; + }; + + xbar_adx2_in_port: port@45 { + reg = <0x45>; + + xbar_adx2_in: endpoint { + remote-endpoint = <&adx2_in>; + }; + }; + + port@46 { + reg = <0x46>; + + xbar_adx2_out1: endpoint { + remote-endpoint = <&adx2_out1>; + }; + }; + + port@47 { + reg = <0x47>; + + xbar_adx2_out2: endpoint { + remote-endpoint = <&adx2_out2>; + }; + }; + + port@48 { + reg = <0x48>; + + xbar_adx2_out3: endpoint { + remote-endpoint = <&adx2_out3>; + }; + }; + + port@49 { + reg = <0x49>; + + xbar_adx2_out4: endpoint { + remote-endpoint = <&adx2_out4>; + }; + }; + + xbar_adx3_in_port: port@4a { + reg = <0x4a>; + + xbar_adx3_in: endpoint { + remote-endpoint = <&adx3_in>; + }; + }; + + port@4b { + reg = <0x4b>; + + xbar_adx3_out1: endpoint { + remote-endpoint = <&adx3_out1>; + }; + }; + + port@4c { + reg = <0x4c>; + + xbar_adx3_out2: endpoint { + remote-endpoint = <&adx3_out2>; + }; + }; + + port@4d { + reg = <0x4d>; + + xbar_adx3_out3: endpoint { + remote-endpoint = <&adx3_out3>; + }; + }; + + port@4e { + reg = <0x4e>; + + xbar_adx3_out4: endpoint { + remote-endpoint = <&adx3_out4>; + }; + }; + + xbar_adx4_in_port: port@4f { + reg = <0x4f>; + + xbar_adx4_in: endpoint { + remote-endpoint = <&adx4_in>; + }; + }; + + port@50 { + reg = <0x50>; + + xbar_adx4_out1: endpoint { + remote-endpoint = <&adx4_out1>; + }; + }; + + port@51 { + reg = <0x51>; + + xbar_adx4_out2: endpoint { + remote-endpoint = <&adx4_out2>; + }; + }; + + port@52 { + reg = <0x52>; + + xbar_adx4_out3: endpoint { + remote-endpoint = <&adx4_out3>; + }; + }; + + port@53 { + reg = <0x53>; + + xbar_adx4_out4: endpoint { + remote-endpoint = <&adx4_out4>; + }; + }; + + xbar_mix_in1_port: port@54 { + reg = <0x54>; + + xbar_mix_in1: endpoint { + remote-endpoint = <&mix_in1>; + }; + }; + + xbar_mix_in2_port: port@55 { + reg = <0x55>; + + xbar_mix_in2: endpoint { + remote-endpoint = <&mix_in2>; + }; + }; + + xbar_mix_in3_port: port@56 { + reg = <0x56>; + + xbar_mix_in3: endpoint { + remote-endpoint = <&mix_in3>; + }; + }; + + xbar_mix_in4_port: port@57 { + reg = <0x57>; + + xbar_mix_in4: endpoint { + remote-endpoint = <&mix_in4>; + }; + }; + + xbar_mix_in5_port: port@58 { + reg = <0x58>; + + xbar_mix_in5: endpoint { + remote-endpoint = <&mix_in5>; + }; + }; + + xbar_mix_in6_port: port@59 { + reg = <0x59>; + + xbar_mix_in6: endpoint { + remote-endpoint = <&mix_in6>; + }; + }; + + xbar_mix_in7_port: port@5a { + reg = <0x5a>; + + xbar_mix_in7: endpoint { + remote-endpoint = <&mix_in7>; + }; + }; + + xbar_mix_in8_port: port@5b { + reg = <0x5b>; + + xbar_mix_in8: endpoint { + remote-endpoint = <&mix_in8>; + }; + }; + + xbar_mix_in9_port: port@5c { + reg = <0x5c>; + + xbar_mix_in9: endpoint { + remote-endpoint = <&mix_in9>; + }; + }; + + xbar_mix_in10_port: port@5d { + reg = <0x5d>; + + xbar_mix_in10: endpoint { + remote-endpoint = <&mix_in10>; + }; + }; + + port@5e { + reg = <0x5e>; + + xbar_mix_out1: endpoint { + remote-endpoint = <&mix_out1>; + }; + }; + + port@5f { + reg = <0x5f>; + + xbar_mix_out2: endpoint { + remote-endpoint = <&mix_out2>; + }; + }; + + port@60 { + reg = <0x60>; + + xbar_mix_out3: endpoint { + remote-endpoint = <&mix_out3>; + }; + }; + + port@61 { + reg = <0x61>; + + xbar_mix_out4: endpoint { + remote-endpoint = <&mix_out4>; + }; + }; + + port@62 { + reg = <0x62>; + + xbar_mix_out5: endpoint { + remote-endpoint = <&mix_out5>; + }; + }; + }; + + i2s@2901000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s1_cif: endpoint { + remote-endpoint = <&xbar_i2s1>; + }; + }; + + i2s1_port: port@1 { + reg = <1>; + + i2s1_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + i2s@2901100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s2_cif: endpoint { + remote-endpoint = <&xbar_i2s2>; + }; + }; + + i2s2_port: port@1 { + reg = <1>; + + i2s2_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + i2s@2901300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s4_cif: endpoint { + remote-endpoint = <&xbar_i2s4>; + }; + }; + + i2s4_port: port@1 { + reg = <1>; + + i2s4_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + i2s@2901500 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s6_cif: endpoint { + remote-endpoint = <&xbar_i2s6>; + }; + }; + + i2s6_port: port@1 { + reg = <1>; + + i2s6_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + sfc@2902000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in: endpoint { + remote-endpoint = <&xbar_sfc1_in>; + }; + }; + + sfc1_out_port: port@1 { + reg = <1>; + + sfc1_cif_out: endpoint { + remote-endpoint = <&xbar_sfc1_out>; + }; + }; + }; + }; + + sfc@2902200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in: endpoint { + remote-endpoint = <&xbar_sfc2_in>; + }; + }; + + sfc2_out_port: port@1 { + reg = <1>; + + sfc2_cif_out: endpoint { + remote-endpoint = <&xbar_sfc2_out>; + }; + }; + }; + }; + + sfc@2902400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc3_cif_in: endpoint { + remote-endpoint = <&xbar_sfc3_in>; + }; + }; + + sfc3_out_port: port@1 { + reg = <1>; + + sfc3_cif_out: endpoint { + remote-endpoint = <&xbar_sfc3_out>; + }; + }; + }; + }; + + sfc@2902600 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc4_cif_in: endpoint { + remote-endpoint = <&xbar_sfc4_in>; + }; + }; + + sfc4_out_port: port@1 { + reg = <1>; + + sfc4_cif_out: endpoint { + remote-endpoint = <&xbar_sfc4_out>; + }; + }; + }; + }; + + amx@2903000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx1_in1: endpoint { + remote-endpoint = <&xbar_amx1_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx1_in2: endpoint { + remote-endpoint = <&xbar_amx1_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx1_in3: endpoint { + remote-endpoint = <&xbar_amx1_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx1_in4: endpoint { + remote-endpoint = <&xbar_amx1_in4>; + }; + }; + + amx1_out_port: port@4 { + reg = <4>; + + amx1_out: endpoint { + remote-endpoint = <&xbar_amx1_out>; + }; + }; + }; + }; + + amx@2903100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx2_in1: endpoint { + remote-endpoint = <&xbar_amx2_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx2_in2: endpoint { + remote-endpoint = <&xbar_amx2_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx2_in3: endpoint { + remote-endpoint = <&xbar_amx2_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx2_in4: endpoint { + remote-endpoint = <&xbar_amx2_in4>; + }; + }; + + amx2_out_port: port@4 { + reg = <4>; + + amx2_out: endpoint { + remote-endpoint = <&xbar_amx2_out>; + }; + }; + }; + }; + + amx@2903200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx3_in1: endpoint { + remote-endpoint = <&xbar_amx3_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx3_in2: endpoint { + remote-endpoint = <&xbar_amx3_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx3_in3: endpoint { + remote-endpoint = <&xbar_amx3_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx3_in4: endpoint { + remote-endpoint = <&xbar_amx3_in4>; + }; + }; + + amx3_out_port: port@4 { + reg = <4>; + + amx3_out: endpoint { + remote-endpoint = <&xbar_amx3_out>; + }; + }; + }; + }; + + amx@2903300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx4_in1: endpoint { + remote-endpoint = <&xbar_amx4_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx4_in2: endpoint { + remote-endpoint = <&xbar_amx4_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx4_in3: endpoint { + remote-endpoint = <&xbar_amx4_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx4_in4: endpoint { + remote-endpoint = <&xbar_amx4_in4>; + }; + }; + + amx4_out_port: port@4 { + reg = <4>; + + amx4_out: endpoint { + remote-endpoint = <&xbar_amx4_out>; + }; + }; + }; + }; + + adx@2903800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx1_in: endpoint { + remote-endpoint = <&xbar_adx1_in>; + }; + }; + + adx1_out1_port: port@1 { + reg = <1>; + + adx1_out1: endpoint { + remote-endpoint = <&xbar_adx1_out1>; + }; + }; + + adx1_out2_port: port@2 { + reg = <2>; + + adx1_out2: endpoint { + remote-endpoint = <&xbar_adx1_out2>; + }; + }; + + adx1_out3_port: port@3 { + reg = <3>; + + adx1_out3: endpoint { + remote-endpoint = <&xbar_adx1_out3>; + }; + }; + + adx1_out4_port: port@4 { + reg = <4>; + + adx1_out4: endpoint { + remote-endpoint = <&xbar_adx1_out4>; + }; + }; + }; + }; + + adx@2903900 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx2_in: endpoint { + remote-endpoint = <&xbar_adx2_in>; + }; + }; + + adx2_out1_port: port@1 { + reg = <1>; + + adx2_out1: endpoint { + remote-endpoint = <&xbar_adx2_out1>; + }; + }; + + adx2_out2_port: port@2 { + reg = <2>; + + adx2_out2: endpoint { + remote-endpoint = <&xbar_adx2_out2>; + }; + }; + + adx2_out3_port: port@3 { + reg = <3>; + + adx2_out3: endpoint { + remote-endpoint = <&xbar_adx2_out3>; + }; + }; + + adx2_out4_port: port@4 { + reg = <4>; + + adx2_out4: endpoint { + remote-endpoint = <&xbar_adx2_out4>; + }; + }; + }; + }; + + adx@2903a00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx3_in: endpoint { + remote-endpoint = <&xbar_adx3_in>; + }; + }; + + adx3_out1_port: port@1 { + reg = <1>; + + adx3_out1: endpoint { + remote-endpoint = <&xbar_adx3_out1>; + }; + }; + + adx3_out2_port: port@2 { + reg = <2>; + + adx3_out2: endpoint { + remote-endpoint = <&xbar_adx3_out2>; + }; + }; + + adx3_out3_port: port@3 { + reg = <3>; + + adx3_out3: endpoint { + remote-endpoint = <&xbar_adx3_out3>; + }; + }; + + adx3_out4_port: port@4 { + reg = <4>; + + adx3_out4: endpoint { + remote-endpoint = <&xbar_adx3_out4>; + }; + }; + }; + }; + + adx@2903b00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in: endpoint { + remote-endpoint = <&xbar_adx4_in>; + }; + }; + + adx4_out1_port: port@1 { + reg = <1>; + + adx4_out1: endpoint { + remote-endpoint = <&xbar_adx4_out1>; + }; + }; + + adx4_out2_port: port@2 { + reg = <2>; + + adx4_out2: endpoint { + remote-endpoint = <&xbar_adx4_out2>; + }; + }; + + adx4_out3_port: port@3 { + reg = <3>; + + adx4_out3: endpoint { + remote-endpoint = <&xbar_adx4_out3>; + }; + }; + + adx4_out4_port: port@4 { + reg = <4>; + + adx4_out4: endpoint { + remote-endpoint = <&xbar_adx4_out4>; + }; + }; + }; + }; + + dmic@2904200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic3_cif: endpoint { + remote-endpoint = <&xbar_dmic3>; + }; + }; + + dmic3_port: port@1 { + reg = <1>; + + dmic3_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + mvc@290a000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in: endpoint { + remote-endpoint = <&xbar_mvc1_in>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out: endpoint { + remote-endpoint = <&xbar_mvc1_out>; + }; + }; + }; + }; + + mvc@290a200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in: endpoint { + remote-endpoint = <&xbar_mvc2_in>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out: endpoint { + remote-endpoint = <&xbar_mvc2_out>; + }; + }; + }; + }; + + amixer@290bb00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + mix_in1: endpoint { + remote-endpoint = <&xbar_mix_in1>; + }; + }; + + port@1 { + reg = <0x1>; + + mix_in2: endpoint { + remote-endpoint = <&xbar_mix_in2>; + }; + }; + + port@2 { + reg = <0x2>; + + mix_in3: endpoint { + remote-endpoint = <&xbar_mix_in3>; + }; + }; + + port@3 { + reg = <0x3>; + + mix_in4: endpoint { + remote-endpoint = <&xbar_mix_in4>; + }; + }; + + port@4 { + reg = <0x4>; + + mix_in5: endpoint { + remote-endpoint = <&xbar_mix_in5>; + }; + }; + + port@5 { + reg = <0x5>; + + mix_in6: endpoint { + remote-endpoint = <&xbar_mix_in6>; + }; + }; + + port@6 { + reg = <0x6>; + + mix_in7: endpoint { + remote-endpoint = <&xbar_mix_in7>; + }; + }; + + port@7 { + reg = <0x7>; + + mix_in8: endpoint { + remote-endpoint = <&xbar_mix_in8>; + }; + }; + + port@8 { + reg = <0x8>; + + mix_in9: endpoint { + remote-endpoint = <&xbar_mix_in9>; + }; + }; + + port@9 { + reg = <0x9>; + + mix_in10: endpoint { + remote-endpoint = <&xbar_mix_in10>; + }; + }; + + mix_out1_port: port@a { + reg = <0xa>; + + mix_out1: endpoint { + remote-endpoint = <&xbar_mix_out1>; + }; + }; + + mix_out2_port: port@b { + reg = <0xb>; + + mix_out2: endpoint { + remote-endpoint = <&xbar_mix_out2>; + }; + }; + + mix_out3_port: port@c { + reg = <0xc>; + + mix_out3: endpoint { + remote-endpoint = <&xbar_mix_out3>; + }; + }; + + mix_out4_port: port@d { + reg = <0xd>; + + mix_out4: endpoint { + remote-endpoint = <&xbar_mix_out4>; + }; + }; + + mix_out5_port: port@e { + reg = <0xe>; + + mix_out5: endpoint { + remote-endpoint = <&xbar_mix_out5>; + }; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0: endpoint { + remote-endpoint = <&xbar_admaif0>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1: endpoint { + remote-endpoint = <&xbar_admaif1>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2: endpoint { + remote-endpoint = <&xbar_admaif2>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3: endpoint { + remote-endpoint = <&xbar_admaif3>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4: endpoint { + remote-endpoint = <&xbar_admaif4>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5: endpoint { + remote-endpoint = <&xbar_admaif5>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6: endpoint { + remote-endpoint = <&xbar_admaif6>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7: endpoint { + remote-endpoint = <&xbar_admaif7>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8: endpoint { + remote-endpoint = <&xbar_admaif8>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9: endpoint { + remote-endpoint = <&xbar_admaif9>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10: endpoint { + remote-endpoint = <&xbar_admaif10>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11: endpoint { + remote-endpoint = <&xbar_admaif11>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12: endpoint { + remote-endpoint = <&xbar_admaif12>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13: endpoint { + remote-endpoint = <&xbar_admaif13>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14: endpoint { + remote-endpoint = <&xbar_admaif14>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15: endpoint { + remote-endpoint = <&xbar_admaif15>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16: endpoint { + remote-endpoint = <&xbar_admaif16>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17: endpoint { + remote-endpoint = <&xbar_admaif17>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18: endpoint { + remote-endpoint = <&xbar_admaif18>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19: endpoint { + remote-endpoint = <&xbar_admaif19>; + }; + }; + }; + }; + }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + + serial@3100000 { + compatible = "nvidia,tegra194-hsuart"; + status = "okay"; + }; + + hda@3510000 { + nvidia,model = "NVIDIA Jetson AGX Orin HDA"; + }; }; chosen { @@ -18,7 +1759,90 @@ stdout-path = "serial0:115200n8"; }; + gpio-keys { + compatible = "gpio-keys"; + status = "okay"; + + force-recovery { + label = "Force Recovery"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + + power-key { + label = "Power"; + gpios = <&gpio_aon TEGRA234_AON_GPIO(EE, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + + suspend { + label = "Suspend"; + gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + }; + }; + serial { status = "okay"; }; + + sound { + status = "okay"; + + compatible = "nvidia,tegra186-audio-graph-card"; + + dais = /* ADMAIF (FE) Ports */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* XBAR Ports */ + <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>, + <&xbar_i2s6_port>, <&xbar_dmic3_port>, + <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, + <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, + <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, + <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, + <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, + <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, + <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, + <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>, + <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>, + <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>, + <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>, + <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, + <&xbar_adx3_in_port>, <&xbar_adx4_in_port>, + <&xbar_mix_in1_port>, <&xbar_mix_in2_port>, + <&xbar_mix_in3_port>, <&xbar_mix_in4_port>, + <&xbar_mix_in5_port>, <&xbar_mix_in6_port>, + <&xbar_mix_in7_port>, <&xbar_mix_in8_port>, + <&xbar_mix_in9_port>, <&xbar_mix_in10_port>, + /* HW accelerators */ + <&sfc1_out_port>, <&sfc2_out_port>, + <&sfc3_out_port>, <&sfc4_out_port>, + <&mvc1_out_port>, <&mvc2_out_port>, + <&amx1_out_port>, <&amx2_out_port>, + <&amx3_out_port>, <&amx4_out_port>, + <&adx1_out1_port>, <&adx1_out2_port>, + <&adx1_out3_port>, <&adx1_out4_port>, + <&adx2_out1_port>, <&adx2_out2_port>, + <&adx2_out3_port>, <&adx2_out4_port>, + <&adx3_out1_port>, <&adx3_out2_port>, + <&adx3_out3_port>, <&adx3_out4_port>, + <&adx4_out1_port>, <&adx4_out2_port>, + <&adx4_out3_port>, <&adx4_out4_port>, + <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>, + <&mix_out4_port>, <&mix_out5_port>, + /* BE I/O Ports */ + <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, + <&dmic3_port>; + + label = "NVIDIA Jetson AGX Orin APE"; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 6b6f15804a1a..aaace605bdaa 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1,9 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 #include +#include #include #include #include +#include #include / { @@ -19,6 +21,424 @@ ranges = <0x0 0x0 0x0 0x40000000>; + aconnect@2900000 { + compatible = "nvidia,tegra234-aconnect", + "nvidia,tegra210-aconnect"; + clocks = <&bpmp TEGRA234_CLK_APE>, + <&bpmp TEGRA234_CLK_APB2APE>; + clock-names = "ape", "apb2ape"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900000 0x02900000 0x200000>; + status = "disabled"; + + tegra_ahub: ahub@2900800 { + compatible = "nvidia,tegra234-ahub"; + reg = <0x02900800 0x800>; + clocks = <&bpmp TEGRA234_CLK_AHUB>; + clock-names = "ahub"; + assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900800 0x02900800 0x11800>; + status = "disabled"; + + tegra_i2s1: i2s@2901000 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901000 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S1>, + <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S1"; + status = "disabled"; + }; + + tegra_i2s2: i2s@2901100 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901100 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S2>, + <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S2"; + status = "disabled"; + }; + + tegra_i2s3: i2s@2901200 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901200 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S3>, + <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S3"; + status = "disabled"; + }; + + tegra_i2s4: i2s@2901300 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901300 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S4>, + <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S4"; + status = "disabled"; + }; + + tegra_i2s5: i2s@2901400 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901400 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S5>, + <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S5"; + status = "disabled"; + }; + + tegra_i2s6: i2s@2901500 { + compatible = "nvidia,tegra234-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901500 0x100>; + clocks = <&bpmp TEGRA234_CLK_I2S6>, + <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S6"; + status = "disabled"; + }; + + tegra_sfc1: sfc@2902000 { + compatible = "nvidia,tegra234-sfc", + "nvidia,tegra210-sfc"; + reg = <0x2902000 0x200>; + sound-name-prefix = "SFC1"; + status = "disabled"; + }; + + tegra_sfc2: sfc@2902200 { + compatible = "nvidia,tegra234-sfc", + "nvidia,tegra210-sfc"; + reg = <0x2902200 0x200>; + sound-name-prefix = "SFC2"; + status = "disabled"; + }; + + tegra_sfc3: sfc@2902400 { + compatible = "nvidia,tegra234-sfc", + "nvidia,tegra210-sfc"; + reg = <0x2902400 0x200>; + sound-name-prefix = "SFC3"; + status = "disabled"; + }; + + tegra_sfc4: sfc@2902600 { + compatible = "nvidia,tegra234-sfc", + "nvidia,tegra210-sfc"; + reg = <0x2902600 0x200>; + sound-name-prefix = "SFC4"; + status = "disabled"; + }; + + tegra_amx1: amx@2903000 { + compatible = "nvidia,tegra234-amx", + "nvidia,tegra194-amx"; + reg = <0x2903000 0x100>; + sound-name-prefix = "AMX1"; + status = "disabled"; + }; + + tegra_amx2: amx@2903100 { + compatible = "nvidia,tegra234-amx", + "nvidia,tegra194-amx"; + reg = <0x2903100 0x100>; + sound-name-prefix = "AMX2"; + status = "disabled"; + }; + + tegra_amx3: amx@2903200 { + compatible = "nvidia,tegra234-amx", + "nvidia,tegra194-amx"; + reg = <0x2903200 0x100>; + sound-name-prefix = "AMX3"; + status = "disabled"; + }; + + tegra_amx4: amx@2903300 { + compatible = "nvidia,tegra234-amx", + "nvidia,tegra194-amx"; + reg = <0x2903300 0x100>; + sound-name-prefix = "AMX4"; + status = "disabled"; + }; + + tegra_adx1: adx@2903800 { + compatible = "nvidia,tegra234-adx", + "nvidia,tegra210-adx"; + reg = <0x2903800 0x100>; + sound-name-prefix = "ADX1"; + status = "disabled"; + }; + + tegra_adx2: adx@2903900 { + compatible = "nvidia,tegra234-adx", + "nvidia,tegra210-adx"; + reg = <0x2903900 0x100>; + sound-name-prefix = "ADX2"; + status = "disabled"; + }; + + tegra_adx3: adx@2903a00 { + compatible = "nvidia,tegra234-adx", + "nvidia,tegra210-adx"; + reg = <0x2903a00 0x100>; + sound-name-prefix = "ADX3"; + status = "disabled"; + }; + + tegra_adx4: adx@2903b00 { + compatible = "nvidia,tegra234-adx", + "nvidia,tegra210-adx"; + reg = <0x2903b00 0x100>; + sound-name-prefix = "ADX4"; + status = "disabled"; + }; + + + tegra_dmic1: dmic@2904000 { + compatible = "nvidia,tegra234-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904000 0x100>; + clocks = <&bpmp TEGRA234_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@2904100 { + compatible = "nvidia,tegra234-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904100 0x100>; + clocks = <&bpmp TEGRA234_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@2904200 { + compatible = "nvidia,tegra234-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904200 0x100>; + clocks = <&bpmp TEGRA234_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + + tegra_dmic4: dmic@2904300 { + compatible = "nvidia,tegra234-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904300 0x100>; + clocks = <&bpmp TEGRA234_CLK_DMIC4>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC4"; + status = "disabled"; + }; + + tegra_dspk1: dspk@2905000 { + compatible = "nvidia,tegra234-dspk", + "nvidia,tegra186-dspk"; + reg = <0x2905000 0x100>; + clocks = <&bpmp TEGRA234_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + }; + + tegra_dspk2: dspk@2905100 { + compatible = "nvidia,tegra234-dspk", + "nvidia,tegra186-dspk"; + reg = <0x2905100 0x100>; + clocks = <&bpmp TEGRA234_CLK_DSPK2>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK2"; + status = "disabled"; + }; + + tegra_mvc1: mvc@290a000 { + compatible = "nvidia,tegra234-mvc", + "nvidia,tegra210-mvc"; + reg = <0x290a000 0x200>; + sound-name-prefix = "MVC1"; + status = "disabled"; + }; + + tegra_mvc2: mvc@290a200 { + compatible = "nvidia,tegra234-mvc", + "nvidia,tegra210-mvc"; + reg = <0x290a200 0x200>; + sound-name-prefix = "MVC2"; + status = "disabled"; + }; + + tegra_amixer: amixer@290bb00 { + compatible = "nvidia,tegra234-amixer", + "nvidia,tegra210-amixer"; + reg = <0x290bb00 0x800>; + sound-name-prefix = "MIXER1"; + status = "disabled"; + }; + + tegra_admaif: admaif@290f000 { + compatible = "nvidia,tegra234-admaif", + "nvidia,tegra186-admaif"; + reg = <0x0290f000 0x1000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso0 TEGRA234_SID_APE>; + status = "disabled"; + }; + }; + + adma: dma-controller@2930000 { + compatible = "nvidia,tegra234-adma", + "nvidia,tegra186-adma"; + reg = <0x02930000 0x20000>; + interrupt-parent = <&agic>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells = <1>; + clocks = <&bpmp TEGRA234_CLK_AHUB>; + clock-names = "d_audio"; + status = "disabled"; + }; + + agic: interrupt-controller@2a40000 { + compatible = "nvidia,tegra234-agic", + "nvidia,tegra210-agic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x02a41000 0x1000>, + <0x02a42000 0x2000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_APE>; + clock-names = "clk"; + status = "disabled"; + }; + }; + misc@100000 { compatible = "nvidia,tegra234-misc"; reg = <0x00100000 0xf000>, @@ -144,6 +564,108 @@ status = "disabled"; }; + gen1_i2c: i2c@3160000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3160000 0x100>; + status = "disabled"; + interrupts = ; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C1 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C1>; + reset-names = "i2c"; + }; + + cam_i2c: i2c@3180000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3180000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C3 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C3>; + reset-names = "i2c"; + }; + + dp_aux_ch1_i2c: i2c@3190000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x3190000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C4 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C4>; + reset-names = "i2c"; + }; + + dp_aux_ch0_i2c: i2c@31b0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31b0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C6 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C6>; + reset-names = "i2c"; + }; + + dp_aux_ch2_i2c: i2c@31c0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31c0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C7 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C7>; + reset-names = "i2c"; + }; + + dp_aux_ch3_i2c: i2c@31e0000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0x31e0000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C9 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + resets = <&bpmp TEGRA234_RESET_I2C9>; + reset-names = "i2c"; + }; + + pwm1: pwm@3280000 { + compatible = "nvidia,tegra194-pwm", + "nvidia,tegra186-pwm"; + reg = <0x3280000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_PWM1>; + clock-names = "pwm"; + resets = <&bpmp TEGRA234_RESET_PWM1>; + reset-names = "pwm"; + status = "disabled"; + #pwm-cells = <2>; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; @@ -159,6 +681,7 @@ interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; @@ -172,6 +695,23 @@ status = "disabled"; }; + hda@3510000 { + compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; + reg = <0x3510000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, + <&bpmp TEGRA234_CLK_AZA_2XBIT>; + clock-names = "hda", "hda2codec_2x"; + resets = <&bpmp TEGRA234_RESET_HDA>, + <&bpmp TEGRA234_RESET_HDACODEC>; + reset-names = "hda", "hda2codec_2x"; + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; + interconnect-names = "dma-mem", "write"; + status = "disabled"; + }; + fuse@3810000 { compatible = "nvidia,tegra234-efuse"; reg = <0x03810000 0x10000>; @@ -197,6 +737,148 @@ #mbox-cells = <2>; }; + smmu_niso1: iommu@8000000 { + compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; + reg = <0x8000000 0x1000000>, + <0x7000000 0x1000000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <2>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; + hsp_aon: hsp@c150000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x0c150000 0x90000>; @@ -212,6 +894,37 @@ #mbox-cells = <2>; }; + gen2_i2c: i2c@c240000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0xc240000 0x100>; + interrupts = ; + status = "disabled"; + clock-frequency = <100000>; + clocks = <&bpmp TEGRA234_CLK_I2C2 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C2>; + reset-names = "i2c"; + }; + + gen8_i2c: i2c@c250000 { + compatible = "nvidia,tegra194-i2c"; + reg = <0xc250000 0x100>; + nvidia,hw-instance-id = <0x7>; + interrupts = ; + status = "disabled"; + clock-frequency = <400000>; + clocks = <&bpmp TEGRA234_CLK_I2C8 + &bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "div-clk", "parent"; + assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_I2C8>; + reset-names = "i2c"; + }; + rtc@c2a0000 { compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; reg = <0x0c2a0000 0x10000>; @@ -261,6 +974,288 @@ #interrupt-cells = <3>; interrupt-controller; }; + + smmu_iso: iommu@10000000{ + compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; + reg = <0x10000000 0x1000000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <1>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; + + smmu_niso0: iommu@12000000 { + compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; + reg = <0x12000000 0x1000000>, + <0x11000000 0x1000000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <2>; + #iommu-cells = <1>; + + nvidia,memory-controller = <&mc>; + status = "okay"; + }; }; sram@40000000 { @@ -296,6 +1291,7 @@ <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; interconnect-names = "read", "write", "dma-mem", "dma-write"; + iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; bpmp_i2c: i2c { compatible = "nvidia,tegra186-bpmp-i2c"; @@ -692,6 +1688,20 @@ status = "disabled"; }; + sound { + status = "disabled"; + + clocks = <&bpmp TEGRA234_CLK_PLLA>, + <&bpmp TEGRA234_CLK_PLLA_OUT0>; + clock-names = "pll_a", "plla_out0"; + assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, + <&bpmp TEGRA234_CLK_PLLA_OUT0>, + <&bpmp TEGRA234_CLK_AUD_MCLK>; + assigned-clock-parents = <0>, + <&bpmp TEGRA234_CLK_PLLA>, + <&bpmp TEGRA234_CLK_PLLA_OUT0>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f7232052d286..f9e6343acd03 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -18,10 +18,11 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8994-huawei-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-octagon-cityman.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-ivy.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-karin.dtb @@ -82,7 +83,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb @@ -90,6 +92,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb @@ -103,7 +106,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb @@ -121,4 +126,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index a5320d6d30e7..7c1eab605c15 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -253,7 +253,6 @@ port@0 { reg = <0>; csiphy0_ep: endpoint { - clock-lanes = <1>; data-lanes = <0 2>; remote-endpoint = <&ov5640_ep>; status = "okay"; @@ -289,7 +288,6 @@ port { ov5640_ep: endpoint { - clock-lanes = <1>; data-lanes = <0 2>; remote-endpoint = <&csiphy0_ep>; }; @@ -351,12 +349,12 @@ pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>; pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>; pinctrl-names = "default", "sleep"; - qcom,model = "DB410c"; - qcom,audio-routing = + model = "DB410c"; + audio-routing = "AMIC2", "MIC BIAS Internal2", "AMIC3", "MIC BIAS External1"; - external-dai-link@0 { + quaternary-dai-link { link-name = "ADV7533"; cpu { sound-dai = <&lpass MI2S_QUATERNARY>; @@ -366,7 +364,7 @@ }; }; - internal-codec-playback-dai-link@0 { + primary-dai-link { link-name = "WCD"; cpu { sound-dai = <&lpass MI2S_PRIMARY>; @@ -376,7 +374,7 @@ }; }; - internal-codec-capture-dai-link@0 { + tertiary-dai-link { link-name = "WCD-Capture"; cpu { sound-dai = <&lpass MI2S_TERTIARY>; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 66ec5615651d..4e7efa97724b 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -373,6 +373,8 @@ intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; + #address-cells = <2>; + #size-cells = <2>; interrupt-controller; #interrupt-cells = <0x3>; reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ @@ -380,6 +382,13 @@ <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ interrupts = ; + ranges = <0 0 0 0xb00a000 0 0xffd>; + + v2m@0 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0x0 0x0 0xffd>; + }; }; pcie_phy: phy@84000 { @@ -425,6 +434,7 @@ linux,pci-domain = <0>; bus-range = <0x00 0xff>; num-lanes = <1>; + max-link-speed = <3>; #address-cells = <3>; #size-cells = <2>; @@ -520,7 +530,6 @@ ranges; compatible = "arm,armv7-timer-mem"; reg = <0x0 0x0b120000 0x0 0x1000>; - clock-frequency = <19200000>; frame@b120000 { frame-number = <0>; @@ -748,7 +757,7 @@ snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; - snps,ref-clock-period-ns = <0x32>; + snps,ref-clock-period-ns = <0x29>; dr_mode = "host"; }; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index e6cc261201ef..d80b1cefab10 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -76,6 +76,25 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + smem@4ab00000 { + compatible = "qcom,smem"; + reg = <0x0 0x4ab00000 0x0 0x00100000>; + no-map; + + hwlocks = <&tcsr_mutex 0>; + }; + + memory@4ac00000 { + no-map; + reg = <0x0 0x4ac00000 0x0 0x00400000>; + }; + }; + firmware { scm { compatible = "qcom,scm-ipq8074", "qcom,scm"; @@ -331,6 +350,12 @@ #reset-cells = <0x1>; }; + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01905000 0x20000>; + #hwlock-cells = <1>; + }; + spmi_bus: spmi@200f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0200f000 0x001000>, @@ -609,9 +634,18 @@ intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; + #address-cells = <1>; + #size-cells = <1>; interrupt-controller; #interrupt-cells = <0x3>; reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + ranges = <0 0xb00a000 0xffd>; + + v2m@0 { + compatible = "arm,gic-v2m-frame"; + msi-controller; + reg = <0x0 0xffd>; + }; }; timer { @@ -636,7 +670,6 @@ ranges; compatible = "arm,armv7-timer-mem"; reg = <0x0b120000 0x1000>; - clock-frequency = <19200000>; frame@b120000 { frame-number = <0>; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 852de624f5af..b3836dde8a54 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -151,6 +151,21 @@ vddio-supply = <&pm8916_l6>; }; + light-sensor@23 { + compatible = "liteon,ltr559"; + reg = <0x23>; + proximity-near-level = <75>; + + interrupt-parent = <&msmgpio>; + interrupts = <115 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&light_int_default>; + + vdd-supply = <&pm8916_l17>; + vio-supply = <&pm8916_l6>; + }; + gyroscope@68 { compatible = "bosch,bmg160"; reg = <0x68>; @@ -392,6 +407,14 @@ bias-disable; }; + light_int_default: light-int-default { + pins = "gpio115"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + magn_int_default: magn-int-default { pins = "gpio113"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts index 687bea438a57..6c408d61de75 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts @@ -41,7 +41,7 @@ }; home-key { - lable = "Home Key"; + label = "Home Key"; gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>; linux,code = ; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 41897eb3736a..0a0be43529f6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1731,8 +1731,10 @@ clock-names = "ref", "sleep"; resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; reset-names = "phy", "por"; - qcom,init-seq = /bits/ 8 <0x0 0x44 - 0x1 0x6b 0x2 0x24 0x3 0x13>; + qcom,init-seq = /bits/ 8 <0x0 0x44>, + <0x1 0x6b>, + <0x2 0x24>, + <0x3 0x13>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi new file mode 100644 index 000000000000..431228faacdd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -0,0 +1,1326 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + next-level-cache = <&L2_1>; + #cooling-cells = <2>; + + l1-icache { + compatible = "cache"; + }; + l1-dcache { + compatible = "cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + L2_0: l2-cache_0 { + compatible = "cache"; + cache-level = <2>; + }; + + L2_1: l2-cache_1 { + compatible = "cache"; + cache-level = <2>; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-msm8953"; + clocks = <&gcc GCC_CRYPTO_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "core", "bus", "iface"; + #reset-cells = <1>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + zap_shader_region: memory@81800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x81800000 0x0 0x2000>; + no-map; + }; + + memory@85b00000 { + reg = <0x0 0x85b00000 0x0 0x800000>; + no-map; + }; + + smem_mem: memory@86300000 { + compatible = "qcom,smem"; + reg = <0x0 0x86300000 0x0 0x100000>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + memory@86400000 { + reg = <0x0 0x86400000 0x0 0x400000>; + no-map; + }; + + mpss_mem: memory@86c00000 { + reg = <0x0 0x86c00000 0x0 0x6a00000>; + no-map; + }; + + adsp_fw_mem: memory@8d600000 { + reg = <0x0 0x8d600000 0x0 0x1100000>; + no-map; + }; + + wcnss_fw_mem: memory@8e700000 { + reg = <0x0 0x8e700000 0x0 0x700000>; + no-map; + }; + + memory@90000000 { + reg = <0 0x90000000 0 0x1000>; + no-map; + }; + + memory@90001000 { + reg = <0x0 0x90001000 0x0 0x13ff000>; + no-map; + }; + + venus_mem: memory@91400000 { + reg = <0x0 0x91400000 0x0 0x700000>; + no-map; + }; + + mba_mem: memory@92000000 { + reg = <0x0 0x92000000 0x0 0x100000>; + no-map; + }; + + memory@f2d00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0xf2d00000 0x0 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + }; + + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm_requests { + compatible = "qcom,rpm-msm8953"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: rpmcc { + compatible = "qcom,rpmcc-msm8953"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8953-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + clocks = <&xo_board>; + clock-names = "ref"; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = ; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = ; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = ; + }; + + rpmpd_opp_svs: opp5 { + opp-level = ; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = ; + }; + + rpmpd_opp_nom: opp7 { + opp-level = ; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = ; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = ; + }; + }; + }; + }; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&apcs 8 13>; + qcom,ipc-3 = <&apcs 8 19>; + + apps_smsm: apps@0 { + reg = <0>; + + #qcom,smem-state-cells = <1>; + }; + }; + + soc: soc@0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + rpm_msg_ram: sram@60000 { + compatible = "qcom,rpm-msg-ram"; + reg = <0x60000 0x8000>; + }; + + hsusb_phy: phy@79000 { + compatible = "qcom,msm8953-qusb2-phy"; + reg = <0x79000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, + <&gcc GCC_QUSB_REF_CLK>; + clock-names = "cfg_ahb", "ref"; + + qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>; + + resets = <&gcc GCC_QUSB2_PHY_BCR>; + + status = "disabled"; + }; + + rng@e3000 { + compatible = "qcom,prng"; + reg = <0x000e3000 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + tsens0: thermal-sensor@4a9000 { + compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>; + }; + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8953-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 155>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart_console_active: uart-console-active-pins { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-disable; + }; + + uart_console_sleep: uart-console-sleep-pins { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-pull-down; + }; + + sdc1_clk_on: sdc1-clk-on-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + sdc1_clk_off: sdc1-clk-off-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc1_cmd_on: sdc1-cmd-on-pins { + pins = "sdc1_cmd"; + bias-disable; + drive-strength = <10>; + }; + + sdc1_cmd_off: sdc1-cmd-off-pins { + pins = "sdc1_cmd"; + bias-disable; + drive-strength = <2>; + }; + + sdc1_data_on: sdc1-data-on-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc1_data_off: sdc1-data-off-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc1_rclk_on: sdc1-rclk-on-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + + sdc1_rclk_off: sdc1-rclk-off-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + + sdc2_clk_on: sdc2-clk-on-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + sdc2_clk_off: sdc2-clk-off-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + sdc2_cmd_on: sdc2-cmd-on-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_cmd_off: sdc2-cmd-off-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_data_on: sdc2-data-on-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sdc2_data_off: sdc2-data-off-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sdc2_cd_on: cd-on-pins { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_cd_off: cd-off-pins { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_key_default: gpio-key-default-pins { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + i2c_1_default: i2c-1-default-pins { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + drive-strength = <2>; + bias-disable; + }; + + i2c_1_sleep: i2c-1-sleep-pins { + pins = "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_2_default: i2c-2-default-pins { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + drive-strength = <2>; + bias-disable; + }; + + i2c_2_sleep: i2c-2-sleep-pins { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_3_default: i2c-3-default-pins { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + drive-strength = <2>; + bias-disable; + }; + + i2c_3_sleep: i2c-3-sleep-pins { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_4_default: i2c-4-default-pins { + pins = "gpio14", "gpio15"; + function = "blsp_i2c4"; + drive-strength = <2>; + bias-disable; + }; + + i2c_4_sleep: i2c-4-sleep-pins { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_5_default: i2c-5-default-pins { + pins = "gpio18", "gpio19"; + function = "blsp_i2c5"; + drive-strength = <2>; + bias-disable; + }; + + i2c_5_sleep: i2c-5-sleep-pins { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_6_default: i2c-6-default-pins { + pins = "gpio22", "gpio23"; + function = "blsp_i2c6"; + drive-strength = <2>; + bias-disable; + }; + + i2c_6_sleep: i2c-6-sleep-pins { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_7_default: i2c-7-default-pins { + pins = "gpio135", "gpio136"; + function = "blsp_i2c7"; + drive-strength = <2>; + bias-disable; + }; + + i2c_7_sleep: i2c-7-sleep-pins { + pins = "gpio135", "gpio136"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + i2c_8_default: i2c-8-default-pins { + pins = "gpio98", "gpio99"; + function = "blsp_i2c8"; + drive-strength = <2>; + bias-disable; + }; + + i2c_8_sleep: i2c-8-sleep-pins { + pins = "gpio98", "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-msm8953"; + reg = <0x1800000 0x80000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "sleep", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte"; + }; + + tcsr_mutex: hwlock@1905000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x1905000 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr: syscon@1937000 { + compatible = "qcom,tcsr-msm8953", "syscon"; + reg = <0x1937000 0x30000>; + }; + + tcsr_phy_clk_scheme_sel: syscon@193f044 { + compatible = "syscon"; + reg = <0x193f044 0x4>; + }; + + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x200f000 0x1000>, + <0x2400000 0x800000>, + <0x2c00000 0x800000>, + <0x3800000 0x200000>, + <0x200a000 0x2100>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + interrupt-controller; + + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + usb3: usb@70f8800 { + compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; + reg = <0x70f8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts = , + ; + interrupt-names = "hs_phy_irq", "ss_phy_irq"; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_PCNOC_USB3_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", + "mock_utmi", "sleep"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133330000>; + + power-domains = <&gcc USB30_GDSC>; + + qcom,select-utmi-as-pipe-clk; + + status = "disabled"; + + usb3_dwc3: usb@7000000 { + compatible = "snps,dwc3"; + reg = <0x07000000 0xcc00>; + interrupts = ; + phys = <&hsusb_phy>; + phy-names = "usb2-phy"; + + snps,usb2-gadget-lpm-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x00>; + + maximum-speed = "high-speed"; + phy_mode = "utmi"; + }; + }; + + sdhc_1: sdhci@7824900 { + compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; + + reg = <0x7824900 0x500>, <0x7824000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + + power-domains = <&rpmpd MSM8953_VDDCX>; + operating-points-v2 = <&sdhc1_opp_table>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; + + mmc-hs400-1_8v; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + bus-width = <8>; + non-removable; + + status = "disabled"; + + sdhc1_opp_table: opp-table-sdhc1 { + compatible = "operating-points-v2"; + + opp-25000000 { + opp-hz = /bits/ 64 <25000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + sdhc_2: sdhci@7864900 { + compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; + + reg = <0x7864900 0x500>, <0x7864000 0x800>; + reg-names = "hc_mem", "core_mem"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; + clock-names = "iface", "core", "xo"; + + power-domains = <&rpmpd MSM8953_VDDCX>; + operating-points-v2 = <&sdhc2_opp_table>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; + + bus-width = <4>; + + status = "disabled"; + + sdhc2_opp_table: opp-table-sdhc2 { + compatible = "operating-points-v2"; + + opp-25000000 { + opp-hz = /bits/ 64 <25000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-177770000 { + opp-hz = /bits/ 64 <177770000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + uart_0: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + + status = "disabled"; + }; + + i2c_1: i2c@78b5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b5000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_1_default>; + pinctrl-1 = <&i2c_1_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_2: i2c@78b6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b6000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_2_default>; + pinctrl-1 = <&i2c_2_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_3: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b7000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_3_default>; + pinctrl-1 = <&i2c_3_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_4: i2c@78b8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b8000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_4_default>; + pinctrl-1 = <&i2c_4_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_5: i2c@7af5000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x7af5000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_5_default>; + pinctrl-1 = <&i2c_5_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_6: i2c@7af6000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x7af6000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_6_default>; + pinctrl-1 = <&i2c_6_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_7: i2c@7af7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x7af7000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_7_default>; + pinctrl-1 = <&i2c_7_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_8: i2c@7af8000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x7af8000 0x600>; + interrupts = ; + clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c_8_default>; + pinctrl-1 = <&i2c_8_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; + }; + + apcs: mailbox@b011000 { + compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; + reg = <0xb011000 0x1000>; + #mbox-cells = <1>; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0xb120000 0x1000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + ranges; + + frame@b121000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xb121000 0x1000>, + <0xb122000 0x1000>; + }; + + frame@b123000 { + frame-number = <1>; + interrupts = ; + reg = <0xb123000 0x1000>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = ; + reg = <0xb124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + frame-number = <3>; + interrupts = ; + reg = <0xb125000 0x1000>; + status = "disabled"; + }; + + frame@b126000 { + frame-number = <4>; + interrupts = ; + reg = <0xb126000 0x1000>; + status = "disabled"; + }; + + frame@b127000 { + frame-number = <5>; + interrupts = ; + reg = <0xb127000 0x1000>; + status = "disabled"; + }; + + frame@b128000 { + frame-number = <6>; + interrupts = ; + reg = <0xb128000 0x1000>; + status = "disabled"; + }; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 9>; + trips { + cpu0_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 10>; + trips { + cpu1_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu1_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 11>; + trips { + cpu2_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu2_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 12>; + trips { + cpu3_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu3_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu4-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 4>; + trips { + cpu4_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu4_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu4_alert>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu5-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 5>; + trips { + cpu5_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu5_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu5_alert>; + cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu6-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 6>; + trips { + cpu6_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu6_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu6_alert>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + cpu7-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsens0 7>; + trips { + cpu7_alert: trip-point0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu7_crit: crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu7_alert>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts new file mode 100644 index 000000000000..7e6bce4af441 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) Jean Thomas + */ + +/dts-v1/; + +#include "msm8992-lg-bullhead.dtsi" + +/ { + model = "LG Nexus 5X rev 1.0"; + + /* required for bootloader to select correct board */ + qcom,board-id = <0xa64 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts new file mode 100644 index 000000000000..e6a5ebd30e2f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) Jean Thomas + */ + +/dts-v1/; + +#include "msm8992-lg-bullhead.dtsi" + +/ { + model = "LG Nexus 5X rev 1.01"; + + /* required for bootloader to select correct board */ + qcom,board-id = <0xb64 0>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi similarity index 98% rename from arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts rename to arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi index 4da6c44bf532..3b0cc85d6674 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi @@ -18,9 +18,7 @@ compatible = "lg,bullhead", "qcom,msm8992"; chassis-type = "handset"; - /* required for bootloader to select correct board */ qcom,msm-id = <251 0>, <252 0>; - qcom,board-id = <0xb64 0>; qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; /* Bullhead firmware doesn't support PSCI */ diff --git a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts similarity index 100% rename from arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts rename to arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 5a9a5ed0565f..8c1dc5155b71 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -444,7 +444,7 @@ }; sdhc1: sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -467,7 +467,7 @@ }; sdhc2: sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -713,6 +713,9 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfc400000 0x2000>; + + clock-names = "xo", "sleep_clk"; + clocks = <&xo_board>, <&sleep_clk>; }; rpm_msg_ram: sram@fc428000 { diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts index 7d9fc35bc7a0..6a1699a96c99 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts @@ -9,7 +9,7 @@ / { model = "Qualcomm Technologies, Inc. MSM 8996 MTP"; - compatible = "qcom,msm8996-mtp"; + compatible = "qcom,msm8996-mtp", "qcom,msm8996"; aliases { serial0 = &blsp2_uart2; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 91bc974aeb0a..f0f81c23c16f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -134,7 +134,7 @@ }; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-cluster0 { compatible = "operating-points-v2-kryo-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; @@ -222,7 +222,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-cluster1 { compatible = "operating-points-v2-kryo-cpu"; nvmem-cells = <&speedbin_efuse>; opp-shared; @@ -679,8 +679,10 @@ #power-domain-cells = <1>; reg = <0x00300000 0x90000>; - clocks = <&rpmcc RPM_SMD_LN_BB_CLK>; - clock-names = "cxo2"; + clocks = <&rpmcc RPM_SMD_BB_CLK1>, + <&rpmcc RPM_SMD_LN_BB_CLK>, + <&sleep_clk>; + clock-names = "cxo", "cxo2", "sleep_clk"; }; tsens0: thermal-sensor@4a9000 { @@ -713,7 +715,7 @@ clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; - qcom,controlled-remotely = <1>; + qcom,controlled-remotely; }; crypto: crypto@67a000 { @@ -887,7 +889,7 @@ #clock-cells = <1>; #phy-cells = <0>; - clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; + clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>; clock-names = "iface", "ref"; status = "disabled"; }; @@ -1546,7 +1548,7 @@ reg = <0x00290000 0x10000>; }; - spmi_bus: qcom,spmi@400f000 { + spmi_bus: spmi@400f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0400f000 0x1000>, <0x04400000 0x800000>, @@ -2593,7 +2595,7 @@ reg = <0x06400000 0x90000>; clock-names = "xo"; - clocks = <&xo_board>; + clocks = <&rpmcc RPM_SMD_BB_CLK1>; #clock-cells = <1>; }; @@ -2693,7 +2695,7 @@ }; sdhc1: sdhci@7464900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07464900 0x11c>, <0x07464000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -2704,7 +2706,7 @@ clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_BB_CLK1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc1_state_on>; @@ -2716,7 +2718,7 @@ }; sdhc2: sdhci@74a4900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; reg = <0x074a4900 0x314>, <0x074a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -2727,7 +2729,7 @@ clock-names = "iface", "core", "xo"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; + <&rpmcc RPM_SMD_BB_CLK1>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&sdc2_state_on>; @@ -3028,7 +3030,7 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; - clocks = <&xo_board>; + clocks = <&rpmcc RPM_SMD_BB_CLK1>; clock-names = "xo"; memory-region = <&adsp_region>; @@ -3054,7 +3056,7 @@ power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; compatible = "qcom,apr-v2"; qcom,smd-channels = "apr_audio_svc"; - qcom,apr-domain = ; + qcom,domain = ; #address-cells = <1>; #size-cells = <0>; @@ -3273,7 +3275,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3295,7 +3297,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index f273bc1ff629..2fda21e810c9 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -138,15 +138,9 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; L2_0: l2-cache { - compatible = "arm,arch-cache"; + compatible = "cache"; cache-level = <2>; }; - L1_I_0: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_0: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU1: cpu@1 { @@ -157,12 +151,6 @@ capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; - L1_I_1: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_1: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU2: cpu@2 { @@ -173,12 +161,6 @@ capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; - L1_I_2: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_2: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU3: cpu@3 { @@ -189,12 +171,6 @@ capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; - L1_I_3: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_3: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU4: cpu@100 { @@ -206,15 +182,9 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; L2_1: l2-cache { - compatible = "arm,arch-cache"; + compatible = "cache"; cache-level = <2>; }; - L1_I_100: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_100: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU5: cpu@101 { @@ -225,12 +195,6 @@ capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; - L1_I_101: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_101: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU6: cpu@102 { @@ -241,12 +205,6 @@ capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; - L1_I_102: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_102: l1-dcache { - compatible = "arm,arch-cache"; - }; }; CPU7: cpu@103 { @@ -257,12 +215,6 @@ capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; - L1_I_103: l1-icache { - compatible = "arm,arch-cache"; - }; - L1_D_103: l1-dcache { - compatible = "arm,arch-cache"; - }; }; cpu-map { @@ -674,7 +626,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -689,7 +641,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 3ca2860bb0cf..7aa2ef90cb6a 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -52,5 +52,15 @@ reg = <0x5 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; + + pm6150l_wled: leds@d800 { + compatible = "qcom,pm6150l-wled"; + reg = <0xd800>, <0xd900>; + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp"; + label = "backlight"; + + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi new file mode 100644 index 000000000000..741c538a9cee --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include + +&spmi_bus { + pmic@0 { + compatible = "qcom,pm8953", "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8953_pon: pon@800 { + compatible = "qcom,pm8916-pon"; + reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x00 0x08 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; + + pm8953_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x00 0x08 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; + }; + + temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8953_vadc VADC_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + + pm8953_vadc: vadc@3100 { + compatible = "qcom,spmi-vadc"; + reg = <0x3100>; + interrupts = <0x00 0x31 0x00 0x01>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + adc-chan@8 { + reg = ; + }; + adc-chan@9 { + reg = ; + }; + adc-chan@a { + reg = ; + }; + adc-chan@c { + reg = ; + }; + adc-chan@e { + reg = ; + }; + adc-chan@f { + reg = ; + }; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + }; + + pmic@1 { + compatible = "qcom,pm8953", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 172be177fc8f..98d173a377d5 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -32,7 +32,7 @@ &spmi_bus { pms405_0: pms405@0 { - compatible = "qcom,spmi-pmic"; + compatible = "qcom,pms405", "qcom,spmi-pmic"; reg = <0x0 SPMI_USID>; #address-cells = <1>; #size-cells = <0>; @@ -139,7 +139,7 @@ }; pms405_1: pms405@1 { - compatible = "qcom,spmi-pmic"; + compatible = "qcom,pms405", "qcom,spmi-pmic"; reg = <0x1 SPMI_USID>; pms405_spmi_regulators: regulators { diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 6db753b49326..3f06f7cd3cf2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -110,7 +110,7 @@ }; }; - cpu_opp_table: cpu-opp-table { + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2-kryo-cpu"; opp-shared; @@ -128,7 +128,7 @@ }; }; - cpr_opp_table: cpr-opp-table { + cpr_opp_table: opp-table-cpr { compatible = "operating-points-v2-qcom-level"; cpr_opp1: opp1 { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 14ed09f30a73..c81805ef2250 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -142,6 +142,22 @@ ap_ts_pen_1v8: &i2c4 { }; }; +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + &pp3300_dx_edp { gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index f32369af1351..bff2b556cc75 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -146,6 +146,22 @@ ap_ts_pen_1v8: &i2c4 { }; }; +&pp1800_uf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp2800_uf_cam { + status = "okay"; +}; + +&pp2800_wf_cam { + status = "okay"; +}; + &pp3300_dx_edp { gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index bd5909ffb3dc..732e1181af48 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -144,6 +144,100 @@ vin-supply = <&ppvar_sys>; }; + pp1800_ec: + pp1800_sensors: + pp1800_ldo: pp1800-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_ldo"; + + /* EC turns on with hibernate_l; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* + * Actually should be pp1800_h1 but we don't have any need to + * model that so we use the parent of pp1800_h1. + */ + vin-supply = <&pp3300_a>; + }; + + pp1800_uf_cam: pp1800-uf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_uf_cam"; + status = "disabled"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&uf_cam_en>; + + vin-supply = <&pp1800_ldo>; + regulator-enable-ramp-delay = <1000>; + }; + + pp1800_wf_cam: pp1800-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_wf_cam"; + status = "disabled"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wf_cam_en>; + + vin-supply = <&pp1800_ldo>; + regulator-enable-ramp-delay = <1000>; + }; + + pp2800_uf_cam: pp2800-uf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp2800_uf_cam"; + status = "disabled"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * pinctrl-names = "default"; + * pinctrl-0 = <&uf_cam_en>; + */ + + vin-supply = <&pp3300_a>; + }; + + pp2800_vcm_wf_cam: + pp2800_wf_cam: pp2800-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp2800_wf_cam"; + status = "disabled"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * pinctrl-names = "default"; + * pinctrl-0 = <&wf_cam_en>; + */ + + vin-supply = <&pp3300_a>; + }; + pp3300_audio: pp3300_codec: pp3300-codec-regulator { compatible = "regulator-fixed"; @@ -190,7 +284,7 @@ vin-supply = <&pp3300_a>; }; - pp3300_hub: pp3300-hub { + pp3300_hub: pp3300-hub-regulator { compatible = "regulator-fixed"; regulator-name = "pp3300_hub"; @@ -543,7 +637,7 @@ pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; @@ -1521,4 +1615,32 @@ ap_spi_fp: &spi10 { drive-strength = <2>; }; }; + + uf_cam_en: uf-cam-en { + pinmux { + pins = "gpio6"; + function = "gpio"; + }; + + pinconf { + pins = "gpio6"; + drive-strength = <2>; + /* External pull down */ + bias-disable; + }; + }; + + wf_cam_en: wf-cam-en { + pinmux { + pins = "gpio7"; + function = "gpio"; + }; + + pinconf { + pins = "gpio7"; + drive-strength = <2>; + /* External pull down */ + bias-disable; + }; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 2151cd8c8c7a..e1c46b80f14a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1459,6 +1459,8 @@ "imem", "config"; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi new file mode 100644 index 000000000000..9f4a9c263c35 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sc7280 fragment for devices with Chrome bootloader + * + * This file mainly tries to abstract out the memory protections put into + * place by the Chrome bootloader which are different than what's put into + * place by Qualcomm's typical bootloader. It also has a smattering of other + * things that will hold true for any conceivable Chrome design + * + * Copyright 2022 Google LLC. + */ + +/* + * Reserved memory changes + * + * Delete all unused memory nodes and define the peripheral memory regions + * required by the setup for Chrome boards. + */ + +/delete-node/ &hyp_mem; +/delete-node/ &xbl_mem; +/delete-node/ &reserved_xbl_uefi_log; +/delete-node/ &sec_apps_mem; + +/ { + reserved-memory { + adsp_mem: memory@86700000 { + reg = <0x0 0x86700000 0x0 0x2800000>; + no-map; + }; + + camera_mem: memory@8ad00000 { + reg = <0x0 0x8ad00000 0x0 0x500000>; + no-map; + }; + + venus_mem: memory@8b200000 { + reg = <0x0 0x8b200000 0x0 0x500000>; + no-map; + }; + + mpss_mem: memory@8b800000 { + reg = <0x0 0x8b800000 0x0 0xf600000>; + no-map; + }; + + wpss_mem: memory@9ae00000 { + reg = <0x0 0x9ae00000 0x0 0x1900000>; + no-map; + }; + + mba_mem: memory@9c700000 { + reg = <0x0 0x9c700000 0x0 0x200000>; + no-map; + }; + }; +}; + +/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */ +&pmk8350_pon { + status = "disabled"; +}; + +/* + * Chrome designs always boot from SPI flash hooked up to the qspi. + * + * It's expected that all boards will support "dual SPI" at 37.5 MHz. + * If some boards need a different speed or have a package that allows + * Quad SPI together with WP then those boards can easily override. + */ +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; + + spi_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + spi-max-frequency = <37500000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + +/* Modem setup is different on Chrome setups than typical Qualcomm setup */ +&remoteproc_mpss { + status = "okay"; + compatible = "qcom,sc7280-mss-pil"; + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; + memory-region = <&mba_mem>, <&mpss_mem>; +}; + +/* Increase the size from 2.5MB to 8MB */ +&rmtfs_mem { + reg = <0x0 0x9c900000 0x0 0x800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts index cd2755ce530d..e2efbdde53a3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -23,6 +23,18 @@ }; }; +&apps_rsc { + pmg1110-regulators { + compatible = "qcom,pmg1110-rpmh-regulators"; + qcom,pmic-id = "k"; + + vreg_s1k_1p0: smps1 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + }; +}; + ap_tp_i2c: &i2c0 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts new file mode 100644 index 000000000000..1779d96c30f6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts @@ -0,0 +1,1352 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Herobrine board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include + +#include "sc7280.dtsi" + +/* PMICs depend on spmi_bus label and so must come after SoC */ +#include "pm7325.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" + +#include "sc7280-chrome-common.dtsi" + +/ { + model = "Google Herobrine (rev0)"; + compatible = "google,herobrine-rev0", "qcom,sc7280"; +}; + +/ { + aliases { + serial0 = &uart5; + serial1 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* FIXED REGULATORS - parents above children */ + + /* This is the top level supply and variable voltage */ + ppvar_sys: ppvar-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + /* This divides ppvar_sys by 2, so voltage is variable */ + src_vph_pwr: src-vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "src_vph_pwr"; + + /* EC turns on with switchcap_on; always on for AP */ + regulator-always-on; + regulator-boot-on; + + vin-supply = <&ppvar_sys>; + }; + + pp5000_s3: pp5000-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp5000_s3"; + + /* EC turns on with en_pp5000_s3; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300_z1: pp3300-z1-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_z1"; + + /* EC turns on with en_pp3300_z1; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300_audio: + pp3300_codec: pp3300-codec-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_codec"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_codec>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_cam: + pp3300_edp: + pp3300_ts: pp3300-edp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_edp"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_dx_edp>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_fp: + pp3300_fp_ls: + pp3300_mcu: pp3300-fp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_fp"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-boot-on; + regulator-always-on; + + /* + * WARNING: it is intentional that GPIO 42 isn't listed here. + * The userspace script for updating the fingerprint firmware + * needs to control the FP regulators during a FW update, + * hence the signal can't be owned by the kernel regulator. + */ + + pinctrl-names = "default"; + pinctrl-0 = <&en_fp_rails>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_hub: pp3300-hub-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_hub"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-boot-on; + regulator-always-on; + + gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_hub>; + + vin-supply = <&pp3300_z1>; + }; + + pp3300_tp: pp3300-tp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp3300_tp"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + /* AP turns on with PP1800_L18B_S0; always on for AP */ + regulator-always-on; + regulator-boot-on; + + vin-supply = <&pp3300_z1>; + }; + + pp2850_uf_cam: pp2850-uf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp2850_uf_cam"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&uf_cam_en>; + + vin-supply = <&pp3300_cam>; + }; + + pp2850_vcm_wf_cam: pp2850-vcm-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp2850_vcm_wf_cam"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wf_cam_en>; + + vin-supply = <&pp3300_cam>; + }; + + pp2850_wf_cam: pp2850-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp2850_wf_cam"; + + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names = "default"; + * pinctrl-0 = <&wf_cam_en>; + */ + + vin-supply = <&pp3300_cam>; + }; + + pp1800_fp: pp1800-fp-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_fp"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + regulator-always-on; + + /* + * WARNING: it is intentional that GPIO 42 isn't listed here. + * The userspace script for updating the fingerprint firmware + * needs to control the FP regulators during a FW update, + * hence the signal can't be owned by the kernel regulator. + */ + + pinctrl-names = "default"; + pinctrl-0 = <&en_fp_rails>; + + vin-supply = <&pp1800_l18b_s0>; + status = "disabled"; + }; + + pp1800_uf_cam: pp1800-uf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_uf_cam"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names = "default"; + * pinctrl-0 = <&uf_cam_en>; + */ + + vin-supply = <&pp1800_l19b>; + }; + + pp1800_wf_cam: pp1800-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1800_wf_cam"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names = "default"; + * pinctrl-0 = <&wf_cam_en>; + */ + + vin-supply = <&pp1800_l19b>; + }; + + pp1200_wf_cam: pp1200-wf-cam-regulator { + compatible = "regulator-fixed"; + regulator-name = "pp1200_wf_cam"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * The pinconf can only be referenced once so we put it on the + * first regulator and comment it out here. + * + * pinctrl-names = "default"; + * pinctrl-0 = <&wf_cam_en>; + */ + + vin-supply = <&pp1200_l6b>; + }; + + /* BOARD-SPECIFIC TOP LEVEL NODES */ + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pen_pdct_l>; + + pen_insert: pen-insert { + label = "Pen Insert"; + + /* Insert = low, eject = high */ + gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-event-action = ; + wakeup-source; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + status = "disabled"; + keyboard_backlight: keyboard-backlight { + status = "disabled"; + label = "cros_ec::kbd_backlight"; + pwms = <&cros_ec_pwm 0>; + max-brightness = <1023>; + }; + }; +}; + +&apps_rsc { + pm7325-regulators { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd19_pmu_pcie_i: + vdd19_pmu_rfa_i: + vreg_s1b_wlan: + vreg_s1b: smps1 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2040000>; + }; + + vdd_pmu_aon_i: + vreg_s7b_wlan: + vreg_s7b: smps7 { + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vdd13_pmu_pcie_i: + vdd13_pmu_rfa_i: + vreg_s8b_wlan: + vreg_s8b: smps8 { + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1500000>; + }; + + vdda_usb_ss_dp_core: + vreg_l1b: ldo1 { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vdda_usb_hs0_3p1: + vreg_l2b: ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + pp1200_l6b: + vdd_ufs_1p2: + vdd_vref: + vdda_csi01_1p2: + vdda_csi23_1p2: + vdda_csi4_1p2: + vdda_dsi0_1p2: + vdda_pcie0_1p2: + vdda_pcie1_1p2: + vdda_usb_ss_dp_1p2: + vdda_qlink0_1p2_ck: + vdda_qlink1_1p2_ck: + vreg_l6b_1p2: + vreg_l6b: ldo6 { + regulator-min-microvolt = <1120000>; + regulator-max-microvolt = <1408000>; + regulator-initial-mode = ; + }; + + pp2950_l7b: + vreg_l7b: ldo7 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + codec_vcc: + pp1800_l18b_s0: + pp1800_ts: + vdd1: + vddpx_0: + vddpx_3: + vddpx_7: + vreg_l18b: ldo18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pp1800_l19b: + vddpx_ts: + vddpx_wl4otp: + vreg_l19b: ldo19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vreg_s1c: smps1 { + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + vddpx_1: + vreg_s9c: smps9 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + pp1800_l1c: + pp1800_pen: + vdd_a_gfx_cs_1p1: + vdd_a_cxo_1p8: + vdd_qfprom: + vdda_apc_cs_1p8: + vdda_qrefs_1p8: + vdda_turing_q6_cs_1p8: + vdda_usb_hs0_1p8: + vreg_l1c: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + dmic_vdd: + pp1800_alc5682: + pp1800_l2c: + pp1800_vreg_alc5682: + vreg_l2c: ldo2 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + pp3300_sar: + pp3300_sensor: + vreg_l3c: ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = ; + }; + + ppvar_uim1: + vddpx_5: + vreg_l4c: ldo4 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + pp2950_l5c: + uim_vcc: + vddpx_6: + vreg_l5c: ldo5 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + ppvar_l6c: + vddpx_2: + vreg_l6c: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vreg_l7c: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + pp1800_prox: + pp1800_sar: + vreg_l8c: ldo8 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pp2950_l9c: + vreg_l9c: ldo9 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vdd_a_gnss_0p9: + vdd_ufs_core: + vdd_usb_hs0_core: + vdd_vref_0p9: + vdda_csi01_0p9: + vdda_csi23_0p9: + vdda_csi4_0p9: + vdda_dsi0_pll_0p9: + vdda_dsi0_0p9: + vdda_pcie0_core: + vdda_pcie1_core: + vdda_qlink0_0p9: + vdda_qlink1_0p9: + vdda_qlink0_0p9_ck: + vdda_qlink1_0p9_ck: + vdda_qrefs_0p875: + vreg_l10c_0p8: + vreg_l10c: ldo10 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + }; + + pp2800_l11c: + vreg_l11c: ldo11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + pp1800_l12c: + vreg_l12c: ldo12 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + pp3300_l13c: + vreg_l13c: ldo13 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +ap_tp_i2c: &i2c1 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <102 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&pp3300_z1>; + + wakeup-source; + }; +}; + +ap_h1_i2c: &i2c12 { + status = "okay"; + clock-frequency = <400000>; + + tpm@50 { + compatible = "google,cr50"; + reg = <0x50>; + + pinctrl-names = "default"; + pinctrl-0 = <&h1_ap_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <54 IRQ_TYPE_EDGE_RISING>; + }; +}; + +ap_ts_pen: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@10 { + compatible = "hid-over-i2c"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <81 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + + vdd-supply = <&pp3300_ts>; + }; +}; + +&pm7325_gpios { + status = "disabled"; /* No GPIOs are connected */ +}; + +&pmk8350_gpios { + status = "disabled"; /* No GPIOs are connected */ +}; + +&pmk8350_rtc { + status = "disabled"; +}; + +&pmk8350_vadc { + pmk8350_die_temp { + reg = ; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmr735a_die_temp { + reg = ; + label = "pmr735a_die_temp"; + qcom,pre-scaling = <1 1>; + }; +}; + +&qfprom { + vcc-supply = <&vdd_qfprom>; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + + vmmc-supply = <&pp2950_l7b>; + vqmmc-supply = <&pp1800_l19b>; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; + vmmc-supply = <&pp2950_l9c>; + vqmmc-supply = <&ppvar_l6c>; + + cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; +}; + +ap_ec_spi: &spi8 { + status = "okay"; + + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs_gpio_init_high>, <&qup_spi8_cs_gpio>; + cs-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <142 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ap_ec_int_l>; + spi-max-frequency = <3000000>; + + cros_ec_pwm: pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + typec { + compatible = "google,cros-ec-typec"; + #address-cells = <1>; + #size-cells = <0>; + + usb_c0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "left"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + + usb_c1: connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + label = "right"; + power-role = "dual"; + data-role = "host"; + try-power-role = "source"; + }; + }; + }; +}; + +#include +#include + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; + +&uart5 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vdd_usb_hs0_core>; + vdda33-supply = <&vdda_usb_hs0_3p1>; + vdda18-supply = <&vdda_usb_hs0_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vdda_usb_ss_dp_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vdd_usb_hs0_core>; + vdda33-supply = <&vdda_usb_hs0_3p1>; + vdda18-supply = <&vdda_usb_hs0_1p8>; +}; + +/* PINCTRL - additions to nodes defined in sc7280.dtsi */ + +&dp_hot_plug_det { + bias-disable; +}; + +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + +&qspi_cs0 { + bias-disable; +}; + +&qspi_clk { + bias-disable; +}; + +&qspi_data01 { + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; +}; + +&qup_uart5_rx { + drive-strength = <2>; + bias-pull-up; +}; + +&qup_uart5_tx { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_cts { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; +}; + +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&sdc1_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc1_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_rclk { + bias-pull-down; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; + +/* PINCTRL - board-specific pinctrl */ + +&pm8350c_gpios { + gpio-line-names = "AP_SUSPEND", + "", + "", + "AP_BL_EN", + "", + "SD_CD_ODL", + "", + "", + "AP_BL_PWM"; + + ap_bl_en: ap-bl-en { + pins = "gpio4"; + function = "normal"; + qcom,drive-strength = ; + bias-disable; + + /* Force backlight to be disabled to match state at boot. */ + output-low; + }; +}; + +&tlmm { + gpio-line-names = "HP_I2C_SDA", /* 0 */ + "HP_I2C_SCL", + "SSD_RST_L", + "PE_WAKE_ODL", + "AP_TP_I2C_SDA", + "AP_TP_I2C_SCL", + "UF_CAM_EN", + "WF_CAM_EN", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + + "", /* 10 */ + "", + "AP_SPI_MOSI", + "AP_SPI_MISO", + "AP_SPI_CLK", + "AP_SPI_CS0_L", + "", + "", + "EDP_HPD", + "", + + "UF_CAM_RST_L", /* 20 */ + "WF_CAM_RST_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "EN_PP3300_HUB", + "", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "BT_UART_CTS", + "BT_UART_RTS", + + "BT_UART_TXD", /* 30 */ + "BT_UART_RXD", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "", + "", + "", + "PEN_PDCT_L", + + "IO_BRD_ID0", /* 40 */ + "IO_BRD_ID1", + "EN_FP_RAILS", + "PEN_IRQ_L", + "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + + "AP_H1_SPI_CLK", /* 50 */ + "AP_H1_SPI_CS_L", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "H1_AP_INT_ODL", + "", + "LCM_RST_1V8_L", + "AMP_EN", + "", + "DP_HOT_PLUG_DET", + + "HUB_RST_L", /* 60 */ + "FP_TO_AP_IRQ_L", + "", + "", + "UF_CAM_MCLK", + "WF_CAM_MCLK", + "IO_BRD_ID2", + "EN_PP3300_CODEC", + "EC_IN_RW_ODL", + "UF_CAM_SDA", + + "UF_CAM_SCL", /* 70 */ + "WF_CAM_SDA", + "WF_CAM_SCL", + "AP_BRD_ID0", + "AP_BRD_ID1", + "AP_BRD_ID2", + "", + "FPMCU_BOOT0", + "FP_RST_L", + "PE_CLKREQ_ODL", + + "EN_EDP_PP3300", /* 80 */ + "TS_INT_L", + "FORCE_USB_BOOT", + "WCD_RST_L", + "WLAN_EN", + "BT_EN", + "WLAN_SW_CTRL", + "PCIE0_RESET_L", + "PCIE0_CLK_REQ_L", + "PCIE0_WAKE_L", + + "AS_EN", /* 90 */ + "SD_CD_ODL", + "", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "BT_WLAN_SB_CLK", + "BT_WLAN_SB_DATA", + "HP_MCLK", + "HP_BCLK", + "HP_DOUT", + "HP_DIN", + + "HP_LRCLK", /* 100 */ + "HP_IRQ", + "TP_INT_ODL", + "", + "IO_SKU_ID2", + "TS_RESET_L", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM2_DATA", + + "UIM2_CLK", /* 110 */ + "UIM2_RST", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RST", + "", + "RFFE0_CLK", + "RFFE0_DATA/BOOT_CONFIG_0", + "RFFE1_CLK", + + "RFFE1_DATA/BOOT_CONFIG_1", /* 120 */ + "RFFE2_CLK", + "RFFE2_DATA/BOOT_CONFIG_2", + "RFFE3_CLK", + "RFFE3_DATA/BOOT_CONFIG_3", + "RFFE4_CLK", + "RFFE4_DATA", + "WCI2_LTE_COEX_RXD", + "WCI2_LTE_COEX_TXD", + "IO_SKU_ID0", + + "IO_SKU_ID1", /* 130 */ + "", + "", + "QLINK0_REQ", + "QLINK0_EN", + "QLINK0_WMSS_RESET_L", + "QLINK1_REQ", + "QLINK1_EN", + "QLINK1_WMSS_RESET_L", + "FORCED_USB_BOOT_POL", + + "", /* 140 */ + "P_SENSOR_INT_L", + "AP_EC_INT_L", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA_0", + "WCD_SWR_TX_DATA_1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA_0", + "WCD_SWR_RX_DATA_1", + + "", /* 150 */ + "", + "", + "", + "", + "", + "", + "", + "WCD_SWR_TX_DATA_2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "SENS_UART_TXD", + "SENS_UART_RXD", + "", + "", + ""; + + /* + * pinctrl settings for pins that have no real owners. + */ + pinctrl-names = "default"; + pinctrl-0 = <&bios_flash_wp_l>; + + amp_en: amp-en { + pins = "gpio57"; + function = "gpio"; + bias-pull-down; + }; + + ap_ec_int_l: ap-ec-int-l { + pins = "gpio142"; + input-enable; + bias-pull-up; + }; + + bios_flash_wp_l: bios-flash-wp-l { + pins = "gpio93"; + function = "gpio"; + input-enable; + bias-disable; + }; + + bt_en: bt-en { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + output-low; + bias-pull-down; + }; + + en_fp_rails: en-fp-rails { + pins = "gpio42"; + drive-strength = <2>; + output-high; + bias-disable; + }; + + en_pp3300_codec: en-pp3300-codec { + pins = "gpio67"; + drive-strength = <2>; + bias-disable; + }; + + en_pp3300_dx_edp: en-pp3300-dx-edp { + pins = "gpio80"; + function = "gpio"; + drive-strength = <2>; + /* Has external pulldown */ + bias-disable; + }; + + en_pp3300_hub: en-pp3300-hub { + pins = "gpio24"; + function = "gpio"; + drive-strength = <2>; + /* Has external pulldown */ + bias-disable; + }; + + fp_to_ap_irq_l: fp-to-ap-irq-l { + pins = "gpio61"; + function = "gpio"; + input-enable; + /* Has external pullup */ + bias-disable; + }; + + h1_ap_int_odl: h1-ap-int-odl { + pins = "gpio54"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + hp_irq: hp-irq { + pins = "gpio101"; + function = "gpio"; + bias-pull-up; + }; + + p_sensor_int_l: p-sensor-int-l { + pins = "gpio141"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + pen_irq_l: pen-irq-l { + pins = "gpio43"; + function = "gpio"; + /* Has external pullup */ + bias-disable; + }; + + pen_pdct_l: pen-pdct-l { + pins = "gpio39"; + function = "gpio"; + /* Has external pullup */ + bias-disable; + }; + + qup_spi8_cs_gpio_init_high: qup-spi8-cs-gpio-init-high { + pins = "gpio35"; + output-high; + }; + + qup_spi11_cs_gpio_init_high: qup-spi11-cs-gpio-init-high { + pins = "gpio47"; + output-high; + }; + + qup_spi12_cs_gpio_init_high: qup-spi12-cs-gpio-init-high { + pins = "gpio51"; + output-high; + }; + + qup_uart7_sleep_cts: qup-uart7-sleep-cts { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + sd_cd: sd-cd { + pins = "gpio91"; + function = "gpio"; + bias-pull-up; + }; + + tp_int_odl: tp-int-odl { + pins = "gpio102"; + function = "gpio"; + /* Has external pullup */ + bias-disable; + }; + + ts_int_l: ts-int-l { + pins = "gpio81"; + function = "gpio"; + /* Has external pullup */ + bias-pull-up; + }; + + ts_reset_l: ts-reset-l { + pins = "gpio105"; + function = "gpio"; + /* Has external pullup */ + bias-disable; + drive-strength = <2>; + }; + + uf_cam_en: uf-cam-en { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + /* Has external pulldown */ + bias-disable; + }; + + wf_cam_en: wf-cam-en { + pins = "gpio7"; + function = "gpio"; + drive-strength = <2>; + /* Has external pulldown */ + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts new file mode 100644 index 000000000000..f95273052da0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Herobrine board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine.dtsi" + +/ { + model = "Google Herobrine (rev1+)"; + compatible = "google,herobrine", "qcom,sc7280"; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +&ap_spi_fp { + status = "okay"; +}; + +/* + * Although the trackpad is really part of the herobrine baseboard, we'll + * put the actual definition in the board device tree since different boards + * might hook up different trackpads (or no i2c trackpad at all in the case + * of tablets / detachables). + */ +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <&pp3300_z1>; + + wakeup-source; + }; +}; + +/* + * The touchscreen connector might come off the Qcard, at least in the case of + * eDP. Like the trackpad, we'll put it in the board device tree file since + * different boards have different touchscreens. + */ +ts_i2c: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@5c { + compatible = "hid-over-i2c"; + reg = <0x5c>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <500>; + hid-descr-addr = <0x0000>; + + vdd-supply = <&ts_avdd>; + }; +}; + +/* For nvme */ +&pcie1 { + status = "okay"; +}; + +/* For nvme */ +&pcie1_phy { + status = "okay"; +}; + +/* For eMMC */ +&sdhc_1 { + status = "okay"; +}; + +/* For SD Card */ +&sdhc_2 { + status = "okay"; +}; + +/* PINCTRL - BOARD-SPECIFIC */ + +/* + * Methodology for gpio-line-names: + * - If a pin goes to herobrine board and is named it gets that name. + * - If a pin goes to herobrine board and is not named, it gets no name. + * - If a pin is totally internal to Qcard then it gets Qcard name. + * - If a pin is not hooked up on Qcard, it gets no name. + */ + +&pm8350c_gpios { + gpio-line-names = "FLASH_STROBE_1", /* 1 */ + "AP_SUSPEND", + "PM8008_1_RST_N", + "", + "", + "", + "PMIC_EDP_BL_EN", + "PMIC_EDP_BL_PWM", + ""; +}; + +&tlmm { + gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ + "AP_TP_I2C_SCL", + "SSD_RST_L", + "PE_WAKE_ODL", + "AP_SAR_SDA", + "AP_SAR_SCL", + "PRB_SC_GPIO_6", + "TP_INT_ODL", + "HP_I2C_SDA", + "HP_I2C_SCL", + + "GNSS_L1_EN", /* 10 */ + "GNSS_L5_EN", + "SPI_AP_MOSI", + "SPI_AP_MISO", + "SPI_AP_CLK", + "SPI_AP_CS0_L", + /* + * AP_FLASH_WP is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_OD. + */ + "AP_FLASH_WP", + "", + "AP_EC_INT_L", + "", + + "UF_CAM_RST_L", /* 20 */ + "WF_CAM_RST_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "", + "PM8008_IRQ_1", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "MOS_BT_UART_CTS", + "MOS_BT_UART_RFR", + + "MOS_BT_UART_TX", /* 30 */ + "MOS_BT_UART_RX", + "PRB_SC_GPIO_32", + "HUB_RST_L", + "", + "", + "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + + "AP_EC_SPI_MISO", /* 40 */ + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "LCM_RST_L", + "EARLY_EUD_N", + "", + "DP_HOT_PLUG_DET", + "IO_BRD_MLB_ID0", + "IO_BRD_MLB_ID1", + + "IO_BRD_MLB_ID2", /* 50 */ + "SSD_EN", + "TS_I2C_SDA_CONN", + "TS_I2C_CLK_CONN", + "TS_RST_CONN", + "TS_INT_CONN", + "AP_I2C_TPM_SDA", + "AP_I2C_TPM_SCL", + "PRB_SC_GPIO_58", + "PRB_SC_GPIO_59", + + "EDP_HOT_PLUG_DET_N", /* 60 */ + "FP_TO_AP_IRQ_L", + "", + "AMP_EN", + "CAM0_MCLK_GPIO_64", + "CAM1_MCLK_GPIO_65", + "WF_CAM_MCLK", + "PRB_SC_GPIO_67", + "FPMCU_BOOT0", + "UF_CAM_SDA", + + "UF_CAM_SCL", /* 70 */ + "", + "", + "WF_CAM_SDA", + "WF_CAM_SCL", + "", + "", + "EN_FP_RAILS", + "FP_RST_L", + "PCIE1_CLKREQ_ODL", + + "EN_PP3300_DX_EDP", /* 80 */ + "SC_GPIO_81", + "FORCED_USB_BOOT", + "WCD_RESET_N", + "MOS_WLAN_EN", + "MOS_BT_EN", + "MOS_SW_CTRL", + "MOS_PCIE0_RST", + "MOS_PCIE0_CLKREQ_N", + "MOS_PCIE0_WAKE_N", + + "MOS_LAA_AS_EN", /* 90 */ + "SD_CD_ODL", + "", + "", + "MOS_BT_WLAN_SLIMBUS_CLK", + "MOS_BT_WLAN_SLIMBUS_DAT0", + "HP_MCLK", + "HP_BCLK", + "HP_DOUT", + "HP_DIN", + + "HP_LRCLK", /* 100 */ + "HP_IRQ", + "", + "", + "GSC_AP_INT_ODL", + "EN_PP3300_CODEC", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM1_DATA_GPIO_109", + + "UIM1_CLK_GPIO_110", /* 110 */ + "UIM1_RESET_GPIO_111", + "PRB_SC_GPIO_112", + "UIM0_DATA", + "UIM0_CLK", + "UIM0_RST", + "UIM0_PRESENT_ODL", + "SDM_RFFE0_CLK", + "SDM_RFFE0_DATA", + "WF_CAM_EN", + + "FASTBOOT_SEL_0", /* 120 */ + "SC_GPIO_121", + "FASTBOOT_SEL_1", + "SC_GPIO_123", + "FASTBOOT_SEL_2", + "SM_RFFE4_CLK_GRFC_8", + "SM_RFFE4_DATA_GRFC_9", + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "PRB_SC_GPIO_129", + + "LCM_ID0", /* 130 */ + "LCM_ID1", + "", + "SDR_QLINK_REQ", + "SDR_QLINK_EN", + "QLINK0_WMSS_RESET_N", + "SMR526_QLINK1_REQ", + "SMR526_QLINK1_EN", + "SMR526_QLINK1_WMSS_RESET_N", + "PRB_SC_GPIO_139", + + "SAR1_IRQ_ODL", /* 140 */ + "SAR0_IRQ_ODL", + "PRB_SC_GPIO_142", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + + "DMIC01_CLK", /* 150 */ + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "", + "", + "EC_IN_RW_ODL", + "HUB_EN", + "WCD_SWR_TX_DATA2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "MOS_BLE_UART_TX", + "MOS_BLE_UART_RX", + "", + "", + ""; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dts deleted file mode 100644 index 7a92679a688b..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dts +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Herobrine board device tree source - * - * Copyright 2021 Google LLC. - */ - -#include "sc7280-herobrine.dtsi" - -/ { - model = "Google Herobrine"; - compatible = "google,herobrine", - "qcom,sc7280"; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 4619fa9fcacd..dc17f2079695 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -1,87 +1,37 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Google Herobrine board device tree source + * Google Herobrine baseboard device tree source * - * Copyright 2021 Google LLC. + * The set of things in this file is a bit loosely defined. It's roughly + * defined as the set of things that the child boards happen to have in + * common. Since all of the child boards started from the same original + * design this is hopefully a large set of things but as more derivatives + * appear things may "bubble down" out of this file. For things that are + * part of the reference design but might not exist on child nodes we will + * follow the lead of the SoC dtsi files and leave their status as "disabled". + * + * Copyright 2022 Google LLC. */ -/dts-v1/; - -#include -#include -#include #include #include -#include -#include -#include "sc7280.dtsi" - -/* PMICs depend on spmi_bus label and so must come after SoC */ -#include "pm7325.dtsi" -#include "pm8350c.dtsi" -#include "pmk8350.dtsi" - -/* - * Reserved memory changes - * - * Delete all unused memory nodes and define the peripheral memory regions - * required by the board dts. - * - */ - -/delete-node/ &hyp_mem; -/delete-node/ &xbl_mem; -/delete-node/ &sec_apps_mem; - -/* Increase the size from 2MB to 8MB */ -&rmtfs_mem { - reg = <0x0 0x83600000 0x0 0x800000>; -}; +#include "sc7280-qcard.dtsi" +#include "sc7280-chrome-common.dtsi" / { - reserved-memory { - adsp_mem: memory@86700000 { - reg = <0x0 0x86700000 0x0 0x2800000>; - no-map; - }; - - camera_mem: memory@8ad00000 { - reg = <0x0 0x8ad00000 0x0 0x500000>; - no-map; - }; - - venus_mem: memory@8b200000 { - reg = <0x0 0x8b200000 0x0 0x500000>; - no-map; - }; - - mpss_mem: memory@8b800000 { - reg = <0x0 0x8b800000 0x0 0xf600000>; - no-map; - }; - - wpss_mem: memory@9ae00000 { - reg = <0x0 0x9ae00000 0x0 0x1900000>; - no-map; - }; - - mba_mem: memory@9c700000 { - reg = <0x0 0x9c700000 0x0 0x200000>; - no-map; - }; - }; - - aliases { - serial0 = &uart5; - serial1 = &uart7; - }; - chosen { stdout-path = "serial0:115200n8"; }; - /* FIXED REGULATORS - parents above children */ + /* + * FIXED REGULATORS + * + * Sort order: + * 1. parents above children. + * 2. higher voltage above lower voltage. + * 3. alphabetically by node name. + */ /* This is the top level supply and variable voltage */ ppvar_sys: ppvar-sys-regulator { @@ -103,11 +53,11 @@ vin-supply = <&ppvar_sys>; }; - pp5000_s3: pp5000-s3-regulator { + pp5000_s5: pp5000-s5-regulator { compatible = "regulator-fixed"; - regulator-name = "pp5000_s3"; + regulator-name = "pp5000_s5"; - /* EC turns on with en_pp5000_s3; always on for AP */ + /* EC turns on with en_pp5000_s5; always on for AP */ regulator-always-on; regulator-boot-on; regulator-min-microvolt = <5000000>; @@ -129,7 +79,6 @@ vin-supply = <&ppvar_sys>; }; - pp3300_audio: pp3300_codec: pp3300-codec-regulator { compatible = "regulator-fixed"; regulator-name = "pp3300_codec"; @@ -137,7 +86,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 105 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; pinctrl-0 = <&en_pp3300_codec>; @@ -145,11 +94,9 @@ vin-supply = <&pp3300_z1>; }; - pp3300_cam: - pp3300_edp: - pp3300_ts: pp3300-edp-regulator { + pp3300_left_in_mlb: pp3300-left-in-mlb-regulator { compatible = "regulator-fixed"; - regulator-name = "pp3300_edp"; + regulator-name = "pp3300_left_in_mlb"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -162,9 +109,9 @@ vin-supply = <&pp3300_z1>; }; - pp3300_fp: + pp3300_mcu_fp: pp3300_fp_ls: - pp3300_mcu: pp3300-fp-regulator { + pp3300_fp_mcu: pp3300-fp-regulator { compatible = "regulator-fixed"; regulator-name = "pp3300_fp"; @@ -175,7 +122,7 @@ regulator-always-on; /* - * WARNING: it is intentional that GPIO 42 isn't listed here. + * WARNING: it is intentional that GPIO 77 isn't listed here. * The userspace script for updating the fingerprint firmware * needs to control the FP regulators during a FW update, * hence the signal can't be owned by the kernel regulator. @@ -197,10 +144,10 @@ regulator-boot-on; regulator-always-on; - gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 157 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_hub>; + pinctrl-0 = <&hub_en>; vin-supply = <&pp3300_z1>; }; @@ -219,44 +166,44 @@ vin-supply = <&pp3300_z1>; }; - pp2850_uf_cam: pp2850-uf-cam { + pp3300_ssd: pp3300-ssd-regulator { compatible = "regulator-fixed"; - regulator-name = "pp2850_uf_cam"; + regulator-name = "pp3300_ssd"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; - gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; - pinctrl-0 = <&uf_cam_en>; + pinctrl-0 = <&ssd_en>; - vin-supply = <&pp3300_cam>; + vin-supply = <&pp3300_z1>; }; - pp2850_vcm_wf_cam: pp2850-vcm-wf-cam { + pp2850_vcm_wf_cam: pp2850-vcm-wf-cam-regulator { compatible = "regulator-fixed"; regulator-name = "pp2850_vcm_wf_cam"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; pinctrl-0 = <&wf_cam_en>; - vin-supply = <&pp3300_cam>; + vin-supply = <&pp3300_z1>; }; - pp2850_wf_cam: pp2850-wf-cam { + pp2850_wf_cam: pp2850-wf-cam-regulator { compatible = "regulator-fixed"; regulator-name = "pp2850_wf_cam"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>; enable-active-high; /* * The pinconf can only be referenced once so we put it on the @@ -266,7 +213,7 @@ * pinctrl-0 = <&wf_cam_en>; */ - vin-supply = <&pp3300_cam>; + vin-supply = <&pp3300_z1>; }; pp1800_fp: pp1800-fp-regulator { @@ -280,7 +227,7 @@ regulator-always-on; /* - * WARNING: it is intentional that GPIO 42 isn't listed here. + * WARNING: it is intentional that GPIO 77 isn't listed here. * The userspace script for updating the fingerprint firmware * needs to control the FP regulators during a FW update, * hence the signal can't be owned by the kernel regulator. @@ -293,34 +240,14 @@ status = "disabled"; }; - pp1800_uf_cam: pp1800-uf-cam { - compatible = "regulator-fixed"; - regulator-name = "pp1800_uf_cam"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&uf_cam_en>; - */ - - vin-supply = <&pp1800_l19b>; - }; - - pp1800_wf_cam: pp1800-wf-cam { + pp1800_wf_cam: pp1800-wf-cam-regulator { compatible = "regulator-fixed"; regulator-name = "pp1800_wf_cam"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>; enable-active-high; /* * The pinconf can only be referenced once so we put it on the @@ -330,17 +257,17 @@ * pinctrl-0 = <&wf_cam_en>; */ - vin-supply = <&pp1800_l19b>; + vin-supply = <&vreg_l19b_s0>; }; - pp1200_wf_cam: pp1200-wf-cam { + pp1200_wf_cam: pp1200-wf-cam-regulator { compatible = "regulator-fixed"; regulator-name = "pp1200_wf_cam"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; + gpio = <&tlmm 119 GPIO_ACTIVE_HIGH>; enable-active-high; /* * The pinconf can only be referenced once so we put it on the @@ -350,29 +277,11 @@ * pinctrl-0 = <&wf_cam_en>; */ - vin-supply = <&pp1200_l6b>; + vin-supply = <&pp3300_z1>; }; /* BOARD-SPECIFIC TOP LEVEL NODES */ - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pen_pdct_l>; - - pen_insert: pen-insert { - label = "Pen Insert"; - - /* Insert = low, eject = high */ - gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-event-action = ; - wakeup-source; - }; - }; - pwmleds { compatible = "pwm-leds"; status = "disabled"; @@ -385,263 +294,54 @@ }; }; -&apps_rsc { - pm7325-regulators { - compatible = "qcom,pm7325-rpmh-regulators"; - qcom,pmic-id = "b"; +/* + * BOARD-LOCAL NAMES FOR REGULATORS THAT CONNECT TO QCARD + * + * Names are only listed here if regulators go somewhere other than a + * testpoint. + */ - vdd19_pmu_pcie_i: - vdd19_pmu_rfa_i: - vreg_s1b_wlan: - vreg_s1b: smps1 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <2040000>; - }; +/* From Qcard to our board; ordered by PMIC-ID / rail number */ - vdd_pmu_aon_i: - vreg_s7b_wlan: - vreg_s7b: smps7 { - regulator-min-microvolt = <535000>; - regulator-max-microvolt = <1120000>; - }; +pp1256_s8b: &vreg_s8b_1p256 {}; - vdd13_pmu_pcie_i: - vdd13_pmu_rfa_i: - vreg_s8b_wlan: - vreg_s8b: smps8 { - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1500000>; - }; +pp1800_l18b_s0: &vreg_l18b_1p8 {}; +pp1800_l18b: &vreg_l18b_1p8 {}; - vdda_usb_ss_dp_core: - vreg_l1b: ldo1 { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <925000>; - regulator-initial-mode = ; - }; +vreg_l19b_s0: &vreg_l19b_1p8 {}; - vdda_usb_hs0_3p1: - vreg_l2b: ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; +pp1800_alc5682: &vreg_l2c_1p8 {}; +pp1800_l2c: &vreg_l2c_1p8 {}; - pp1200_l6b: - vdd_ufs_1p2: - vdd_vref: - vdda_csi01_1p2: - vdda_csi23_1p2: - vdda_csi4_1p2: - vdda_dsi0_1p2: - vdda_pcie0_1p2: - vdda_pcie1_1p2: - vdda_usb_ss_dp_1p2: - vdda_qlink0_1p2_ck: - vdda_qlink1_1p2_ck: - vreg_l6b_1p2: - vreg_l6b: ldo6 { - regulator-min-microvolt = <1120000>; - regulator-max-microvolt = <1408000>; - regulator-initial-mode = ; - }; +vreg_l4c: &vreg_l4c_1p8_3p0 {}; - pp2950_l7b: - vreg_l7b: ldo7 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; +ppvar_l6c: &vreg_l6c_2p96 {}; - codec_vcc: - pp1800_l18b_s0: - pp1800_ts: - vdd1: - vddpx_0: - vddpx_3: - vddpx_7: - vreg_l18b: ldo18 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; +pp3000_l7c: &vreg_l7c_3p0 {}; - pp1800_l19b: - vddpx_ts: - vddpx_wl4otp: - vreg_l19b: ldo19 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; +pp1800_prox: &vreg_l8c_1p8 {}; +pp1800_l8c: &vreg_l8c_1p8 {}; - pm8350c-regulators { - compatible = "qcom,pm8350c-rpmh-regulators"; - qcom,pmic-id = "c"; +pp2950_l9c: &vreg_l9c_2p96 {}; - vreg_s1c: smps1 { - regulator-min-microvolt = <2190000>; - regulator-max-microvolt = <2210000>; - }; +pp1800_lcm: &vreg_l12c_1p8 {}; +pp1800_mipi: &vreg_l12c_1p8 {}; +pp1800_l12c: &vreg_l12c_1p8 {}; - vddpx_1: - vreg_s9c: smps9 { - regulator-min-microvolt = <1010000>; - regulator-max-microvolt = <1170000>; - }; +pp3300_lcm: &vreg_l13c_3p0 {}; +pp3300_mipi: &vreg_l13c_3p0 {}; +pp3300_l13c: &vreg_l13c_3p0 {}; - pp1800_l1c: - pp1800_pen: - vdd_a_gfx_cs_1p1: - vdd_a_cxo_1p8: - vdd_qfprom: - vdda_apc_cs_1p8: - vdda_qrefs_1p8: - vdda_turing_q6_cs_1p8: - vdda_usb_hs0_1p8: - vreg_l1c: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1980000>; - regulator-initial-mode = ; - }; +/* From our board to Qcard; ordered same as node definition above */ - dmic_vdd: - pp1800_alc5682: - pp1800_l2c: - pp1800_vreg_alc5682: - vreg_l2c: ldo2 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-initial-mode = ; - }; +vreg_edp_bl: &ppvar_sys {}; - pp3300_sar: - pp3300_sensor: - vreg_l3c: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3540000>; - regulator-initial-mode = ; - }; +ts_avdd: &pp3300_left_in_mlb {}; +vreg_edp_3p3: &pp3300_left_in_mlb {}; - ppvar_uim1: - vddpx_5: - vreg_l4c: ldo4 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = ; - }; +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ - pp2950_l5c: - uim_vcc: - vddpx_6: - vreg_l5c: ldo5 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = ; - }; - - ppvar_l6c: - vddpx_2: - vreg_l6c: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-initial-mode = ; - }; - - vreg_l7c: ldo7 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - pp1800_prox: - pp1800_sar: - vreg_l8c: ldo8 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - pp2950_l9c: - vreg_l9c: ldo9 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vdd_a_gnss_0p9: - vdd_ufs_core: - vdd_usb_hs0_core: - vdd_vref_0p9: - vdda_csi01_0p9: - vdda_csi23_0p9: - vdda_csi4_0p9: - vdda_dsi0_pll_0p9: - vdda_dsi0_0p9: - vdda_pcie0_core: - vdda_pcie1_core: - vdda_qlink0_0p9: - vdda_qlink1_0p9: - vdda_qlink0_0p9_ck: - vdda_qlink1_0p9_ck: - vdda_qrefs_0p875: - vreg_l10c_0p8: - vreg_l10c: ldo10 { - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1050000>; - regulator-initial-mode = ; - }; - - pp2800_l11c: - vreg_l11c: ldo11 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - pp1800_l12c: - vreg_l12c: ldo12 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - pp3300_l13c: - vreg_l13c: ldo13 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - vreg_bob: bob { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - }; -}; - -ap_tp_i2c: &i2c1 { - status = "okay"; - clock-frequency = <400000>; - - trackpad: trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - pinctrl-names = "default"; - pinctrl-0 = <&tp_int_odl>; - - interrupt-parent = <&tlmm>; - interrupts = <102 IRQ_TYPE_EDGE_FALLING>; - - vcc-supply = <&pp3300_z1>; - - wakeup-source; - }; -}; - -ap_h1_i2c: &i2c12 { +ap_i2c_tpm: &i2c14 { status = "okay"; clock-frequency = <400000>; @@ -650,82 +350,26 @@ ap_h1_i2c: &i2c12 { reg = <0x50>; pinctrl-names = "default"; - pinctrl-0 = <&h1_ap_int_odl>; + pinctrl-0 = <&gsc_ap_int_odl>; interrupt-parent = <&tlmm>; - interrupts = <54 IRQ_TYPE_EDGE_RISING>; + interrupts = <104 IRQ_TYPE_EDGE_RISING>; }; }; -ap_ts_pen: &i2c13 { - status = "okay"; - clock-frequency = <400000>; +/* NVMe drive, enabled on a per-board basis */ +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>; - ap_ts: touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <81 IRQ_TYPE_LEVEL_LOW>; - - post-power-on-delay-ms = <20>; - hid-descr-addr = <0x0001>; - - vdd-supply = <&pp3300_ts>; - }; -}; - -&pm7325_gpios { - status = "disabled"; /* No GPIOs are connected */ -}; - -&pmk8350_gpios { - status = "disabled"; /* No GPIOs are connected */ -}; - -&pmk8350_pon { - status = "disabled"; + perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>; + vddpe-3v3-supply = <&pp3300_ssd>; }; &pmk8350_rtc { status = "disabled"; }; -&pmk8350_vadc { - pmk8350_die_temp { - reg = ; - label = "pmk8350_die_temp"; - qcom,pre-scaling = <1 1>; - }; - - pmr735a_die_temp { - reg = ; - label = "pmr735a_die_temp"; - qcom,pre-scaling = <1 1>; - }; -}; - -&qfprom { - vcc-supply = <&vdd_qfprom>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - - spi-max-frequency = <37500000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - &qupv3_id_0 { status = "okay"; }; @@ -734,44 +378,50 @@ ap_ts_pen: &i2c13 { status = "okay"; }; -&sdhc_1 { - status = "okay"; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - vmmc-supply = <&pp2950_l7b>; - vqmmc-supply = <&pp1800_l19b>; -}; - +/* SD Card, enabled on a per-board basis */ &sdhc_2 { - status = "okay"; + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd_odl>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd_odl>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; vmmc-supply = <&pp2950_l9c>; vqmmc-supply = <&ppvar_l6c>; cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; }; -ap_ec_spi: &spi8 { - status = "okay"; +/* Fingerprint, enabled on a per-board basis */ +ap_spi_fp: &spi9 { + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs_gpio_init_high>, <&qup_spi9_cs_gpio>; - pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs_gpio_init_high>, <&qup_spi8_cs_gpio>; - cs-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + cs-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + + cros_ec_fp: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&tlmm>; + interrupts = <61 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>; + spi-max-frequency = <3000000>; + }; +}; + +ap_ec_spi: &spi10 { + status = "okay"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>; + + cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; cros_ec: ec@0 { compatible = "google,cros-ec-spi"; reg = <0>; interrupt-parent = <&tlmm>; - interrupts = <142 IRQ_TYPE_LEVEL_LOW>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; @@ -841,15 +491,6 @@ ap_ec_spi: &spi8 { >; }; -&uart5 { - compatible = "qcom,geni-debug-uart"; - status = "okay"; -}; - -&uart7 { - status = "okay"; -}; - &usb_1 { status = "okay"; }; @@ -860,17 +501,10 @@ ap_ec_spi: &spi8 { &usb_1_hsphy { status = "okay"; - - vdda-pll-supply = <&vdd_usb_hs0_core>; - vdda33-supply = <&vdda_usb_hs0_3p1>; - vdda18-supply = <&vdda_usb_hs0_1p8>; }; &usb_1_qmpphy { status = "okay"; - - vdda-phy-supply = <&vdda_usb_ss_dp_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core>; }; &usb_2 { @@ -883,407 +517,186 @@ ap_ec_spi: &spi8 { &usb_2_hsphy { status = "okay"; - - vdda-pll-supply = <&vdd_usb_hs0_core>; - vdda33-supply = <&vdda_usb_hs0_3p1>; - vdda18-supply = <&vdda_usb_hs0_1p8>; }; -/* PINCTRL - additions to nodes defined in sc7280.dtsi */ +/* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES */ + +&dp_hot_plug_det { + bias-disable; +}; + +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; &qspi_cs0 { bias-disable; + drive-strength = <8>; }; &qspi_clk { bias-disable; + drive-strength = <8>; }; &qspi_data01 { /* High-Z when no transfers; nice to park the lines */ bias-pull-up; + drive-strength = <8>; }; +/* For ap_tp_i2c */ +&qup_i2c0_data_clk { + /* Has external pull */ + bias-disable; + drive-strength = <2>; +}; + +/* For ap_i2c_tpm */ +&qup_i2c14_data_clk { + /* Has external pull */ + bias-disable; + drive-strength = <2>; +}; + +/* For ap_spi_fp */ +&qup_spi9_data_clk { + bias-disable; + drive-strength = <2>; +}; + +/* For ap_spi_fp */ +&qup_spi9_cs_gpio { + bias-disable; + drive-strength = <2>; +}; + +/* For ap_ec_spi */ +&qup_spi10_data_clk { + bias-disable; + drive-strength = <2>; +}; + +/* For ap_ec_spi */ +&qup_spi10_cs_gpio { + bias-disable; + drive-strength = <2>; +}; + +/* For uart_dbg */ &qup_uart5_rx { - drive-strength = <2>; bias-pull-up; }; +/* For uart_dbg */ &qup_uart5_tx { - drive-strength = <2>; bias-disable; -}; - -&qup_uart7_cts { - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - bias-pull-down; -}; - -&qup_uart7_rts { - /* We'll drive RTS, so no pull */ drive-strength = <2>; - bias-disable; }; -&qup_uart7_tx { - /* We'll drive TX, so no pull */ - drive-strength = <2>; +&sdc2_clk { bias-disable; + drive-strength = <16>; }; -&qup_uart7_rx { - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ +&sdc2_cmd { bias-pull-up; + drive-strength = <10>; }; -&sdc1_on { - clk { - bias-disable; - drive-strength = <16>; - }; - - cmd { - bias-pull-up; - drive-strength = <10>; - }; - - data { - bias-pull-up; - drive-strength = <10>; - }; - - rclk { - bias-pull-down; - }; -}; - -&sdc2_on { - clk { - bias-disable; - drive-strength = <16>; - }; - - cmd { - bias-pull-up; - drive-strength = <10>; - }; - - data { - bias-pull-up; - drive-strength = <10>; - }; - - sd-cd { - pins = "gpio91"; - bias-pull-up; - }; +&sdc2_data { + bias-pull-up; + drive-strength = <10>; }; /* PINCTRL - board-specific pinctrl */ -&pm8350c_gpios { - gpio-line-names = "AP_SUSPEND", - "", - "", - "AP_BL_EN", - "", - "SD_CD_ODL", - "", - "", - "AP_BL_PWM"; +&pm7325_gpios { + /* + * On a quick glance it might look like KYPD_VOL_UP_N is used, but + * that only passes through to a debug connector and not to the actual + * volume up key. + */ + status = "disabled"; /* No GPIOs are connected */ +}; - ap_bl_en: ap-bl-en { - pins = "gpio4"; - function = "normal"; - qcom,drive-strength = ; - bias-disable; - - /* Force backlight to be disabled to match state at boot. */ - output-low; - }; +&pmk8350_gpios { + status = "disabled"; /* No GPIOs are connected */ }; &tlmm { - gpio-line-names = "HP_I2C_SDA", /* 0 */ - "HP_I2C_SCL", - "SSD_RST_L", - "PE_WAKE_ODL", - "AP_TP_I2C_SDA", - "AP_TP_I2C_SCL", - "UF_CAM_EN", - "WF_CAM_EN", - "AP_SAR_SENSOR_SDA", - "AP_SAR_SENSOR_SCL", - - "", /* 10 */ - "", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "AP_SPI_CLK", - "AP_SPI_CS0_L", - "", - "", - "EDP_HPD", - "", - - "UF_CAM_RST_L", /* 20 */ - "WF_CAM_RST_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "EN_PP3300_HUB", - "", - "HOST2WLAN_SOL", - "WLAN2HOST_SOL", - "BT_UART_CTS", - "BT_UART_RTS", - - "BT_UART_TXD", /* 30 */ - "BT_UART_RXD", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "", - "", - "", - "PEN_PDCT_L", - - "IO_BRD_ID0", /* 40 */ - "IO_BRD_ID1", - "EN_FP_RAILS", - "PEN_IRQ_L", - "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - - "AP_H1_SPI_CLK", /* 50 */ - "AP_H1_SPI_CS_L", - "AP_TS_PEN_I2C_SDA", - "AP_TS_PEN_I2C_SCL", - "H1_AP_INT_ODL", - "", - "LCM_RST_1V8_L", - "AMP_EN", - "", - "DP_HOT_PLUG_DET", - - "HUB_RST_L", /* 60 */ - "FP_TO_AP_IRQ_L", - "", - "", - "UF_CAM_MCLK", - "WF_CAM_MCLK", - "IO_BRD_ID2", - "EN_PP3300_CODEC", - "EC_IN_RW_ODL", - "UF_CAM_SDA", - - "UF_CAM_SCL", /* 70 */ - "WF_CAM_SDA", - "WF_CAM_SCL", - "AP_BRD_ID0", - "AP_BRD_ID1", - "AP_BRD_ID2", - "", - "FPMCU_BOOT0", - "FP_RST_L", - "PE_CLKREQ_ODL", - - "EN_EDP_PP3300", /* 80 */ - "TS_INT_L", - "FORCE_USB_BOOT", - "WCD_RST_L", - "WLAN_EN", - "BT_EN", - "WLAN_SW_CTRL", - "PCIE0_RESET_L", - "PCIE0_CLK_REQ_L", - "PCIE0_WAKE_L", - - "AS_EN", /* 90 */ - "SD_CD_ODL", - "", - /* - * AP_FLASH_WP_L is crossystem ABI. Schematics - * call it BIOS_FLASH_WP_L. - */ - "AP_FLASH_WP_L", - "BT_WLAN_SB_CLK", - "BT_WLAN_SB_DATA", - "HP_MCLK", - "HP_BCLK", - "HP_DOUT", - "HP_DIN", - - "HP_LRCLK", /* 100 */ - "HP_IRQ", - "TP_INT_ODL", - "", - "IO_SKU_ID2", - "TS_RESET_L", - "AMP_BCLK", - "AMP_DIN", - "AMP_LRCLK", - "UIM2_DATA", - - "UIM2_CLK", /* 110 */ - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "RFFE0_CLK", - "RFFE0_DATA/BOOT_CONFIG_0", - "RFFE1_CLK", - - "RFFE1_DATA/BOOT_CONFIG_1", /* 120 */ - "RFFE2_CLK", - "RFFE2_DATA/BOOT_CONFIG_2", - "RFFE3_CLK", - "RFFE3_DATA/BOOT_CONFIG_3", - "RFFE4_CLK", - "RFFE4_DATA", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "IO_SKU_ID0", - - "IO_SKU_ID1", /* 130 */ - "", - "", - "QLINK0_REQ", - "QLINK0_EN", - "QLINK0_WMSS_RESET_L", - "QLINK1_REQ", - "QLINK1_EN", - "QLINK1_WMSS_RESET_L", - "FORCED_USB_BOOT_POL", - - "", /* 140 */ - "P_SENSOR_INT_L", - "AP_EC_INT_L", - "", - "WCD_SWR_TX_CLK", - "WCD_SWR_TX_DATA_0", - "WCD_SWR_TX_DATA_1", - "WCD_SWR_RX_CLK", - "WCD_SWR_RX_DATA_0", - "WCD_SWR_RX_DATA_1", - - "", /* 150 */ - "", - "", - "", - "", - "", - "", - "", - "WCD_SWR_TX_DATA_2", - "", - - "", /* 160 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - - "", /* 170 */ - "SENS_UART_TXD", - "SENS_UART_RXD", - "", - "", - ""; - - /* - * pinctrl settings for pins that have no real owners. - */ + /* pinctrl settings for pins that have no real owners. */ pinctrl-names = "default"; - pinctrl-0 = <&bios_flash_wp_l>; + pinctrl-0 = <&bios_flash_wp_od>; amp_en: amp-en { - pins = "gpio57"; + pins = "gpio63"; function = "gpio"; - bias-pull-down; + bias-disable; + drive-strength = <2>; }; ap_ec_int_l: ap-ec-int-l { - pins = "gpio142"; - input-enable; + pins = "gpio18"; + function = "gpio"; bias-pull-up; }; - bios_flash_wp_l: bios-flash-wp-l { - pins = "gpio93"; + bios_flash_wp_od: bios-flash-wp-od { + pins = "gpio16"; function = "gpio"; - input-enable; + /* Has external pull */ bias-disable; }; - bt_en: bt-en { - pins = "gpio85"; - function = "gpio"; - drive-strength = <2>; - output-low; - bias-pull-down; - }; - en_fp_rails: en-fp-rails { - pins = "gpio42"; + pins = "gpio77"; + function = "gpio"; + bias-disable; drive-strength = <2>; output-high; - bias-disable; }; en_pp3300_codec: en-pp3300-codec { - pins = "gpio67"; - drive-strength = <2>; + pins = "gpio105"; + function = "gpio"; bias-disable; + drive-strength = <2>; }; en_pp3300_dx_edp: en-pp3300-dx-edp { pins = "gpio80"; function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ bias-disable; + drive-strength = <2>; }; - en_pp3300_hub: en-pp3300-hub { - pins = "gpio24"; + fp_rst_l: fp-rst-l { + pins = "gpio78"; function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ bias-disable; + drive-strength = <2>; + output-high; }; fp_to_ap_irq_l: fp-to-ap-irq-l { pins = "gpio61"; function = "gpio"; - input-enable; /* Has external pullup */ bias-disable; }; - h1_ap_int_odl: h1-ap-int-odl { - pins = "gpio54"; + fpmcu_boot0: fpmcu-boot0 { + pins = "gpio68"; + function = "gpio"; + bias-disable; + output-low; + }; + + gsc_ap_int_odl: gsc-ap-int-odl { + pins = "gpio104"; function = "gpio"; - input-enable; bias-pull-up; }; @@ -1293,120 +706,80 @@ ap_ec_spi: &spi8 { bias-pull-up; }; - p_sensor_int_l: p-sensor-int-l { - pins = "gpio141"; + hub_en: hub-en { + pins = "gpio157"; function = "gpio"; - input-enable; - bias-pull-up; - }; - - pen_irq_l: pen-irq-l { - pins = "gpio43"; - function = "gpio"; - /* Has external pullup */ bias-disable; + drive-strength = <2>; }; - pen_pdct_l: pen-pdct-l { + pe_wake_odl: pe-wake-odl { + pins = "gpio3"; + function = "gpio"; + /* Has external pull */ + bias-disable; + drive-strength = <2>; + }; + + /* For ap_spi_fp */ + qup_spi9_cs_gpio_init_high: qup-spi9-cs-gpio-init-high { pins = "gpio39"; function = "gpio"; - /* Has external pullup */ - bias-disable; - }; - - qup_spi8_cs_gpio_init_high: qup-spi8-cs-gpio-init-high { - pins = "gpio35"; output-high; }; - qup_spi11_cs_gpio_init_high: qup-spi11-cs-gpio-init-high { - pins = "gpio47"; + /* For ap_ec_spi */ + qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high { + pins = "gpio43"; + function = "gpio"; output-high; }; - qup_spi12_cs_gpio_init_high: qup-spi12-cs-gpio-init-high { + sar0_irq_odl: sar0-irq-odl { + pins = "gpio141"; + function = "gpio"; + bias-pull-up; + }; + + sar1_irq_odl: sar0-irq-odl { + pins = "gpio140"; + function = "gpio"; + bias-pull-up; + }; + + sd_cd_odl: sd-cd-odl { + pins = "gpio91"; + function = "gpio"; + bias-pull-up; + }; + + ssd_en: ssd-en { pins = "gpio51"; - output-high; + function = "gpio"; + bias-disable; + drive-strength = <2>; }; - qup_uart7_sleep_cts: qup-uart7-sleep-cts { - pins = "gpio28"; + ssd_rst_l: ssd-rst-l { + pins = "gpio2"; function = "gpio"; - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - bias-pull-down; - }; - - qup_uart7_sleep_rts: qup-uart7-sleep-rts { - pins = "gpio29"; - function = "gpio"; - /* - * Configure pull-down on RTS. As RTS is active low - * signal, pull it low to indicate the BT SoC that it - * can wakeup the system anytime from suspend state by - * pulling RX low (by sending wakeup bytes). - */ - bias-pull-down; - }; - - qup_uart7_sleep_rx: qup-uart7-sleep-rx { - pins = "gpio31"; - function = "gpio"; - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module - * is floating which may cause spurious wakeups. - */ - bias-pull-up; - }; - - qup_uart7_sleep_tx: qup-uart7-sleep-tx { - pins = "gpio30"; - function = "gpio"; - /* - * Configure pull-up on TX when it isn't actively driven - * to prevent BT SoC from receiving garbage during sleep. - */ - bias-pull-up; + bias-disable; + drive-strength = <2>; + output-low; }; tp_int_odl: tp-int-odl { - pins = "gpio102"; + pins = "gpio7"; function = "gpio"; /* Has external pullup */ bias-disable; }; - ts_int_l: ts-int-l { - pins = "gpio81"; - function = "gpio"; - /* Has external pullup */ - bias-pull-up; - }; - - ts_reset_l: ts-reset-l { - pins = "gpio105"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - drive-strength = <2>; - }; - - uf_cam_en: uf-cam-en { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; - wf_cam_en: wf-cam-en { - pins = "gpio7"; + pins = "gpio119"; function = "gpio"; - drive-strength = <2>; /* Has external pulldown */ bias-disable; + drive-strength = <2>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi index 0896a6151817..a7c346aa3b02 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -20,7 +20,7 @@ ap_ec_spi: &spi10 { pinctrl-0 = <&ap_ec_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 9b991ba5daaf..a7be133a782f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -56,6 +56,10 @@ }; }; +&bluetooth { + vddio-supply = <&vreg_l19b_1p8>; +}; + &ipa { status = "okay"; modem-init; @@ -80,3 +84,19 @@ qcom,pre-scaling = <1 1>; }; }; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index d623d71d8bd4..ecbf2b89d896 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -5,7 +5,6 @@ * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ -#include #include #include #include "sc7280.dtsi" @@ -13,7 +12,14 @@ #include "pm8350c.dtsi" #include "pmk8350.dtsi" +#include "sc7280-chrome-common.dtsi" + / { + aliases { + bluetooth0 = &bluetooth; + serial1 = &uart7; + }; + gpio-keys { compatible = "gpio-keys"; label = "gpio-keys"; @@ -45,58 +51,6 @@ }; }; -/* - * Reserved memory changes - * - * Delete all unused memory nodes and define the peripheral memory regions - * required by the board dts. - * - */ - -/delete-node/ &hyp_mem; -/delete-node/ &xbl_mem; -/delete-node/ &reserved_xbl_uefi_log; -/delete-node/ &sec_apps_mem; - -/* Increase the size from 2.5MB to 8MB */ -&rmtfs_mem { - reg = <0x0 0x9c900000 0x0 0x800000>; -}; - -/ { - reserved-memory { - adsp_mem: memory@86700000 { - reg = <0x0 0x86700000 0x0 0x2800000>; - no-map; - }; - - camera_mem: memory@8ad00000 { - reg = <0x0 0x8ad00000 0x0 0x500000>; - no-map; - }; - - venus_mem: memory@8b200000 { - reg = <0x0 0x8b200000 0x0 0x500000>; - no-map; - }; - - mpss_mem: memory@8b800000 { - reg = <0x0 0x8b800000 0x0 0xf600000>; - no-map; - }; - - wpss_mem: memory@9ae00000 { - reg = <0x0 0x9ae00000 0x0 0x1900000>; - no-map; - }; - - mba_mem: memory@9c700000 { - reg = <0x0 0x9c700000 0x0 0x200000>; - no-map; - }; - }; -}; - &apps_rsc { pm7325-regulators { compatible = "qcom,pm7325-rpmh-regulators"; @@ -313,20 +267,6 @@ vcc-supply = <&vreg_l1c_1p8>; }; -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <37500000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - }; -}; - &qupv3_id_0 { status = "okay"; }; @@ -335,20 +275,9 @@ status = "okay"; }; -&remoteproc_mpss { - status = "okay"; - compatible = "qcom,sc7280-mss-pil"; - iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; - memory-region = <&mba_mem &mpss_mem>; -}; - &sdhc_1 { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc1_on>; - pinctrl-1 = <&sdc1_off>; - non-removable; no-sd; no-sdio; @@ -360,9 +289,8 @@ &sdhc_2 { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_on>; - pinctrl-1 = <&sdc2_off>; + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; vmmc-supply = <&vreg_l9c_2p9>; vqmmc-supply = <&vreg_l6c_2p9>; @@ -398,22 +326,6 @@ vdda-pll-supply = <&vreg_l1b_0p8>; }; -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "peripheral"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdda-pll-supply = <&vreg_l10c_0p8>; - vdda33-supply = <&vreg_l2b_3p0>; - vdda18-supply = <&vreg_l1c_1p8>; -}; - &uart7 { status = "okay"; @@ -422,10 +334,31 @@ <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default", "sleep"; pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en>, <&sw_ctrl>; + enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; + vddaon-supply = <&vreg_s7b_0p9>; + vddbtcxmx-supply = <&vreg_s7b_0p9>; + vddrfacmn-supply = <&vreg_s7b_0p9>; + vddrfa0p8-supply = <&vreg_s7b_0p9>; + vddrfa1p7-supply = <&vreg_s1b_1p8>; + vddrfa1p2-supply = <&vreg_s8b_1p2>; + vddrfa2p2-supply = <&vreg_s1c_2p2>; + vddasd-supply = <&vreg_l11c_2p8>; + max-speed = <3200000>; + }; }; /* PINCTRL - additions to nodes defined in sc7280.dtsi */ +&dp_hot_plug_det { + bias-disable; +}; + &pm7325_gpios { key_vol_up_default: key-vol-up-default { pins = "gpio6"; @@ -437,6 +370,11 @@ }; }; +&pcie1_clkreq_n { + bias-pull-up; + drive-strength = <2>; +}; + &qspi_cs0 { bias-disable; }; @@ -490,7 +428,48 @@ bias-pull-up; }; +&sdc1_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc1_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_rclk { + bias-pull-down; +}; + +&sdc2_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength = <10>; +}; + &tlmm { + bt_en: bt-en { + pins = "gpio85"; + function = "gpio"; + output-low; + bias-disable; + }; + nvme_pwren: nvme-pwren { function = "gpio"; }; @@ -554,47 +533,17 @@ */ bias-pull-up; }; -}; -&sdc1_on { - clk { - bias-disable; - drive-strength = <16>; - }; - - cmd { + sd_cd: sd-cd { + pins = "gpio91"; + function = "gpio"; bias-pull-up; - drive-strength = <10>; }; - data { - bias-pull-up; - drive-strength = <10>; - }; - - rclk { + sw_ctrl: sw-ctrl { + pins = "gpio86"; + function = "gpio"; bias-pull-down; }; }; -&sdc2_on { - clk { - bias-disable; - drive-strength = <16>; - }; - - cmd { - bias-pull-up; - drive-strength = <10>; - }; - - data { - bias-pull-up; - drive-strength = <10>; - }; - - sd-cd { - pins = "gpio91"; - bias-pull-up; - }; -}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts index 0382c770650a..73b9911dd802 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts @@ -23,6 +23,10 @@ }; }; +&bluetooth { + vddio-supply = <&vreg_l18b_1p8>; +}; + &nvme_pwren { pins = "gpio51"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi new file mode 100644 index 000000000000..b833ba1e8f4a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sc7280 Qcard device tree source + * + * Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector (if + * stuffed) on it. This device tree tries to encapsulate all the things that + * all boards using Qcard will have in common. Given that there are stuffing + * options, some things may be left with status "disabled" and enabled in + * the actual board device tree files. + * + * Copyright 2022 Google LLC. + */ + +#include +#include +#include +#include + +#include "sc7280.dtsi" + +/* PMICs depend on spmi_bus label and so must come after SoC */ +#include "pm7325.dtsi" +#include "pm8350c.dtsi" +#include "pmk8350.dtsi" + +/ { + aliases { + bluetooth0 = &bluetooth; + serial0 = &uart5; + serial1 = &uart7; + }; +}; + +&apps_rsc { + /* + * Regulators are given labels corresponding to the various names + * they are referred to on schematics. They are also given labels + * corresponding to named voltage inputs on the SoC or components + * bundled with the SoC (like radio companion chips). We totally + * ignore it when one regulator is the input to another regulator. + * That's handled automatically by the initial config given to + * RPMH by the firmware. + * + * Regulators that the HLOS (High Level OS) doesn't touch at all + * are left out of here since they are managed elsewhere. + */ + + pm7325-regulators { + compatible = "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd19_pmu_pcie_i: + vdd19_pmu_rfa_i: + vreg_s1b_1p856: smps1 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2040000>; + }; + + vdd_pmu_aon_i: + vdd09_pmu_rfa_i: + vdd095_mx_pmu: + vdd095_pmu: + vreg_s7b_0p952: smps7 { + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + vdd13_pmu_rfa_i: + vdd13_pmu_pcie_i: + vreg_s8b_1p256: smps8 { + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1500000>; + }; + + vdd_a_usbssdp_0_core: + vreg_l1b_0p912: ldo1 { + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + regulator-initial-mode = ; + }; + + vdd_a_usbhs_3p1: + vreg_l2b_3p072: ldo2 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vdd_a_csi_0_1_1p2: + vdd_a_csi_2_3_1p2: + vdd_a_csi_4_1p2: + vdd_a_dsi_0_1p2: + vdd_a_edp_0_1p2: + vdd_a_qlink_0_1p2: + vdd_a_qlink_1_1p2: + vdd_a_pcie_0_1p2: + vdd_a_pcie_1_1p2: + vdd_a_ufs_0_1p2: + vdd_a_usbssdp_0_1p2: + vreg_l6b_1p2: ldo6 { + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + }; + + /* + * Despite the fact that this is named to be 2.5V on the + * schematic, it powers eMMC which doesn't accept 2.5V + */ + vreg_l7b_2p5: ldo7 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vdd_px_wcd9385: + vdd_txrx: + vddpx_0: + vddpx_3: + vddpx_7: + vreg_l18b_1p8: ldo18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vdd_1p8: + vdd_px_sdr735: + vdd_pxm: + vdd18_io: + vddio_px_1: + vddio_px_2: + vddio_px_3: + vddpx_ts: + vddpx_wl4otp: + vreg_l19b_1p8: ldo19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd22_wlbtpa_ch0: + vdd22_wlbtpa_ch1: + vdd22_wlbtppa_ch0: + vdd22_wlbtppa_ch1: + vdd22_wlpa5g_ch0: + vdd22_wlpa5g_ch1: + vdd22_wlppa5g_ch0: + vdd22_wlppa5g_ch1: + vreg_s1c_2p2: smps1 { + regulator-min-microvolt = <2190000>; + regulator-max-microvolt = <2210000>; + }; + + lp4_vdd2_1p052: + vreg_s9c_0p676: smps9 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + vdda_apc_cs_1p8: + vdda_gfx_cs_1p8: + vdda_turing_q6_cs_1p8: + vdd_a_cxo_1p8: + vdd_a_qrefs_1p8: + vdd_a_usbhs_1p8: + vdd_qfprom: + vreg_l1c_1p8: ldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l2c_1p8: ldo2 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3540000>; + regulator-initial-mode = ; + }; + + vddpx_5: + vreg_l4c_1p8_3p0: ldo4 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vddpx_6: + vreg_l5c_1p8_3p0: ldo5 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l6c_2p96: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vdd_a_csi_0_1_0p9: + vdd_a_csi_2_3_0p9: + vdd_a_csi_4_0p9: + vdd_a_dsi_0_0p9: + vdd_a_dsi_0_pll_0p9: + vdd_a_edp_0_0p9: + vdd_a_gnss_0p9: + vdd_a_pcie_0_core: + vdd_a_pcie_1_core: + vdd_a_qlink_0_0p9: + vdd_a_qlink_0_0p9_ck: + vdd_a_qlink_1_0p9: + vdd_a_qlink_1_0p9_ck: + vdd_a_qrefs_0p875_0: + vdd_a_qrefs_0p875_1: + vdd_a_qrefs_0p875_2: + vdd_a_qrefs_0p875_3: + vdd_a_qrefs_0p875_4_5: + vdd_a_qrefs_0p875_6: + vdd_a_qrefs_0p875_7: + vdd_a_qrefs_0p875_8: + vdd_a_qrefs_0p875_9: + vdd_a_ufs_0_core: + vdd_a_usbhs_core: + vreg_l10c_0p88: ldo10 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + regulator-initial-mode = ; + }; + + vreg_l11c_2p8: ldo11 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + regulator-initial-mode = ; + }; + + vdd_flash: + vdd_iris_rgb: + vdd_mic_bias: + vreg_bob: bob { + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + }; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +&ipa { + status = "okay"; + modem-init; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + +&pmk8350_vadc { + pmk8350-die-temp@3 { + reg = ; + label = "pmk8350_die_temp"; + qcom,pre-scaling = <1 1>; + }; + + pmr735a-die-temp@403 { + reg = ; + label = "pmr735a_die_temp"; + qcom,pre-scaling = <1 1>; + }; +}; + +&qfprom { + vcc-supply = <&vdd_qfprom>; +}; + +/* For eMMC. NOTE: not all Qcards have eMMC stuffed */ +&sdhc_1 { + vmmc-supply = <&vreg_l7b_2p5>; + vqmmc-supply = <&vreg_l19b_1p8>; + + non-removable; + no-sd; + no-sdio; +}; + +uart_dbg: &uart5 { + compatible = "qcom,geni-debug-uart"; + status = "okay"; +}; + +mos_bt_uart: &uart7 { + status = "okay"; + + /delete-property/ interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>; + + bluetooth: bluetooth { + compatible = "qcom,wcn6750-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&mos_bt_en>; + enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>; + vddaon-supply = <&vreg_s7b_0p952>; + vddbtcxmx-supply = <&vreg_s7b_0p952>; + vddrfacmn-supply = <&vreg_s7b_0p952>; + vddrfa0p8-supply = <&vreg_s7b_0p952>; + vddrfa1p7-supply = <&vdd19_pmu_rfa_i>; + vddrfa1p2-supply = <&vdd13_pmu_rfa_i>; + vddrfa2p2-supply = <&vreg_s1c_2p2>; + vddasd-supply = <&vreg_l11c_2p8>; + vddio-supply = <&vreg_l18b_1p8>; + max-speed = <3200000>; + }; +}; + +&usb_1_hsphy { + vdda-pll-supply = <&vdd_a_usbhs_core>; + vdda33-supply = <&vdd_a_usbhs_3p1>; + vdda18-supply = <&vdd_a_usbhs_1p8>; +}; + +&usb_1_qmpphy { + vdda-phy-supply = <&vdd_a_usbssdp_0_1p2>; + vdda-pll-supply = <&vdd_a_usbssdp_0_core>; +}; + +&usb_2_hsphy { + vdda-pll-supply = <&vdd_a_usbhs_core>; + vdda33-supply = <&vdd_a_usbhs_3p1>; + vdda18-supply = <&vdd_a_usbhs_1p8>; +}; + +/* + * PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES + * + * NOTE: In general if pins leave the Qcard then the pinctrl goes in the + * baseboard or board device tree, not here. + */ + +/* + * For ts_i2c + * + * Technically this i2c bus actually leaves the Qcard, but it leaves directly + * via the eDP connector (it doesn't hit the baseboard). The external pulls + * are on Qcard. + */ +&qup_i2c13_data_clk { + /* Has external pull */ + bias-disable; + drive-strength = <2>; +}; + +/* For mos_bt_uart */ +&qup_uart7_cts { + /* Configure a pull-down on CTS to match the pull of the Bluetooth module. */ + bias-pull-down; +}; + +/* For mos_bt_uart */ +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + bias-disable; + drive-strength = <2>; +}; + +/* For mos_bt_uart */ +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + bias-disable; + drive-strength = <2>; +}; + +/* For mos_bt_uart */ +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +/* eMMC, if stuffed, is straight on the Qcard */ +&sdc1_clk { + bias-disable; + drive-strength = <16>; +}; + +&sdc1_cmd { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_data { + bias-pull-up; + drive-strength = <10>; +}; + +&sdc1_rclk { + bias-pull-down; +}; + +/* + * PINCTRL - QCARD + * + * This has entries that are defined by Qcard even if they go to the main + * board. In cases where the pulls may be board dependent we defer those + * settings to the board device tree. Drive strengths tend to be assinged here + * but could conceivably be overwridden by board device trees. + */ + +&pm8350c_gpios { + pmic_edp_bl_en: pmic-edp-bl-en { + pins = "gpio7"; + function = "normal"; + bias-disable; + qcom,drive-strength = ; + + /* Force backlight to be disabled to match state at boot. */ + output-low; + }; + + pmic_edp_bl_pwm: pmic-edp-bl-pwm { + pins = "gpio8"; + function = "func1"; + bias-disable; + qcom,drive-strength = ; + output-low; + power-source = <0>; + }; +}; + +&tlmm { + mos_bt_en: mos-bt-en { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + output-low; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_cts: qup-uart7-sleep-cts { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_rts: qup-uart7-sleep-rts { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_rx: qup-uart7-sleep-rx { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; + + /* For mos_bt_uart */ + qup_uart7_sleep_tx: qup-uart7-sleep-tx { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + ts_int_conn: ts-int-conn { + pins = "gpio55"; + function = "gpio"; + bias-pull-up; + }; + + ts_rst_conn: ts-rst-conn { + pins = "gpio54"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 937c2e0e93eb..f0b64be63c21 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4,12 +4,14 @@ * * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ - +#include #include #include #include #include #include +#include +#include #include #include #include @@ -162,6 +164,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_0: l2-cache { @@ -182,6 +187,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_100>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_100: l2-cache { @@ -199,6 +207,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_200>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_200: l2-cache { @@ -216,6 +227,9 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_300>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_300: l2-cache { @@ -233,6 +247,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_400>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_400: l2-cache { @@ -250,6 +267,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_500>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_500: l2-cache { @@ -267,6 +287,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_600>; + operating-points-v2 = <&cpu4_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_600: l2-cache { @@ -284,6 +307,9 @@ &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache = <&L2_700>; + operating-points-v2 = <&cpu7_opp_table>; + interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, + <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; L2_700: l2-cache { @@ -383,6 +409,211 @@ }; }; + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp_300mhz: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <800000 9600000>; + }; + + cpu0_opp_691mhz: opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <800000 17817600>; + }; + + cpu0_opp_806mhz: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <800000 20889600>; + }; + + cpu0_opp_941mhz: opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <1804000 24576000>; + }; + + cpu0_opp_1152mhz: opp-1152000000 { + opp-hz = /bits/ 64 <1152000000>; + opp-peak-kBps = <2188000 27033600>; + }; + + cpu0_opp_1325mhz: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <2188000 33792000>; + }; + + cpu0_opp_1517mhz: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <3072000 38092800>; + }; + + cpu0_opp_1651mhz: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <3072000 41779200>; + }; + + cpu0_opp_1805mhz: opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <4068000 48537600>; + }; + + cpu0_opp_1958mhz: opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + opp-peak-kBps = <4068000 48537600>; + }; + + cpu0_opp_2016mhz: opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-peak-kBps = <6220000 48537600>; + }; + }; + + cpu4_opp_table: cpu4-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu4_opp_691mhz: opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <1804000 9600000>; + }; + + cpu4_opp_941mhz: opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <2188000 17817600>; + }; + + cpu4_opp_1229mhz: opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu4_opp_1344mhz: opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu4_opp_1517mhz: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu4_opp_1651mhz: opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu4_opp_1901mhz: opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2054mhz: opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2131mhz: opp-2131200000 { + opp-hz = /bits/ 64 <2131200000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2208mhz: opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu4_opp_2400mhz: opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <8532000 48537600>; + }; + + cpu4_opp_2611mhz: opp-2611200000 { + opp-hz = /bits/ 64 <2611200000>; + opp-peak-kBps = <8532000 48537600>; + }; + }; + + cpu7_opp_table: cpu7-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + cpu7_opp_806mhz: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <1804000 9600000>; + }; + + cpu7_opp_1056mhz: opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-peak-kBps = <2188000 17817600>; + }; + + cpu7_opp_1325mhz: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu7_opp_1517mhz: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <4068000 24576000>; + }; + + cpu7_opp_1766mhz: opp-1766400000 { + opp-hz = /bits/ 64 <1766400000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu7_opp_1862mhz: opp-1862400000 { + opp-hz = /bits/ 64 <1862400000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu7_opp_2035mhz: opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <6220000 38092800>; + }; + + cpu7_opp_2112mhz: opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu7_opp_2208mhz: opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <6220000 44851200>; + }; + + cpu7_opp_2381mhz: opp-2380800000 { + opp-hz = /bits/ 64 <2380800000>; + opp-peak-kBps = <6832000 44851200>; + }; + + cpu7_opp_2400mhz: opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-peak-kBps = <8532000 48537600>; + }; + + cpu7_opp_2515mhz: opp-2515200000 { + opp-hz = /bits/ 64 <2515200000>; + opp-peak-kBps = <8532000 48537600>; + }; + + cpu7_opp_2707mhz: opp-2707200000 { + opp-hz = /bits/ 64 <2707200000>; + opp-peak-kBps = <8532000 48537600>; + }; + + cpu7_opp_3014mhz: opp-3014400000 { + opp-hz = /bits/ 64 <3014400000>; + opp-peak-kBps = <8532000 48537600>; + }; + }; + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -615,6 +846,9 @@ sdhc_1: sdhci@7c4000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; + pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; status = "disabled"; reg = <0 0x007c4000 0 0x1000>, @@ -1714,6 +1948,8 @@ interconnect-names = "memory", "config"; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", @@ -1790,7 +2026,7 @@ }; }; - gmu: gmu@3d69000 { + gmu: gmu@3d6a000 { compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; reg = <0 0x03d6a000 0 0x34000>, <0 0x3de0000 0 0x10000>, @@ -2424,6 +2660,9 @@ sdhc_2: sdhci@8804000 { compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; + pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; status = "disabled"; reg = <0 0x08804000 0 0x1000>; @@ -2761,13 +3000,31 @@ #power-domain-cells = <1>; }; + camcc: clock-controller@ad00000 { + compatible = "qcom,sc7280-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sc7280-dispcc"; reg = <0 0xaf00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <0>, <0>, <0>, <0>, <0>, <0>; - clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", + <&mdss_dsi_phy 0>, + <&mdss_dsi_phy 1>, + <&dp_phy 0>, + <&dp_phy 1>, + <&mdss_edp_phy 0>, + <&mdss_edp_phy 1>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", @@ -2779,6 +3036,389 @@ #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sc7280-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x900 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sc7280-dpu"; + reg = <0 0x0ae01000 0 0x8f030>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + assigned-clock-rates = <300000000>, + <19200000>, + <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-506666667 { + opp-hz = /bits/ 64 <506666667>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + phys = <&mdss_dsi_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi_phy: phy@ae94400 { + compatible = "qcom,sc7280-dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_edp: edp@aea0000 { + compatible = "qcom,sc7280-edp"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hot_plug_det>; + + reg = <0 0xaea0000 0 0x200>, + <0 0xaea0200 0 0x200>, + <0 0xaea0400 0 0xc00>, + <0 0xaea1000 0 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <14>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_CLKREF_EN>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; + clock-names = "core_xo", + "core_ref", + "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; + + phys = <&mdss_edp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&edp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dpu_intf5_out>; + }; + }; + + port@1 { + reg = <1>; + edp_out: endpoint { }; + }; + }; + + edp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_edp_phy: phy@aec2a00 { + compatible = "qcom,sc7280-edp-phy"; + + reg = <0 0xaec2a00 0 0x19c>, + <0 0xaec2200 0 0xa0>, + <0 0xaec2600 0 0xa0>, + <0 0xaec2000 0 0x1c0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dp: displayport-controller@ae90000 { + compatible = "qcom,sc7280-dp"; + + reg = <0 0x0ae90000 0 0x1400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; + phys = <&dp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + #sound-dai-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + + dp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; @@ -2872,11 +3512,19 @@ gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; + dp_hot_plug_det: dp-hot-plug-det { + pins = "gpio47"; + function = "dp_hot"; + }; + + edp_hot_plug_det: edp-hot-plug-det { + pins = "gpio60"; + function = "edp_hot"; + }; + pcie1_clkreq_n: pcie1-clkreq-n { pins = "gpio79"; function = "pcie1_clkreqn"; - drive-strength = <2>; - bias-pull-up; }; qspi_clk: qspi-clk { @@ -3384,83 +4032,6 @@ function = "qup07"; }; - sdc1_on: sdc1-on { - clk { - pins = "sdc1_clk"; - }; - - cmd { - pins = "sdc1_cmd"; - }; - - data { - pins = "sdc1_data"; - }; - - rclk { - pins = "sdc1_rclk"; - }; - }; - - sdc1_off: sdc1-off { - clk { - pins = "sdc1_clk"; - drive-strength = <2>; - bias-bus-hold; - }; - - cmd { - pins = "sdc1_cmd"; - drive-strength = <2>; - bias-bus-hold; - }; - - data { - pins = "sdc1_data"; - drive-strength = <2>; - bias-bus-hold; - }; - - rclk { - pins = "sdc1_rclk"; - bias-bus-hold; - }; - }; - - sdc2_on: sdc2-on { - clk { - pins = "sdc2_clk"; - }; - - cmd { - pins = "sdc2_cmd"; - }; - - data { - pins = "sdc2_data"; - }; - }; - - sdc2_off: sdc2-off { - clk { - pins = "sdc2_clk"; - drive-strength = <2>; - bias-bus-hold; - }; - - cmd { - pins ="sdc2_cmd"; - drive-strength = <2>; - bias-bus-hold; - }; - - data { - pins ="sdc2_data"; - drive-strength = <2>; - bias-bus-hold; - }; - }; - qup_uart8_cts: qup-uart8-cts { pins = "gpio32"; function = "qup10"; @@ -3620,6 +4191,76 @@ pins = "gpio63"; function = "qup17"; }; + + sdc1_clk: sdc1-clk { + pins = "sdc1_clk"; + }; + + sdc1_cmd: sdc1-cmd { + pins = "sdc1_cmd"; + }; + + sdc1_data: sdc1-data { + pins = "sdc1_data"; + }; + + sdc1_rclk: sdc1-rclk { + pins = "sdc1_rclk"; + }; + + sdc1_clk_sleep: sdc1-clk-sleep { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + sdc1_cmd_sleep: sdc1-cmd-sleep { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + sdc1_data_sleep: sdc1-data-sleep { + pins = "sdc1_data"; + drive-strength = <2>; + bias-bus-hold; + }; + + sdc1_rclk_sleep: sdc1-rclk-sleep { + pins = "sdc1_rclk"; + drive-strength = <2>; + bias-bus-hold; + }; + + sdc2_clk: sdc2-clk { + pins = "sdc2_clk"; + }; + + sdc2_cmd: sdc2-cmd { + pins = "sdc2_cmd"; + }; + + sdc2_data: sdc2-data { + pins = "sdc2_data"; + }; + + sdc2_clk_sleep: sdc2-clk-sleep { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + sdc2_cmd_sleep: sdc2-cmd-sleep { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + sdc2_data_sleep: sdc2-data-sleep { + pins = "sdc2_data"; + drive-strength = <2>; + bias-bus-hold; + }; }; imem@146a5000 { @@ -3885,6 +4526,14 @@ }; }; + epss_l3: interconnect@18590000 { + compatible = "qcom,sc7280-epss-l3"; + reg = <0 0x18590000 0 0x1000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,cpufreq-epss"; reg = <0 0x18591000 0 0x1000>, diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 9217c3a51f79..240293592ef9 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -2160,7 +2160,7 @@ apr { compatible = "qcom,apr-v2"; qcom,glink-channels = "apr_audio_svc"; - qcom,apr-domain = ; + qcom,domain = ; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts new file mode 100644 index 000000000000..8b815b2a60a7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Luca Weiss + */ +/dts-v1/; + +#include "sdm632.dtsi" +#include "pm8953.dtsi" + +/ { + model = "Fairphone 3"; + compatible = "fairphone,fp3", "qcom,sdm632"; + chassis-type = "handset"; + qcom,msm-id = <349 0>; + qcom,board-id = <8 0x10000>; + + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &uart_0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + volume-up { + label = "volume_up"; + linux,code = ; + gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hsusb_phy { + status = "okay"; + vdd-supply = <&pm8953_l3>; + vdda-pll-supply = <&pm8953_l7>; + vdda-phy-dpdm-supply = <&pm8953_l13>; +}; + +&pm8953_resin { + status = "okay"; + linux,code = ; +}; + +&sdhc_1 { + status = "okay"; + vmmc-supply = <&pm8953_l8>; + vqmmc-supply = <&pm8953_l5>; +}; + +&sdhc_2 { + status = "okay"; + vmmc-supply = <&pm8953_l11>; + vqmmc-supply = <&pm8953_l12>; + + cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; +}; + +&rpm_requests { + pm8953-regulators { + compatible = "qcom,rpm-pm8953-regulators"; + + vdd_l1-supply = <&pm8953_s3>; + vdd_l2_l3-supply = <&pm8953_s3>; + vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>; + vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>; + vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>; + + pm8953_s3: s3 { + regulator-min-microvolt = <984000>; + regulator-max-microvolt = <1240000>; + }; + pm8953_s4: s4 { + regulator-min-microvolt = <1036000>; + regulator-max-microvolt = <2040000>; + }; + pm8953_s5: s5 { + regulator-min-microvolt = <1036000>; + regulator-max-microvolt = <2040000>; + }; + + pm8953_l1: l1 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1050000>; + }; + pm8953_l2: l2 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1175000>; + }; + pm8953_l3: l3 { + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + }; + pm8953_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8953_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8953_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + }; + pm8953_l8: l8 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + }; + pm8953_l9: l9 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + pm8953_l10: l10 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3000000>; + }; + pm8953_l11: l11 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + pm8953_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + pm8953_l13: l13 { + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3125000>; + }; + pm8953_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + pm8953_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + pm8953_l19: l19 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + pm8953_l22: l22 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + pm8953_l23: l23 { + regulator-min-microvolt = <975000>; + regulator-max-microvolt = <1225000>; + }; + }; +}; + +&tlmm { + /* + * 0-3: unused but protected by TZ + * 135-138: fingerprint reader (SPI) + */ + gpio-reserved-ranges = <0 4>, <135 4>; +}; + +&uart_0 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm632.dtsi b/arch/arm64/boot/dts/qcom/sdm632.dtsi new file mode 100644 index 000000000000..645b9f6a801f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm632.dtsi @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ + +#include "msm8953.dtsi" + +/ { + thermal-zones { + /delete-node/cpu1-thermal; + /delete-node/cpu2-thermal; + /delete-node/cpu3-thermal; + + cpu0-thermal { + thermal-sensors = <&tsens0 13>; + + cooling-maps { + map0 { + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu4-thermal { + thermal-sensors = <&tsens0 5>; + }; + + cpu5-thermal { + thermal-sensors = <&tsens0 6>; + }; + + cpu6-thermal { + thermal-sensors = <&tsens0 7>; + }; + + cpu7-thermal { + thermal-sensors = <&tsens0 8>; + }; + }; +}; + +/* + * SDM632 uses Kryo 250 instead of Cortex A53 + * CPU0-3 are efficiency cores, CPU4-7 are performance cores + */ +&CPU0 { + compatible = "qcom,kryo250"; +}; + +&CPU1 { + compatible = "qcom,kryo250"; +}; + +&CPU2 { + compatible = "qcom,kryo250"; +}; + +&CPU3 { + compatible = "qcom,kryo250"; +}; + +&CPU4 { + compatible = "qcom,kryo250"; + capacity-dmips-mhz = <1980>; +}; + +&CPU5 { + compatible = "qcom,kryo250"; + capacity-dmips-mhz = <1980>; +}; + +&CPU6 { + compatible = "qcom,kryo250"; + capacity-dmips-mhz = <1980>; +}; + +&CPU7 { + compatible = "qcom,kryo250"; + capacity-dmips-mhz = <1980>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 4a6285a25f77..e7e4cc5936aa 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -708,7 +708,7 @@ ap_ts_i2c: &i2c14 { pinctrl-0 = <&ec_ap_int_l>; spi-max-frequency = <3000000>; - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 13f80a0b6faa..28fe45c5d516 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -425,6 +425,10 @@ status = "okay"; }; +&gpi_dma0 { + status = "okay"; +}; + &gpu { status = "okay"; zap-shader { @@ -1125,7 +1129,6 @@ port@0 { reg = <0>; csiphy0_ep: endpoint { - clock-lanes = <7>; data-lanes = <0 1 2 3>; remote-endpoint = <&ov8856_ep>; }; @@ -1166,7 +1169,6 @@ port { ov8856_ep: endpoint { - clock-lanes = <1>; link-frequencies = /bits/ 64 <360000000 180000000>; data-lanes = <1 2 3 4>; @@ -1211,7 +1213,6 @@ port { ov7251_ep: endpoint { - clock-lanes = <1>; data-lanes = <0 1>; // remote-endpoint = <&csiphy3_ep>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi index 7f42e5315ecb..1084d5ce9ac7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi @@ -54,7 +54,7 @@ * it is otherwise possible for an allocation adjacent to the * rmtfs_mem region to trigger an XPU violation, causing a crash. */ - rmtfs_lower_guard: memory@f5b00000 { + rmtfs_lower_guard: rmtfs-lower-guard@f5b00000 { no-map; reg = <0 0xf5b00000 0 0x1000>; }; @@ -63,7 +63,7 @@ * but given the same address every time. Hard code it as this address is * where the modem firmware expects it to be. */ - rmtfs_mem: memory@f5b01000 { + rmtfs_mem: rmtfs-mem@f5b01000 { compatible = "qcom,rmtfs-mem"; reg = <0 0xf5b01000 0 0x200000>; no-map; @@ -71,7 +71,7 @@ qcom,client-id = <1>; qcom,vmid = <15>; }; - rmtfs_upper_guard: memory@f5d01000 { + rmtfs_upper_guard: rmtfs-upper-guard@f5d01000 { no-map; reg = <0 0xf5d01000 0 0x1000>; }; @@ -80,7 +80,7 @@ * It seems like reserving the old rmtfs_mem region is also needed to prevent * random crashes which are most likely modem related, more testing needed. */ - removed_region: memory@88f00000 { + removed_region: removed-region@88f00000 { no-map; reg = <0 0x88f00000 0 0x1c00000>; }; @@ -376,6 +376,17 @@ }; }; +&i2c10 { + status = "okay"; + clock-frequency = <100000>; + + bq27441_fg: bq27441-battery@55 { + compatible = "ti,bq27411"; + status = "okay"; + reg = <0x55>; + }; +}; + &i2c12 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 5936b47dee5f..bf2cf92e8976 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -13,6 +13,14 @@ chassis-type = "handset"; qcom,msm-id = <0x141 0x20001>; qcom,board-id = <8 0 17819 22>; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <3300000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; }; &display_panel { @@ -20,3 +28,7 @@ compatible = "samsung,sofef00"; }; + +&bq27441_fg { + monitored-battery = <&battery>; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts index 78a0b99144e6..1b6b5bf368df 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts @@ -13,6 +13,14 @@ chassis-type = "handset"; qcom,msm-id = <0x141 0x20001>; qcom,board-id = <8 0 18801 41>; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <3700000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4400000>; + }; }; &display_panel { @@ -21,6 +29,10 @@ compatible = "samsung,s6e3fc2x01"; }; +&bq27441_fg { + monitored-battery = <&battery>; +}; + &rmi4_f12 { touchscreen-y-mm = <148>; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts new file mode 100644 index 000000000000..8553c8bf79bd --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, Alexander Martinz + * Copyright (c) 2022, Caleb Connolly + */ + +/dts-v1/; + +#include +#include +#include "sdm845.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" + +/ { + model = "SHIFT SHIFT6mq"; + compatible = "shift,axolotl", "qcom,sdm845"; + qcom,msm-id = <321 0x20001>; + qcom,board-id = <11 0>; + + aliases { + display0 = &framebuffer0; + serial0 = &uart9; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + /* Use framebuffer setup by the bootloader. */ + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>; + width = <1080>; + height = <2160>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&volume_up_gpio>; + + vol-up { + label = "volume_up"; + linux,code = ; + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + }; + }; + + reserved-memory { + framebuffer_region@9d400000 { + reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>; + no-map; + }; + + ramoops: ramoops@b0000000 { + compatible = "ramoops"; + reg = <0 0xb0000000 0 0x00400000>; + record-size = <0x40000>; + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size = <0x200000>; + ecc-size = <0x0>; + }; + }; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <3850000>; + voltage-min-design-microvolt = <3600000>; + voltage-max-design-microvolt = <4400000>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_s4a_1p8: pm8998-smps4 { + compatible = "regulator-fixed"; + regulator-name = "vreg_s4a_1p8"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&vph_pwr>; + }; +}; + +&adsp_pas { + status = "okay"; + firmware-name = "qcom/sdm845/axolotl/adsp.mbn"; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + vdd-s13-supply = <&vph_pwr>; + vdd-l1-l27-supply = <&vreg_s7a_1p025>; + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l3-l11-supply = <&vreg_s7a_1p025>; + vdd-l4-l5-supply = <&vreg_s7a_1p025>; + vdd-l6-supply = <&vph_pwr>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + vdd-l9-supply = <&vreg_bob>; + vdd-l10-l23-l25-supply = <&vreg_bob>; + vdd-l13-l19-l21-supply = <&vreg_bob>; + vdd-l16-l28-supply = <&vreg_bob>; + vdd-l18-l22-supply = <&vreg_bob>; + vdd-l20-l24-supply = <&vreg_bob>; + vdd-l26-supply = <&vreg_s3a_1p35>; + vin-lvs-1-2-supply = <&vreg_s4a_1p8>; + + vreg_s2a_1p125: smps2 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2040000>; + }; + + vreg_s7a_1p025: smps7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + + vdd_qusb_hs0: + vdda_hp_pcie_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vdda_qrefs_0p875: + vdda_pcie_core: + vdda_pll_cc_ebi01: + vdda_pll_cc_ebi23: + vdda_sp_sensor: + vdda_ufs1_core: + vdda_ufs2_core: + vdda_usb1_ss_core: + vdda_usb2_ss_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vddpx_10: + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = ; + }; + + vdd_wcss_cx: + vdd_wcss_mx: + vdda_wcss_pll: + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vddpx_13: + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <1856000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8a_1p2: ldo8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = ; + }; + + vreg_l9a_1p8: ldo9 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l10a_1p8: ldo10 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = ; + }; + + vreg_l11a_1p0: ldo11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1048000>; + regulator-initial-mode = ; + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc1_cs_1p8: + vdda_gfx_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l13a_2p95: ldo13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l15a_1p8: ldo15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l16a_2p7: ldo16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + regulator-initial-mode = ; + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l18a_2p7: ldo18 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l19a_3p0: ldo19 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p95: ldo21 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l22a_2p85: ldo22 { + regulator-min-microvolt = <2864000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vdda_qusb_hs0_3p1: + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vdda_hp_pcie_1p2: + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_mipi_csi_1p25: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_pcie_1p2: + vdda_ufs1_1p2: + vdda_ufs2_1p2: + vdda_usb1_ss_1p2: + vdda_usb2_ss_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l28a_3p0: ldo28 { + regulator-min-microvolt = <2856000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + pmi8998-rpmh-regulators { + compatible = "qcom,pmi8998-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + regulator-initial-mode = ; + regulator-allow-bypass; + }; + }; + + pm8005-rpmh-regulators { + compatible = "qcom,pm8005-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + + vreg_s3c_0p6: smps3 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <600000>; + }; + }; +}; + +&cdsp_pas { + status = "okay"; + firmware-name = "qcom/sdm845/axolotl/cdsp.mbn"; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vdda_mipi_dsi0_1p2>; + + panel@0 { + compatible = "visionox,rm69299-shift"; + status = "okay"; + reg = <0>; + vdda-supply = <&vreg_l14a_1p88>; + vdd3p3-supply = <&vreg_l28a_3p0>; + + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active &sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; + + port { + panel_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&panel_in_0>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vdda_mipi_dsi0_pll>; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn"; + }; +}; + +&i2c5 { + status="okay"; + + touchscreen@38 { + compatible = "focaltech,fts8719"; + reg = <0x38>; + wakeup-source; + interrupt-parent = <&tlmm>; + interrupts = <125 0x2>; + vdd-supply = <&vreg_l28a_3p0>; + vcc-i2c-supply = <&vreg_l14a_1p88>; + + pinctrl-names = "default", "suspend"; + pinctrl-0 = <&ts_int_active &ts_reset_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + + reset-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; + irq-gpio = <&tlmm 125 GPIO_TRANSITORY>; + touchscreen-size-x = <1080>; + touchscreen-size-y = <2160>; + focaltech,max-touch-number = <5>; + }; +}; + +&ipa { + status = "okay"; + + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm845/axolotl/ipa_fws.mbn"; +}; + +&mdss { + status = "okay"; +}; + +&mss_pil { + status = "okay"; + firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn"; +}; + +&pm8998_gpio { + volume_up_gpio: pm8998_gpio6 { + pinconf { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,drive-strength = <0>; + }; + }; +}; + +&pm8998_pon { + volume_down_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + +&qup_uart9_default { + pinconf-rx { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + + pinconf-tx { + pins = "gpio4"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + sde_dsi_active: sde-dsi-active { + mux { + pins = "gpio6", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio11"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + + sde_dsi_suspend: sde-dsi-suspend { + mux { + pins = "gpio6", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sde_te_active: sde-te-active { + mux { + pins = "gpio10"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sde_te_suspend: sde-te-suspend { + mux { + pins = "gpio10"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + ts_int_active: ts-int-active { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <8>; + bias-pull-up; + input-enable; + }; + }; + + ts_int_suspend: ts-int-suspend { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + ts_reset_active: ts-reset-active { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + ts_reset_suspend: ts-reset-suspend { + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&uart6 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + }; +}; + +&uart9 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vreg_l1a_0p875>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; + vdda-pll-supply = <&vreg_l12a_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l26a_1p2>; + vdda-pll-supply = <&vreg_l1a_0p875>; +}; + +&venus { + status = "okay"; + firmware-name = "qcom/sdm845/axolotl/venus.mbn"; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index cfdeaa81f1bb..41f4e46e1f85 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -79,22 +80,22 @@ #size-cells = <2>; ranges; - hyp_mem: memory@85700000 { + hyp_mem: hyp-mem@85700000 { reg = <0 0x85700000 0 0x600000>; no-map; }; - xbl_mem: memory@85e00000 { + xbl_mem: xbl-mem@85e00000 { reg = <0 0x85e00000 0 0x100000>; no-map; }; - aop_mem: memory@85fc0000 { + aop_mem: aop-mem@85fc0000 { reg = <0 0x85fc0000 0 0x20000>; no-map; }; - aop_cmd_db_mem: memory@85fe0000 { + aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { compatible = "qcom,cmd-db"; reg = <0x0 0x85fe0000 0 0x20000>; no-map; @@ -107,12 +108,12 @@ hwlocks = <&tcsr_mutex 3>; }; - tz_mem: memory@86200000 { + tz_mem: tz@86200000 { reg = <0 0x86200000 0 0x2d00000>; no-map; }; - rmtfs_mem: memory@88f00000 { + rmtfs_mem: rmtfs@88f00000 { compatible = "qcom,rmtfs-mem"; reg = <0 0x88f00000 0 0x200000>; no-map; @@ -121,67 +122,67 @@ qcom,vmid = <15>; }; - qseecom_mem: memory@8ab00000 { + qseecom_mem: qseecom@8ab00000 { reg = <0 0x8ab00000 0 0x1400000>; no-map; }; - camera_mem: memory@8bf00000 { + camera_mem: camera-mem@8bf00000 { reg = <0 0x8bf00000 0 0x500000>; no-map; }; - ipa_fw_mem: memory@8c400000 { + ipa_fw_mem: ipa-fw@8c400000 { reg = <0 0x8c400000 0 0x10000>; no-map; }; - ipa_gsi_mem: memory@8c410000 { + ipa_gsi_mem: ipa-gsi@8c410000 { reg = <0 0x8c410000 0 0x5000>; no-map; }; - gpu_mem: memory@8c415000 { + gpu_mem: gpu@8c415000 { reg = <0 0x8c415000 0 0x2000>; no-map; }; - adsp_mem: memory@8c500000 { + adsp_mem: adsp@8c500000 { reg = <0 0x8c500000 0 0x1a00000>; no-map; }; - wlan_msa_mem: memory@8df00000 { + wlan_msa_mem: wlan-msa@8df00000 { reg = <0 0x8df00000 0 0x100000>; no-map; }; - mpss_region: memory@8e000000 { + mpss_region: mpss@8e000000 { reg = <0 0x8e000000 0 0x7800000>; no-map; }; - venus_mem: memory@95800000 { + venus_mem: venus@95800000 { reg = <0 0x95800000 0 0x500000>; no-map; }; - cdsp_mem: memory@95d00000 { + cdsp_mem: cdsp@95d00000 { reg = <0 0x95d00000 0 0x800000>; no-map; }; - mba_region: memory@96500000 { + mba_region: mba@96500000 { reg = <0 0x96500000 0 0x200000>; no-map; }; - slpi_mem: memory@96700000 { + slpi_mem: slpi@96700000 { reg = <0 0x96700000 0 0x1400000>; no-map; }; - spss_mem: memory@97b00000 { + spss_mem: spss@97b00000 { reg = <0 0x97b00000 0 0x100000>; no-map; }; @@ -787,7 +788,7 @@ apr { compatible = "qcom,apr-v2"; qcom,glink-channels = "apr_audio_svc"; - qcom,apr-domain = ; + qcom,domain = ; #address-cells = <1>; #size-cells = <0>; qcom,intents = <512 20>; @@ -1125,6 +1126,29 @@ }; }; + gpi_dma0: dma-controller@800000 { + #dma-cells = <3>; + compatible = "qcom,sdm845-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x0016 0x0>; + status = "disabled"; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x6000>; @@ -1171,6 +1195,9 @@ interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1544,6 +1571,29 @@ }; }; + gpi_dma1: dma-controller@0xa00000 { + #dma-cells = <3>; + compatible = "qcom,sdm845-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + iommus = <&apps_smmu 0x06d6 0x0>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x6000>; @@ -1967,7 +2017,7 @@ }; }; - system-cache-controller@1100000 { + llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; @@ -2587,6 +2637,13 @@ "gpio2", "gpio3"; function = "qup0"; }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; }; qup_spi1_default: qup-spi1-default { @@ -3613,10 +3670,10 @@ #clock-cells = <0>; clock-frequency = <9600000>; clock-output-names = "mclk"; - qcom,micbias1-millivolt = <1800>; - qcom,micbias2-millivolt = <1800>; - qcom,micbias3-millivolt = <1800>; - qcom,micbias4-millivolt = <1800>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; #address-cells = <1>; #size-cells = <1>; @@ -4139,6 +4196,8 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; }; dsi_opp_table: dsi-opp-table { @@ -4619,7 +4678,7 @@ }; aoss_qmp: power-controller@c300000 { - compatible = "qcom,sdm845-aoss-qmp"; + compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x100000>; interrupts = ; mboxes = <&apss_shared 0>; @@ -5258,7 +5317,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -5273,7 +5332,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index e2b9ec134cb1..f1619b3f97ef 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -56,19 +56,6 @@ }; }; - panel { - compatible = "boe,nv133fhm-n61"; - no-hpd; - - ports { - port { - panel_in_edp: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - }; - /* Reserved memory changes for IPA */ reserved-memory { wlan_msa_mem: memory@8c400000 { @@ -98,6 +85,12 @@ clock-frequency = <19200000>; }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&sn65dsi86 1000000>; + enable-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>; + }; }; &adsp_pas { @@ -419,6 +412,7 @@ clock-names = "refclk"; no-hpd; + #pwm-cells = <1>; ports { #address-cells = <1>; @@ -438,6 +432,19 @@ }; }; }; + + aux-bus { + panel: panel { + compatible = "boe,nv133fhm-n61"; + backlight = <&backlight>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts new file mode 100644 index 000000000000..2a552d817b03 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Samsung Galaxy Book2 + * + * Copyright (c) 2022, Xilin Wu + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "sdm850.dtsi" +#include "pm8998.dtsi" + +/* + * Update following upstream (sdm845.dtsi) reserved + * memory mappings for firmware loading to succeed + */ +/delete-node/ &qseecom_mem; +/delete-node/ &wlan_msa_mem; +/delete-node/ &slpi_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &ipa_gsi_mem; +/delete-node/ &gpu_mem; +/delete-node/ &mpss_region; +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &venus_mem; +/delete-node/ &mba_region; +/delete-node/ &spss_mem; + +/ { + model = "Samsung Galaxy Book2"; + compatible = "samsung,w737", "qcom,sdm845"; + chassis-type = "convertible"; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + // Firmware initialized the display at 1280p instead of 1440p + framebuffer0: framebuffer@80400000 { + compatible = "simple-framebuffer"; + reg = <0 0x80400000 0 (1920 * 1280 * 4)>; + width = <1920>; + height = <1280>; + stride = <(1920 * 4)>; + format = "a8r8g8b8"; + }; + }; + + aliases { + hsuart0 = &uart6; + }; + + /* Reserved memory changes */ + reserved-memory { + /* Bootloader display framebuffer region */ + cont_splash_mem: memory@80400000 { + reg = <0x0 0x80400000 0x0 0x960000>; + no-map; + }; + + qseecom_mem: memory@8b500000 { + reg = <0 0x8b500000 0 0xa00000>; + no-map; + }; + + wlan_msa_mem: memory@8c400000 { + reg = <0 0x8c400000 0 0x100000>; + no-map; + }; + + slpi_mem: memory@8c500000 { + reg = <0 0x8c500000 0 0x1200000>; + no-map; + }; + + ipa_fw_mem: memory@8d700000 { + reg = <0 0x8d700000 0 0x100000>; + no-map; + }; + + gpu_mem: memory@8d800000 { + reg = <0 0x8d800000 0 0x5000>; + no-map; + }; + + mpss_region: memory@8e000000 { + reg = <0 0x8e000000 0 0x8000000>; + no-map; + }; + + adsp_mem: memory@96000000 { + reg = <0 0x96000000 0 0x2000000>; + no-map; + }; + + cdsp_mem: memory@98000000 { + reg = <0 0x98000000 0 0x800000>; + no-map; + }; + + venus_mem: memory@98800000 { + reg = <0 0x98800000 0 0x500000>; + no-map; + }; + + mba_region: memory@98d00000 { + reg = <0 0x98d00000 0 0x200000>; + no-map; + }; + + spss_mem: memory@98f00000 { + reg = <0 0x98f00000 0 0x100000>; + no-map; + }; + }; +}; + +&adsp_pas { + firmware-name = "qcom/samsung/w737/qcadsp850.mbn"; + status = "okay"; +}; + +&apps_rsc { + pm8998-rpmh-regulators { + compatible = "qcom,pm8998-rpmh-regulators"; + qcom,pmic-id = "a"; + + vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; + vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; + + vreg_s2a_1p125: smps2 { + }; + + vreg_s3a_1p35: smps3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + regulator-initial-mode = ; + }; + + vreg_s4a_1p8: smps4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_s5a_2p04: smps5 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s7a_1p025: smps7 { + }; + + vdd_qusb_hs0: + vdda_hp_pcie_core: + vdda_mipi_csi0_0p9: + vdda_mipi_csi1_0p9: + vdda_mipi_csi2_0p9: + vdda_mipi_dsi0_pll: + vdda_mipi_dsi1_pll: + vdda_qlink_lv: + vdda_qlink_lv_ck: + vdda_qrefs_0p875: + vdda_pcie_core: + vdda_pll_cc_ebi01: + vdda_pll_cc_ebi23: + vdda_sp_sensor: + vdda_ufs1_core: + vdda_ufs2_core: + vdda_usb1_ss_core: + vdda_usb2_ss_core: + vreg_l1a_0p875: ldo1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-initial-mode = ; + }; + + vddpx_10: + vreg_l2a_1p2: ldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l3a_1p0: ldo3 { + }; + + vdd_wcss_cx: + vdd_wcss_mx: + vdda_wcss_pll: + vreg_l5a_0p8: ldo5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = ; + }; + + vddpx_13: + vreg_l6a_1p8: ldo6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l7a_1p8: ldo7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l8a_1p2: ldo8 { + }; + + vreg_l9a_1p8: ldo9 { + }; + + vreg_l10a_1p8: ldo10 { + }; + + vreg_l11a_1p0: ldo11 { + }; + + vdd_qfprom: + vdd_qfprom_sp: + vdda_apc1_cs_1p8: + vdda_gfx_cs_1p8: + vdda_qrefs_1p8: + vdda_qusb_hs0_1p8: + vddpx_11: + vreg_l12a_1p8: ldo12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vddpx_2: + vreg_l13a_2p95: ldo13 { + }; + + vreg_l14a_1p88: ldo14 { + regulator-min-microvolt = <1880000>; + regulator-max-microvolt = <1880000>; + regulator-initial-mode = ; + regulator-always-on; + }; + + vreg_l15a_1p8: ldo15 { + }; + + vreg_l16a_2p7: ldo16 { + }; + + vreg_l17a_1p3: ldo17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + regulator-initial-mode = ; + }; + + vreg_l18a_1p8: ldo18 { + }; + + vreg_l19a_3p0: ldo19 { + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3108000>; + regulator-initial-mode = ; + }; + + vreg_l20a_2p95: ldo20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-initial-mode = ; + }; + + vreg_l21a_2p95: ldo21 { + }; + + vreg_l22a_2p85: ldo22 { + }; + + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + + vdda_qusb_hs0_3p1: + vreg_l24a_3p075: ldo24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3083000>; + regulator-initial-mode = ; + }; + + vreg_l25a_3p3: ldo25 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3112000>; + regulator-initial-mode = ; + }; + + vdda_hp_pcie_1p2: + vdda_hv_ebi0: + vdda_hv_ebi1: + vdda_hv_ebi2: + vdda_hv_ebi3: + vdda_mipi_csi_1p25: + vdda_mipi_dsi0_1p2: + vdda_mipi_dsi1_1p2: + vdda_pcie_1p2: + vdda_ufs1_1p2: + vdda_ufs2_1p2: + vdda_usb1_ss_1p2: + vdda_usb2_ss_1p2: + vreg_l26a_1p2: ldo26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1208000>; + regulator-initial-mode = ; + }; + + vreg_l28a_3p0: ldo28 { + }; + + vreg_lvs1a_1p8: lvs1 { + }; + + vreg_lvs2a_1p8: lvs2 { + }; + }; +}; + +&cdsp_pas { + firmware-name = "qcom/samsung/w737/qccdsp850.mbn"; + status = "okay"; +}; + +&gcc { + protected-clocks = , + , + , + , + ; +}; + +&i2c10 { + status = "okay"; + clock-frequency = <400000>; + + /* SN65DSI86 @ 0x2c */ + /* The panel requires dual DSI, which is not supported by the bridge driver */ +}; + +&i2c11 { + status = "okay"; + clock-frequency = <400000>; + + /* HID-I2C Touchscreen @ 0x20 */ +}; + +&i2c15 { + status = "okay"; + clock-frequency = <400000>; + + digitizer@9 { + compatible = "wacom,w9013", "hid-over-i2c"; + reg = <0x9>; + pinctrl-names = "default"; + pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; + + post-power-on-delay-ms = <120>; + + interrupt-parent = <&tlmm>; + interrupts = <119 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x1>; + }; +}; + +&ipa { + status = "okay"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/samsung/w737/ipa_fws.elf"; +}; + +/* No idea why it causes an SError when enabled */ +&llcc { + status = "disabled"; +}; + +&mss_pil { + status = "okay"; + firmware-name = "qcom/samsung/w737/qcdsp1v2850.mbn", "qcom/samsung/w737/qcdsp2850.mbn"; +}; + +&qup_i2c10_default { + pinconf { + pins = "gpio55", "gpio56"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_i2c11_default { + pinconf { + pins = "gpio31", "gpio32"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_i2c12_default { + drive-strength = <2>; + bias-disable; +}; + +&qup_uart6_default { + pinmux { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; + function = "qup6"; + }; + + cts { + pins = "gpio45"; + bias-pull-down; + }; + + rts-tx { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + bias-disable; + }; + + rx { + pins = "gpio48"; + bias-pull-up; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + +&sound { + compatible = "qcom,sdm845-sndcard"; + model = "Samsung-W737"; + + audio-routing = + "RX_BIAS", "MCLK", + "AMIC2", "MIC BIAS2", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT", + "MM_DL1", "MultiMedia1 Playback", + "MM_DL3", "MultiMedia3 Playback", + "MultiMedia2 Capture", "MM_UL2"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 1>; + }; + }; + + slim-wcd-dai-link { + link-name = "SLIM WCD Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_1_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9340 2>; + }; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 6>, <85 4>; + + pen_irq_l: pen-irq-l { + pinmux { + pins = "gpio119"; + function = "gpio"; + }; + + pinconf { + pins = "gpio119"; + bias-disable; + }; + }; + + pen_pdct_l: pen-pdct-l { + pinmux { + pins = "gpio124"; + function = "gpio"; + }; + + pinconf { + pins = "gpio124"; + bias-disable; + drive-strength = <2>; + output-high; + }; + }; + + pen_rst_l: pen-rst-l { + pinmux { + pins = "gpio21"; + function = "gpio"; + }; + + pinconf { + pins = "gpio21"; + bias-disable; + drive-strength = <2>; + + /* + * The pen driver doesn't currently support + * driving this reset line. By specifying + * output-high here we're relying on the fact + * that this pin has a default pulldown at boot + * (which makes sure the pen was in reset if it + * was powered) and then we set it high here to + * take it out of reset. Better would be if the + * pen driver could control this and we could + * remove "output-high" here. + */ + output-high; + }; + }; + + wcd_intr_default: wcd_intr_default { + pins = "gpio54"; + function = "gpio"; + + input-enable; + bias-pull-down; + drive-strength = <2>; + }; +}; + +&uart6 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + vddch1-supply = <&vreg_l23a_3p3>; + max-speed = <3200000>; + }; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdd-supply = <&vdda_usb1_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; + qcom,preemphasis-level = ; + qcom,preemphasis-width = ; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vdda_usb1_ss_1p2>; + vdda-pll-supply = <&vdda_usb1_ss_core>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdd-supply = <&vdda_usb2_ss_core>; + vdda-pll-supply = <&vdda_qusb_hs0_1p8>; + vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; + + qcom,imp-res-offset-value = <8>; + qcom,hstx-trim-value = ; +}; + +&usb_2_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vdda_usb2_ss_1p2>; + vdda-pll-supply = <&vdda_usb2_ss_core>; +}; + +&venus { + status = "okay"; + firmware-name = "qcom/samsung/w737/qcvss850.mbn"; +}; + +&wcd9340{ + pinctrl-0 = <&wcd_intr_default>; + pinctrl-names = "default"; + clock-names = "extclk"; + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + reset-gpios = <&tlmm 64 0>; + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-io-supply = <&vreg_s4a_1p8>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + + swm: swm@c85 { + left_spkr: wsa8810-left{ + compatible = "sdw10217211000"; + reg = <0 3>; + powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #sound-dai-cells = <0>; + }; + + right_spkr: wsa8810-right{ + compatible = "sdw10217211000"; + powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>; + reg = <0 4>; + #thermal-sensor-cells = <0>; + sound-name-prefix = "SpkrRight"; + #sound-dai-cells = <0>; + }; + }; +}; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>; + vdd-1.8-xo-supply = <&vreg_l7a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; + + qcom,snoc-host-cap-8bit-quirk; +}; diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 49e6bca646c2..e81b2a7794fb 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -449,7 +449,7 @@ <&xo_board>; clock-names = "iface", "core", "xo"; - power-domains = <&rpmpd 0>; + power-domains = <&rpmpd SM6125_VDDCX>; bus-width = <8>; non-removable; @@ -474,7 +474,7 @@ pinctrl-1 = <&sdc2_state_off>; pinctrl-names = "default", "sleep"; - power-domains = <&rpmpd 0>; + power-domains = <&rpmpd SM6125_VDDCX>; bus-width = <4>; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index d4af9e0dad87..adb6ca2be2a5 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -10,6 +10,7 @@ #include #include #include "sm7225.dtsi" +#include "pm6150l.dtsi" #include "pm6350.dtsi" / { @@ -300,6 +301,14 @@ firmware-name = "qcom/sm7225/fairphone4/modem.mdt"; }; +&pm6150l_wled { + status = "okay"; + + qcom,switching-freq = <800>; + qcom,current-limit-microamp = <20000>; + qcom,num-strings = <2>; +}; + &pm6350_gpios { gpio_keys_pin: gpio-keys-pin { pins = "gpio2"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts index 5901c28e6696..a73317e1a824 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts @@ -430,18 +430,8 @@ /* MAX34417 @ 0x1e */ }; -&pon { - pwrkey { - status = "okay"; - }; - - resin { - compatible = "qcom,pm8941-resin"; - interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; - linux,code = ; - }; +&pon_pwrkey { + status = "okay"; }; &qupv3_id_0 { @@ -476,6 +466,12 @@ firmware-name = "qcom/sm8150/microsoft/slpi.mdt"; }; +&pon_resin { + status = "okay"; + + linux,code = ; +}; + &tlmm { gpio-reserved-ranges = <126 4>; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 6012322a5984..d15fee495238 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -932,6 +932,9 @@ reg = <0 0x00880000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = ; @@ -946,6 +949,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_default>; interrupts = ; @@ -960,6 +966,9 @@ reg = <0 0x00884000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_default>; interrupts = ; @@ -974,6 +983,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi1_default>; interrupts = ; @@ -988,6 +1000,9 @@ reg = <0 0x00888000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = ; @@ -1002,6 +1017,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi2_default>; interrupts = ; @@ -1016,6 +1034,9 @@ reg = <0 0x0088c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c3_default>; interrupts = ; @@ -1030,6 +1051,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi3_default>; interrupts = ; @@ -1044,6 +1068,9 @@ reg = <0 0x00890000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_default>; interrupts = ; @@ -1058,6 +1085,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_default>; interrupts = ; @@ -1072,6 +1102,9 @@ reg = <0 0x00894000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_default>; interrupts = ; @@ -1086,6 +1119,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi5_default>; interrupts = ; @@ -1100,6 +1136,9 @@ reg = <0 0x00898000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = ; @@ -1114,6 +1153,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi6_default>; interrupts = ; @@ -1128,6 +1170,9 @@ reg = <0 0x0089c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = ; @@ -1142,6 +1187,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi7_default>; interrupts = ; @@ -1192,6 +1240,9 @@ reg = <0 0x00a80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = ; @@ -1206,6 +1257,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi8_default>; interrupts = ; @@ -1220,6 +1274,9 @@ reg = <0 0x00a84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_default>; interrupts = ; @@ -1234,6 +1291,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi9_default>; interrupts = ; @@ -1248,6 +1308,9 @@ reg = <0 0x00a88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = ; @@ -1262,6 +1325,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi10_default>; interrupts = ; @@ -1276,6 +1342,9 @@ reg = <0 0x00a8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_default>; interrupts = ; @@ -1290,6 +1359,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi11_default>; interrupts = ; @@ -1313,6 +1385,9 @@ reg = <0 0x00a90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_default>; interrupts = ; @@ -1327,6 +1402,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi12_default>; interrupts = ; @@ -1341,6 +1419,9 @@ reg = <0 0x0094000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c16_default>; interrupts = ; @@ -1355,6 +1436,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi16_default>; interrupts = ; @@ -1406,6 +1490,9 @@ reg = <0 0x00c80000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c17_default>; interrupts = ; @@ -1420,6 +1507,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi17_default>; interrupts = ; @@ -1434,6 +1524,9 @@ reg = <0 0x00c84000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c18_default>; interrupts = ; @@ -1448,6 +1541,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi18_default>; interrupts = ; @@ -1462,6 +1558,9 @@ reg = <0 0x00c88000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c19_default>; interrupts = ; @@ -1476,6 +1575,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi19_default>; interrupts = ; @@ -1490,6 +1592,9 @@ reg = <0 0x00c8c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_default>; interrupts = ; @@ -1504,6 +1609,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi13_default>; interrupts = ; @@ -1518,6 +1626,9 @@ reg = <0 0x00c90000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_default>; interrupts = ; @@ -1532,6 +1643,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi14_default>; interrupts = ; @@ -1546,6 +1660,9 @@ reg = <0 0x00c94000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_default>; interrupts = ; @@ -1560,6 +1677,9 @@ reg-names = "se"; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_spi15_default>; interrupts = ; @@ -3556,9 +3676,9 @@ qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , - , - , - ; + , + , + ; rpmhcc: clock-controller { compatible = "qcom,sm8150-rpmh-clk"; @@ -3649,6 +3769,30 @@ #freq-domain-cells = <1>; }; + lmh_cluster1: lmh@18350800 { + compatible = "qcom,sm8150-lmh"; + reg = <0 0x18350800 0 0x400>; + interrupts = ; + cpus = <&CPU4>; + qcom,lmh-temp-arm-millicelsius = <60000>; + qcom,lmh-temp-low-millicelsius = <84500>; + qcom,lmh-temp-high-millicelsius = <85000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh_cluster0: lmh@18358800 { + compatible = "qcom,sm8150-lmh"; + reg = <0 0x18358800 0 0x400>; + interrupts = ; + cpus = <&CPU0>; + qcom,lmh-temp-arm-millicelsius = <60000>; + qcom,lmh-temp-low-millicelsius = <84500>; + qcom,lmh-temp-high-millicelsius = <85000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + wifi: wifi@18800000 { compatible = "qcom,wcn3990-wifi"; reg = <0 0x18800000 0 0x800000>; @@ -4265,7 +4409,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -4445,7 +4589,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 5617a46e5ccd..fdaf303ba047 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -98,6 +98,8 @@ capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -120,6 +122,8 @@ capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; next-level-cache = <&L2_100>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -139,6 +143,8 @@ capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; next-level-cache = <&L2_200>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -158,6 +164,8 @@ capacity-dmips-mhz = <448>; dynamic-power-coefficient = <205>; next-level-cache = <&L2_300>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -177,6 +185,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; next-level-cache = <&L2_400>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -196,6 +206,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; next-level-cache = <&L2_500>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -216,6 +228,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <379>; next-level-cache = <&L2_600>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -235,6 +249,8 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <444>; next-level-cache = <&L2_700>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; operating-points-v2 = <&cpu7_opp_table>; interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -281,6 +297,42 @@ }; }; }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <360>; + exit-latency-us = <531>; + min-residency-us = <3934>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <702>; + exit-latency-us = <1061>; + min-residency-us = <4488>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-llcc-off"; + arm,psci-suspend-param = <0x4100c244>; + entry-latency-us = <3264>; + exit-latency-us = <6562>; + min-residency-us = <9987>; + local-timer-stop; + }; + }; }; cpu0_opp_table: cpu0_opp_table { @@ -594,6 +646,59 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>; + }; }; reserved-memory { @@ -1740,8 +1845,8 @@ phys = <&pcie0_lane>; phy-names = "pciephy"; - perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -1801,7 +1906,7 @@ ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; + interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -1844,8 +1949,8 @@ phys = <&pcie1_lane>; phy-names = "pciephy"; - perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; @@ -1907,7 +2012,7 @@ ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; - interrupts = ; + interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -1950,8 +2055,8 @@ phys = <&pcie2_lane>; phy-names = "pciephy"; - perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; @@ -4320,7 +4425,7 @@ apr { compatible = "qcom,apr-v2"; qcom,glink-channels = "apr_audio_svc"; - qcom,apr-domain = ; + qcom,domain = ; #address-cells = <1>; #size-cells = <0>; @@ -4571,7 +4676,10 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; - + interrupts = , + , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; }; }; @@ -5172,7 +5280,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -5307,7 +5415,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 4b19744bcfb3..d242bab69c2e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1443,6 +1443,8 @@ interconnect-names = "memory", "config"; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; qcom,smem-state-names = "ipa-clock-enabled-valid", @@ -1820,7 +1822,7 @@ qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = , , - , ; + , ; rpmhcc: clock-controller { compatible = "qcom,sm8350-rpmh-clk"; @@ -3009,7 +3011,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3024,7 +3026,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3114,7 +3116,7 @@ }; }; - modem1-thermal-top { + modem1-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3129,7 +3131,7 @@ }; }; - modem2-thermal-top { + modem2-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3144,7 +3146,7 @@ }; }; - modem3-thermal-top { + modem3-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3159,7 +3161,7 @@ }; }; - modem4-thermal-top { + modem4-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3174,7 +3176,7 @@ }; }; - camera-thermal-top { + camera-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -3189,7 +3191,7 @@ }; }; - cam-thermal-bottom { + cam-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts new file mode 100644 index 000000000000..f0fcb1428449 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +/dts-v1/; + +#include +#include "sm8450.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8450 HDK"; + compatible = "qcom,sm8450-hdk", "qcom,sm8450"; + + aliases { + serial0 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + pm8350-rpmh-regulators { + compatible = "qcom,pm8350-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-s11-supply = <&vph_pwr>; + vdd-s12-supply = <&vph_pwr>; + + vdd-l1-l4-supply = <&vreg_s11b_0p95>; + vdd-l2-l7-supply = <&vreg_bob>; + vdd-l3-l5-supply = <&vreg_bob>; + vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>; + vdd-l8-supply = <&vreg_s2h_0p95>; + + vreg_s10b_1p8: smps10 { + regulator-name = "vreg_s10b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vreg_s11b_0p95: smps11 { + regulator-name = "vreg_s11b_0p95"; + regulator-min-microvolt = <966000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s12b_1p25: smps12 { + regulator-name = "vreg_s12b_1p25"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1400000>; + }; + + vreg_l1b_0p91: ldo1 { + regulator-name = "vreg_l1b_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = ; + }; + + vreg_l2b_3p07: ldo2 { + regulator-name = "vreg_l2b_3p07"; + regulator-min-microvolt = <3072000>; + regulator-max-microvolt = <3072000>; + regulator-initial-mode = ; + }; + + vreg_l3b_0p9: ldo3 { + regulator-name = "vreg_l3b_0p9"; + regulator-min-microvolt = <904000>; + regulator-max-microvolt = <904000>; + regulator-initial-mode = ; + }; + + vreg_l5b_0p88: ldo5 { + regulator-name = "vreg_l5b_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <888000>; + regulator-initial-mode = ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name = "vreg_l6b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + + vreg_l7b_2p5: ldo7 { + regulator-name = "vreg_l7b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name = "vreg_l9b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = ; + }; + }; + + pm8350c-rpmh-regulators { + compatible = "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id = "c"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + + vdd-l1-l12-supply = <&vreg_bob>; + vdd-l2-l8-supply = <&vreg_bob>; + vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>; + vdd-l6-l9-l11-supply = <&vreg_bob>; + vdd-l10-supply = <&vreg_s12b_1p25>; + + vdd-bob-supply = <&vph_pwr>; + + vreg_s1c_1p86: smps1 { + regulator-name = "vreg_s1c_1p86"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + }; + + vreg_s10c_1p05: smps10 { + regulator-name = "vreg_s10c_1p05"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_bob: bob { + regulator-name = "vreg_bob"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = ; + }; + + vreg_l1c_1p8: ldo1 { + regulator-name = "vreg_l1c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l3c_3p0: ldo3 { + regulator-name = "vreg_l3c_3p0"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3304000>; + regulator-initial-mode = ; + }; + + vreg_l4c_1p8: ldo4 { + regulator-name = "vreg_l4c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l5c_1p8: ldo5 { + regulator-name = "vreg_l5c_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + + vreg_l6c_1p8: ldo6 { + regulator-name = "vreg_l6c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l7c_3p0: ldo7 { + regulator-name = "vreg_l7c_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l8c_1p8: ldo8 { + regulator-name = "vreg_l8c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name = "vreg_l9c_2p96"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = ; + }; + + vreg_l12c_1p8: ldo12 { + regulator-name = "vreg_l12c_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1968000>; + regulator-initial-mode = ; + }; + + vreg_l13c_3p0: ldo13 { + regulator-name = "vreg_l13c_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = ; + }; + }; + + pm8450-rpmh-regulators { + compatible = "qcom,pm8450-rpmh-regulators"; + qcom,pmic-id = "h"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + vdd-l2-supply = <&vreg_bob>; + vdd-l3-supply = <&vreg_bob>; + vdd-l4-supply = <&vreg_bob>; + + vreg_s2h_0p95: smps2 { + regulator-name = "vreg_s2h_0p95"; + regulator-min-microvolt = <848000>; + regulator-max-microvolt = <1104000>; + }; + + vreg_s3h_0p5: smps3 { + regulator-name = "vreg_s3h_0p5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <500000>; + }; + + vreg_l2h_0p91: ldo2 { + regulator-name = "vreg_l2h_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + vreg_l3h_0p91: ldo3 { + regulator-name = "vreg_l3h_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = ; + }; + + }; + + pmr735a-rpmh-regulators { + compatible = "qcom,pmr735a-rpmh-regulators"; + qcom,pmic-id = "e"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + + vdd-l1-l2-supply = <&vreg_s2e_0p85>; + vdd-l3-supply = <&vreg_s1e_1p25>; + vdd-l4-supply = <&vreg_s1c_1p86>; + vdd-l5-l6-supply = <&vreg_s1c_1p86>; + vdd-l7-bob-supply = <&vreg_bob>; + + vreg_s1e_1p25: smps1 { + regulator-name = "vreg_s1e_1p25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1296000>; + }; + + vreg_s2e_0p85: smps2 { + regulator-name = "vreg_s2e_0p85"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + }; + + vreg_l1e_0p8: ldo1 { + regulator-name = "vreg_l1e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l2e_0p8: ldo2 { + regulator-name = "vreg_l2e_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name = "vreg_l3e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l4e_1p7: ldo4 { + regulator-name = "vreg_l4e_1p7"; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + }; + + vreg_l5e_0p88: ldo5 { + regulator-name = "vreg_l5e_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + }; + + vreg_l6e_1p2: ldo6 { + regulator-name = "vreg_l6e_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vreg_l7e_2p8: ldo7 { + regulator-name = "vreg_l7e_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <28 4>, <36 4>; +}; + +&uart7 { + status = "okay"; +}; + +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7b_2p5>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l9b_1p2>; + vccq-max-microamp = <1200000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + vdda-max-microamp = <173000>; + vdda-pll-max-microamp = <24900>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l5b_0p88>; + vdda18-supply = <&vreg_l1c_1p8>; + vdda33-supply = <&vreg_l2b_3p07>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p91>; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index b68ab247e6ae..9526632d4029 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -346,6 +346,26 @@ status = "okay"; }; +&remoteproc_adsp { + status = "okay"; + firmware-name = "qcom/sm8450/adsp.mbn"; +}; + +&remoteproc_cdsp { + status = "okay"; + firmware-name = "qcom/sm8450/cdsp.mbn"; +}; + +&remoteproc_mpss { + status = "okay"; + firmware-name = "qcom/sm8450/modem.mbn"; +}; + +&remoteproc_slpi { + status = "okay"; + firmware-name = "qcom/sm8450/slpi.mbn"; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 02b97e838c47..934e29b9e153 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -7,7 +7,9 @@ #include #include #include +#include #include +#include #include / { @@ -203,9 +205,9 @@ compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <274>; - exit-latency-us = <480>; - min-residency-us = <3934>; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; local-timer-stop; }; @@ -213,9 +215,9 @@ compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <327>; - exit-latency-us = <1502>; - min-residency-us = <4488>; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; local-timer-stop; }; }; @@ -224,10 +226,10 @@ CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; idle-state-name = "cluster-l3-off"; - arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <584>; - exit-latency-us = <2332>; - min-residency-us = <6118>; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; local-timer-stop; }; @@ -235,9 +237,9 @@ compatible = "domain-idle-state"; idle-state-name = "cluster-power-collapse"; arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <2893>; - exit-latency-us = <4023>; - min-residency-us = <9987>; + entry-latency-us = <2700>; + exit-latency-us = <3500>; + min-residency-us = <13959>; local-timer-stop; }; }; @@ -250,6 +252,18 @@ }; }; + clk_virt: interconnect@0 { + compatible = "qcom,sm8450-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect@1 { + compatible = "qcom,sm8450-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + memory@a0000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -315,7 +329,7 @@ CLUSTER_PD: cpu-cluster0 { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; }; }; @@ -460,6 +474,15 @@ no-map; }; + rmtfs_mem: memory@9fd00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x9fd00000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + global_sync_mem: memory@a6f00000 { reg = <0x0 0xa6f00000 0x0 0x100000>; no-map; @@ -540,6 +563,113 @@ }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + qcom,smem = <443>, <429>; + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + qcom,smem = <94>, <432>; + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-slpi { + compatible = "qcom,smp2p"; + qcom,smem = <481>, <430>; + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid = <0>; + qcom,remote-pid = <3>; + + smp2p_slpi_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_slpi_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -620,6 +750,54 @@ }; }; + config_noc: interconnect@1500000 { + compatible = "qcom,sm8450-config-noc"; + reg = <0 0x01500000 0 0x1c000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,sm8450-system-noc"; + reg = <0 0x01680000 0 0x1e200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,sm8450-pcie-anoc"; + reg = <0 0x016c0000 0 0xe280>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm8450-aggre1-noc"; + reg = <0 0x016e0000 0 0x1c080>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm8450-aggre2-noc"; + reg = <0 0x01700000 0 0x31080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; + }; + + mmss_noc: interconnect@1740000 { + compatible = "qcom,sm8450-mmss-noc"; + reg = <0 0x01740000 0 0x1f080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; @@ -672,6 +850,167 @@ }; }; + remoteproc_slpi: remoteproc@2400000 { + compatible = "qcom,sm8450-slpi-pas"; + reg = <0 0x02400000 0 0x4000>; + + interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8450_LCX>, + <&rpmhpd SM8450_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&slpi_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_slpi_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_SLPI + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "slpi"; + qcom,remote-pid = <3>; + }; + }; + + remoteproc_adsp: remoteproc@30000000 { + compatible = "qcom,sm8450-adsp-pas"; + reg = <0 0x030000000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8450_LCX>, + <&rpmhpd SM8450_LMX>; + power-domain-names = "lcx", "lmx"; + + memory-region = <&adsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "lpass"; + qcom,remote-pid = <2>; + }; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,sm8450-cdsp-pas"; + reg = <0 0x032300000 0 0x1400000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SM8450_CX>, + <&rpmhpd SM8450_MXC>; + power-domain-names = "cx", "mxc"; + + memory-region = <&cdsp_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "cdsp"; + qcom,remote-pid = <5>; + }; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sm8450-mpss-pas"; + reg = <0x0 0x04080000 0x0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd 0>, + <&rpmhpd 12>; + power-domain-names = "cx", "mss"; + + memory-region = <&mpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8450-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; @@ -682,6 +1021,25 @@ interrupt-controller; }; + aoss_qmp: power-controller@c300000 { + compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + ipcc: mailbox@ed18000 { + compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; + reg = <0 0x0ed18000 0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sm8450-tlmm"; reg = <0 0x0f100000 0 0x300000>; @@ -989,6 +1347,20 @@ #freq-domain-cells = <1>; }; + gem_noc: interconnect@19100000 { + compatible = "qcom,sm8450-gem-noc"; + reg = <0 0x19100000 0 0xbb800>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system-cache-controller@19200000 { + compatible = "qcom,sm8450-llcc"; + reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = ; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -1005,6 +1377,9 @@ iommus = <&apps_smmu 0xe0 0x0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; clock-names = "core_clk", "bus_aggr_clk", @@ -1104,6 +1479,20 @@ phy-names = "usb2-phy", "usb3-phy"; }; }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,sm8450-nsp-noc"; + reg = <0 0x320c0000 0 0x10000>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible = "qcom,sm8450-lpass-ag-noc"; + reg = <0 0x3c40000 0 0x17200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; }; timer { diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 5bc8065a7864..d000f6b131dc 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -75,4 +75,7 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb +dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb + +dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 2692cc64bff6..5ad6cd1864c1 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -359,11 +359,10 @@ clocks = <&x304_clk>; clock-names = "xin"; - assigned-clocks = <&versaclock6_bb 1>, - <&versaclock6_bb 2>, - <&versaclock6_bb 3>, - <&versaclock6_bb 4>; - assigned-clock-rates = <24000000>, <24000000>, <24000000>, <24576000>; + assigned-clocks = <&versaclock6_bb 1>, <&versaclock6_bb 2>, + <&versaclock6_bb 3>, <&versaclock6_bb 4>; + assigned-clock-rates = <24000000>, <24000000>, <24000000>, + <24576000>; OUT1 { idt,mode = ; diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 0d136809eb96..877d076ffcc9 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -77,7 +77,7 @@ }; &gpio6 { - usb_hub_reset { + usb-hub-reset-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_HIGH>; output-high; @@ -293,7 +293,6 @@ vqmmc-supply = <®_1p8v>; non-removable; cap-power-off-card; - pm-ignore-notify; keep-power-in-suspend; mmc-pwrseq = <&wlan_pwrseq>; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi b/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi new file mode 100644 index 000000000000..d45f072f8cdf --- /dev/null +++ b/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi @@ -0,0 +1,332 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Ideas on Board + * Copyright (C) 2021 Jacopo Mondi + * + * Device Tree Source (overlay) that describes GMSL camera connected to + * Fakra connectors for the Eagle V3M and Condor V3H (and compatible) boards. + * + * The following cameras are currently supported: RDACM20 and RDACM21. + * + * The board .dts file that include this has to select which cameras are in use + * by specifying the camera model with: + * + * #define GMSL_CAMERA_RDACM20 + * or + * #define GMSL_CAMERA_RDACM21 + * + * And which cameras are connected to the board by defining: + * for GMSL channel 0: + * #define GMSL_CAMERA_0 + * #define GMSL_CAMERA_1 + * #define GMSL_CAMERA_2 + * #define GMSL_CAMERA_3 + * + * for GMSL channel 1: + * #define GMSL_CAMERA_4 + * #define GMSL_CAMERA_5 + * #define GMSL_CAMERA_6 + * #define GMSL_CAMERA_7 + */ + +#include + +/* Validate the board file settings. */ +#if !defined(GMSL_CAMERA_RDACM20) && !defined(GMSL_CAMERA_RDACM21) +#error "Camera model should be defined by the board file" +#endif + +#if defined(GMSL_CAMERA_RDACM20) && defined(GMSL_CAMERA_RDACM21) +#error "A single camera model should be selected" +#endif + +#if !defined(GMSL_CAMERA_0) && !defined(GMSL_CAMERA_1) && \ + !defined(GMSL_CAMERA_2) && !defined(GMSL_CAMERA_3) && \ + !defined(GMSL_CAMERA_4) && !defined(GMSL_CAMERA_5) && \ + !defined(GMSL_CAMERA_6) && !defined(GMSL_CAMERA_7) +#error "At least one camera should be selected" +#endif + +/* Deduce from the enabled cameras which GMSL channels are active. */ +#if defined(GMSL_CAMERA_0) || defined(GMSL_CAMERA_1) || \ + defined(GMSL_CAMERA_2) || defined(GMSL_CAMERA_3) +#define GMSL_0 +#endif + +#if defined(GMSL_CAMERA_4) || defined(GMSL_CAMERA_5) || \ + defined(GMSL_CAMERA_6) || defined(GMSL_CAMERA_7) +#define GMSL_1 +#endif + +/* Deduce the camera model compatible string. */ +#if defined(GMSL_CAMERA_RDACM20) +#define GMSL_CAMERA_MODEL "imi,rdacm20" +#elif defined(GMSL_CAMERA_RDACM21) +#define GMSL_CAMERA_MODEL "imi,rdacm21" +#endif + +#ifdef GMSL_0 +&vin0 { + status = "okay"; +}; + +&vin1 { + status = "okay"; +}; + +&vin2 { + status = "okay"; +}; + +&vin3 { + status = "okay"; +}; + +&gmsl0 { + status = "okay"; + +#if defined(GMSL_CAMERA_RDACM21) + maxim,reverse-channel-microvolt = <100000>; +#endif + + ports { +#ifdef GMSL_CAMERA_0 + port@0 { + max9286_in0: endpoint { + remote-endpoint = <&fakra_con0>; + }; + }; +#endif + +#ifdef GMSL_CAMERA_1 + port@1 { + max9286_in1: endpoint{ + remote-endpoint = <&fakra_con1>; + }; + + }; +#endif + +#ifdef GMSL_CAMERA_2 + port@2 { + max9286_in2: endpoint { + remote-endpoint = <&fakra_con2>; + }; + + }; +#endif + +#ifdef GMSL_CAMERA_3 + port@3 { + max9286_in3: endpoint { + remote-endpoint = <&fakra_con3>; + }; + + }; +#endif + }; + + i2c-mux { +#ifdef GMSL_CAMERA_0 + i2c@0 { + status = "okay"; + + camera@51 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x51>, <0x61>; + + port { + fakra_con0: endpoint { + remote-endpoint = <&max9286_in0>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_1 + i2c@1 { + status = "okay"; + + camera@52 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x52>, <0x62>; + + port { + fakra_con1: endpoint { + remote-endpoint = <&max9286_in1>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_2 + i2c@2 { + status = "okay"; + + camera@53 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x53>, <0x63>; + + port { + fakra_con2: endpoint { + remote-endpoint = <&max9286_in2>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_3 + i2c@3 { + status = "okay"; + + camera@54 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x54>, <0x64>; + + port { + fakra_con3: endpoint { + remote-endpoint = <&max9286_in3>; + }; + }; + }; + }; +#endif + }; +}; +#endif /* ifdef GMSL_0 */ + +#ifdef GMSL_1 +&vin4 { + status = "okay"; +}; + +&vin5 { + status = "okay"; +}; + +&vin6 { + status = "okay"; +}; + +&vin7 { + status = "okay"; +}; + +&gmsl1 { + status = "okay"; + +#if defined(GMSL_CAMERA_RDACM21) + maxim,reverse-channel-microvolt = <100000>; +#endif + + ports { +#ifdef GMSL_CAMERA_4 + port@0 { + max9286_in4: endpoint { + remote-endpoint = <&fakra_con4>; + }; + }; +#endif + +#ifdef GMSL_CAMERA_5 + port@1 { + max9286_in5: endpoint{ + remote-endpoint = <&fakra_con5>; + }; + + }; +#endif + +#ifdef GMSL_CAMERA_6 + port@2 { + max9286_in6: endpoint { + remote-endpoint = <&fakra_con6>; + }; + + }; +#endif + +#ifdef GMSL_CAMERA_7 + port@3 { + max9286_in7: endpoint { + remote-endpoint = <&fakra_con7>; + }; + + }; +#endif + }; + + i2c-mux { +#ifdef GMSL_CAMERA_4 + i2c@0 { + status = "okay"; + + camera@55 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x55>, <0x65>; + + port { + fakra_con4: endpoint { + remote-endpoint = <&max9286_in4>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_5 + i2c@1 { + status = "okay"; + + camera@56 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x56>, <0x66>; + + port { + fakra_con5: endpoint { + remote-endpoint = <&max9286_in5>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_6 + i2c@2 { + status = "okay"; + + camera@57 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x57>, <0x67>; + + port { + fakra_con6: endpoint { + remote-endpoint = <&max9286_in6>; + }; + }; + }; + }; +#endif + +#ifdef GMSL_CAMERA_7 + i2c@3 { + status = "okay"; + + camera@58 { + compatible = GMSL_CAMERA_MODEL; + reg = <0x58>, <0x68>; + + port { + fakra_con7: endpoint { + remote-endpoint = <&max9286_in7>; + }; + }; + }; + }; +#endif + }; +}; +#endif /* ifdef GMSL_1 */ diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi index 0c7e6f790590..935d06515aa6 100644 --- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi @@ -140,7 +140,7 @@ }; &gpio6 { - usb1-reset { + usb1-reset-hog { gpio-hog; gpios = <10 GPIO_ACTIVE_LOW>; output-low; diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi index 40c5e8d6d841..d66d17e34694 100644 --- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex-lvds.dtsi @@ -20,7 +20,7 @@ * When GP1_20 is LOW LVDS0 is connected to the LVDS connector * When GP1_20 is HIGH LVDS0 is connected to the LT8918L */ - lvds-connector-en-gpio { + lvds-connector-en-hog { gpio-hog; gpios = <20 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index eda6a840371a..12846125a4c9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1698,12 +1698,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a774a1", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -2010,7 +2010,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts b/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts index 3c0d59def8ee..89d708346ba8 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts +++ b/arch/arm64/boot/dts/renesas/r8a774b1-beacon-rzg2n-kit.dts @@ -11,7 +11,7 @@ / { model = "Beacon Embedded Works RZ/G2N Development Kit"; - compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1"; + compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1"; aliases { serial0 = &scif2; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 44f79fbd75dc..a4b406a346f9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1571,7 +1571,7 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; + compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ @@ -1883,7 +1883,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts index a7b27d09f6c2..c1812d1ef06a 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-ek874-idk-2121wr.dts @@ -68,7 +68,7 @@ * When GP0_17 is low LVDS[01] are connected to the LVDS connector * When GP0_17 is high LVDS[01] are connected to the LT8918L */ - lvds-connector-en-gpio{ + lvds-connector-en-hog { gpio-hog; gpios = <17 GPIO_ACTIVE_HIGH>; output-low; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index b8dcbbbf3db5..e123c8d1bab9 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1328,11 +1328,11 @@ */ compatible = "renesas,rcar_sound-r8a774c0", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, diff --git a/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts b/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts index 7b6649a3ded0..3e9ced3b2d33 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts +++ b/arch/arm64/boot/dts/renesas/r8a774e1-beacon-rzg2h-kit.dts @@ -11,7 +11,7 @@ / { model = "Beacon Embedded Works RZ/G2H Development Kit"; - compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1"; + compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1"; aliases { serial0 = &scif2; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index e6d8610730a8..989c1c00dcdc 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1784,7 +1784,7 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; + compatible = "renesas,rcar_sound-r8a774e1", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ @@ -2043,7 +2043,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 9265a5702792..4e87e8776a2b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2018,12 +2018,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -2277,7 +2277,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { @@ -2412,6 +2412,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a7795-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a7795", "renesas,rcar-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 26f7103d11da..6f79da8cc8c0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1890,12 +1890,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -2202,7 +2202,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { @@ -2284,6 +2284,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a7796-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a7796", "renesas,rcar-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index ac9b587f6fc5..68cbbb322acf 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1734,7 +1734,7 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; + compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ @@ -2046,7 +2046,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { @@ -2128,6 +2128,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a77961-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a77961", "renesas,rcar-dmac"; @@ -2722,6 +2734,33 @@ port@2 { reg = <2>; du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a77961-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index f898aad72b9d..9f858af8b762 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1753,12 +1753,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a77965", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -2012,7 +2012,7 @@ dma-names = "rx", "tx"; }; ssiu40: ssiu-32 { - dmas = <&audma0 0x71>, <&audma1 0x72>; + dmas = <&audma0 0x71>, <&audma1 0x72>; dma-names = "rx", "tx"; }; ssiu41: ssiu-33 { @@ -2147,6 +2147,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a77965-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a77965", "renesas,rcar-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index b579d3189a93..49d1a929aef7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -113,6 +113,20 @@ }; }; +&csi40 { + status = "okay"; + + ports { + port@0 { + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max9286_out0>; + }; + }; + }; +}; + &du { clocks = <&cpg CPG_MOD 724>, <&x1_clk>; clock-names = "du.0", "dclkin.0"; @@ -172,6 +186,89 @@ }; }; +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + gmsl0: gmsl-deserializer@48 { + compatible = "maxim,max9286"; + reg = <0x48>; + + maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; + enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + max9286_out0: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + status = "disabled"; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + status = "disabled"; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + status = "disabled"; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + status = "disabled"; + }; + }; + }; +}; + &lvds0 { status = "okay"; @@ -200,6 +297,11 @@ function = "i2c0"; }; + i2c3_pins: i2c3 { + groups = "i2c3_a"; + function = "i2c3"; + }; + qspi0_pins: qspi0 { groups = "qspi0_ctrl", "qspi0_data4"; function = "qspi0"; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 3d6d10c82f48..43ed033eb512 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -108,6 +108,34 @@ }; }; +&csi40 { + status = "okay"; + + ports { + port@0 { + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max9286_out0>; + }; + }; + }; +}; + +&csi41 { + status = "okay"; + + ports { + port@0 { + csi41_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max9286_out1>; + }; + }; + }; +}; + &du { clocks = <&cpg CPG_MOD 724>, <&x1_clk>; @@ -200,6 +228,164 @@ }; }; +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + gmsl0: gmsl-deserializer@48 { + compatible = "maxim,max9286"; + reg = <0x48>; + + maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; + enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + max9286_out0: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + status = "disabled"; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + status = "disabled"; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + status = "disabled"; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + status = "disabled"; + }; + }; + }; + + gmsl1: gmsl-deserializer@4a { + compatible = "maxim,max9286"; + reg = <0x4a>; + + maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; + enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + max9286_out1: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi41_in>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + status = "disabled"; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + status = "disabled"; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + status = "disabled"; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + status = "disabled"; + }; + }; + }; +}; + &lvds0 { status = "okay"; @@ -256,6 +442,11 @@ function = "i2c0"; }; + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + mmc_pins: mmc { groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; function = "mmc"; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 14caedd0c959..7e0f1aab2135 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1489,12 +1489,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -1682,6 +1682,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a77990-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a77990", "renesas,rcar-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index f29f3982a492..cac1f9467ffa 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1046,12 +1046,12 @@ * clkout : #clock-cells = <0>; <&rcar_sound>; * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; */ - compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3"; - reg = <0 0xec500000 0 0x1000>, /* SCU */ - <0 0xec5a0000 0 0x100>, /* ADG */ - <0 0xec540000 0 0x1000>, /* SSIU */ - <0 0xec541000 0 0x280>, /* SSI */ - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; clocks = <&cpg CPG_MOD 1005>, @@ -1132,6 +1132,18 @@ }; }; + mlp: mlp@ec520000 { + compatible = "renesas,r8a77995-mlp", + "renesas,rcar-gen3-mlp"; + reg = <0 0xec520000 0 0x800>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 802>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 802>; + status = "disabled"; + }; + audma0: dma-controller@ec700000 { compatible = "renesas,dmac-r8a77995", "renesas,rcar-dmac"; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi index f791c76f1bcf..e06b8eda85e1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-csi-dsi.dtsi @@ -5,6 +5,63 @@ * Copyright (C) 2021 Glider bv */ +&csi40 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max96712_out0>; + }; + }; + }; +}; + +&csi42 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi42_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max96712_out1>; + }; + }; + }; +}; + +&csi43 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csi43_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max96712_out2>; + }; + }; + }; +}; + &i2c0 { pca9654_a: gpio@21 { compatible = "onnn,pca9654"; @@ -34,3 +91,175 @@ pagesize = <8>; }; }; + +&i2c1 { + gmsl0: gmsl-deserializer@49 { + compatible = "maxim,max96712"; + reg = <0x49>; + enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96712_out0: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + }; + + gmsl1: gmsl-deserializer@4b { + compatible = "maxim,max96712"; + reg = <0x4b>; + enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96712_out1: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + lane-polarities = <0 0 0 0 1>; + remote-endpoint = <&csi42_in>; + }; + }; + }; + }; + + gmsl2: gmsl-deserializer@6b { + compatible = "maxim,max96712"; + reg = <0x6b>; + enable-gpios = <&pca9654_c 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@4 { + reg = <4>; + max96712_out2: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + lane-polarities = <0 0 0 0 1>; + remote-endpoint = <&csi43_in>; + }; + }; + }; + }; +}; + +&isp0 { + status = "okay"; +}; + +&isp2 { + status = "okay"; +}; + +&isp3 { + status = "okay"; +}; + +&vin00 { + status = "okay"; +}; + +&vin01 { + status = "okay"; +}; + +&vin02 { + status = "okay"; +}; + +&vin03 { + status = "okay"; +}; + +&vin04 { + status = "okay"; +}; + +&vin05 { + status = "okay"; +}; + +&vin06 { + status = "okay"; +}; + +&vin07 { + status = "okay"; +}; + +&vin16 { + status = "okay"; +}; + +&vin17 { + status = "okay"; +}; + +&vin18 { + status = "okay"; +}; + +&vin19 { + status = "okay"; +}; + +&vin20 { + status = "okay"; +}; + +&vin21 { + status = "okay"; +}; + +&vin22 { + status = "okay"; +}; + +&vin23 { + status = "okay"; +}; + +&vin24 { + status = "okay"; +}; + +&vin25 { + status = "okay"; +}; + +&vin26 { + status = "okay"; +}; + +&vin27 { + status = "okay"; +}; + +&vin28 { + status = "okay"; +}; + +&vin29 { + status = "okay"; +}; + +&vin30 { + status = "okay"; +}; + +&vin31 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 1e7ed12ebc87..c4be288b1912 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -102,7 +102,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 916>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 916>; + resets = <&cpg 916>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 0 28>; @@ -116,7 +116,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 915>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 915>; + resets = <&cpg 915>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 32 31>; @@ -130,7 +130,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 915>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 915>; + resets = <&cpg 915>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 64 25>; @@ -144,7 +144,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 916>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 916>; + resets = <&cpg 916>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 96 17>; @@ -158,7 +158,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 917>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 917>; + resets = <&cpg 917>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 128 27>; @@ -172,7 +172,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 917>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 917>; + resets = <&cpg 917>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 160 21>; @@ -186,7 +186,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; + resets = <&cpg 918>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 192 21>; @@ -200,7 +200,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; + resets = <&cpg 918>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 224 21>; @@ -214,7 +214,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; + resets = <&cpg 918>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 256 21>; @@ -228,7 +228,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 918>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; - resets = <&cpg 918>; + resets = <&cpg 918>; gpio-controller; #gpio-cells = <2>; gpio-ranges = <&pfc 0 288 21>; @@ -340,6 +340,21 @@ #thermal-sensor-cells = <1>; }; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a779a0", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + ; + clocks = <&cpg CPG_CORE R8A779A0_CLK_CP>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + }; + tmu0: timer@e61e0000 { compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; reg = <0 0xe61e0000 0 0x30>; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 156586532c84..6e07c54148e7 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -31,6 +31,34 @@ clock-frequency = <32768>; }; -&scif3 { +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif3_pins: scif3 { + groups = "scif3_data", "scif3_ctrl"; + function = "scif3"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rwdt { + timeout-sec = <60>; status = "okay"; }; + +&scif3 { + pinctrl-0 = <&scif3_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index eda597766eaf..f4e549867371 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -59,6 +59,22 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a779f0-wdt", + "renesas,rcar-gen4-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 907>; + status = "disabled"; + }; + + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a779f0"; + reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, + <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779f0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; @@ -94,6 +110,76 @@ status = "disabled"; }; + dmac0: dma-controller@e7350000 { + compatible = "renesas,dmac-r8a779f0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7350000 0 0x1000>, + <0 0xe7300000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 709>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 709>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac1: dma-controller@e7351000 { + compatible = "renesas,dmac-r8a779f0", + "renesas,rcar-gen4-dmac"; + reg = <0 0xe7351000 0 0x1000>, + <0 0xe7310000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", + "ch5", "ch6", "ch7", "ch8", "ch9", + "ch10", "ch11", "ch12", "ch13", + "ch14", "ch15"; + clocks = <&cpg CPG_MOD 710>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 710>; + #dma-cells = <1>; + dma-channels = <16>; + }; + gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi new file mode 100644 index 000000000000..1d57df706939 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c1.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC R9A07G044C1 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044c1", "renesas,r9a07g044"; + + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + }; + + timer { + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; + +&soc { + /delete-node/ ssi@1004a800; + /delete-node/ serial@1004c800; + /delete-node/ adc@10059000; + /delete-node/ ethernet@11c30000; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts new file mode 100644 index 000000000000..5a5cea82a5d9 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC EVK board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044c2.dtsi" +#include "rzg2lc-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g044c2"; + compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; +}; + +&ehci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ehci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&hsusb { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c3 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ohci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ohci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&phyrst { + status = "disabled"; +}; + +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ssi0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi new file mode 100644 index 000000000000..7bb8917fe421 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC R9A07G044C2 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g044.dtsi" + +/ { + compatible = "renesas,r9a07g044c2", "renesas,r9a07g044"; +}; + +&soc { + /delete-node/ ssi@1004a800; + /delete-node/ serial@1004c800; + /delete-node/ adc@10059000; + /delete-node/ ethernet@11c30000; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts index 247b0b3f1b58..bc2af6c92ccd 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -8,6 +8,8 @@ /dts-v1/; #include "r9a07g044l2.dtsi" #include "rzg2l-smarc-som.dtsi" +#include "rzg2l-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" #include "rzg2l-smarc.dtsi" / { diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi new file mode 100644 index 000000000000..5d39e765c291 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2L SoC + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a07g054"; + #address-cells = <2>; + #size-cells = <2>; + + audio_clk1: audio_clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + audio_clk2: audio_clk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + #cooling-cells = <2>; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ssi0: ssi@10049c00 { + reg = <0 0x10049c00 0 0x400>; + #sound-dai-cells = <0>; + /* place holder */ + }; + + spi1: spi@1004b000 { + reg = <0 0x1004b000 0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a07g054", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + + sci0: serial@1004d000 { + compatible = "renesas,r9a07g054-sci", "renesas,sci"; + reg = <0 0x1004d000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCI0_RST>; + status = "disabled"; + }; + + sci1: serial@1004d400 { + compatible = "renesas,r9a07g054-sci", "renesas,sci"; + reg = <0 0x1004d400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_SCI1_RST>; + status = "disabled"; + }; + + canfd: can@10050000 { + reg = <0 0x10050000 0 0x8000>; + /* place holder */ + }; + + i2c0: i2c@10058000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058000 0 0x400>; + /* place holder */ + }; + + i2c1: i2c@10058400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058400 0 0x400>; + /* place holder */ + }; + + i2c3: i2c@10058c00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058c00 0 0x400>; + /* place holder */ + }; + + adc: adc@10059000 { + reg = <0 0x10059000 0 0x400>; + /* place holder */ + }; + + sbc: spi@10060000 { + reg = <0 0x10060000 0 0x10000>, + <0 0x20000000 0 0x10000000>, + <0 0x10070000 0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g054-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g054-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g054-pinctrl", + "renesas,r9a07g044-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 392>; + clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_GPIO_RSTN>, + <&cpg R9A07G054_GPIO_PORT_RESETN>, + <&cpg R9A07G054_GPIO_SPARE_RESETN>; + }; + + dmac: dma-controller@11820000 { + compatible = "renesas,r9a07g054-dmac", + "renesas,rz-dmac"; + reg = <0 0x11820000 0 0x10000>, + <0 0x11830000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>, + <&cpg CPG_MOD R9A07G054_DMAC_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_DMAC_ARESETN>, + <&cpg R9A07G054_DMAC_RST_ASYNC>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + gpu: gpu@11840000 { + reg = <0x0 0x11840000 0x0 0x10000>; + /* place holder */ + }; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = ; + }; + + sdhi0: mmc@11c00000 { + reg = <0x0 0x11c00000 0 0x10000>; + /* place holder */ + }; + + sdhi1: mmc@11c10000 { + reg = <0x0 0x11c10000 0 0x10000>; + /* place holder */ + }; + + eth0: ethernet@11c20000 { + compatible = "renesas,r9a07g054-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c20000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>, + <&cpg CPG_CORE R9A07G054_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G054_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c30000 { + compatible = "renesas,r9a07g054-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>, + <&cpg CPG_CORE R9A07G054_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G054_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + phyrst: usbphy-ctrl@11c40000 { + reg = <0 0x11c40000 0 0x10000>; + /* place holder */ + }; + + ohci0: usb@11c50000 { + reg = <0 0x11c50000 0 0x100>; + /* place holder */ + }; + + ohci1: usb@11c70000 { + reg = <0 0x11c70000 0 0x100>; + /* place holder */ + }; + + ehci0: usb@11c50100 { + reg = <0 0x11c50100 0 0x100>; + /* place holder */ + }; + + ehci1: usb@11c70100 { + reg = <0 0x11c70100 0 0x100>; + /* place holder */ + }; + + usb2_phy0: usb-phy@11c50200 { + reg = <0 0x11c50200 0 0x700>; + /* place holder */ + }; + + usb2_phy1: usb-phy@11c70200 { + reg = <0 0x11c70200 0 0x700>; + /* place holder */ + }; + + hsusb: usb@11c60000 { + reg = <0 0x11c60000 0 0x10000>; + /* place holder */ + }; + + wdt0: watchdog@12800800 { + reg = <0 0x12800800 0 0x400>; + /* place holder */ + }; + + wdt1: watchdog@12800c00 { + reg = <0 0x12800C00 0 0x400>; + /* place holder */ + }; + + wdt2: watchdog@12800400 { + reg = <0 0x12800400 0 0x400>; + /* place holder */ + }; + + ostm0: timer@12801000 { + reg = <0x0 0x12801000 0x0 0x400>; + /* place holder */ + }; + + ostm1: timer@12801400 { + reg = <0x0 0x12801400 0x0 0x400>; + /* place holder */ + }; + + ostm2: timer@12801800 { + reg = <0x0 0x12801800 0x0 0x400>; + /* place holder */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi new file mode 100644 index 000000000000..c448cc6634c1 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l1.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2L R9A07G054L1 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g054.dtsi" + +/ { + compatible = "renesas,r9a07g054l1", "renesas,r9a07g054"; + + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + }; + + timer { + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts new file mode 100644 index 000000000000..fc334b4c2aa4 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2L SMARC EVK board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g054l2.dtsi" +#include "rzg2l-smarc-som.dtsi" +#include "rzg2l-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" +#include "rzg2l-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g054l2"; + compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054"; +}; + +&pinctrl { + /delete-node/ can0-stb-hog; + /delete-node/ can1-stb-hog; + /delete-node/ gpio-sd0-pwr-en-hog; + /delete-node/ sd0-dev-sel-hog; + /delete-node/ sd1-pwr-en-hog; +}; diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi new file mode 100644 index 000000000000..4d5914bc95d3 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2L R9A07G054L2 SoC specific parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g054.dtsi" + +/ { + compatible = "renesas,r9a07g054l2", "renesas,r9a07g054"; +}; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi new file mode 100644 index 000000000000..588117aafaca --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/{G2L,G2LC,V2L} SMARC EVK common parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/* + * SSI-WM8978 + * + * This command is required when Playback/Capture + * + * amixer cset name='Left Input Mixer L2 Switch' on + * amixer cset name='Right Input Mixer R2 Switch' on + * amixer cset name='Headphone Playback Volume' 100 + * amixer cset name='PCM Volume' 100% + * amixer cset name='Input PGA Volume' 25 + * + */ + +/ { + aliases { + serial0 = &scif0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c3 = &i2c3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + audio_mclock: audio_mclock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + snd_rzg2l: sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&cpu_dai>; + simple-audio-card,frame-master = <&cpu_dai>; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,widgets = "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "L2", "Mic Bias", + "R2", "Mic Bias", + "Mic Bias", "Microphone Jack"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&ssi0>; + }; + + codec_dai: simple-audio-card,codec { + clocks = <&audio_mclock>; + sound-dai = <&wm8978>; + }; + }; + + usb0_vbus_otg: regulator-usb0-vbus-otg { + compatible = "regulator-fixed"; + + regulator-name = "USB0_VBUS_OTG"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1>, <1800000 0>; + }; +}; + +&audio_clk1{ + clock-frequency = <11289600>; +}; + +&audio_clk2{ + clock-frequency = <12288000>; +}; + +&canfd { + pinctrl-0 = <&can0_pins &can1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; + + channel1 { + status = "okay"; + }; +}; + +&ehci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&hsusb { + dr_mode = "otg"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + +&ohci0 { + dr_mode = "otg"; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&phyrst { + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ssi0 { + pinctrl-0 = <&ssi0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&usb0_vbus_otg>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi new file mode 100644 index 000000000000..9085d8c76ce1 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/{G2L,V2L} SMARC pincontrol parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include + +&pinctrl { + pinctrl-0 = <&sound_clk_pins>; + pinctrl-names = "default"; + + can0_pins: can0 { + pinmux = , /* TX */ + ; /* RX */ + }; + + /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */ + can0-stb-hog { + gpio-hog; + gpios = ; + output-low; + line-name = "can0_stb"; + }; + + can1_pins: can1 { + pinmux = , /* TX */ + ; /* RX */ + }; + + /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ + can1-stb-hog { + gpio-hog; + gpios = ; + output-low; + line-name = "can1_stb"; + }; + + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c3_pins: i2c3 { + pinmux = , /* SDA */ + ; /* SCL */ + }; + + scif0_pins: scif0 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + scif2_pins: scif2 { + pinmux = , /* TxD */ + , /* RxD */ + , /* CTS# */ + ; /* RTS# */ + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + sd1_mux { + pinmux = ; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1_uhs { + sd1_data_uhs { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + sd1_ctrl_uhs { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + sd1_mux_uhs { + pinmux = ; /* SD1_CD */ + }; + }; + + sound_clk_pins: sound_clk { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; + + spi1_pins: spi1 { + pinmux = , /* CK */ + , /* MOSI */ + , /* MISO */ + ; /* SSL */ + }; + + ssi0_pins: ssi0 { + pinmux = , /* BCK */ + , /* RCK */ + , /* TXD */ + ; /* RXD */ + }; + + usb0_pins: usb0 { + pinmux = , /* VBUS */ + , /* OVC */ + ; /* OTG_ID */ + }; + + usb1_pins: usb1 { + pinmux = , /* VBUS */ + ; /* OVC */ + }; +}; + diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 9112e79079a1..aeacd22e9eb0 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2L SMARC SOM common parts + * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts * * Copyright (C) 2021 Renesas Electronics Corp. */ diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 6f2a8bdfa225..33ddfd18bd56 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the RZ/G2L SMARC EVK common parts + * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts * * Copyright (C) 2021 Renesas Electronics Corp. */ @@ -8,291 +8,13 @@ #include #include -/* - * SSI-WM8978 - * - * This command is required when Playback/Capture - * - * amixer cset name='Left Input Mixer L2 Switch' on - * amixer cset name='Right Input Mixer R2 Switch' on - * amixer cset name='Headphone Playback Volume' 100 - * amixer cset name='PCM Volume' 100% - * amixer cset name='Input PGA Volume' 25 - * - */ - /* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ #define PMOD1_SER0 1 / { aliases { - serial0 = &scif0; serial1 = &scif2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c3 = &i2c3; }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - audio_mclock: audio_mclock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - - snd_rzg2l: sound { - compatible = "simple-audio-card"; - simple-audio-card,format = "i2s"; - simple-audio-card,bitclock-master = <&cpu_dai>; - simple-audio-card,frame-master = <&cpu_dai>; - simple-audio-card,mclk-fs = <256>; - - simple-audio-card,widgets = "Microphone", "Microphone Jack"; - simple-audio-card,routing = - "L2", "Mic Bias", - "R2", "Mic Bias", - "Mic Bias", "Microphone Jack"; - - cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssi0>; - }; - - codec_dai: simple-audio-card,codec { - clocks = <&audio_mclock>; - sound-dai = <&wm8978>; - }; - }; - - usb0_vbus_otg: regulator-usb0-vbus-otg { - compatible = "regulator-fixed"; - - regulator-name = "USB0_VBUS_OTG"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - vccq_sdhi1: regulator-vccq-sdhi1 { - compatible = "regulator-gpio"; - regulator-name = "SDHI1 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; - gpios-states = <1>; - states = <3300000 1>, <1800000 0>; - }; -}; - -&audio_clk1{ - clock-frequency = <11289600>; -}; - -&audio_clk2{ - clock-frequency = <12288000>; -}; - -&canfd { - pinctrl-0 = <&can0_pins &can1_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; - - channel1 { - status = "okay"; - }; -}; - -&ehci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&hsusb { - dr_mode = "otg"; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - - status = "okay"; - - wm8978: codec@1a { - compatible = "wlf,wm8978"; - #sound-dai-cells = <0>; - reg = <0x1a>; - }; -}; - -&ohci0 { - dr_mode = "otg"; - status = "okay"; -}; - -&ohci1 { - status = "okay"; -}; - -&phyrst { - status = "okay"; -}; - -&pinctrl { - pinctrl-0 = <&sound_clk_pins>; - pinctrl-names = "default"; - - can0_pins: can0 { - pinmux = , /* TX */ - ; /* RX */ - }; - - /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */ - can0-stb { - gpio-hog; - gpios = ; - output-low; - line-name = "can0_stb"; - }; - - can1_pins: can1 { - pinmux = , /* TX */ - ; /* RX */ - }; - - /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ - can1-stb { - gpio-hog; - gpios = ; - output-low; - line-name = "can1_stb"; - }; - - i2c0_pins: i2c0 { - pins = "RIIC0_SDA", "RIIC0_SCL"; - input-enable; - }; - - i2c1_pins: i2c1 { - pins = "RIIC1_SDA", "RIIC1_SCL"; - input-enable; - }; - - i2c3_pins: i2c3 { - pinmux = , /* SDA */ - ; /* SCL */ - }; - - scif0_pins: scif0 { - pinmux = , /* TxD */ - ; /* RxD */ - }; - - scif2_pins: scif2 { - pinmux = , /* TxD */ - , /* RxD */ - , /* CTS# */ - ; /* RTS# */ - }; - - sd1-pwr-en-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "sd1_pwr_en"; - }; - - sdhi1_pins: sd1 { - sd1_data { - pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; - power-source = <3300>; - }; - - sd1_ctrl { - pins = "SD1_CLK", "SD1_CMD"; - power-source = <3300>; - }; - - sd1_mux { - pinmux = ; /* SD1_CD */ - }; - }; - - sdhi1_pins_uhs: sd1_uhs { - sd1_data_uhs { - pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; - power-source = <1800>; - }; - - sd1_ctrl_uhs { - pins = "SD1_CLK", "SD1_CMD"; - power-source = <1800>; - }; - - sd1_mux_uhs { - pinmux = ; /* SD1_CD */ - }; - }; - - sound_clk_pins: sound_clk { - pins = "AUDIO_CLK1", "AUDIO_CLK2"; - input-enable; - }; - - spi1_pins: spi1 { - pinmux = , /* CK */ - , /* MOSI */ - , /* MISO */ - ; /* SSL */ - }; - - ssi0_pins: ssi0 { - pinmux = , /* BCK */ - , /* RCK */ - , /* TXD */ - ; /* RXD */ - }; - - usb0_pins: usb0 { - pinmux = , /* VBUS */ - , /* OVC */ - ; /* OTG_ID */ - }; - - usb1_pins: usb1 { - pinmux = , /* VBUS */ - ; /* OVC */ - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>; - pinctrl-names = "default"; - status = "okay"; }; /* @@ -311,45 +33,3 @@ status = "okay"; }; #endif - -&sdhi1 { - pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins_uhs>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <&vccq_sdhi1>; - bus-width = <4>; - sd-uhs-sdr50; - sd-uhs-sdr104; - status = "okay"; -}; - -&spi1 { - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&ssi0 { - pinctrl-0 = <&ssi0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&usb2_phy0 { - pinctrl-0 = <&usb0_pins>; - pinctrl-names = "default"; - - vbus-supply = <&usb0_vbus_otg>; - status = "okay"; -}; - -&usb2_phy1 { - pinctrl-0 = <&usb1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi new file mode 100644 index 000000000000..37ff2091582e --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC pincontrol parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include + +&pinctrl { + pinctrl-0 = <&sound_clk_pins>; + pinctrl-names = "default"; + + scif0_pins: scif0 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + +#if SW_SCIF_CAN + /* SW8 should be at position 2->1 */ + can1_pins: can1 { + pinmux = , /* TxD */ + ; /* RxD */ + }; +#endif + + scif1_pins: scif1 { + pinmux = , /* TxD */ + , /* RxD */ + , /* CTS# */ + ; /* RTS# */ + }; + +#if SW_RSPI_CAN + /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ + can1-stb-hog { + gpio-hog; + gpios = ; + output-low; + line-name = "can1_stb"; + }; + + can1_pins: can1 { + pinmux = , /* TxD */ + ; /* RxD */ + }; +#endif + + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + sd1_mux { + pinmux = ; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1_uhs { + sd1_data_uhs { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + sd1_ctrl_uhs { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + sd1_mux_uhs { + pinmux = ; /* SD1_CD */ + }; + }; + + sound_clk_pins: sound_clk { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; +}; + diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi new file mode 100644 index 000000000000..88a7938017aa --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC SOM common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include + +/ { + aliases { + ethernet0 = ð0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <3300000 1>, <1800000 0>; + regulator-boot-on; + gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; +}; + +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux = , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TXC */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + ; /* ET0_RXD3 */ + }; + + gpio-sd0-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "gpio_sd0_pwr_en"; + }; + + /* + * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] + * The below switch logic can be used to select the device between + * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. + * SW1[2] should be at OFF position to enable 64 GB eMMC + * SW1[2] should be at position ON to enable uSD card CN3 + */ + gpio-sd0-dev-sel-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "gpio_sd0_dev_sel"; + }; + + sdhi0_emmc_pins: sd0emmc { + sd0_emmc_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0_emmc_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_emmc_rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; + + sdhi0_pins: sd0 { + sd0_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + sd0_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + sd0_mux { + pinmux = ; /* SD0_CD */ + }; + }; + + sdhi0_pins_uhs: sd0_uhs { + sd0_data_uhs { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + sd0_ctrl_uhs { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_mux_uhs { + pinmux = ; /* SD0_CD */ + }; + }; +}; + +#if (!SW_SD0_DEV_SEL) +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif + +#if SW_SD0_DEV_SEL +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; +#endif + +&wdt0 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt1 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt2 { + status = "okay"; + timeout-sec = <60>; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi new file mode 100644 index 000000000000..df7631fe5fac --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC EVK parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/* + * DIP-Switch SW1 setting on SoM + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) + * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) + * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) + * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) + * Please change below macros according to SW1 setting + */ + +#define SW_SD0_DEV_SEL 1 + +#define SW_SCIF_CAN 0 +#if (SW_SCIF_CAN) +/* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ +#define SW_RSPI_CAN 0 +#else +/* Please set SW_RSPI_CAN. Default value is 1 */ +#define SW_RSPI_CAN 1 +#endif + +#if (SW_SCIF_CAN & SW_RSPI_CAN) +#error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" +#endif + +#include "rzg2lc-smarc-som.dtsi" +#include "rzg2lc-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" + +/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/ { + aliases { + serial1 = &scif1; + }; +}; + +#if (SW_SCIF_CAN || SW_RSPI_CAN) +&canfd { + pinctrl-0 = <&can1_pins>; + /delete-node/ channel@0; +}; +#else +&canfd { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif + +/* + * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board + * SW1 should be at position 2->3 so that SER0_CTS# line is activated + * SW2 should be at position 2->3 so that SER0_TX line is activated + * SW3 should be at position 2->3 so that SER0_RX line is activated + * SW4 should be at position 2->3 so that SER0_RTS# line is activated + */ +#if (!SW_SCIF_CAN && PMOD1_SER0) +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; +#endif diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 61bd4df09df0..ae532cd21708 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -26,6 +26,38 @@ select-gpios = <&gpio_exp_75 13 GPIO_ACTIVE_HIGH>; }; + hdmi1-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con: endpoint { + remote-endpoint = <&adv7513_out>; + }; + }; + }; + + accel_3v3: regulator-acc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "accel-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + hdmi_1v8: regulator-hdmi-1v8 { + compatible = "regulator-fixed"; + regulator-name = "hdmi-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + hdmi_3v3: regulator-hdmi-3v3 { + compatible = "regulator-fixed"; + regulator-name = "hdmi-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + snd_3p3v: regulator-snd_3p3v { compatible = "regulator-fixed"; regulator-name = "snd-3.3v"; @@ -65,6 +97,10 @@ status = "okay"; }; +&du_out_rgb { + remote-endpoint = <&adv7513_in>; +}; + &ehci0 { dr_mode = "otg"; status = "okay"; @@ -91,12 +127,72 @@ reg = <0x71>; reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + /* HDMIoSDA, HDMIoSCL */ + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + + hdmi@3d { + compatible = "adi,adv7513"; + reg = <0x3d>; + + pinctrl-0 = <&hdmi1_pins>; + pinctrl-names = "default"; + + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + clocks = <&cs2000>; + clock-names = "cec"; + + pd-gpios = <&gpio_exp_75 5 GPIO_ACTIVE_LOW>; + + avdd-supply = <&hdmi_1v8>; + dvdd-supply = <&hdmi_1v8>; + pvdd-supply = <&hdmi_1v8>; + dvdd-3v-supply = <&hdmi_3v3>; + bgvdd-supply = <&hdmi_1v8>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7513_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + adv7513_out: endpoint { + remote-endpoint = <&hdmi1_con>; + }; + }; + }; + }; + }; + /* Audio_SDA, Audio_SCL */ i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; + accelerometer@1d { + compatible = "st,lsm9ds0-imu"; + reg = <0x1d>; + + vdd-supply = <&accel_3v3>; + vddio-supply = <&accel_3v3>; + }; + pcm3168a: audio-codec@44 { #sound-dai-cells = <0>; compatible = "ti,pcm3168a"; @@ -131,6 +227,14 @@ }; }; }; + + gyroscope@6b { + compatible = "st,lsm9ds0-gyro"; + reg = <0x6b>; + + vdd-supply = <&accel_3v3>; + vddio-supply = <&accel_3v3>; + }; }; }; @@ -264,6 +368,19 @@ function = "can1"; }; + hdmi1_pins: hdmi1 { + adv7513-interrupt { + pins = "GP_2_14"; + bias-pull-up; + }; + + du { + groups = "du_rgb888", "du_sync", "du_clk_out_0", + "du_disp"; + function = "du"; + }; + }; + hscif0_pins: hscif0 { groups = "hscif0_data", "hscif0_ctrl"; function = "hscif0"; @@ -297,17 +414,14 @@ &sound_pcm_pins>; ports { - /* rsnd_port0/1 are on salvator-common */ + /* rsnd_port0/1 are defined in ulcb.dtsi */ rsnd_port2: port@2 { reg = <2>; rsnd_for_pcm3168a_play: endpoint { remote-endpoint = <&pcm3168a_endpoint_p>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_pcm3168a_play>; - frame-master = <&rsnd_for_pcm3168a_play>; + bitclock-master; + frame-master; dai-tdm-slot-num = <8>; - playback = <&ssi3>; }; }; @@ -315,12 +429,9 @@ reg = <3>; rsnd_for_pcm3168a_capture: endpoint { remote-endpoint = <&pcm3168a_endpoint_c>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_pcm3168a_capture>; - frame-master = <&rsnd_for_pcm3168a_capture>; + bitclock-master; + frame-master; dai-tdm-slot-num = <6>; - capture = <&ssi4>; }; }; @@ -360,10 +471,10 @@ }; &sound_card { - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ - &rsnd_port2 /* pcm3168a playback */ - &rsnd_port3 /* pcm3168a capture */ + links = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ + &rsnd_port2 /* pcm3168a playback */ + &rsnd_port3 /* pcm3168a capture */ >; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index a7e93df4ced8..b4bdb2d7e4ba 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -95,11 +95,11 @@ }; sound_card: sound { - compatible = "audio-graph-card"; + compatible = "audio-graph-card2"; label = "rcar-sound"; - dais = <&rsnd_port0 /* ak4613 */ - &rsnd_port1 /* HDMI0 */ + links = <&rsnd_port0 /* ak4613 */ + &rsnd_port1 /* HDMI0 */ >; }; @@ -408,11 +408,8 @@ reg = <0>; rsnd_for_ak4613: endpoint { remote-endpoint = <&ak4613_endpoint>; - - dai-format = "left_j"; - bitclock-master = <&rsnd_for_ak4613>; - frame-master = <&rsnd_for_ak4613>; - + bitclock-master; + frame-master; playback = <&ssi0>, <&src0>, <&dvc0>; capture = <&ssi1>, <&src1>, <&dvc1>; }; @@ -421,11 +418,8 @@ reg = <1>; rsnd_for_hdmi: endpoint { remote-endpoint = <&dw_hdmi0_snd_in>; - - dai-format = "i2s"; - bitclock-master = <&rsnd_for_hdmi>; - frame-master = <&rsnd_for_hdmi>; - + bitclock-master; + frame-master; playback = <&ssi2>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 479906f3ad7b..4ae9f35434b8 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -56,5 +56,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts index de2d3e88e27f..40bf808642b9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328-a1.dts +++ b/arch/arm64/boot/dts/rockchip/rk3328-a1.dts @@ -160,6 +160,7 @@ pinctrl-0 = <&pmic_int_l>; rockchip,system-power-controller; wakeup-source; + #clock-cells = <0>; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index c4dd2a6b4836..c654b6b02f3f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -245,12 +245,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <430000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; }; }; @@ -298,6 +298,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &hdmi { ddc-i2c-bus = <&i2c3>; pinctrl-names = "default"; @@ -770,8 +775,8 @@ sd-uhs-sdr104; /* Power supply */ - vqmmc-supply = &vcc1v8_s3; /* IO line */ - vmmc-supply = &vcc_sdio; /* card's power */ + vqmmc-supply = <&vcc1v8_s3>; /* IO line */ + vmmc-supply = <&vcc_sdio>; /* card's power */ #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 9b2c679f5eca..3355fb90fa54 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -462,7 +462,7 @@ ap_i2c_tp: &i2c5 { }; &cros_ec { - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi index f1fcc6b5b402..7ba3ed24084b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi @@ -80,12 +80,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vsys_3v3>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vsys_3v3>; }; vsys: vsys { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts index e890166e7fd4..5bbe74bed0ea 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts @@ -102,12 +102,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc5v0_sys>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts index 04b54abea3cc..9d3a718f66f6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts @@ -166,12 +166,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts index c2f021a1a18f..d6b68d77d63a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts @@ -243,12 +243,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sysin>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sysin>; regulator-state-mem { regulator-on-in-suspend; @@ -472,8 +472,6 @@ vcc10-supply = <&vcc_sysin>; vcc11-supply = <&vcc_sysin>; vcc12-supply = <&vcc3v3_sys>; - vcc13-supply = <&vcc_sysin>; - vcc14-supply = <&vcc_sysin>; regulators { /* rk3399 center logic supply */ diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index 08fa00364b42..b1ac3a89f259 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -78,6 +78,17 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; }; &cpu_b0 { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi index d1aaf8e83391..0e45cc2d195b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi @@ -310,8 +310,6 @@ vcc10-supply = <&vcc3v3_sys>; vcc11-supply = <&vcc3v3_sys>; vcc12-supply = <&vcc3v3_sys>; - vcc13-supply = <&vcc3v3_sys>; - vcc14-supply = <&vcc3v3_sys>; vddio-supply = <&vcc_3v0>; regulators { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 92acf6ea299b..401e1ae9d944 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -144,12 +144,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc5v0_sys>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi index 83db4ca67334..45e77f86d329 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi @@ -213,12 +213,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc5v0_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1700000>; - vin-supply = <&vcc5v0_sys>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi index 46b0f97a0b1c..2aa0fad8f893 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi @@ -133,12 +133,12 @@ vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; - vin-supply = <&vcc_sys>; }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.1.dts new file mode 100644 index 000000000000..5b0b7ebf9fee --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.1.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinenote.dtsi" + +/ { + model = "Pine64 PineNote v1.1"; + compatible = "pine64,pinenote-v1.1", "pine64,pinenote", "rockchip,rk3566"; +}; + +&pmu_io_domains { + vccio7-supply = <&vcc_1v8>; +}; + +&spk_amp { + VCC-supply = <&dcdc_boost>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts b/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts new file mode 100644 index 000000000000..6bbc4c675d64 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote-v1.2.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-pinenote.dtsi" + +/ { + model = "Pine64 PineNote v1.2"; + compatible = "pine64,pinenote-v1.2", "pine64,pinenote", "rockchip,rk3566"; +}; + +&pmu_io_domains { + vccio7-supply = <&vcc_3v3>; +}; + +&spk_amp { + VCC-supply = <&vcc_bat>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi new file mode 100644 index 000000000000..fea748adfa90 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -0,0 +1,639 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include +#include +#include +#include + +#include "rk3566.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1750000>; + + recovery { + label = "recovery"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + spk_amp: audio-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&spk_amp_enable_h>; + pinctrl-names = "default"; + sound-name-prefix = "Speaker Amp"; + }; + + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <6>; + #sound-dai-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&hall_int_l>; + pinctrl-names = "default"; + + cover { + label = "cover"; + gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-event-action = ; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pin>; + pinctrl-names = "default"; + + led-0 { + color = ; + function = LED_FUNCTION_CHARGING; + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "PineNote"; + simple-audio-card,aux-devs = <&spk_amp>; + simple-audio-card,widgets = "Headphone", "Headphones", + "Speaker", "Internal Speakers"; + simple-audio-card,routing = "Headphones", "HPOL", + "Headphones", "HPOR", + "Internal Speakers", "Speaker Amp OUTL", + "Internal Speakers", "Speaker Amp OUTR", + "Speaker Amp INL", "HPOL", + "Speaker Amp INR", "HPOR"; + simple-audio-card,pin-switches = "Internal Speakers"; + #address-cells = <1>; + #size-cells = <0>; + + simple-audio-card,dai-link@0 { + reg = <0>; + bitclock-master = <&link0_cpu>; + format = "i2s"; + frame-master = <&link0_cpu>; + mclk-fs = <256>; + + link0_cpu: cpu { + sound-dai = <&i2s1_8ch>; + }; + + link0_codec: codec { + sound-dai = <&rk817>; + }; + }; + + simple-audio-card,dai-link@1 { + reg = <1>; + bitclock-master = <&link1_cpu>; + format = "pdm"; + frame-master = <&link1_cpu>; + + link1_cpu: cpu { + sound-dai = <&pdm>; + }; + + link1_codec: codec { + sound-dai = <&dmic_codec>; + }; + }; + }; + + vbat_4g: vbat-4g { + compatible = "regulator-fixed"; + regulator-name = "vbat_4g"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + /* powered by vcc_bat, enabled by vbat_4g_en */ + vin-supply = <&vbat_4g_en>; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + /* powered by vcc_sys, enabled by vcc_1v8_en */ + vin-supply = <&vcc_1v8_en>; + }; + + vcc_bat: vcc-bat { + compatible = "regulator-fixed"; + regulator-name = "vcc_bat"; + regulator-always-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_hall_3v3: vcc-hall-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_hall_3v3"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + vin-supply = <&vcc_bat>; + }; + + vcc_wl: vcc-wl { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc_wl_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_wl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_bat>; + }; + + vdda_0v9: vdda-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + /* powered by vcc_sys, enabled by vcc_1v8_en */ + vin-supply = <&vcc_1v8_en>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <0>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + #clock-cells = <1>; + pinctrl-0 = <&i2s1m0_mclk>, <&pmic_int_l>, <&pmic_sleep>; + pinctrl-names = "default"; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu_npu: DCDC_REG2 { + regulator-name = "vdd_gpu_npu"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_pmu: LDO_REG1 { + regulator-name = "vcca_1v8_pmu"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* unused */ + vdda_0v9_ldo: LDO_REG2 { + regulator-name = "vdda_0v9_ldo"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9_pmu: LDO_REG3 { + regulator-name = "vdda_0v9_pmu"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* unused */ + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_pmu: LDO_REG6 { + regulator-name = "vcc_3v3_pmu"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8_en: LDO_REG7 { + regulator-name = "vcc_1v8_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vbat_4g_en: LDO_REG8 { + regulator-name = "vbat_4g_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + sleep_sta_ctl: LDO_REG9 { + regulator-name = "sleep_sta_ctl"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-name = "boost"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + digitizer@9 { + compatible = "wacom,w9013", "hid-over-i2c"; + reg = <0x09>; + interrupt-parent = <&gpio0>; + interrupts = ; + hid-descr-addr = <0x1>; + pinctrl-0 = <&pen_fwe>, <&pen_irq_l>, <&pen_rst_l>; + pinctrl-names = "default"; + vdd-supply = <&vcc_3v3_pmu>; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3m1_xfer>; + status = "okay"; + + led-controller@36 { + compatible = "ti,lm3630a"; + reg = <0x36>; + enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&backlight_hwen_h>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + label = "backlight_cool"; + default-brightness = <0>; + }; + + led@1 { + reg = <1>; + label = "backlight_warm"; + default-brightness = <0>; + }; + }; +}; + +&i2s1_8ch { + pinctrl-0 = <&i2s1m0_lrcktx>, <&i2s1m0_sclktx>, <&i2s1m0_sdi0>, <&i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pdm { + pinctrl-0 = <&pdmm0_clk1>, <&pdmm0_sdi1>, <&pdmm0_sdi2>; + /* microphones are on channels 1 and 2 */ + rockchip,path-map = <1>, <2>, <0>, <3>; + status = "okay"; +}; + +&pinctrl { + audio-amplifier { + spk_amp_enable_h: spk-amp-enable-h { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + backlight { + backlight_hwen_h: backlight-hwen-h { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_wake_h: bt-wake-h { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + led { + led_pin: led-pin { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hall { + hall_int_l: hall-int-l { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pen { + pen_fwe: pen-fwe { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pen_irq_l: pen-irq-l { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pen_rst_l: pen-rst-l { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pmic_sleep: pmic-sleep { + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc-wl { + vcc_wl_pin: vcc-wl-pin { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3_pmu>; + pmuio2-supply = <&vcc_3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcca_1v8_pmu>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_datastrobe>, <&emmc_rstnout>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-0 = <&sdmmc1_bus4>, <&sdmmc1_clk>, <&sdmmc1_cmd>; + pinctrl-names = "default"; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vcca_1v8_pmu>; + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1m0_ctsn>, <&uart1m0_rtsn>, <&uart1m0_xfer>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk817 1>; + clock-names = "lpo"; + device-wake-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&bt_enable_h>, <&bt_host_wake_l>, <&bt_wake_h>; + pinctrl-names = "default"; + vbat-supply = <&vcc_wl>; + vddio-supply = <&vcca_1v8_pmu>; + }; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index d9eb92d59099..dd7f4b9b686b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -73,6 +73,17 @@ }; }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + }; + spdif_dit: spdif-dit { compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; @@ -124,6 +135,22 @@ vin-supply = <&vcc12v_dcin>; }; + /* all four ports are controlled by one gpio + * the host ports are sourced from vcc5v0_usb + * the otg port is sourced from vcc5v0_midu + */ + vcc5v0_usb20_host: vcc5v0_usb20_host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb20_host_en>; + regulator-name = "vcc5v0_usb20_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + vcc3v3_sd: vcc3v3_sd { compatible = "regulator-fixed"; enable-active-low; @@ -147,6 +174,17 @@ regulator-max-microvolt = <4400000>; vin-supply = <&vbus>; }; + + /* sourced from vcc_sys, sdio module operates internally at 3.3v */ + vcc_wl: vcc_wl { + compatible = "regulator-fixed"; + regulator-name = "vcc_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; }; &cpu0 { @@ -205,6 +243,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -427,6 +470,14 @@ }; }; +/* i2c3 is exposed on con40 + * pin 3 - i2c3_sda_m0, pullup to vcc_3v3 + * pin 5 - i2c3_scl_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "okay"; +}; + &i2s1_8ch { pinctrl-names = "default"; pinctrl-0 = <&i2s1m0_sclktx @@ -475,6 +526,18 @@ }; }; + usb2 { + vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + vcc_sd { vcc_sd_h: vcc-sd-h { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; @@ -482,6 +545,19 @@ }; }; +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + &sdhci { bus-width = <8>; mmc-hs200-1_8v; @@ -503,10 +579,32 @@ status = "okay"; }; +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_wl>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +/* spdif is exposed on con40 pin 18 */ &spdif { status = "okay"; }; +/* spi1 is exposed on con40 + * pin 11 - spi1_mosi_m1 + * pin 13 - spi1_miso_m1 + * pin 15 - spi1_clk_m1 + * pin 17 - spi1_cs0_m1 + */ &spi1 { pinctrl-names = "default"; pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; @@ -520,6 +618,10 @@ status = "okay"; }; +/* uart0 is exposed on con40 + * pin 12 - uart0_tx + * pin 14 - uart0_rx + */ &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; @@ -546,6 +648,40 @@ }; }; +/* uart2 is exposed on con40 + * pin 8 - uart2_tx_m0_debug + * pin 10 - uart2_rx_m0_debug + */ &uart2 { status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts new file mode 100644 index 000000000000..a01886b467ed --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Author: Frank Wunderlich + * + */ + +/dts-v1/; +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; + compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&blue_led_pin &green_led_pin>; + + blue_led: led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + }; + + green_led: led-1 { + color = ; + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + clock_in_out = "input"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c5 { + /* pin 3 (SDA) + 4 (SCL) of header con2 */ + status = "disabled"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pinctrl { + leds { + blue_led_pin: blue-led-pin { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + green_led_pin: green-led-pin { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm8 { + /* fan 5v - gnd - pwm */ + status = "okay"; +}; + +&pwm10 { + /* pin 7 of header con2 */ + status = "disabled"; +}; + +&pwm11 { + /* pin 15 of header con2 */ + status = "disabled"; +}; + +&pwm12 { + /* pin 21 of header con2 */ + /* shared with uart9 + spi3 */ + pinctrl-0 = <&pwm12m1_pins>; + status = "disabled"; +}; + +&pwm13 { + /* pin 24 of header con2 */ + /* shared with uart9 */ + pinctrl-0 = <&pwm13m1_pins>; + status = "disabled"; +}; + +&pwm14 { + /* pin 23 of header con2 */ + /* shared with spi3 */ + pinctrl-0 = <&pwm14m1_pins>; + status = "disabled"; +}; + +&pwm15 { + /* pin 19 of header con2 */ + /* shared with spi3 */ + pinctrl-0 = <&pwm15m1_pins>; + status = "disabled"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&spi3 { + /* pin 19 (MO) + 21 (MI) + 23 (CK) of header con2 */ + /* shared with pwm12/14/15 and uart9 */ + pinctrl-0 = <&spi3m1_pins>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&uart0 { + /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */ + status = "disabled"; +}; + +&uart2 { + /* debug-uart */ + status = "okay"; +}; + +&uart7 { + /* pin 11 (TX) + 13 (RX) of header con2 */ + pinctrl-0 = <&uart7m1_xfer>; + status = "disabled"; +}; + +&uart9 { + /* pin 21 (TX) + 24 (RX) of header con2 */ + /* shared with pwm13 and pwm12/spi3 */ + pinctrl-0 = <&uart9m1_xfer>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index 184e2aa2416a..a794a0ea5c70 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include "rk3568.dtsi" @@ -33,6 +34,33 @@ regulator-max-microvolt = <12000000>; }; + leds { + compatible = "gpio-leds"; + + led_work: led-0 { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_work_en>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; @@ -53,10 +81,38 @@ vin-supply = <&dc_12v>; }; + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + vcc3v3_lcd0_n: vcc3v3-lcd0-n { compatible = "regulator-fixed"; regulator-name = "vcc3v3_lcd0_n"; - regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_lcd0_n_en>; regulator-state-mem { regulator-off-in-suspend; @@ -66,7 +122,13 @@ vcc3v3_lcd1_n: vcc3v3-lcd1-n { compatible = "regulator-fixed"; regulator-name = "vcc3v3_lcd1_n"; - regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_lcd1_n_en>; regulator-state-mem { regulator-off-in-suspend; @@ -74,6 +136,22 @@ }; }; +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + &gmac0 { assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; @@ -106,18 +184,45 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &i2c0 { status = "okay"; + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + rk809: pmic@20 { compatible = "rockchip,rk809"; reg = <0x20>; interrupt-parent = <&gpio0>; interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; rockchip,system-power-controller; + #sound-dai-cells = <0>; vcc1-supply = <&vcc3v3_sys>; vcc2-supply = <&vcc3v3_sys>; vcc3-supply = <&vcc3v3_sys>; @@ -147,6 +252,7 @@ vdd_gpu: DCDC_REG2 { regulator-name = "vdd_gpu"; + regulator-always-on; regulator-init-microvolt = <900000>; regulator-initial-mode = <0x2>; regulator-min-microvolt = <500000>; @@ -231,6 +337,7 @@ vccio_acodec: LDO_REG4 { regulator-name = "vccio_acodec"; + regulator-always-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -315,9 +422,35 @@ }; }; }; + + codec { + mic-in-differential; + }; }; }; +&i2c1 { + status = "okay"; + + touchscreen0: goodix@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = ; + AVDD28-supply = <&vcc3v3_lcd0_n>; + irq-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int &touch_rst>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + VDDIO-supply = <&vcc3v3_lcd0_n>; + }; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + &mdio0 { rgmii_phy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -339,12 +472,42 @@ }; &pinctrl { + display { + vcc3v3_lcd0_n_en: vcc3v3_lcd0_n_en { + rockchip,pins = <0 RK_PC7 0 &pcfg_pull_none>; + }; + vcc3v3_lcd1_n_en: vcc3v3_lcd1_n_en { + rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>; + }; + }; + + leds { + led_work_en: led_work_en { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int: pmic_int { rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + touchscreen { + touch_int: touch_int { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + touch_rst: touch_rst { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pmu_io_domains { @@ -387,6 +550,42 @@ status = "okay"; }; +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + &uart2 { status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index d91df1cde736..5b0f528d6818 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,11 @@ / { compatible = "rockchip,rk3568"; + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + qos_pcie3x1: qos@fe190080 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe190080 0x0 0x20>; @@ -69,6 +74,22 @@ queue0 {}; }; }; + + combphy0: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, + <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; + status = "disabled"; + }; }; &cpu0_opp_table { diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 8ccce54ee8e7..7cdef800cb3c 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -144,6 +144,40 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <825000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <900000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + }; + }; + pmu { compatible = "arm,cortex-a55-pmu"; interrupts = , @@ -208,6 +242,50 @@ msi-controller; }; + usb_host0_ehci: usb@fd800000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd800000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>; + phys = <&usb2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@fd840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd840000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>; + phys = <&usb2phy1_otg>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@fd880000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd880000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>; + phys = <&usb2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@fd8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd8c0000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>; + phys = <&usb2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + pmugrf: syscon@fdc20000 { compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; reg = <0x0 0xfdc20000 0x0 0x10000>; @@ -218,11 +296,36 @@ }; }; + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + grf: syscon@fdc60000 { compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; reg = <0x0 0xfdc60000 0x0 0x10000>; }; + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + + usb2phy0_grf: syscon@fdca0000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca0000 0x0 0x8000>; + }; + + usb2phy1_grf: syscon@fdca8000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca8000 0x0 0x8000>; + }; + pmucru: clock-controller@fdd00000 { compatible = "rockchip,rk3568-pmucru"; reg = <0x0 0xfdd00000 0x0 0x1000>; @@ -390,6 +493,21 @@ }; }; + gpu: gpu@fde60000 { + compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; + reg = <0x0 0xfde60000 0x0 0x4000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&scmi_clk 1>, <&cru CLK_GPU>; + clock-names = "gpu", "bus"; + #cooling-cells = <2>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3568_PD_GPU>; + status = "disabled"; + }; + sdmmc2: mmc@fe000000 { compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe000000 0x0 0x4000>; @@ -651,6 +769,43 @@ status = "disabled"; }; + i2s3_2ch: i2s@fe430000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe430000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, + <&cru HCLK_I2S3_2CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 6>, <&dmac1 7>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm: pdm@fe440000 { + compatible = "rockchip,rk3568-pdm"; + reg = <0x0 0xfe440000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac1 9>; + dma-names = "rx"; + pinctrl-0 = <&pdmm0_clk + &pdmm0_clk1 + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + pinctrl-names = "default"; + resets = <&cru SRST_M_PDM>; + reset-names = "pdm-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + dmac0: dma-controller@fe530000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfe530000 0x0 0x4000>; @@ -974,6 +1129,32 @@ polling-delay = <1000>; /* milliseconds */ thermal-sensors = <&tsadc 1>; + + trips { + gpu_threshold: gpu-threshold { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_target: gpu-target { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: gpu-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_target>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; @@ -1141,6 +1322,82 @@ status = "disabled"; }; + combphy1: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, + <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY1>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + #phy-cells = <1>; + status = "disabled"; + }; + + combphy2: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, + <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY2>; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + #phy-cells = <1>; + status = "disabled"; + }; + + usb2phy0: usb2phy@fe8a0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8a0000 0x0 0x10000>; + clocks = <&pmucru CLK_USBPHY0_REF>; + clock-names = "phyclk"; + clock-output-names = "clk_usbphy0_480m"; + interrupts = ; + rockchip,usbgrf = <&usb2phy0_grf>; + #clock-cells = <0>; + status = "disabled"; + + usb2phy0_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + usb2phy1: usb2phy@fe8b0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8b0000 0x0 0x10000>; + clocks = <&pmucru CLK_USBPHY1_REF>; + clock-names = "phyclk"; + clock-output-names = "clk_usbphy1_480m"; + interrupts = ; + rockchip,usbgrf = <&usb2phy1_grf>; + #clock-cells = <0>; + status = "disabled"; + + usb2phy1_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3568-pinctrl"; rockchip,grf = <&grf>; diff --git a/arch/arm64/boot/dts/tesla/Makefile b/arch/arm64/boot/dts/tesla/Makefile new file mode 100644 index 000000000000..a1ee50e2fd06 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_TESLA_FSD) += \ + fsd-evb.dtb diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts new file mode 100644 index 000000000000..5af560c1b5e6 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Tesla FSD board device tree source + * + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2021 Tesla, Inc. + * https://www.tesla.com + */ + +/dts-v1/; +#include "fsd.dtsi" + +/ { + model = "Tesla Full Self-Driving (FSD) Evaluation board"; + compatible = "tesla,fsd-evb", "tesla,fsd"; + + aliases { + serial0 = &serial_0; + serial1 = &serial_1; + }; + + chosen { + stdout-path = &serial_0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; +}; + +&fin_pll { + clock-frequency = <24000000>; +}; + +&serial_0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi new file mode 100644 index 000000000000..d4d0cb005712 --- /dev/null +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tesla Full Self-Driving SoC device tree source + * + * Copyright (c) 2017-2021 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2021 Tesla, Inc. + * https://www.tesla.com + */ + +#include + +&pinctrl_fsys0 { + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf6: gpf6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf4: gpf4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf5: gpf5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&pinctrl_peric { + gpc8: gpc8-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb4: gpb4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb5: gpb5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb6: gpb6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb7: gpb7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd2: gpd2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd3: gpd3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg4: gpg4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg5: gpg5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg6: gpg6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg7: gpg7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pwm0_out: pwm0-out-pins { + samsung,pins = "gpb6-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + pwm1_out: pwm1-out-pins { + samsung,pins = "gpb6-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c0_bus: hs-i2c0-bus-pins { + samsung,pins = "gpb0-0", "gpb0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c1_bus: hs-i2c1-bus-pins { + samsung,pins = "gpb0-2", "gpb0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c2_bus: hs-i2c2-bus-pins { + samsung,pins = "gpb0-4", "gpb0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c3_bus: hs-i2c3-bus-pins { + samsung,pins = "gpb0-6", "gpb0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c4_bus: hs-i2c4-bus-pins { + samsung,pins = "gpb1-0", "gpb1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c5_bus: hs-i2c5-bus-pins { + samsung,pins = "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c6_bus: hs-i2c6-bus-pins { + samsung,pins = "gpb1-4", "gpb1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + hs_i2c7_bus: hs-i2c7-bus-pins { + samsung,pins = "gpb1-6", "gpb1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart0_data: uart0-data-pins { + samsung,pins = "gpb7-0", "gpb7-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + uart1_data: uart1-data-pins { + samsung,pins = "gpb7-4", "gpb7-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins = "gpb4-0", "gpb4-2", "gpb4-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi1_bus: spi1-bus-pins { + samsung,pins = "gpb4-4", "gpb4-6", "gpb4-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + spi2_bus: spi2-bus-pins { + samsung,pins = "gpb5-0", "gpb5-2", "gpb5-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_pmu { + gpq0: gpq0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi new file mode 100644 index 000000000000..9a652abcbcac --- /dev/null +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -0,0 +1,754 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Tesla Full Self-Driving SoC device tree source + * + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2022 Tesla, Inc. + * https://www.tesla.com + */ + +#include +#include + +/ { + compatible = "tesla,fsd"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &hsi2c_0; + i2c1 = &hsi2c_1; + i2c2 = &hsi2c_2; + i2c3 = &hsi2c_3; + i2c4 = &hsi2c_4; + i2c5 = &hsi2c_5; + i2c6 = &hsi2c_6; + i2c7 = &hsi2c_7; + pinctrl0 = &pinctrl_fsys0; + pinctrl1 = &pinctrl_peric; + pinctrl2 = &pinctrl_pmu; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpucl0_0>; + }; + core1 { + cpu = <&cpucl0_1>; + }; + core2 { + cpu = <&cpucl0_2>; + }; + core3 { + cpu = <&cpucl0_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpucl1_0>; + }; + core1 { + cpu = <&cpucl1_1>; + }; + core2 { + cpu = <&cpucl1_2>; + }; + core3 { + cpu = <&cpucl1_3>; + }; + }; + + cluster2 { + core0 { + cpu = <&cpucl2_0>; + }; + core1 { + cpu = <&cpucl2_1>; + }; + core2 { + cpu = <&cpucl2_2>; + }; + core3 { + cpu = <&cpucl2_3>; + }; + }; + }; + + /* Cluster 0 */ + cpucl0_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x000>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl0_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x001>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl0_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x002>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl0_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x003>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP>; + }; + + /* Cluster 1 */ + cpucl1_0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x100>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl1_1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x101>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl1_2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x102>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl1_3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x103>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + /* Cluster 2 */ + cpucl2_0: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x200>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl2_1: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x201>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl2_2: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x202>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpucl2_3: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x203>; + enable-method = "psci"; + clock-frequency = <2400000000>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + idle-state-name = "c2"; + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <30>; + exit-latency-us = <75>; + min-residency-us = <300>; + }; + }; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>, + <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>, + <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>, + <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + fin_pll: clock { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + + gic: interrupt-controller@10400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ + <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ + interrupts = ; + }; + + smmu_imem: iommu@10200000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x10200000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <7>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for FSYS1_0 */ + , /* for FSYS1_1 */ + , /* for IMEM_0 */ + /* Per context non-secure context interrupts, 0-3 interrupts */ + , /* for CONTEXT_0 */ + , /* for CONTEXT_1 */ + , /* for CONTEXT_2 */ + ; /* for CONTEXT_3 */ + }; + + smmu_isp: iommu@12100000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x12100000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <11>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for CAM_CSI */ + , /* for CAM_DP_0 */ + , /* for CAM_DP_1 */ + , /* for CAM_ISP_0 */ + , /* for CAM_ISP_1 */ + , /* for CAM_MFC_0 */ + , /* for CAM_MFC_1 */ + /* Per context non-secure context interrupts, 0-7 interrupts */ + , /* for CONTEXT_0 */ + , /* for CONTEXT_1 */ + , /* for CONTEXT_2 */ + , /* for CONTEXT_3 */ + , /* for CONTEXT_4 */ + , /* for CONTEXT_5 */ + , /* for CONTEXT_6 */ + ; /* for CONTEXT_7 */ + }; + + smmu_peric: iommu@14900000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x14900000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <5>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for PERIC */ + /* Per context non-secure context interrupts, 0-1 interrupts */ + , /* for CONTEXT_0 */ + ; /* for CONTEXT_1 */ + }; + + smmu_fsys0: iommu@15450000 { + compatible = "arm,mmu-500"; + reg = <0x0 0x15450000 0x0 0x10000>; + #iommu-cells = <2>; + #global-interrupts = <5>; + interrupts = , /* Global secure fault */ + , /* Global non-secure fault */ + , /* Combined secure interrupt */ + , /* Combined non-secure interrupt */ + /* Performance counter interrupts */ + , /* for FSYS0 */ + /* Per context non-secure context interrupts, 0-1 interrupts */ + , /* for CONTEXT_0 */ + ; /* for CONTEXT_1 */ + }; + + clock_imem: clock-controller@10010000 { + compatible = "tesla,fsd-clock-imem"; + reg = <0x0 0x10010000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, + <&clock_cmu DOUT_CMU_IMEM_ACLK>, + <&clock_cmu DOUT_CMU_IMEM_DMACLK>; + clock-names = "fin_pll", + "dout_cmu_imem_tcuclk", + "dout_cmu_imem_aclk", + "dout_cmu_imem_dmaclk"; + }; + + clock_cmu: clock-controller@11c10000 { + compatible = "tesla,fsd-clock-cmu"; + reg = <0x0 0x11c10000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + clock_csi: clock-controller@12610000 { + compatible = "tesla,fsd-clock-cam_csi"; + reg = <0x0 0x12610000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + clock_mfc: clock-controller@12810000 { + compatible = "tesla,fsd-clock-mfc"; + reg = <0x0 0x12810000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>; + clock-names = "fin_pll"; + }; + + clock_peric: clock-controller@14010000 { + compatible = "tesla,fsd-clock-peric"; + reg = <0x0 0x14010000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>, + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>, + <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>, + <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; + clock-names = "fin_pll", + "dout_cmu_pll_shared0_div4", + "dout_cmu_peric_shared1div36", + "dout_cmu_peric_shared0div3_tbuclk", + "dout_cmu_peric_shared0div20", + "dout_cmu_peric_shared1div4_dmaclk"; + }; + + clock_fsys0: clock-controller@15010000 { + compatible = "tesla,fsd-clock-fsys0"; + reg = <0x0 0x15010000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, + <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, + <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; + clock-names = "fin_pll", + "dout_cmu_pll_shared0_div6", + "dout_cmu_fsys0_shared1div4", + "dout_cmu_fsys0_shared0div4"; + }; + + clock_fsys1: clock-controller@16810000 { + compatible = "tesla,fsd-clock-fsys1"; + reg = <0x0 0x16810000 0x0 0x3000>; + #clock-cells = <1>; + clocks = <&fin_pll>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, + <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; + clock-names = "fin_pll", + "dout_cmu_fsys1_shared0div8", + "dout_cmu_fsys1_shared0div4"; + }; + + mdma0: dma-controller@10100000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x10100000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_imem 0x800 0x0>; + }; + + mdma1: dma-controller@10110000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x10110000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_imem 0x801 0x0>; + }; + + pdma0: dma-controller@14280000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x14280000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_peric 0x2 0x0>; + }; + + pdma1: dma-controller@14290000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x14290000 0x0 0x1000>; + interrupts = ; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; + clock-names = "apb_pclk"; + iommus = <&smmu_peric 0x1 0x0>; + }; + + serial_0: serial@14180000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x0 0x14180000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 1>, <&pdma1 0>; + dma-names = "rx", "tx"; + clocks = <&clock_peric PERIC_PCLK_UART0>, + <&clock_peric PERIC_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_1: serial@14190000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x0 0x14190000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 3>, <&pdma1 2>; + dma-names = "rx", "tx"; + clocks = <&clock_peric PERIC_PCLK_UART1>, + <&clock_peric PERIC_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + pmu_system_controller: system-controller@11400000 { + compatible = "samsung,exynos7-pmu", "syscon"; + reg = <0x0 0x11400000 0x0 0x5000>; + }; + + watchdog_0: watchdog@100a0000 { + compatible = "samsung,exynos7-wdt"; + reg = <0x0 0x100a0000 0x0 0x100>; + interrupts = ; + samsung,syscon-phandle = <&pmu_system_controller>; + clocks = <&fin_pll>; + clock-names = "watchdog"; + }; + + watchdog_1: watchdog@100b0000 { + compatible = "samsung,exynos7-wdt"; + reg = <0x0 0x100b0000 0x0 0x100>; + interrupts = ; + samsung,syscon-phandle = <&pmu_system_controller>; + clocks = <&fin_pll>; + clock-names = "watchdog"; + }; + + watchdog_2: watchdog@100c0000 { + compatible = "samsung,exynos7-wdt"; + reg = <0x0 0x100c0000 0x0 0x100>; + interrupts = ; + samsung,syscon-phandle = <&pmu_system_controller>; + clocks = <&fin_pll>; + clock-names = "watchdog"; + }; + + pwm_0: pwm@14100000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x0 0x14100000 0x0 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; + clock-names = "timers"; + status = "disabled"; + }; + + pwm_1: pwm@14110000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x0 0x14110000 0x0 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; + clock-names = "timers"; + status = "disabled"; + }; + + hsi2c_0: i2c@14200000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14200000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c0_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C0>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_1: i2c@14210000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14210000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c1_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C1>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_2: i2c@14220000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14220000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c2_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C2>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_3: i2c@14230000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14230000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c3_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C3>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_4: i2c@14240000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14240000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c4_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C4>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_5: i2c@14250000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14250000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c5_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C5>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_6: i2c@14260000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14260000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c6_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C6>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + hsi2c_7: i2c@14270000 { + compatible = "samsung,exynos7-hsi2c"; + reg = <0x0 0x14270000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hs_i2c7_bus>; + clocks = <&clock_peric PERIC_PCLK_HSI2C7>; + clock-names = "hsi2c"; + status = "disabled"; + }; + + pinctrl_pmu: pinctrl@114f0000 { + compatible = "tesla,fsd-pinctrl"; + reg = <0x0 0x114f0000 0x0 0x1000>; + }; + + pinctrl_peric: pinctrl@141f0000 { + compatible = "tesla,fsd-pinctrl"; + reg = <0x0 0x141f0000 0x0 0x1000>; + interrupts = ; + }; + + pinctrl_fsys0: pinctrl@15020000 { + compatible = "tesla,fsd-pinctrl"; + reg = <0x0 0x15020000 0x0 0x1000>; + interrupts = ; + }; + + spi_0: spi@14140000 { + compatible = "tesla,fsd-spi"; + reg = <0x0 0x14140000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 4>, <&pdma1 5>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_peric PERIC_PCLK_SPI0>, + <&clock_peric PERIC_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + num-cs = <1>; + status = "disabled"; + }; + + spi_1: spi@14150000 { + compatible = "tesla,fsd-spi"; + reg = <0x0 0x14150000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 6>, <&pdma1 7>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_peric PERIC_PCLK_SPI1>, + <&clock_peric PERIC_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + num-cs = <1>; + status = "disabled"; + }; + + spi_2: spi@14160000 { + compatible = "tesla,fsd-spi"; + reg = <0x0 0x14160000 0x0 0x100>; + interrupts = ; + dmas = <&pdma1 8>, <&pdma1 9>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clock_peric PERIC_PCLK_SPI2>, + <&clock_peric PERIC_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + num-cs = <1>; + status = "disabled"; + }; + + timer@10040000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x0 0x10040000 0x0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + }; + }; +}; + +#include "fsd-pinctrl.dtsi" diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 90be511bc4d0..02e5d80344d0 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -21,3 +21,5 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb + +dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi new file mode 100644 index 000000000000..c68472c692f4 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -0,0 +1,267 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family Main Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + main_conf: syscon@100000 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x00100000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x00100000 0x20000>; + }; + + dmss: bus@48000000 { + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d000000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + interrupt-names = "rx_012"; + interrupts = ; + }; + }; + + dmsc: system-controller@44043000 { + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + reg-names = "debug_messages"; + reg = <0x00 0x44043000 0x00 0xfe0>; + + k3_pds: power-controller { + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + main_pmx0: pinctrl@f4000 { + compatible = "pinctrl-single"; + reg = <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + }; + + main_uart2: serial@2820000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02820000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 153 0>; + clock-names = "fclk"; + }; + + main_uart3: serial@2830000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02830000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 154 0>; + clock-names = "fclk"; + }; + + main_uart4: serial@2840000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02840000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 155 0>; + clock-names = "fclk"; + }; + + main_uart5: serial@2850000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02850000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 156 0>; + clock-names = "fclk"; + }; + + main_uart6: serial@2860000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02860000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 158 0>; + clock-names = "fclk"; + }; + + main_i2c0: i2c@20000000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20000000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 102 2>; + clock-names = "fck"; + }; + + main_i2c1: i2c@20010000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20010000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 103 2>; + clock-names = "fck"; + }; + + main_i2c2: i2c@20020000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20020000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 104 2>; + clock-names = "fck"; + }; + + main_i2c3: i2c@20030000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x20030000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 2>; + clock-names = "fck"; + }; + + main_gpio_intr: interrupt-controller@a00000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x00a00000 0x00 0x800>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <3>; + ti,interrupt-ranges = <0 32 16>; + }; + + main_gpio0: gpio@600000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x0 0x00600000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <190>, <191>, <192>, + <193>, <194>, <195>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <87>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 77 0>; + clock-names = "gpio"; + }; + + main_gpio1: gpio@601000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x0 0x00601000 0x0 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <180>, <181>, <182>, + <183>, <184>, <185>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <88>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 78 0>; + clock-names = "gpio"; + }; + + hwspinlock: spinlock@2a000000 { + compatible = "ti,am64-hwspinlock"; + reg = <0x00 0x2a000000 0x00 0x1000>; + #hwlock-cells = <1>; + }; + + mailbox0_cluster0: mailbox@29000000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29000000 0x00 0x200>; + interrupts = , + ; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi new file mode 100644 index 000000000000..9d210d55fc71 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family MCU Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + mcu_uart0: serial@4a00000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x04a00000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 149 0>; + clock-names = "fclk"; + }; + + mcu_i2c0: i2c@4900000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x04900000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 106 2>; + clock-names = "fck"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi new file mode 100644 index 000000000000..4090134676cf --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_wakeup { + wkup_conf: syscon@43000000 { + compatible = "syscon", "simple-mfd"; + reg = <0x00 0x43000000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x43000000 0x20000>; + + chipid: chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x2b300000 0x00 0x100>; + interrupts = ; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fclk"; + }; + + wkup_i2c0: i2c@2b200000 { + compatible = "ti,am64-i2c", "ti,omap4-i2c"; + reg = <0x00 0x02b200000 0x00 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 4>; + clock-names = "fck"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi new file mode 100644 index 000000000000..bc2997b18556 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62 SoC Family + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include +#include +#include +#include +#include + +/ { + model = "Texas Instruments K3 AM625 SoC"; + compatible = "ti,am625"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + cbass_main: bus@f0000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + + /* Wakeup Domain Range */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ + }; + + cbass_wakeup: bus@2b000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am62-main.dtsi" +#include "k3-am62-mcu.dtsi" +#include "k3-am62-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts new file mode 100644 index 000000000000..0de4113ccd5d --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM625 SK: https://www.ti.com/lit/zip/sprr448 + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include +#include +#include "k3-am625.dtsi" + +/ { + compatible = "ti,am625-sk", "ti,am625"; + model = "Texas Instruments AM625 SK"; + + aliases { + serial2 = &main_uart0; + }; + + chosen { + stdout-path = "serial2:115200n8"; + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; + }; + + memory@80000000 { + device_type = "memory"; + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + alignment = <0x1000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + alignment = <0x1000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + }; + + vmain_pd: regulator-0 { + /* TPS65988 PD CONTROLLER OUTPUT */ + compatible = "regulator-fixed"; + regulator-name = "vmain_pd"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_5v0: regulator-1 { + /* Output of LM34936 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_3v3_sys: regulator-2 { + /* output of LM61460-Q1 */ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vmain_pd>; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pins_default>; + + led-0 { + label = "am62-sk:green:heartbeat"; + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_HEARTBEAT; + default-state = "off"; + }; + }; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ + >; + }; + + usr_led_pins_default: usr-led-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ + >; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status = "reserved"; +}; + +&mcu_uart0 { + status = "disabled"; +}; + +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +&main_uart2 { + status = "disabled"; +}; + +&main_uart3 { + status = "disabled"; +}; + +&main_uart4 { + status = "disabled"; +}; + +&main_uart5 { + status = "disabled"; +}; + +&main_uart6 { + status = "disabled"; +}; + +&mcu_i2c0 { + status = "disabled"; +}; + +&wkup_i2c0 { + status = "disabled"; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; +}; + +&main_i2c2 { + status = "disabled"; +}; + +&main_i2c3 { + status = "disabled"; +}; + +&mailbox0_cluster0 { + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi new file mode 100644 index 000000000000..887f31c23fef --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM625 SoC family in Quad core configuration + * + * TRM: https://www.ti.com/lit/pdf/spruiv7 + * + * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; + +#include "k3-am62.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 012011dc619a..f64b368c6c37 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -59,7 +59,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01840000 0x00 0xC0000>; /* GICR */ + <0x00 0x01840000 0x00 0xC0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ /* * vcpumntirq: * virtual CPU interface maintenance interrupt @@ -982,6 +985,24 @@ clock-names = "fck"; }; + main_rti0: watchdog@e000000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0xe000000 0x00 0x100>; + clocks = <&k3_clks 125 0>; + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 125 0>; + assigned-clock-parents = <&k3_clks 125 2>; + }; + + main_rti1: watchdog@e010000 { + compatible = "ti,j7-rti-wdt"; + reg = <0x00 0xe010000 0x00 0x100>; + clocks = <&k3_clks 126 0>; + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; + assigned-clocks = <&k3_clks 126 0>; + assigned-clock-parents = <&k3_clks 126 2>; + }; + icssg0: icssg@30000000 { compatible = "ti,am642-icssg"; reg = <0x00 0x30000000 0x00 0x80000>; diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi index 120974726be8..016dd8511ca6 100644 --- a/arch/arm64/boot/dts/ti/k3-am64.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi @@ -66,11 +66,14 @@ #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */ + <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */ <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */ @@ -87,6 +90,7 @@ <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */ <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index e94ae178b1ae..8e7893e58b03 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -498,7 +498,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -509,8 +509,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index a9785bec12df..1d7db8bf3a5c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -369,7 +369,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -380,8 +380,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index 3079eaee01c0..6e41f2fa044a 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -603,8 +603,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index ce8bb4a61011..e749343acced 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -35,7 +35,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01880000 0x00 0x90000>; /* GICR */ + <0x00 0x01880000 0x00 0x90000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* * vcpumntirq: * virtual CPU interface maintenance interrupt diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi index a58a39fa42db..c538a0bf3cdd 100644 --- a/arch/arm64/boot/dts/ti/k3-am65.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -86,6 +86,7 @@ <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>, <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 9043f91c9bec..57497cb1ed68 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -333,14 +333,12 @@ #size-cells= <0>; ti,pindir-d0-out-d1-in; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <48000000>; - #address-cells = <1>; - #size-cells= <1>; }; }; @@ -498,7 +496,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -509,8 +507,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 05a627ad6cdc..16684a2f054d 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -54,7 +54,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = ; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index 34724440171a..2d615c3e9fa1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -256,7 +256,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -267,7 +267,5 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index 64fef4e67d76..b6da0454cc5b 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -129,6 +129,7 @@ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */ <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2d7596911b27..f5ca8e26ed99 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -482,7 +482,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; @@ -493,8 +493,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <2>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 599861259a30..db0669985e42 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -76,7 +76,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = ; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index b726310d867c..f25d85169e0d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -475,8 +475,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 2fee2906183d..e36335232cf8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -171,7 +171,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -182,8 +182,6 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; - #address-cells = <1>; - #size-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 4a3872fce533..0e23886c9fd1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -139,6 +139,7 @@ <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/ <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */ <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index b04db1d3ab61..be7f39299894 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -34,7 +34,10 @@ #interrupt-cells = <3>; interrupt-controller; reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ - <0x00 0x01900000 0x00 0x100000>; /* GICR */ + <0x00 0x01900000 0x00 0x100000>, /* GICR */ + <0x00 0x6f000000 0x00 0x2000>, /* GICC */ + <0x00 0x6f010000 0x00 0x1000>, /* GICH */ + <0x00 0x6f020000 0x00 0x2000>; /* GICV */ /* vcpumntirq: virtual CPU interface maintenance interrupt */ interrupts = ; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index 7521963719ff..6c5c02edb375 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -108,7 +108,7 @@ reg = <0x00 0x42110000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; + interrupt-parent = <&wkup_gpio_intr>; interrupts = <103>, <104>, <105>, <106>, <107>, <108>; interrupt-controller; #interrupt-cells = <2>; @@ -124,7 +124,7 @@ reg = <0x00 0x42100000 0x00 0x100>; gpio-controller; #gpio-cells = <2>; - interrupt-parent = <&main_gpio_intr>; + interrupt-parent = <&wkup_gpio_intr>; interrupts = <112>, <113>, <114>, <115>, <116>, <117>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index fe5234c40f6c..7b930a85a29d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -119,6 +119,7 @@ <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ + <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 74e66443e4ce..3e15391e5b37 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -254,106 +254,106 @@ }; /* GDMA */ - fpd_dma_chan1: dma@fd500000 { + fpd_dma_chan1: dma-controller@fd500000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan2: dma@fd510000 { + fpd_dma_chan2: dma-controller@fd510000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan3: dma@fd520000 { + fpd_dma_chan3: dma-controller@fd520000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan4: dma@fd530000 { + fpd_dma_chan4: dma-controller@fd530000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan5: dma@fd540000 { + fpd_dma_chan5: dma-controller@fd540000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan6: dma@fd550000 { + fpd_dma_chan6: dma-controller@fd550000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan7: dma@fd560000 { + fpd_dma_chan7: dma-controller@fd560000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; power-domains = <&zynqmp_firmware PD_GDMA>; }; - fpd_dma_chan8: dma@fd570000 { + fpd_dma_chan8: dma-controller@fd570000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <128>; - #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; power-domains = <&zynqmp_firmware PD_GDMA>; }; @@ -375,106 +375,106 @@ * These dma channels, Users should ensure that these dma * Channels are allowed for non secure access. */ - lpd_dma_chan1: dma@ffa80000 { + lpd_dma_chan1: dma-controller@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x868>; power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan2: dma@ffa90000 { + lpd_dma_chan2: dma-controller@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x869>; power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan3: dma@ffaa0000 { + lpd_dma_chan3: dma-controller@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86a>; power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan4: dma@ffab0000 { + lpd_dma_chan4: dma-controller@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86b>; power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan5: dma@ffac0000 { + lpd_dma_chan5: dma-controller@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86c>; power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan6: dma@ffad0000 { + lpd_dma_chan6: dma-controller@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86d>; power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan7: dma@ffae0000 { + lpd_dma_chan7: dma-controller@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86e>; power-domains = <&zynqmp_firmware PD_ADMA>; }; - lpd_dma_chan8: dma@ffaf0000 { + lpd_dma_chan8: dma-controller@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; xlnx,bus-width = <64>; - #stream-id-cells = <1>; iommus = <&smmu 0x86f>; power-domains = <&zynqmp_firmware PD_ADMA>; }; @@ -495,7 +495,6 @@ interrupts = <0 14 4>; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; @@ -509,7 +508,6 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x874>; power-domains = <&zynqmp_firmware PD_ETH_0>; }; @@ -523,7 +521,6 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x875>; power-domains = <&zynqmp_firmware PD_ETH_1>; }; @@ -537,7 +534,6 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x876>; power-domains = <&zynqmp_firmware PD_ETH_2>; }; @@ -551,7 +547,6 @@ clock-names = "pclk", "hclk", "tx_clk"; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x877>; power-domains = <&zynqmp_firmware PD_ETH_3>; }; @@ -621,7 +616,6 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - #stream-id-cells = <1>; iommus = <&smmu 0x4d0>; power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { @@ -642,7 +636,6 @@ <0x0 0xc0000000 0x0 0x8000000>; #address-cells = <1>; #size-cells = <0>; - #stream-id-cells = <1>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; @@ -674,7 +667,6 @@ interrupts = <0 133 4>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; - #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; }; @@ -686,7 +678,6 @@ interrupts = <0 48 4>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - #stream-id-cells = <1>; iommus = <&smmu 0x870>; #clock-cells = <1>; clock-output-names = "clk_out_sd0", "clk_in_sd0"; @@ -700,7 +691,6 @@ interrupts = <0 49 4>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; - #stream-id-cells = <1>; iommus = <&smmu 0x871>; #clock-cells = <1>; clock-output-names = "clk_out_sd1", "clk_in_sd1"; @@ -825,7 +815,6 @@ interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg"; interrupts = <0 65 4>, <0 69 4>; - #stream-id-cells = <1>; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; /* dma-coherent; */ @@ -852,7 +841,6 @@ interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg"; interrupts = <0 70 4>, <0 74 4>; - #stream-id-cells = <1>; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; /* dma-coherent; */ diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 30516dc0b70e..50aa3d75ab4f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -3,17 +3,19 @@ CONFIG_POSIX_MQUEUE=y CONFIG_AUDIT=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y CONFIG_PREEMPT=y CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_NUMA_BALANCING=y CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_PIDS=y CONFIG_CGROUP_HUGETLB=y @@ -21,6 +23,7 @@ CONFIG_CPUSETS=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y CONFIG_USER_NS=y CONFIG_SCHED_AUTOGROUP=y CONFIG_BLK_DEV_INITRD=y @@ -54,6 +57,7 @@ CONFIG_ARCH_SEATTLE=y CONFIG_ARCH_INTEL_SOCFPGA=y CONFIG_ARCH_SYNQUACER=y CONFIG_ARCH_TEGRA=y +CONFIG_ARCH_TESLA_FSD=y CONFIG_ARCH_SPRD=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_THUNDER2=y @@ -66,7 +70,6 @@ CONFIG_ARM64_VA_BITS_48=y CONFIG_SCHED_MC=y CONFIG_SCHED_SMT=y CONFIG_NUMA=y -CONFIG_SECCOMP=y CONFIG_KEXEC=y CONFIG_KEXEC_FILE=y CONFIG_CRASH_DUMP=y @@ -84,7 +87,6 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=m CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPUFREQ_DT=y CONFIG_ACPI_CPPC_CPUFREQ=m CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m @@ -96,16 +98,8 @@ CONFIG_ARM_QCOM_CPUFREQ_HW=y CONFIG_ARM_RASPBERRYPI_CPUFREQ=m CONFIG_ARM_SCMI_CPUFREQ=y CONFIG_ARM_TEGRA186_CPUFREQ=y +CONFIG_ARM_MEDIATEK_CPUFREQ=y CONFIG_QORIQ_CPUFREQ=y -CONFIG_ARM_SCMI_PROTOCOL=y -CONFIG_ARM_SCPI_PROTOCOL=y -CONFIG_RASPBERRYPI_FIRMWARE=y -CONFIG_INTEL_STRATIX10_SERVICE=y -CONFIG_INTEL_STRATIX10_RSU=m -CONFIG_QCOM_SCM=y -CONFIG_EFI_CAPSULE_LOADER=y -CONFIG_IMX_SCU=y -CONFIG_IMX_SCU_PD=y CONFIG_ACPI=y CONFIG_ACPI_APEI=y CONFIG_ACPI_APEI_GHES=y @@ -127,6 +121,7 @@ CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_CRYPTO_AES_ARM64_BS=m CONFIG_JUMP_LABEL=y +CONFIG_SECCOMP=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set @@ -182,14 +177,13 @@ CONFIG_NET_ACT_GATE=m CONFIG_QRTR=m CONFIG_QRTR_SMD=m CONFIG_QRTR_TUN=m -CONFIG_BPF_JIT=y CONFIG_CAN=m +CONFIG_CAN_FLEXCAN=m CONFIG_CAN_RCAR=m CONFIG_CAN_RCAR_CANFD=m -CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_MCP251XFD=m CONFIG_BT=m CONFIG_BT_HIDP=m -# CONFIG_BT_HS is not set # CONFIG_BT_LE is not set CONFIG_BT_LEDS=y # CONFIG_BT_DEBUGFS is not set @@ -198,6 +192,9 @@ CONFIG_BT_HCIUART=m CONFIG_BT_HCIUART_LL=y CONFIG_BT_HCIUART_BCM=y CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m CONFIG_BT_QCOMSMD=m CONFIG_CFG80211=m CONFIG_MAC80211=m @@ -210,6 +207,7 @@ CONFIG_NFC_NCI=m CONFIG_NFC_S3FWRN5_I2C=m CONFIG_PCI=y CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y CONFIG_PCI_IOV=y CONFIG_PCI_PASID=y CONFIG_HOTPLUG_PCI=y @@ -228,7 +226,6 @@ CONFIG_PCIE_ROCKCHIP_HOST=m CONFIG_PCIE_BRCMSTB=m CONFIG_PCI_IMX6=y CONFIG_PCI_LAYERSCAPE=y -CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCI_HISI=y CONFIG_PCIE_QCOM=y CONFIG_PCIE_ARMADA_8K=y @@ -236,6 +233,7 @@ CONFIG_PCIE_KIRIN=y CONFIG_PCIE_HISI_STB=y CONFIG_PCIE_TEGRA194_HOST=m CONFIG_PCIE_VISCONTI_HOST=y +CONFIG_PCIE_LAYERSCAPE_GEN4=y CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y CONFIG_PCI_EPF_TEST=m @@ -243,8 +241,15 @@ CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_FW_LOADER_USER_HELPER=y CONFIG_HISILICON_LPC=y -CONFIG_FSL_MC_BUS=y CONFIG_TEGRA_ACONNECT=m +CONFIG_ARM_SCMI_PROTOCOL=y +CONFIG_ARM_SCPI_PROTOCOL=y +CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_INTEL_STRATIX10_SERVICE=y +CONFIG_INTEL_STRATIX10_RSU=m +CONFIG_EFI_CAPSULE_LOADER=y +CONFIG_IMX_SCU=y +CONFIG_IMX_SCU_PD=y CONFIG_GNSS=m CONFIG_GNSS_MTK_SERIAL=m CONFIG_MTD=y @@ -259,13 +264,12 @@ CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_DATAFLASH=y CONFIG_MTD_SST25L=y CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_BRCMNAND=m CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_MARVELL=y CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_NAND_QCOM=y CONFIG_MTD_SPI_NOR=y -CONFIG_MTK_DEVAPC=m -CONFIG_SPI_CADENCE_QUADSPI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m CONFIG_VIRTIO_BLK=y @@ -290,6 +294,7 @@ CONFIG_SCSI_UFS_EXYNOS=y CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_BRCM=m CONFIG_AHCI_CEVA=y CONFIG_AHCI_MVEBU=y CONFIG_AHCI_XGENE=y @@ -309,11 +314,13 @@ CONFIG_MACVTAP=m CONFIG_TUN=y CONFIG_VETH=m CONFIG_VIRTIO_NET=y +CONFIG_NET_DSA_BCM_SF2=m CONFIG_NET_DSA_MSCC_FELIX=m CONFIG_AMD_XGBE=y CONFIG_NET_XGENE=y CONFIG_ATL1C=m CONFIG_BCMGENET=m +CONFIG_SYSTEMPORT=m CONFIG_BNX2X=m CONFIG_MACB=y CONFIG_THUNDER_NIC_PF=y @@ -342,6 +349,7 @@ CONFIG_MLX5_CORE=m CONFIG_MLX5_CORE_EN=y CONFIG_QCOM_EMAC=m CONFIG_RMNET=m +CONFIG_R8169=m CONFIG_SH_ETH=y CONFIG_RAVB=y CONFIG_SMC91X=y @@ -351,13 +359,11 @@ CONFIG_SNI_NETSEC=y CONFIG_STMMAC_ETH=m CONFIG_TI_K3_AM65_CPSW_NUSS=y CONFIG_QCOM_IPA=m -CONFIG_MDIO_BUS_MUX_MMIOREG=y -CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_MESON_GXL_PHY=m CONFIG_AQUANTIA_PHY=y CONFIG_BCM54140_PHY=m CONFIG_MARVELL_PHY=m CONFIG_MARVELL_10G_PHY=m -CONFIG_MESON_GXL_PHY=m CONFIG_MICREL_PHY=y CONFIG_MICROSEMI_PHY=y CONFIG_AT803X_PHY=y @@ -365,6 +371,9 @@ CONFIG_REALTEK_PHY=y CONFIG_ROCKCHIP_PHY=y CONFIG_DP83867_PHY=y CONFIG_VITESSE_PHY=y +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_USB_BRCMSTB=m CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m CONFIG_USB_RTL8152=m @@ -382,6 +391,7 @@ CONFIG_ATH10K_SNOC=m CONFIG_WCN36XX=m CONFIG_BRCMFMAC=m CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m CONFIG_MWIFIEX_PCIE=m CONFIG_WL18XX=m CONFIG_WLCORE_SDIO=m @@ -473,6 +483,7 @@ CONFIG_SPI=y CONFIG_SPI_ARMADA_3700=y CONFIG_SPI_BCM2835=m CONFIG_SPI_BCM2835AUX=m +CONFIG_SPI_CADENCE_QUADSPI=y CONFIG_SPI_DESIGNWARE=m CONFIG_SPI_DW_DMA=y CONFIG_SPI_DW_MMIO=m @@ -487,6 +498,7 @@ CONFIG_SPI_ORION=y CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=y CONFIG_SPI_RPCIF=m +CONFIG_SPI_RSPI=m CONFIG_SPI_QCOM_QSPI=m CONFIG_SPI_QUP=y CONFIG_SPI_QCOM_GENI=m @@ -495,8 +507,8 @@ CONFIG_SPI_SH_MSIOF=m CONFIG_SPI_SUN6I=y CONFIG_SPI_SPIDEV=m CONFIG_SPMI=y -CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y +CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_OWL=y CONFIG_PINCTRL_S700=y CONFIG_PINCTRL_S900=y @@ -524,6 +536,7 @@ CONFIG_PINCTRL_SDM845=y CONFIG_PINCTRL_SM8150=y CONFIG_PINCTRL_SM8250=y CONFIG_PINCTRL_SM8350=y +CONFIG_PINCTRL_SM8450=y CONFIG_PINCTRL_LPASS_LPI=m CONFIG_GPIO_ALTERA=m CONFIG_GPIO_DAVINCI=y @@ -544,9 +557,6 @@ CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_BD9571MWV=m CONFIG_GPIO_MAX77620=y CONFIG_GPIO_SL28CPLD=m -CONFIG_POWER_AVS=y -CONFIG_QCOM_CPR=y -CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_POWER_RESET_MSM=y CONFIG_POWER_RESET_QCOM_PON=m CONFIG_POWER_RESET_XGENE=y @@ -554,12 +564,13 @@ CONFIG_POWER_RESET_SYSCON=y CONFIG_SYSCON_REBOOT_MODE=y CONFIG_BATTERY_SBS=m CONFIG_BATTERY_BQ27XXX=y -CONFIG_SENSORS_ARM_SCMI=y CONFIG_BATTERY_MAX17042=m CONFIG_CHARGER_BQ25890=m CONFIG_CHARGER_BQ25980=m +CONFIG_SENSORS_ARM_SCMI=y CONFIG_SENSORS_ARM_SCPI=y CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m CONFIG_SENSORS_LM90=m CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=m @@ -569,20 +580,21 @@ CONFIG_SENSORS_INA3221=m CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y CONFIG_THERMAL_EMULATION=y -CONFIG_QORIQ_THERMAL=m -CONFIG_SUN8I_THERMAL=y CONFIG_IMX_SC_THERMAL=m CONFIG_IMX8MM_THERMAL=m +CONFIG_QORIQ_THERMAL=m +CONFIG_SUN8I_THERMAL=y CONFIG_ROCKCHIP_THERMAL=m CONFIG_RCAR_THERMAL=y CONFIG_RCAR_GEN3_THERMAL=y +CONFIG_RZG2L_THERMAL=y CONFIG_ARMADA_THERMAL=y CONFIG_BCM2711_THERMAL=m CONFIG_BCM2835_THERMAL=m CONFIG_BRCMSTB_THERMAL=m CONFIG_EXYNOS_THERMAL=y -CONFIG_TEGRA_BPMP_THERMAL=m CONFIG_TEGRA_SOCTHERM=m +CONFIG_TEGRA_BPMP_THERMAL=m CONFIG_QCOM_TSENS=y CONFIG_QCOM_SPMI_TEMP_ALARM=m CONFIG_QCOM_LMH=m @@ -591,8 +603,8 @@ CONFIG_WATCHDOG=y CONFIG_SL28CPLD_WATCHDOG=m CONFIG_ARM_SP805_WATCHDOG=y CONFIG_ARM_SBSA_WATCHDOG=y -CONFIG_ARM_SMC_WATCHDOG=y CONFIG_S3C2410_WATCHDOG=y +CONFIG_BCM7038_WDT=m CONFIG_DW_WATCHDOG=y CONFIG_SUNXI_WATCHDOG=m CONFIG_IMX2_WDT=y @@ -600,7 +612,9 @@ CONFIG_IMX_SC_WDT=m CONFIG_QCOM_WDT=m CONFIG_MESON_GXBB_WATCHDOG=m CONFIG_MESON_WATCHDOG=m +CONFIG_ARM_SMC_WATCHDOG=y CONFIG_RENESAS_WDT=y +CONFIG_RENESAS_RZG2LWDT=y CONFIG_UNIPHIER_WATCHDOG=y CONFIG_BCM2835_WDT=y CONFIG_MFD_ALTERA_SYSMGR=y @@ -652,16 +666,16 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_ANALOG_TV_SUPPORT=y CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_CONTROLLER=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_MEDIA_PLATFORM_SUPPORT=y # CONFIG_DVB_NET is not set CONFIG_MEDIA_USB_SUPPORT=y CONFIG_USB_VIDEO_CLASS=m CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_RCAR_CSI2=m CONFIG_VIDEO_RCAR_VIN=m CONFIG_VIDEO_SUN6I_CSI=m +CONFIG_VIDEO_RCAR_ISP=m CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m @@ -675,7 +689,6 @@ CONFIG_VIDEO_RCAR_DRIF=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_OV5640=m CONFIG_VIDEO_OV5645=m -CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_DRM=m CONFIG_DRM_I2C_NXP_TDA998X=m CONFIG_DRM_MALI_DISPLAY=m @@ -696,30 +709,30 @@ CONFIG_ROCKCHIP_INNO_HDMI=y CONFIG_ROCKCHIP_LVDS=y CONFIG_DRM_RCAR_DU=m CONFIG_DRM_RCAR_DW_HDMI=m +CONFIG_DRM_RCAR_MIPI_DSI=m CONFIG_DRM_SUN4I=m CONFIG_DRM_SUN6I_DSI=m CONFIG_DRM_SUN8I_DW_HDMI=m CONFIG_DRM_SUN8I_MIXER=m CONFIG_DRM_MSM=m CONFIG_DRM_TEGRA=m +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m CONFIG_DRM_PANEL_LVDS=m CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_EDP=m -CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m CONFIG_DRM_PANEL_RAYDIUM_RM67191=m CONFIG_DRM_PANEL_SITRONIX_ST7703=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m -CONFIG_DRM_DISPLAY_CONNECTOR=m CONFIG_DRM_LONTIUM_LT8912B=m -CONFIG_DRM_NWL_MIPI_DSI=m CONFIG_DRM_LONTIUM_LT9611=m +CONFIG_DRM_LONTIUM_LT9611UXC=m +CONFIG_DRM_NWL_MIPI_DSI=m CONFIG_DRM_PARADE_PS8640=m CONFIG_DRM_SII902X=m CONFIG_DRM_SIMPLE_BRIDGE=m CONFIG_DRM_THINE_THC63LVD1024=m CONFIG_DRM_TI_SN65DSI86=m -CONFIG_DRM_LONTIUM_LT9611UXC=m CONFIG_DRM_I2C_ADV7511=m CONFIG_DRM_I2C_ADV7511_AUDIO=y CONFIG_DRM_DW_HDMI_AHB_AUDIO=m @@ -750,15 +763,14 @@ CONFIG_SND_HDA_TEGRA=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_SOC=y CONFIG_SND_BCM2835_SOC_I2S=m -CONFIG_SND_SOC_FSL_SAI=m CONFIG_SND_SOC_FSL_ASRC=m CONFIG_SND_SOC_FSL_MICFIL=m CONFIG_SND_SOC_FSL_EASRC=m CONFIG_SND_IMX_SOC=m CONFIG_SND_SOC_IMX_SGTL5000=m CONFIG_SND_SOC_IMX_SPDIF=m -CONFIG_SND_SOC_IMX_AUDMIX=m CONFIG_SND_SOC_FSL_ASOC_CARD=m +CONFIG_SND_SOC_IMX_AUDMIX=m CONFIG_SND_MESON_AXG_SOUND_CARD=m CONFIG_SND_MESON_GX_SOUND_CARD=m CONFIG_SND_SOC_QCOM=m @@ -805,18 +817,18 @@ CONFIG_SND_SOC_WM8960=m CONFIG_SND_SOC_WM8962=m CONFIG_SND_SOC_WM8978=m CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_NAU8822=m CONFIG_SND_SOC_LPASS_WSA_MACRO=m CONFIG_SND_SOC_LPASS_VA_MACRO=m CONFIG_SND_SIMPLE_CARD=m CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_SND_AUDIO_GRAPH_CARD2=m CONFIG_HID_MULTITOUCH=m CONFIG_I2C_HID_ACPI=m CONFIG_I2C_HID_OF=m -CONFIG_USB_CONN_GPIO=m CONFIG_USB=y CONFIG_USB_OTG=y CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PCI=m CONFIG_USB_XHCI_PCI_RENESAS=m CONFIG_USB_XHCI_TEGRA=y CONFIG_USB_EHCI_HCD=y @@ -829,6 +841,10 @@ CONFIG_USB_RENESAS_USBHS_HCD=m CONFIG_USB_RENESAS_USBHS=m CONFIG_USB_ACM=m CONFIG_USB_STORAGE=y +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y CONFIG_USB_MTU3=y CONFIG_USB_MUSB_HDRC=y CONFIG_USB_MUSB_SUNXI=y @@ -863,8 +879,8 @@ CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m CONFIG_TYPEC_FUSB302=m -CONFIG_TYPEC_HD3SS3220=m CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_HD3SS3220=m CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y @@ -935,16 +951,18 @@ CONFIG_RTC_DRV_TEGRA=y CONFIG_RTC_DRV_SNVS=m CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_XGENE=y +CONFIG_RTC_DRV_MT6397=m CONFIG_DMADEVICES=y CONFIG_DMA_BCM2835=y CONFIG_DMA_SUN6I=m CONFIG_FSL_EDMA=y -CONFIG_IMX_SDMA=y +CONFIG_IMX_SDMA=m CONFIG_K3_DMA=y CONFIG_MV_XOR=y CONFIG_MV_XOR_V2=y CONFIG_OWL_DMA=y CONFIG_PL330_DMA=y +CONFIG_TEGRA186_GPC_DMA=m CONFIG_TEGRA20_APB_DMA=y CONFIG_TEGRA210_ADMA=m CONFIG_QCOM_BAM_DMA=y @@ -962,7 +980,6 @@ CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_MMIO=y CONFIG_XEN_GNTDEV=y CONFIG_XEN_GRANT_DEV_ALLOC=y -CONFIG_MFD_CROS_EC_DEV=y CONFIG_STAGING=y CONFIG_STAGING_MEDIA=y CONFIG_VIDEO_HANTRO=m @@ -972,15 +989,14 @@ CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_CHARDEV=m -CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_RK808=y +CONFIG_COMMON_CLK_SCMI=y CONFIG_COMMON_CLK_SCPI=y CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_FSL_SAI=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_COMMON_CLK_PWM=y CONFIG_COMMON_CLK_VC5=y -CONFIG_COMMON_CLK_ZYNQMP=y CONFIG_COMMON_CLK_BD718XX=m CONFIG_CLK_RASPBERRYPI=m CONFIG_CLK_IMX8MM=y @@ -996,8 +1012,8 @@ CONFIG_QCOM_CLK_APCS_MSM8916=y CONFIG_QCOM_CLK_APCC_MSM8996=y CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y -CONFIG_IPQ_GCC_8074=y CONFIG_IPQ_GCC_6018=y +CONFIG_IPQ_GCC_8074=y CONFIG_MSM_GCC_8916=y CONFIG_MSM_GCC_8994=y CONFIG_MSM_MMCC_8996=y @@ -1006,21 +1022,19 @@ CONFIG_QCS_GCC_404=y CONFIG_SC_GCC_7180=y CONFIG_SC_GCC_7280=y CONFIG_SDM_CAMCC_845=m -CONFIG_SDM_GCC_845=y CONFIG_SDM_GPUCC_845=y CONFIG_SDM_VIDEOCC_845=y CONFIG_SDM_DISPCC_845=y -CONFIG_SM_GCC_8150=y -CONFIG_SM_GCC_8250=y CONFIG_SM_GCC_8350=y +CONFIG_SM_GCC_8450=y CONFIG_SM_GPUCC_8150=y CONFIG_SM_GPUCC_8250=y -CONFIG_SM_DISPCC_8250=y CONFIG_QCOM_HFPLL=y CONFIG_CLK_GFM_LPASS_SM8250=m CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y CONFIG_HWSPINLOCK=y CONFIG_HWSPINLOCK_QCOM=y +CONFIG_RENESAS_OSTM=y CONFIG_ARM_MHU=y CONFIG_IMX_MBOX=y CONFIG_PLATFORM_MHU=y @@ -1049,9 +1063,11 @@ CONFIG_RASPBERRYPI_POWER=y CONFIG_FSL_DPAA=y CONFIG_FSL_MC_DPIO=y CONFIG_FSL_RCPM=y +CONFIG_MTK_DEVAPC=m CONFIG_MTK_PMIC_WRAP=y CONFIG_QCOM_AOSS_QMP=y CONFIG_QCOM_COMMAND_DB=y +CONFIG_QCOM_CPR=y CONFIG_QCOM_GENI_SE=y CONFIG_QCOM_RMTFS_MEM=m CONFIG_QCOM_RPMH=y @@ -1062,25 +1078,26 @@ CONFIG_QCOM_SMD_RPM=y CONFIG_QCOM_SMP2P=y CONFIG_QCOM_SMSM=y CONFIG_QCOM_SOCINFO=m -CONFIG_QCOM_WCNSS_CTRL=m CONFIG_QCOM_STATS=m +CONFIG_QCOM_WCNSS_CTRL=m CONFIG_QCOM_APR=m -CONFIG_ARCH_R8A774A1=y -CONFIG_ARCH_R8A774B1=y -CONFIG_ARCH_R8A774C0=y -CONFIG_ARCH_R8A774E1=y +CONFIG_ARCH_R8A77995=y +CONFIG_ARCH_R8A77990=y CONFIG_ARCH_R8A77950=y CONFIG_ARCH_R8A77951=y +CONFIG_ARCH_R8A77965=y CONFIG_ARCH_R8A77960=y CONFIG_ARCH_R8A77961=y -CONFIG_ARCH_R8A77965=y -CONFIG_ARCH_R8A77970=y -CONFIG_ARCH_R8A77980=y -CONFIG_ARCH_R8A77990=y -CONFIG_ARCH_R8A77995=y -CONFIG_ARCH_R8A779A0=y CONFIG_ARCH_R8A779F0=y +CONFIG_ARCH_R8A77980=y +CONFIG_ARCH_R8A77970=y +CONFIG_ARCH_R8A779A0=y +CONFIG_ARCH_R8A774C0=y +CONFIG_ARCH_R8A774E1=y +CONFIG_ARCH_R8A774A1=y +CONFIG_ARCH_R8A774B1=y CONFIG_ARCH_R9A07G044=y +CONFIG_ROCKCHIP_IODOMAIN=y CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y @@ -1101,6 +1118,7 @@ CONFIG_QCOM_SPMI_VADC=m CONFIG_QCOM_SPMI_ADC5=m CONFIG_ROCKCHIP_SARADC=m CONFIG_RZG2L_ADC=m +CONFIG_TI_ADS1015=m CONFIG_IIO_CROS_EC_SENSORS_CORE=m CONFIG_IIO_CROS_EC_SENSORS=m CONFIG_IIO_ST_LSM6DSX=m @@ -1112,6 +1130,7 @@ CONFIG_IIO_CROS_EC_BARO=m CONFIG_MPL3115=m CONFIG_PWM=y CONFIG_PWM_BCM2835=m +CONFIG_PWM_BRCMSTB=m CONFIG_PWM_CROS_EC=m CONFIG_PWM_IMX27=m CONFIG_PWM_MESON=m @@ -1134,7 +1153,9 @@ CONFIG_RESET_RZG2L_USBPHY_CTRL=y CONFIG_RESET_TI_SCI=y CONFIG_PHY_XGENE=y CONFIG_PHY_SUN4I_USB=y +CONFIG_PHY_CADENCE_SIERRA=m CONFIG_PHY_MIXEL_MIPI_DPHY=m +CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_HI6220_USB=y CONFIG_PHY_HISTB_COMBPHY=y CONFIG_PHY_HISI_INNO_USB2=y @@ -1157,21 +1178,25 @@ CONFIG_PHY_SAMSUNG_UFS=y CONFIG_PHY_UNIPHIER_USB2=y CONFIG_PHY_UNIPHIER_USB3=y CONFIG_PHY_TEGRA_XUSB=y +CONFIG_PHY_AM654_SERDES=m +CONFIG_PHY_J721E_WIZ=m CONFIG_ARM_SMMU_V3_PMU=m CONFIG_FSL_IMX8_DDR_PMU=m -CONFIG_HISI_PMU=y CONFIG_QCOM_L2_PMU=y CONFIG_QCOM_L3_PMU=y +CONFIG_HISI_PMU=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_IMX_OCOTP_SCU=y -CONFIG_QCOM_QFPROM=y CONFIG_MTK_EFUSE=y +CONFIG_QCOM_QFPROM=y CONFIG_ROCKCHIP_EFUSE=y CONFIG_NVMEM_SUNXI_SID=y CONFIG_UNIPHIER_EFUSE=y CONFIG_MESON_EFUSE=m CONFIG_NVMEM_RMEM=m +CONFIG_NVMEM_LAYERSCAPE_SFP=m CONFIG_FPGA=y +CONFIG_FPGA_MGR_ALTERA_CVP=m CONFIG_FPGA_MGR_STRATIX10_SOC=m CONFIG_FPGA_BRIDGE=m CONFIG_ALTERA_FREEZE_BRIDGE=m @@ -1179,10 +1204,10 @@ CONFIG_FPGA_REGION=m CONFIG_OF_FPGA_REGION=m CONFIG_TEE=y CONFIG_OPTEE=y +CONFIG_MUX_MMIO=y CONFIG_SLIMBUS=m CONFIG_SLIM_QCOM_CTRL=m CONFIG_SLIM_QCOM_NGD_CTRL=m -CONFIG_MUX_MMIO=y CONFIG_INTERCONNECT=y CONFIG_INTERCONNECT_IMX=m CONFIG_INTERCONNECT_IMX8MM=m @@ -1196,6 +1221,7 @@ CONFIG_INTERCONNECT_QCOM_SDM845=y CONFIG_INTERCONNECT_QCOM_SM8150=m CONFIG_INTERCONNECT_QCOM_SM8250=m CONFIG_INTERCONNECT_QCOM_SM8350=m +CONFIG_INTERCONNECT_QCOM_SM8450=m CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_POSIX_ACL=y diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 3a5ff5e20586..e8dce0cc5eaa 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -26,7 +26,7 @@ #include #include -#define HAVE_GET_KERNEL_NOFAULT +static inline int __access_ok(const void __user *ptr, unsigned long size); /* * Test whether a block of memory is a valid user space address. @@ -35,10 +35,8 @@ * This is equivalent to the following test: * (u65)addr + (u65)size <= (u65)TASK_SIZE_MAX */ -static inline unsigned long __range_ok(const void __user *addr, unsigned long size) +static inline int access_ok(const void __user *addr, unsigned long size) { - unsigned long ret, limit = TASK_SIZE_MAX - 1; - /* * Asynchronous I/O running in a kernel thread does not have the * TIF_TAGGED_ADDR flag of the process owning the mm, so always untag @@ -48,28 +46,11 @@ static inline unsigned long __range_ok(const void __user *addr, unsigned long si (current->flags & PF_KTHREAD || test_thread_flag(TIF_TAGGED_ADDR))) addr = untagged_addr(addr); - __chk_user_ptr(addr); - asm volatile( - // A + B <= C + 1 for all A,B,C, in four easy steps: - // 1: X = A + B; X' = X % 2^64 - " adds %0, %3, %2\n" - // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4 - " csel %1, xzr, %1, hi\n" - // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X' - // to compensate for the carry flag being set in step 4. For - // X > 2^64, X' merely has to remain nonzero, which it does. - " csinv %0, %0, xzr, cc\n" - // 4: For X < 2^64, this gives us X' - C - 1 <= 0, where the -1 - // comes from the carry in being clear. Otherwise, we are - // testing X' - C == 0, subject to the previous adjustments. - " sbcs xzr, %0, %1\n" - " cset %0, ls\n" - : "=&r" (ret), "+r" (limit) : "Ir" (size), "0" (addr) : "cc"); - - return ret; + return likely(__access_ok(addr, size)); } +#define access_ok access_ok -#define access_ok(addr, size) __range_ok(addr, size) +#include /* * User access enabling/disabling. diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index bb878f52ca0a..0529fd57567e 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -518,7 +518,7 @@ void do_ptrauth_fault(struct pt_regs *regs, unsigned int esr) NOKPROBE_SYMBOL(do_ptrauth_fault); #define __user_cache_maint(insn, address, res) \ - if (address >= user_addr_max()) { \ + if (address >= TASK_SIZE_MAX) { \ res = -EFAULT; \ } else { \ uaccess_ttbr0_enable(); \ diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig index 132f43f12dd8..75ef86605d69 100644 --- a/arch/csky/Kconfig +++ b/arch/csky/Kconfig @@ -79,7 +79,6 @@ config CSKY select PCI_DOMAINS_GENERIC if PCI select PCI_SYSCALL if PCI select PCI_MSI if PCI - select SET_FS select TRACE_IRQFLAGS_SUPPORT config LOCKDEP_SUPPORT diff --git a/arch/csky/include/asm/processor.h b/arch/csky/include/asm/processor.h index 817dd60ff152..688c7548b559 100644 --- a/arch/csky/include/asm/processor.h +++ b/arch/csky/include/asm/processor.h @@ -4,7 +4,6 @@ #define __ASM_CSKY_PROCESSOR_H #include -#include #include #include #include @@ -59,7 +58,6 @@ struct thread_struct { */ #define start_thread(_regs, _pc, _usp) \ do { \ - set_fs(USER_DS); /* reads from user space */ \ (_regs)->pc = (_pc); \ (_regs)->regs[1] = 0; /* ABIV1 is R7, uClibc_main rtdl arg */ \ (_regs)->regs[2] = 0; \ diff --git a/arch/csky/include/asm/segment.h b/arch/csky/include/asm/segment.h deleted file mode 100644 index 5bc1cc62b87f..000000000000 --- a/arch/csky/include/asm/segment.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef __ASM_CSKY_SEGMENT_H -#define __ASM_CSKY_SEGMENT_H - -typedef struct { - unsigned long seg; -} mm_segment_t; - -#endif /* __ASM_CSKY_SEGMENT_H */ diff --git a/arch/csky/include/asm/thread_info.h b/arch/csky/include/asm/thread_info.h index 8c349a8f904d..b5ed788f0c68 100644 --- a/arch/csky/include/asm/thread_info.h +++ b/arch/csky/include/asm/thread_info.h @@ -16,7 +16,6 @@ struct thread_info { unsigned long flags; int preempt_count; unsigned long tp_value; - mm_segment_t addr_limit; struct restart_block restart_block; struct pt_regs *regs; unsigned int cpu; @@ -26,7 +25,6 @@ struct thread_info { { \ .task = &tsk, \ .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ .cpu = 0, \ .restart_block = { \ .fn = do_no_restart_syscall, \ diff --git a/arch/csky/include/asm/uaccess.h b/arch/csky/include/asm/uaccess.h index c40f06ee8d3e..2e927c21d8a1 100644 --- a/arch/csky/include/asm/uaccess.h +++ b/arch/csky/include/asm/uaccess.h @@ -3,17 +3,6 @@ #ifndef __ASM_CSKY_UACCESS_H #define __ASM_CSKY_UACCESS_H -#define user_addr_max() \ - (uaccess_kernel() ? KERNEL_DS.seg : get_fs().seg) - -static inline int __access_ok(unsigned long addr, unsigned long size) -{ - unsigned long limit = current_thread_info()->addr_limit.seg; - - return ((addr < limit) && ((addr + size) < limit)); -} -#define __access_ok __access_ok - /* * __put_user_fn */ @@ -209,7 +198,6 @@ unsigned long raw_copy_to_user(void *to, const void *from, unsigned long n); unsigned long __clear_user(void __user *to, unsigned long n); #define __clear_user __clear_user -#include #include #endif /* __ASM_CSKY_UACCESS_H */ diff --git a/arch/csky/kernel/asm-offsets.c b/arch/csky/kernel/asm-offsets.c index 1cbcba4b0dd1..d1e903579473 100644 --- a/arch/csky/kernel/asm-offsets.c +++ b/arch/csky/kernel/asm-offsets.c @@ -25,7 +25,6 @@ int main(void) /* offsets into the thread_info struct */ DEFINE(TINFO_FLAGS, offsetof(struct thread_info, flags)); DEFINE(TINFO_PREEMPT, offsetof(struct thread_info, preempt_count)); - DEFINE(TINFO_ADDR_LIMIT, offsetof(struct thread_info, addr_limit)); DEFINE(TINFO_TP_VALUE, offsetof(struct thread_info, tp_value)); DEFINE(TINFO_TASK, offsetof(struct thread_info, task)); diff --git a/arch/csky/kernel/perf_callchain.c b/arch/csky/kernel/perf_callchain.c index 92057de08f4f..1612f4354087 100644 --- a/arch/csky/kernel/perf_callchain.c +++ b/arch/csky/kernel/perf_callchain.c @@ -49,7 +49,7 @@ static unsigned long user_backtrace(struct perf_callchain_entry_ctx *entry, { struct stackframe buftail; unsigned long lr = 0; - unsigned long *user_frame_tail = (unsigned long *)fp; + unsigned long __user *user_frame_tail = (unsigned long __user *)fp; /* Check accessibility of one struct frame_tail beyond */ if (!access_ok(user_frame_tail, sizeof(buftail))) diff --git a/arch/csky/kernel/signal.c b/arch/csky/kernel/signal.c index c7b763d2f526..8867ddf3e6c7 100644 --- a/arch/csky/kernel/signal.c +++ b/arch/csky/kernel/signal.c @@ -136,7 +136,7 @@ static inline void __user *get_sigframe(struct ksignal *ksig, static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) { - struct rt_sigframe *frame; + struct rt_sigframe __user *frame; int err = 0; frame = get_sigframe(ksig, regs, sizeof(*frame)); diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig index 3e3e0f16f7e0..fe48c4f26cc8 100644 --- a/arch/h8300/Kconfig +++ b/arch/h8300/Kconfig @@ -24,7 +24,6 @@ config H8300 select HAVE_ARCH_KGDB select HAVE_ARCH_HASH select CPU_NO_EFFICIENT_FFS - select SET_FS select UACCESS_MEMCPY config CPU_BIG_ENDIAN diff --git a/arch/h8300/include/asm/processor.h b/arch/h8300/include/asm/processor.h index 141a23eb62b7..ba171aa4dacb 100644 --- a/arch/h8300/include/asm/processor.h +++ b/arch/h8300/include/asm/processor.h @@ -13,7 +13,6 @@ #define __ASM_H8300_PROCESSOR_H #include -#include #include #include diff --git a/arch/h8300/include/asm/segment.h b/arch/h8300/include/asm/segment.h deleted file mode 100644 index 37950725d9b9..000000000000 --- a/arch/h8300/include/asm/segment.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _H8300_SEGMENT_H -#define _H8300_SEGMENT_H - -/* define constants */ -#define USER_DATA (1) -#ifndef __USER_DS -#define __USER_DS (USER_DATA) -#endif -#define USER_PROGRAM (2) -#define SUPER_DATA (3) -#ifndef __KERNEL_DS -#define __KERNEL_DS (SUPER_DATA) -#endif -#define SUPER_PROGRAM (4) - -#ifndef __ASSEMBLY__ - -typedef struct { - unsigned long seg; -} mm_segment_t; - -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) -#define USER_DS MAKE_MM_SEG(__USER_DS) -#define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS) - -/* - * Get/set the SFC/DFC registers for MOVES instructions - */ - -static inline mm_segment_t get_fs(void) -{ - return USER_DS; -} - -#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) - -#endif /* __ASSEMBLY__ */ - -#endif /* _H8300_SEGMENT_H */ diff --git a/arch/h8300/include/asm/thread_info.h b/arch/h8300/include/asm/thread_info.h index a518214d4ddd..ff2d873749a4 100644 --- a/arch/h8300/include/asm/thread_info.h +++ b/arch/h8300/include/asm/thread_info.h @@ -10,7 +10,6 @@ #define _ASM_THREAD_INFO_H #include -#include #ifdef __KERNEL__ @@ -31,7 +30,6 @@ struct thread_info { unsigned long flags; /* low level flags */ int cpu; /* cpu we're on */ int preempt_count; /* 0 => preemptable, <0 => BUG */ - mm_segment_t addr_limit; }; /* @@ -43,7 +41,6 @@ struct thread_info { .flags = 0, \ .cpu = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ } /* how to get the thread information struct from C */ diff --git a/arch/h8300/include/uapi/asm/signal.h b/arch/h8300/include/uapi/asm/signal.h index 2cd0dce2b6a6..1165481f80f6 100644 --- a/arch/h8300/include/uapi/asm/signal.h +++ b/arch/h8300/include/uapi/asm/signal.h @@ -85,7 +85,7 @@ struct sigaction { typedef struct sigaltstack { void *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; diff --git a/arch/h8300/kernel/entry.S b/arch/h8300/kernel/entry.S index c6e289b5f1f2..42db87c17917 100644 --- a/arch/h8300/kernel/entry.S +++ b/arch/h8300/kernel/entry.S @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/h8300/kernel/head_ram.S b/arch/h8300/kernel/head_ram.S index dbf8429f5fab..489462f0ee57 100644 --- a/arch/h8300/kernel/head_ram.S +++ b/arch/h8300/kernel/head_ram.S @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/h8300/mm/init.c b/arch/h8300/mm/init.c index f7bf4693e3b2..9fa13312720a 100644 --- a/arch/h8300/mm/init.c +++ b/arch/h8300/mm/init.c @@ -34,7 +34,6 @@ #include #include -#include #include #include @@ -71,11 +70,6 @@ void __init paging_init(void) panic("%s: Failed to allocate %lu bytes align=0x%lx\n", __func__, PAGE_SIZE, PAGE_SIZE); - /* - * Set up SFC/DFC registers (user data space). - */ - set_fs(USER_DS); - pr_debug("before free_area_init\n"); pr_debug("free_area_init -> start_mem is %#lx\nvirtual_end is %#lx\n", diff --git a/arch/h8300/mm/memory.c b/arch/h8300/mm/memory.c index 4a60e2b5eb96..c950571064d2 100644 --- a/arch/h8300/mm/memory.c +++ b/arch/h8300/mm/memory.c @@ -24,7 +24,6 @@ #include #include -#include #include #include #include diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig index 15dd8f38b698..54eadf265178 100644 --- a/arch/hexagon/Kconfig +++ b/arch/hexagon/Kconfig @@ -30,7 +30,6 @@ config HEXAGON select GENERIC_CLOCKEVENTS_BROADCAST select MODULES_USE_ELF_RELA select GENERIC_CPU_DEVICES - select SET_FS select ARCH_WANT_LD_ORPHAN_WARN select TRACE_IRQFLAGS_SUPPORT help diff --git a/arch/hexagon/include/asm/thread_info.h b/arch/hexagon/include/asm/thread_info.h index 535976665bf0..e90f280b9ce3 100644 --- a/arch/hexagon/include/asm/thread_info.h +++ b/arch/hexagon/include/asm/thread_info.h @@ -22,10 +22,6 @@ #ifndef __ASSEMBLY__ -typedef struct { - unsigned long seg; -} mm_segment_t; - /* * This is union'd with the "bottom" of the kernel stack. * It keeps track of thread info which is handy for routines @@ -37,7 +33,6 @@ struct thread_info { unsigned long flags; /* low level flags */ __u32 cpu; /* current cpu */ int preempt_count; /* 0=>preemptible,<0=>BUG */ - mm_segment_t addr_limit; /* segmentation sux */ /* * used for syscalls somehow; * seems to have a function pointer and four arguments @@ -66,7 +61,6 @@ struct thread_info { .flags = 0, \ .cpu = 0, \ .preempt_count = 1, \ - .addr_limit = KERNEL_DS, \ .sp = 0, \ .regs = NULL, \ } diff --git a/arch/hexagon/include/asm/uaccess.h b/arch/hexagon/include/asm/uaccess.h index ef5bfef8d490..bff77efc0d9a 100644 --- a/arch/hexagon/include/asm/uaccess.h +++ b/arch/hexagon/include/asm/uaccess.h @@ -12,31 +12,6 @@ */ #include -/* - * access_ok: - Checks if a user space pointer is valid - * @addr: User space pointer to start of block to check - * @size: Size of block to check - * - * Context: User context only. This function may sleep if pagefaults are - * enabled. - * - * Checks if a pointer to a block of memory in user space is valid. - * - * Returns true (nonzero) if the memory block *may* be valid, false (zero) - * if it is definitely invalid. - * - * User address space in Hexagon, like x86, goes to 0xbfffffff, so the - * simple MSB-based tests used by MIPS won't work. Some further - * optimization is probably possible here, but for now, keep it - * reasonably simple and not *too* slow. After all, we've got the - * MMU for backup. - */ - -#define __access_ok(addr, size) \ - ((get_fs().seg == KERNEL_DS.seg) || \ - (((unsigned long)addr < get_fs().seg) && \ - (unsigned long)size < (get_fs().seg - (unsigned long)addr))) - /* * When a kernel-mode page fault is taken, the faulting instruction * address is checked against a table of exception_table_entries. diff --git a/arch/hexagon/kernel/process.c b/arch/hexagon/kernel/process.c index 232dfd8956aa..dfa6b2757c05 100644 --- a/arch/hexagon/kernel/process.c +++ b/arch/hexagon/kernel/process.c @@ -105,7 +105,6 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, unsigned long arg, /* * Parent sees new pid -- not necessary, not even possible at * this point in the fork process - * Might also want to set things like ti->addr_limit */ return 0; diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index e003b2473c64..b2317324827f 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -62,7 +62,6 @@ config IA64 select NEED_SG_DMA_LENGTH select NUMA if !FLATMEM select PCI_MSI_ARCH_FALLBACKS if PCI_MSI - select SET_FS select ZONE_DMA32 default y help diff --git a/arch/ia64/include/asm/processor.h b/arch/ia64/include/asm/processor.h index 45365c2ef598..7cbce290f4e5 100644 --- a/arch/ia64/include/asm/processor.h +++ b/arch/ia64/include/asm/processor.h @@ -243,10 +243,6 @@ DECLARE_PER_CPU(struct cpuinfo_ia64, ia64_cpu_info); extern void print_cpu_info (struct cpuinfo_ia64 *); -typedef struct { - unsigned long seg; -} mm_segment_t; - #define SET_UNALIGN_CTL(task,value) \ ({ \ (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \ diff --git a/arch/ia64/include/asm/thread_info.h b/arch/ia64/include/asm/thread_info.h index 1684716f0820..21b257117e0a 100644 --- a/arch/ia64/include/asm/thread_info.h +++ b/arch/ia64/include/asm/thread_info.h @@ -27,7 +27,6 @@ struct thread_info { __u32 cpu; /* current CPU */ __u32 last_cpu; /* Last CPU thread ran on */ __u32 status; /* Thread synchronous flags */ - mm_segment_t addr_limit; /* user-level address space limit */ int preempt_count; /* 0=premptable, <0=BUG; will also serve as bh-counter */ #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE __u64 utime; @@ -48,7 +47,6 @@ struct thread_info { .task = &tsk, \ .flags = 0, \ .cpu = 0, \ - .addr_limit = KERNEL_DS, \ .preempt_count = INIT_PREEMPT_COUNT, \ } diff --git a/arch/ia64/include/asm/uaccess.h b/arch/ia64/include/asm/uaccess.h index e19d2dcc0ced..60adadeb3e9e 100644 --- a/arch/ia64/include/asm/uaccess.h +++ b/arch/ia64/include/asm/uaccess.h @@ -42,30 +42,20 @@ #include /* - * For historical reasons, the following macros are grossly misnamed: - */ -#define KERNEL_DS ((mm_segment_t) { ~0UL }) /* cf. access_ok() */ -#define USER_DS ((mm_segment_t) { TASK_SIZE-1 }) /* cf. access_ok() */ - -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(x) (current_thread_info()->addr_limit = (x)) - -#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) - -/* - * When accessing user memory, we need to make sure the entire area really is in - * user-level space. In order to do this efficiently, we make sure that the page at - * address TASK_SIZE is never valid. We also need to make sure that the address doesn't + * When accessing user memory, we need to make sure the entire area really is + * in user-level space. We also need to make sure that the address doesn't * point inside the virtually mapped linear page table. */ static inline int __access_ok(const void __user *p, unsigned long size) { + unsigned long limit = TASK_SIZE; unsigned long addr = (unsigned long)p; - unsigned long seg = get_fs().seg; - return likely(addr <= seg) && - (seg == KERNEL_DS.seg || likely(REGION_OFFSET(addr) < RGN_MAP_LIMIT)); + + return likely((size <= limit) && (addr <= (limit - size)) && + likely(REGION_OFFSET(addr) < RGN_MAP_LIMIT)); } -#define access_ok(addr, size) __access_ok((addr), (size)) +#define __access_ok __access_ok +#include /* * These are the main single-value transfer routines. They automatically diff --git a/arch/ia64/include/uapi/asm/signal.h b/arch/ia64/include/uapi/asm/signal.h index 38166a88e4c9..63d574e802a2 100644 --- a/arch/ia64/include/uapi/asm/signal.h +++ b/arch/ia64/include/uapi/asm/signal.h @@ -90,7 +90,7 @@ struct siginfo; typedef struct sigaltstack { void __user *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; diff --git a/arch/ia64/kernel/unaligned.c b/arch/ia64/kernel/unaligned.c index 6c1a8951dfbb..0acb5a0cd7ab 100644 --- a/arch/ia64/kernel/unaligned.c +++ b/arch/ia64/kernel/unaligned.c @@ -749,9 +749,25 @@ emulate_load_updates (update_t type, load_store_t ld, struct pt_regs *regs, unsi } } +static int emulate_store(unsigned long ifa, void *val, int len, bool kernel_mode) +{ + if (kernel_mode) + return copy_to_kernel_nofault((void *)ifa, val, len); + + return copy_to_user((void __user *)ifa, val, len); +} + +static int emulate_load(void *val, unsigned long ifa, int len, bool kernel_mode) +{ + if (kernel_mode) + return copy_from_kernel_nofault(val, (void *)ifa, len); + + return copy_from_user(val, (void __user *)ifa, len); +} static int -emulate_load_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs) +emulate_load_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs, + bool kernel_mode) { unsigned int len = 1 << ld.x6_sz; unsigned long val = 0; @@ -774,7 +790,7 @@ emulate_load_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs) return -1; } /* this assumes little-endian byte-order: */ - if (copy_from_user(&val, (void __user *) ifa, len)) + if (emulate_load(&val, ifa, len, kernel_mode)) return -1; setreg(ld.r1, val, 0, regs); @@ -872,7 +888,8 @@ emulate_load_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs) } static int -emulate_store_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs) +emulate_store_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs, + bool kernel_mode) { unsigned long r2; unsigned int len = 1 << ld.x6_sz; @@ -901,7 +918,7 @@ emulate_store_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs) } /* this assumes little-endian byte-order: */ - if (copy_to_user((void __user *) ifa, &r2, len)) + if (emulate_store(ifa, &r2, len, kernel_mode)) return -1; /* @@ -1021,7 +1038,7 @@ float2mem_double (struct ia64_fpreg *init, struct ia64_fpreg *final) } static int -emulate_load_floatpair (unsigned long ifa, load_store_t ld, struct pt_regs *regs) +emulate_load_floatpair (unsigned long ifa, load_store_t ld, struct pt_regs *regs, bool kernel_mode) { struct ia64_fpreg fpr_init[2]; struct ia64_fpreg fpr_final[2]; @@ -1050,8 +1067,8 @@ emulate_load_floatpair (unsigned long ifa, load_store_t ld, struct pt_regs *regs * This assumes little-endian byte-order. Note that there is no "ldfpe" * instruction: */ - if (copy_from_user(&fpr_init[0], (void __user *) ifa, len) - || copy_from_user(&fpr_init[1], (void __user *) (ifa + len), len)) + if (emulate_load(&fpr_init[0], ifa, len, kernel_mode) + || emulate_load(&fpr_init[1], (ifa + len), len, kernel_mode)) return -1; DPRINT("ld.r1=%d ld.imm=%d x6_sz=%d\n", ld.r1, ld.imm, ld.x6_sz); @@ -1126,7 +1143,8 @@ emulate_load_floatpair (unsigned long ifa, load_store_t ld, struct pt_regs *regs static int -emulate_load_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs) +emulate_load_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs, + bool kernel_mode) { struct ia64_fpreg fpr_init; struct ia64_fpreg fpr_final; @@ -1152,7 +1170,7 @@ emulate_load_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs) * See comments in ldX for descriptions on how the various loads are handled. */ if (ld.x6_op != 0x2) { - if (copy_from_user(&fpr_init, (void __user *) ifa, len)) + if (emulate_load(&fpr_init, ifa, len, kernel_mode)) return -1; DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz); @@ -1202,7 +1220,8 @@ emulate_load_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs) static int -emulate_store_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs) +emulate_store_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs, + bool kernel_mode) { struct ia64_fpreg fpr_init; struct ia64_fpreg fpr_final; @@ -1244,7 +1263,7 @@ emulate_store_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs) DDUMP("fpr_init =", &fpr_init, len); DDUMP("fpr_final =", &fpr_final, len); - if (copy_to_user((void __user *) ifa, &fpr_final, len)) + if (emulate_store(ifa, &fpr_final, len, kernel_mode)) return -1; /* @@ -1295,7 +1314,6 @@ void ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) { struct ia64_psr *ipsr = ia64_psr(regs); - mm_segment_t old_fs = get_fs(); unsigned long bundle[2]; unsigned long opcode; const struct exception_table_entry *eh = NULL; @@ -1304,6 +1322,7 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) load_store_t insn; } u; int ret = -1; + bool kernel_mode = false; if (ia64_psr(regs)->be) { /* we don't support big-endian accesses */ @@ -1367,13 +1386,13 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) if (unaligned_dump_stack) dump_stack(); } - set_fs(KERNEL_DS); + kernel_mode = true; } DPRINT("iip=%lx ifa=%lx isr=%lx (ei=%d, sp=%d)\n", regs->cr_iip, ifa, regs->cr_ipsr, ipsr->ri, ipsr->it); - if (__copy_from_user(bundle, (void __user *) regs->cr_iip, 16)) + if (emulate_load(bundle, regs->cr_iip, 16, kernel_mode)) goto failure; /* @@ -1467,7 +1486,7 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) case LDCCLR_IMM_OP: case LDCNC_IMM_OP: case LDCCLRACQ_IMM_OP: - ret = emulate_load_int(ifa, u.insn, regs); + ret = emulate_load_int(ifa, u.insn, regs, kernel_mode); break; case ST_OP: @@ -1478,7 +1497,7 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) fallthrough; case ST_IMM_OP: case STREL_IMM_OP: - ret = emulate_store_int(ifa, u.insn, regs); + ret = emulate_store_int(ifa, u.insn, regs, kernel_mode); break; case LDF_OP: @@ -1486,21 +1505,21 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) case LDFCCLR_OP: case LDFCNC_OP: if (u.insn.x) - ret = emulate_load_floatpair(ifa, u.insn, regs); + ret = emulate_load_floatpair(ifa, u.insn, regs, kernel_mode); else - ret = emulate_load_float(ifa, u.insn, regs); + ret = emulate_load_float(ifa, u.insn, regs, kernel_mode); break; case LDF_IMM_OP: case LDFA_IMM_OP: case LDFCCLR_IMM_OP: case LDFCNC_IMM_OP: - ret = emulate_load_float(ifa, u.insn, regs); + ret = emulate_load_float(ifa, u.insn, regs, kernel_mode); break; case STF_OP: case STF_IMM_OP: - ret = emulate_store_float(ifa, u.insn, regs); + ret = emulate_store_float(ifa, u.insn, regs, kernel_mode); break; default: @@ -1521,7 +1540,6 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) DPRINT("ipsr->ri=%d iip=%lx\n", ipsr->ri, regs->cr_iip); done: - set_fs(old_fs); /* restore original address limit */ return; failure: diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu index 0d00ef5117dc..16ea9a67723c 100644 --- a/arch/m68k/Kconfig.cpu +++ b/arch/m68k/Kconfig.cpu @@ -453,6 +453,7 @@ config CPU_HAS_NO_UNALIGNED config CPU_HAS_ADDRESS_SPACES bool + select ALTERNATE_USER_ADDRESS_SPACE config FPU bool diff --git a/arch/m68k/include/asm/uaccess.h b/arch/m68k/include/asm/uaccess.h index ba670523885c..64914872a5c9 100644 --- a/arch/m68k/include/asm/uaccess.h +++ b/arch/m68k/include/asm/uaccess.h @@ -10,17 +10,7 @@ #include #include #include - -/* We let the MMU do all checking */ -static inline int access_ok(const void __user *addr, - unsigned long size) -{ - /* - * XXX: for !CONFIG_CPU_HAS_ADDRESS_SPACES this really needs to check - * for TASK_SIZE! - */ - return 1; -} +#include /* * Not all varients of the 68k family support the notion of address spaces. @@ -390,8 +380,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) #define INLINE_COPY_FROM_USER #define INLINE_COPY_TO_USER -#define HAVE_GET_KERNEL_NOFAULT - #define __get_kernel_nofault(dst, src, type, err_label) \ do { \ type *__gk_dst = (type *)(dst); \ diff --git a/arch/m68k/include/uapi/asm/signal.h b/arch/m68k/include/uapi/asm/signal.h index 4619291df601..80f520b9b10b 100644 --- a/arch/m68k/include/uapi/asm/signal.h +++ b/arch/m68k/include/uapi/asm/signal.h @@ -83,7 +83,7 @@ struct sigaction { typedef struct sigaltstack { void __user *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; #endif /* _UAPI_M68K_SIGNAL_H */ diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index da568e981604..8cf429ad1c84 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -42,7 +42,6 @@ config MICROBLAZE select CPU_NO_EFFICIENT_FFS select MMU_GATHER_NO_RANGE select SPARSE_IRQ - select SET_FS select ZONE_DMA select TRACE_IRQFLAGS_SUPPORT select GENERIC_IRQ_MULTI_HANDLER diff --git a/arch/microblaze/include/asm/thread_info.h b/arch/microblaze/include/asm/thread_info.h index 44f5ca331862..a0ddd2a36fb9 100644 --- a/arch/microblaze/include/asm/thread_info.h +++ b/arch/microblaze/include/asm/thread_info.h @@ -56,17 +56,12 @@ struct cpu_context { __u32 fsr; }; -typedef struct { - unsigned long seg; -} mm_segment_t; - struct thread_info { struct task_struct *task; /* main task structure */ unsigned long flags; /* low level flags */ unsigned long status; /* thread-synchronous flags */ __u32 cpu; /* current CPU */ __s32 preempt_count; /* 0 => preemptable,< 0 => BUG*/ - mm_segment_t addr_limit; /* thread address space */ struct cpu_context cpu_context; }; @@ -80,7 +75,6 @@ struct thread_info { .flags = 0, \ .cpu = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ } /* how to get the thread information struct from C */ diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h index d2a8ef9f8978..3aab2f17e046 100644 --- a/arch/microblaze/include/asm/uaccess.h +++ b/arch/microblaze/include/asm/uaccess.h @@ -15,48 +15,7 @@ #include #include #include - -/* - * On Microblaze the fs value is actually the top of the corresponding - * address space. - * - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - * - * For historical reasons, these macros are grossly misnamed. - * - * For non-MMU arch like Microblaze, KERNEL_DS and USER_DS is equal. - */ -# define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) - -# define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFF) -# define USER_DS MAKE_MM_SEG(TASK_SIZE - 1) - -# define get_fs() (current_thread_info()->addr_limit) -# define set_fs(val) (current_thread_info()->addr_limit = (val)) -# define user_addr_max() get_fs().seg - -# define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) - -static inline int access_ok(const void __user *addr, unsigned long size) -{ - if (!size) - goto ok; - - if ((get_fs().seg < ((unsigned long)addr)) || - (get_fs().seg < ((unsigned long)addr + size - 1))) { - pr_devel("ACCESS fail at 0x%08x (size 0x%x), seg 0x%08x\n", - (__force u32)addr, (u32)size, - (u32)get_fs().seg); - return 0; - } -ok: - pr_devel("ACCESS OK at 0x%08x (size 0x%x), seg 0x%08x\n", - (__force u32)addr, (u32)size, - (u32)get_fs().seg); - return 1; -} +#include # define __FIXUP_SECTION ".section .fixup,\"ax\"\n" # define __EX_TABLE_SECTION ".section __ex_table,\"a\"\n" @@ -141,27 +100,27 @@ extern long __user_bad(void); #define __get_user(x, ptr) \ ({ \ - unsigned long __gu_val = 0; \ long __gu_err; \ switch (sizeof(*(ptr))) { \ case 1: \ - __get_user_asm("lbu", (ptr), __gu_val, __gu_err); \ + __get_user_asm("lbu", (ptr), x, __gu_err); \ break; \ case 2: \ - __get_user_asm("lhu", (ptr), __gu_val, __gu_err); \ + __get_user_asm("lhu", (ptr), x, __gu_err); \ break; \ case 4: \ - __get_user_asm("lw", (ptr), __gu_val, __gu_err); \ + __get_user_asm("lw", (ptr), x, __gu_err); \ break; \ - case 8: \ - __gu_err = __copy_from_user(&__gu_val, ptr, 8); \ - if (__gu_err) \ - __gu_err = -EFAULT; \ + case 8: { \ + __u64 __x = 0; \ + __gu_err = raw_copy_from_user(&__x, ptr, 8) ? \ + -EFAULT : 0; \ + (x) = (typeof(x))(typeof((x) - (x)))__x; \ break; \ + } \ default: \ /* __gu_val = 0; __gu_err = -EINVAL;*/ __gu_err = __user_bad();\ } \ - x = (__force __typeof__(*(ptr))) __gu_val; \ __gu_err; \ }) diff --git a/arch/microblaze/kernel/asm-offsets.c b/arch/microblaze/kernel/asm-offsets.c index b77dd188dec4..47ee409508b1 100644 --- a/arch/microblaze/kernel/asm-offsets.c +++ b/arch/microblaze/kernel/asm-offsets.c @@ -86,7 +86,6 @@ int main(int argc, char *argv[]) /* struct thread_info */ DEFINE(TI_TASK, offsetof(struct thread_info, task)); DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); - DEFINE(TI_ADDR_LIMIT, offsetof(struct thread_info, addr_limit)); DEFINE(TI_CPU_CONTEXT, offsetof(struct thread_info, cpu_context)); DEFINE(TI_PREEMPT_COUNT, offsetof(struct thread_info, preempt_count)); BLANK(); diff --git a/arch/microblaze/kernel/process.c b/arch/microblaze/kernel/process.c index 5e2b91c1e8ce..1b944d319d73 100644 --- a/arch/microblaze/kernel/process.c +++ b/arch/microblaze/kernel/process.c @@ -18,7 +18,6 @@ #include #include #include -#include /* for USER_DS macros */ #include void show_regs(struct pt_regs *regs) diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h index f8f74f9f5883..c0cede273c7c 100644 --- a/arch/mips/include/asm/uaccess.h +++ b/arch/mips/include/asm/uaccess.h @@ -19,6 +19,7 @@ #ifdef CONFIG_32BIT #define __UA_LIMIT 0x80000000UL +#define TASK_SIZE_MAX KSEG0 #define __UA_ADDR ".word" #define __UA_LA "la" @@ -33,6 +34,7 @@ extern u64 __ua_limit; #define __UA_LIMIT __ua_limit +#define TASK_SIZE_MAX XKSSEG #define __UA_ADDR ".dword" #define __UA_LA "dla" @@ -42,50 +44,7 @@ extern u64 __ua_limit; #endif /* CONFIG_64BIT */ -/* - * Is a address valid? This does a straightforward calculation rather - * than tests. - * - * Address valid if: - * - "addr" doesn't have any high-bits set - * - AND "size" doesn't have any high-bits set - * - AND "addr+size" doesn't have any high-bits set - * - OR we are in kernel mode. - * - * __ua_size() is a trick to avoid runtime checking of positive constant - * sizes; for those we already know at compile time that the size is ok. - */ -#define __ua_size(size) \ - ((__builtin_constant_p(size) && (signed long) (size) > 0) ? 0 : (size)) - -/* - * access_ok: - Checks if a user space pointer is valid - * @addr: User space pointer to start of block to check - * @size: Size of block to check - * - * Context: User context only. This function may sleep if pagefaults are - * enabled. - * - * Checks if a pointer to a block of memory in user space is valid. - * - * Returns true (nonzero) if the memory block may be valid, false (zero) - * if it is definitely invalid. - * - * Note that, depending on architecture, this function probably just - * checks that the pointer is in the user space range - after calling - * this function, memory access functions may still return -EFAULT. - */ - -static inline int __access_ok(const void __user *p, unsigned long size) -{ - unsigned long addr = (unsigned long)p; - unsigned long end = addr + size - !!size; - - return (__UA_LIMIT & (addr | end | __ua_size(size))) == 0; -} - -#define access_ok(addr, size) \ - likely(__access_ok((addr), (size))) +#include /* * put_user: - Write a simple value into user space. @@ -296,8 +255,6 @@ struct __large_struct { unsigned long buf[100]; }; (val) = __gu_tmp.t; \ } -#define HAVE_GET_KERNEL_NOFAULT - #define __get_kernel_nofault(dst, src, type, err_label) \ do { \ int __gu_err; \ diff --git a/arch/mips/include/uapi/asm/shmbuf.h b/arch/mips/include/uapi/asm/shmbuf.h index 680bb95b2240..eb74d304b779 100644 --- a/arch/mips/include/uapi/asm/shmbuf.h +++ b/arch/mips/include/uapi/asm/shmbuf.h @@ -2,6 +2,9 @@ #ifndef _ASM_SHMBUF_H #define _ASM_SHMBUF_H +#include +#include + /* * The shmid64_ds structure for the MIPS architecture. * Note extra padding because this structure is passed back and forth @@ -16,7 +19,7 @@ #ifdef __mips64 struct shmid64_ds { struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ + __kernel_size_t shm_segsz; /* size of segment (bytes) */ long shm_atime; /* last attach time */ long shm_dtime; /* last detach time */ long shm_ctime; /* last change time */ @@ -29,7 +32,7 @@ struct shmid64_ds { #else struct shmid64_ds { struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ + __kernel_size_t shm_segsz; /* size of segment (bytes) */ unsigned long shm_atime; /* last attach time */ unsigned long shm_dtime; /* last detach time */ unsigned long shm_ctime; /* last change time */ diff --git a/arch/mips/include/uapi/asm/signal.h b/arch/mips/include/uapi/asm/signal.h index e6c78a15cb2f..94a00f82e373 100644 --- a/arch/mips/include/uapi/asm/signal.h +++ b/arch/mips/include/uapi/asm/signal.h @@ -100,7 +100,7 @@ struct sigaction { /* IRIX compatible stack_t */ typedef struct sigaltstack { void __user *ss_sp; - size_t ss_size; + __kernel_size_t ss_size; int ss_flags; } stack_t; diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index df4b708c04a9..7b5aba5df02e 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -1480,6 +1480,23 @@ asmlinkage void do_ade(struct pt_regs *regs) prev_state = exception_enter(); perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, regs->cp0_badvaddr); + +#ifdef CONFIG_64BIT + /* + * check, if we are hitting space between CPU implemented maximum + * virtual user address and 64bit maximum virtual user address + * and do exception handling to get EFAULTs for get_user/put_user + */ + if ((regs->cp0_badvaddr >= (1UL << cpu_vmbits)) && + (regs->cp0_badvaddr < XKSSEG)) { + if (fixup_exception(regs)) { + current->thread.cp0_baduaddr = regs->cp0_badvaddr; + return; + } + goto sigbus; + } +#endif + /* * Did we catch a fault trying to load an instruction? */ diff --git a/arch/nds32/Kbuild b/arch/nds32/Kbuild deleted file mode 100644 index 4e39f7abdeb6..000000000000 --- a/arch/nds32/Kbuild +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -# for cleaning -subdir- += boot diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig deleted file mode 100644 index 4d1421b18734..000000000000 --- a/arch/nds32/Kconfig +++ /dev/null @@ -1,102 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# For a description of the syntax of this configuration file, -# see Documentation/kbuild/kconfig-language.rst. -# - -config NDS32 - def_bool y - select ARCH_32BIT_OFF_T - select ARCH_HAS_DMA_PREP_COHERENT - select ARCH_HAS_SYNC_DMA_FOR_CPU - select ARCH_HAS_SYNC_DMA_FOR_DEVICE - select ARCH_WANT_FRAME_POINTERS if FTRACE - select CLKSRC_MMIO - select CLONE_BACKWARDS - select COMMON_CLK - select DMA_DIRECT_REMAP - select GENERIC_ATOMIC64 - select GENERIC_CPU_DEVICES - select GENERIC_IRQ_CHIP - select GENERIC_IRQ_SHOW - select GENERIC_IOREMAP - select GENERIC_LIB_ASHLDI3 - select GENERIC_LIB_ASHRDI3 - select GENERIC_LIB_CMPDI2 - select GENERIC_LIB_LSHRDI3 - select GENERIC_LIB_MULDI3 - select GENERIC_LIB_UCMPDI2 - select GENERIC_TIME_VSYSCALL - select HAVE_ARCH_TRACEHOOK - select HAVE_DEBUG_KMEMLEAK - select HAVE_EXIT_THREAD - select HAVE_REGS_AND_STACK_ACCESS_API - select HAVE_PERF_EVENTS - select IRQ_DOMAIN - select LOCKDEP_SUPPORT - select MODULES_USE_ELF_RELA - select OF - select OF_EARLY_FLATTREE - select NO_IOPORT_MAP - select RTC_LIB - select THREAD_INFO_IN_TASK - select HAVE_FUNCTION_TRACER - select HAVE_FUNCTION_GRAPH_TRACER - select HAVE_FTRACE_MCOUNT_RECORD - select HAVE_DYNAMIC_FTRACE - select SET_FS - select TRACE_IRQFLAGS_SUPPORT - help - Andes(nds32) Linux support. - -config GENERIC_CALIBRATE_DELAY - def_bool y - -config GENERIC_CSUM - def_bool y - -config GENERIC_HWEIGHT - def_bool y - -config GENERIC_LOCKBREAK - def_bool y - depends on PREEMPTION - -config STACKTRACE_SUPPORT - def_bool y - -config FIX_EARLYCON_MEM - def_bool y - -config PGTABLE_LEVELS - default 2 - -menu "System Type" -source "arch/nds32/Kconfig.cpu" -config NR_CPUS - int - default 1 - -config MMU - def_bool y - -config NDS32_BUILTIN_DTB - string "Builtin DTB" - default "" - help - User can use it to specify the dts of the SoC -endmenu - -menu "Kernel Features" -source "kernel/Kconfig.hz" -endmenu - -menu "Power management options" -config SYS_SUPPORTS_APM_EMULATION - bool - -config ARCH_SUSPEND_POSSIBLE - def_bool y - -source "kernel/power/Kconfig" -endmenu diff --git a/arch/nds32/Kconfig.cpu b/arch/nds32/Kconfig.cpu deleted file mode 100644 index c10759952485..000000000000 --- a/arch/nds32/Kconfig.cpu +++ /dev/null @@ -1,218 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -comment "Processor Features" - -config CPU_BIG_ENDIAN - def_bool !CPU_LITTLE_ENDIAN - -config CPU_LITTLE_ENDIAN - bool "Little endian" - default y - -config FPU - bool "FPU support" - default n - help - If FPU ISA is used in user space, this configuration shall be Y to - enable required support in kernel such as fpu context switch and - fpu exception handler. - - If no FPU ISA is used in user space, say N. - -config LAZY_FPU - bool "lazy FPU support" - depends on FPU - default y - help - Say Y here to enable the lazy FPU scheme. The lazy FPU scheme can - enhance system performance by reducing the context switch - frequency of the FPU register. - - For normal case, say Y. - -config SUPPORT_DENORMAL_ARITHMETIC - bool "Denormal arithmetic support" - depends on FPU - default n - help - Say Y here to enable arithmetic of denormalized number. Enabling - this feature can enhance the precision for tininess number. - However, performance loss in float point calculations is - possibly significant due to additional FPU exception. - - If the calculated tolerance for tininess number is not critical, - say N to prevent performance loss. - -config HWZOL - bool "hardware zero overhead loop support" - depends on CPU_D10 || CPU_D15 - default n - help - A set of Zero-Overhead Loop mechanism is provided to reduce the - instruction fetch and execution overhead of loop-control instructions. - It will save 3 registers($LB, $LC, $LE) for context saving if say Y. - You don't need to save these registers if you can make sure your user - program doesn't use these registers. - - If unsure, say N. - -config CPU_CACHE_ALIASING - bool "Aliasing cache" - depends on CPU_N10 || CPU_D10 || CPU_N13 || CPU_V3 - default y - help - If this CPU is using VIPT data cache and its cache way size is larger - than page size, say Y. If it is using PIPT data cache, say N. - - If unsure, say Y. - -choice - prompt "minimum CPU type" - default CPU_V3 - help - The data cache of N15/D15 is implemented as PIPT and it will not cause - the cache aliasing issue. The rest cpus(N13, N10 and D10) are - implemented as VIPT data cache. It may cause the cache aliasing issue - if its cache way size is larger than page size. You can specify the - CPU type directly or choose CPU_V3 if unsure. - - A kernel built for N10 is able to run on N15, D15, N13, N10 or D10. - A kernel built for N15 is able to run on N15 or D15. - A kernel built for D10 is able to run on D10 or D15. - A kernel built for D15 is able to run on D15. - A kernel built for N13 is able to run on N15, N13 or D15. - -config CPU_N15 - bool "AndesCore N15" -config CPU_N13 - bool "AndesCore N13" - select CPU_CACHE_ALIASING if ANDES_PAGE_SIZE_4KB -config CPU_N10 - bool "AndesCore N10" - select CPU_CACHE_ALIASING -config CPU_D15 - bool "AndesCore D15" -config CPU_D10 - bool "AndesCore D10" - select CPU_CACHE_ALIASING -config CPU_V3 - bool "AndesCore v3 compatible" - select CPU_CACHE_ALIASING -endchoice -choice - prompt "Paging -- page size " - default ANDES_PAGE_SIZE_4KB -config ANDES_PAGE_SIZE_4KB - bool "use 4KB page size" -config ANDES_PAGE_SIZE_8KB - bool "use 8KB page size" -endchoice - -config CPU_ICACHE_DISABLE - bool "Disable I-Cache" - help - Say Y here to disable the processor instruction cache. Unless - you have a reason not to or are unsure, say N. - -config CPU_DCACHE_DISABLE - bool "Disable D-Cache" - help - Say Y here to disable the processor data cache. Unless - you have a reason not to or are unsure, say N. - -config CPU_DCACHE_WRITETHROUGH - bool "Force write through D-cache" - depends on !CPU_DCACHE_DISABLE - help - Say Y here to use the data cache in writethrough mode. Unless you - specifically require this or are unsure, say N. - -config WBNA - bool "WBNA" - default n - help - Say Y here to enable write-back memory with no-write-allocation policy. - -config ALIGNMENT_TRAP - bool "Kernel support unaligned access handling by sw" - depends on PROC_FS - default n - help - Andes processors cannot load/store information which is not - naturally aligned on the bus, i.e., a 4 byte load must start at an - address divisible by 4. On 32-bit Andes processors, these non-aligned - load/store instructions will be emulated in software if you say Y - here, which has a severe performance impact. With an IP-only - configuration it is safe to say N, otherwise say Y. - -config HW_SUPPORT_UNALIGNMENT_ACCESS - bool "Kernel support unaligned access handling by hw" - depends on !ALIGNMENT_TRAP - default n - help - Andes processors load/store world/half-word instructions can access - unaligned memory locations without generating the Data Alignment - Check exceptions. With an IP-only configuration it is safe to say N, - otherwise say Y. - -config HIGHMEM - bool "High Memory Support" - depends on MMU && !CPU_CACHE_ALIASING - select KMAP_LOCAL - help - The address space of Andes processors is only 4 Gigabytes large - and it has to accommodate user address space, kernel address - space as well as some memory mapped IO. That means that, if you - have a large amount of physical memory and/or IO, not all of the - memory can be "permanently mapped" by the kernel. The physical - memory that is not permanently mapped is called "high memory". - - Depending on the selected kernel/user memory split, minimum - vmalloc space and actual amount of RAM, you may not need this - option which should result in a slightly faster kernel. - - If unsure, say N. - -config CACHE_L2 - bool "Support L2 cache" - default y - help - Say Y here to enable L2 cache if your SoC are integrated with L2CC. - If unsure, say N. - -config HW_PRE - bool "Enable hardware prefetcher" - default y - help - Say Y here to enable hardware prefetcher feature. - Only when CPU_VER.REV >= 0x09 can support. - -menu "Memory configuration" - -choice - prompt "Memory split" - depends on MMU - default VMSPLIT_3G_OPT - help - Select the desired split between kernel and user memory. - - If you are not absolutely sure what you are doing, leave this - option alone! - - config VMSPLIT_3G - bool "3G/1G user/kernel split" - config VMSPLIT_3G_OPT - bool "3G/1G user/kernel split (for full 1G low memory)" - config VMSPLIT_2G - bool "2G/2G user/kernel split" - config VMSPLIT_1G - bool "1G/3G user/kernel split" -endchoice - -config PAGE_OFFSET - hex - default 0x40000000 if VMSPLIT_1G - default 0x80000000 if VMSPLIT_2G - default 0xB0000000 if VMSPLIT_3G_OPT - default 0xC0000000 - -endmenu diff --git a/arch/nds32/Kconfig.debug b/arch/nds32/Kconfig.debug deleted file mode 100644 index 295942fe3fd5..000000000000 --- a/arch/nds32/Kconfig.debug +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# dummy file, do not delete diff --git a/arch/nds32/Makefile b/arch/nds32/Makefile deleted file mode 100644 index b33d5d81b6ae..000000000000 --- a/arch/nds32/Makefile +++ /dev/null @@ -1,63 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -LDFLAGS_vmlinux := --no-undefined -X -OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment -S - -ifdef CONFIG_FUNCTION_TRACER -arch-y += -malways-save-lp -mno-relax -endif - -# Avoid generating FPU instructions -arch-y += -mno-ext-fpu-sp -mno-ext-fpu-dp -mfloat-abi=soft - -# Enable -KBUILD_CFLAGS += -isystem $(shell $(CC) -print-file-name=include) -KBUILD_CFLAGS += $(call cc-option, -mno-sched-prolog-epilog) -KBUILD_CFLAGS += -mcmodel=large - -KBUILD_CFLAGS +=$(arch-y) $(tune-y) -KBUILD_AFLAGS +=$(arch-y) $(tune-y) - -#Default value -head-y := arch/nds32/kernel/head.o -textaddr-y := $(CONFIG_PAGE_OFFSET)+0xc000 - -TEXTADDR := $(textaddr-y) - -export TEXTADDR - - -# If we have a machine-specific directory, then include it in the build. -core-y += arch/nds32/kernel/ arch/nds32/mm/ -core-$(CONFIG_FPU) += arch/nds32/math-emu/ -libs-y += arch/nds32/lib/ - -ifdef CONFIG_CPU_LITTLE_ENDIAN -KBUILD_CFLAGS += $(call cc-option, -EL) -KBUILD_AFLAGS += $(call cc-option, -EL) -KBUILD_LDFLAGS += $(call cc-option, -EL) -CHECKFLAGS += -D__NDS32_EL__ -else -KBUILD_CFLAGS += $(call cc-option, -EB) -KBUILD_AFLAGS += $(call cc-option, -EB) -KBUILD_LDFLAGS += $(call cc-option, -EB) -CHECKFLAGS += -D__NDS32_EB__ -endif - -boot := arch/nds32/boot -core-y += $(boot)/dts/ - -Image: vmlinux - $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ - - -PHONY += vdso_install -vdso_install: - $(Q)$(MAKE) $(build)=arch/nds32/kernel/vdso $@ - -prepare: vdso_prepare -vdso_prepare: prepare0 - $(Q)$(MAKE) $(build)=arch/nds32/kernel/vdso include/generated/vdso-offsets.h - -define archhelp - echo ' Image - kernel image (arch/$(ARCH)/boot/Image)' -endef diff --git a/arch/nds32/boot/.gitignore b/arch/nds32/boot/.gitignore deleted file mode 100644 index 9182a3a1ea0a..000000000000 --- a/arch/nds32/boot/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -/Image diff --git a/arch/nds32/boot/Makefile b/arch/nds32/boot/Makefile deleted file mode 100644 index c4cc0c2689f7..000000000000 --- a/arch/nds32/boot/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -targets := Image Image.gz - -$(obj)/Image: vmlinux FORCE - $(call if_changed,objcopy) - -$(obj)/Image.gz: $(obj)/Image FORCE - $(call if_changed,gzip) - -install: $(obj)/Image - $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ - $(obj)/Image System.map "$(INSTALL_PATH)" - -zinstall: $(obj)/Image.gz - $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ - $(obj)/Image.gz System.map "$(INSTALL_PATH)" diff --git a/arch/nds32/boot/dts/Makefile b/arch/nds32/boot/dts/Makefile deleted file mode 100644 index 4fc69562eae8..000000000000 --- a/arch/nds32/boot/dts/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_OF) += $(addsuffix .dtb.o, $(CONFIG_NDS32_BUILTIN_DTB)) diff --git a/arch/nds32/boot/dts/ae3xx.dts b/arch/nds32/boot/dts/ae3xx.dts deleted file mode 100644 index 16a9f54a805e..000000000000 --- a/arch/nds32/boot/dts/ae3xx.dts +++ /dev/null @@ -1,90 +0,0 @@ -/dts-v1/; -/ { - compatible = "andestech,ae3xx"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - - chosen { - stdout-path = &serial0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x40000000>; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - device_type = "cpu"; - compatible = "andestech,n13", "andestech,nds32v3"; - reg = <0>; - clock-frequency = <60000000>; - next-level-cache = <&L2>; - }; - }; - - intc: interrupt-controller { - compatible = "andestech,ativic32"; - #interrupt-cells = <1>; - interrupt-controller; - }; - - clock: clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <30000000>; - }; - - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - serial0: serial@f0300000 { - compatible = "andestech,uart16550", "ns16550a"; - reg = <0xf0300000 0x1000>; - interrupts = <8>; - clock-frequency = <14745600>; - reg-shift = <2>; - reg-offset = <32>; - no-loopback-test = <1>; - }; - - timer0: timer@f0400000 { - compatible = "andestech,atcpit100"; - reg = <0xf0400000 0x1000>; - interrupts = <2>; - clocks = <&clock>; - clock-names = "PCLK"; - }; - }; - - ahb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - L2: cache-controller@e0500000 { - compatible = "andestech,atl2c"; - reg = <0xe0500000 0x1000>; - cache-unified; - cache-level = <2>; - }; - - mac0: ethernet@e0100000 { - compatible = "andestech,atmac100"; - reg = <0xe0100000 0x1000>; - interrupts = <18>; - }; - }; - - pmu { - compatible = "andestech,nds32v3-pmu"; - interrupts= <13>; - }; -}; diff --git a/arch/nds32/configs/defconfig b/arch/nds32/configs/defconfig deleted file mode 100644 index f9a89cf00aa6..000000000000 --- a/arch/nds32/configs/defconfig +++ /dev/null @@ -1,104 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_USER_NS=y -CONFIG_RELAY=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -CONFIG_PROFILING=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_CACHE_L2 is not set -CONFIG_PREEMPT=y -# CONFIG_COMPACTION is not set -CONFIG_HZ_100=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_BLK_DEV is not set -CONFIG_NETDEVICES=y -# CONFIG_NET_CADENCE is not set -# CONFIG_NET_VENDOR_BROADCOM is not set -CONFIG_FTMAC100=y -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_STMICRO is not set -# CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_SERIO is not set -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_SERIAL_8250=y -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_OF_PLATFORM=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_ITE is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_GENERIC_PHY=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_FS_ENCRYPTION=y -CONFIG_FUSE_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_CONFIGFS_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_USE_LEGACY_DNS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_INFO_DWARF4=y -CONFIG_GDB_SCRIPTS=y -CONFIG_READABLE_ASM=y -CONFIG_HEADERS_INSTALL=y -CONFIG_HEADERS_CHECK=y -CONFIG_DEBUG_SECTION_MISMATCH=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_PANIC_ON_OOPS=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_STACKTRACE=y -CONFIG_RCU_CPU_STALL_TIMEOUT=300 -# CONFIG_CRYPTO_HW is not set diff --git a/arch/nds32/include/asm/Kbuild b/arch/nds32/include/asm/Kbuild deleted file mode 100644 index 82a4453c9c2d..000000000000 --- a/arch/nds32/include/asm/Kbuild +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -generic-y += asm-offsets.h -generic-y += cmpxchg.h -generic-y += export.h -generic-y += gpio.h -generic-y += kvm_para.h -generic-y += parport.h -generic-y += user.h diff --git a/arch/nds32/include/asm/assembler.h b/arch/nds32/include/asm/assembler.h deleted file mode 100644 index 5e7c56926049..000000000000 --- a/arch/nds32/include/asm/assembler.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __NDS32_ASSEMBLER_H__ -#define __NDS32_ASSEMBLER_H__ - -.macro gie_disable - setgie.d - dsb -.endm - -.macro gie_enable - setgie.e - dsb -.endm - -.macro gie_save oldpsw - mfsr \oldpsw, $ir0 - setgie.d - dsb -.endm - -.macro gie_restore oldpsw - andi \oldpsw, \oldpsw, #0x1 - beqz \oldpsw, 7001f - setgie.e - dsb -7001: -.endm - - -#define USER(insn, reg, addr, opr) \ -9999: insn reg, addr, opr; \ - .section __ex_table,"a"; \ - .align 3; \ - .long 9999b, 9001f; \ - .previous - -#endif /* __NDS32_ASSEMBLER_H__ */ diff --git a/arch/nds32/include/asm/barrier.h b/arch/nds32/include/asm/barrier.h deleted file mode 100644 index 16413172fd50..000000000000 --- a/arch/nds32/include/asm/barrier.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __NDS32_ASM_BARRIER_H -#define __NDS32_ASM_BARRIER_H - -#ifndef __ASSEMBLY__ -#define mb() asm volatile("msync all":::"memory") -#define rmb() asm volatile("msync all":::"memory") -#define wmb() asm volatile("msync store":::"memory") -#include - -#endif /* __ASSEMBLY__ */ - -#endif /* __NDS32_ASM_BARRIER_H */ diff --git a/arch/nds32/include/asm/bitfield.h b/arch/nds32/include/asm/bitfield.h deleted file mode 100644 index b02a58e71f80..000000000000 --- a/arch/nds32/include/asm/bitfield.h +++ /dev/null @@ -1,985 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __NDS32_BITFIELD_H__ -#define __NDS32_BITFIELD_H__ -/****************************************************************************** - * cr0: CPU_VER (CPU Version Register) - *****************************************************************************/ -#define CPU_VER_offCFGID 0 /* Minor configuration */ -#define CPU_VER_offREV 16 /* Revision of the CPU version */ -#define CPU_VER_offCPUID 24 /* Major CPU versions */ - -#define CPU_VER_mskCFGID ( 0xFFFF << CPU_VER_offCFGID ) -#define CPU_VER_mskREV ( 0xFF << CPU_VER_offREV ) -#define CPU_VER_mskCPUID ( 0xFF << CPU_VER_offCPUID ) - -/****************************************************************************** - * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register) - *****************************************************************************/ -#define ICM_CFG_offISET 0 /* I-cache sets (# of cache lines) per way */ -#define ICM_CFG_offIWAY 3 /* I-cache ways */ -#define ICM_CFG_offISZ 6 /* I-cache line size */ -#define ICM_CFG_offILCK 9 /* I-cache locking support */ -#define ICM_CFG_offILMB 10 /* On-chip ILM banks */ -#define ICM_CFG_offBSAV 13 /* ILM base register alignment version */ -/* bit 15:31 reserved */ - -#define ICM_CFG_mskISET ( 0x7 << ICM_CFG_offISET ) -#define ICM_CFG_mskIWAY ( 0x7 << ICM_CFG_offIWAY ) -#define ICM_CFG_mskISZ ( 0x7 << ICM_CFG_offISZ ) -#define ICM_CFG_mskILCK ( 0x1 << ICM_CFG_offILCK ) -#define ICM_CFG_mskILMB ( 0x7 << ICM_CFG_offILMB ) -#define ICM_CFG_mskBSAV ( 0x3 << ICM_CFG_offBSAV ) - -/****************************************************************************** - * cr2: DCM_CFG (Data Cache/Memory Configuration Register) - *****************************************************************************/ -#define DCM_CFG_offDSET 0 /* D-cache sets (# of cache lines) per way */ -#define DCM_CFG_offDWAY 3 /* D-cache ways */ -#define DCM_CFG_offDSZ 6 /* D-cache line size */ -#define DCM_CFG_offDLCK 9 /* D-cache locking support */ -#define DCM_CFG_offDLMB 10 /* On-chip DLM banks */ -#define DCM_CFG_offBSAV 13 /* DLM base register alignment version */ -/* bit 15:31 reserved */ - -#define DCM_CFG_mskDSET ( 0x7 << DCM_CFG_offDSET ) -#define DCM_CFG_mskDWAY ( 0x7 << DCM_CFG_offDWAY ) -#define DCM_CFG_mskDSZ ( 0x7 << DCM_CFG_offDSZ ) -#define DCM_CFG_mskDLCK ( 0x1 << DCM_CFG_offDLCK ) -#define DCM_CFG_mskDLMB ( 0x7 << DCM_CFG_offDLMB ) -#define DCM_CFG_mskBSAV ( 0x3 << DCM_CFG_offBSAV ) - -/****************************************************************************** - * cr3: MMU_CFG (MMU Configuration Register) - *****************************************************************************/ -#define MMU_CFG_offMMPS 0 /* Memory management protection scheme */ -#define MMU_CFG_offMMPV 2 /* Memory management protection version number */ -#define MMU_CFG_offFATB 7 /* Fully-associative or non-fully-associative TLB */ - -#define MMU_CFG_offTBW 8 /* TLB ways(non-associative) TBS */ -#define MMU_CFG_offTBS 11 /* TLB sets per way(non-associative) TBS */ -/* bit 14:14 reserved */ - -#define MMU_CFG_offEP8MIN4 15 /* 8KB page supported while minimum page is 4KB */ -#define MMU_CFG_offfEPSZ 16 /* Extra page size supported */ -#define MMU_CFG_offTLBLCK 24 /* TLB locking support */ -#define MMU_CFG_offHPTWK 25 /* Hardware Page Table Walker implemented */ -#define MMU_CFG_offDE 26 /* Default endian */ -#define MMU_CFG_offNTPT 27 /* Partitions for non-translated attributes */ -#define MMU_CFG_offIVTB 28 /* Invisible TLB */ -#define MMU_CFG_offVLPT 29 /* VLPT for fast TLB fill handling implemented */ -#define MMU_CFG_offNTME 30 /* Non-translated VA to PA mapping */ -/* bit 31 reserved */ - -#define MMU_CFG_mskMMPS ( 0x3 << MMU_CFG_offMMPS ) -#define MMU_CFG_mskMMPV ( 0x1F << MMU_CFG_offMMPV ) -#define MMU_CFG_mskFATB ( 0x1 << MMU_CFG_offFATB ) -#define MMU_CFG_mskTBW ( 0x7 << MMU_CFG_offTBW ) -#define MMU_CFG_mskTBS ( 0x7 << MMU_CFG_offTBS ) -#define MMU_CFG_mskEP8MIN4 ( 0x1 << MMU_CFG_offEP8MIN4 ) -#define MMU_CFG_mskfEPSZ ( 0xFF << MMU_CFG_offfEPSZ ) -#define MMU_CFG_mskTLBLCK ( 0x1 << MMU_CFG_offTLBLCK ) -#define MMU_CFG_mskHPTWK ( 0x1 << MMU_CFG_offHPTWK ) -#define MMU_CFG_mskDE ( 0x1 << MMU_CFG_offDE ) -#define MMU_CFG_mskNTPT ( 0x1 << MMU_CFG_offNTPT ) -#define MMU_CFG_mskIVTB ( 0x1 << MMU_CFG_offIVTB ) -#define MMU_CFG_mskVLPT ( 0x1 << MMU_CFG_offVLPT ) -#define MMU_CFG_mskNTME ( 0x1 << MMU_CFG_offNTME ) - -/****************************************************************************** - * cr4: MSC_CFG (Misc Configuration Register) - *****************************************************************************/ -#define MSC_CFG_offEDM 0 -#define MSC_CFG_offLMDMA 1 -#define MSC_CFG_offPFM 2 -#define MSC_CFG_offHSMP 3 -#define MSC_CFG_offTRACE 4 -#define MSC_CFG_offDIV 5 -#define MSC_CFG_offMAC 6 -#define MSC_CFG_offAUDIO 7 -#define MSC_CFG_offL2C 9 -#define MSC_CFG_offRDREG 10 -#define MSC_CFG_offADR24 11 -#define MSC_CFG_offINTLC 12 -#define MSC_CFG_offBASEV 13 -#define MSC_CFG_offNOD 16 -/* bit 13:31 reserved */ - -#define MSC_CFG_mskEDM ( 0x1 << MSC_CFG_offEDM ) -#define MSC_CFG_mskLMDMA ( 0x1 << MSC_CFG_offLMDMA ) -#define MSC_CFG_mskPFM ( 0x1 << MSC_CFG_offPFM ) -#define MSC_CFG_mskHSMP ( 0x1 << MSC_CFG_offHSMP ) -#define MSC_CFG_mskTRACE ( 0x1 << MSC_CFG_offTRACE ) -#define MSC_CFG_mskDIV ( 0x1 << MSC_CFG_offDIV ) -#define MSC_CFG_mskMAC ( 0x1 << MSC_CFG_offMAC ) -#define MSC_CFG_mskAUDIO ( 0x3 << MSC_CFG_offAUDIO ) -#define MSC_CFG_mskL2C ( 0x1 << MSC_CFG_offL2C ) -#define MSC_CFG_mskRDREG ( 0x1 << MSC_CFG_offRDREG ) -#define MSC_CFG_mskADR24 ( 0x1 << MSC_CFG_offADR24 ) -#define MSC_CFG_mskINTLC ( 0x1 << MSC_CFG_offINTLC ) -#define MSC_CFG_mskBASEV ( 0x7 << MSC_CFG_offBASEV ) -#define MSC_CFG_mskNOD ( 0x1 << MSC_CFG_offNOD ) - -/****************************************************************************** - * cr5: CORE_CFG (Core Identification Register) - *****************************************************************************/ -#define CORE_ID_offCOREID 0 -/* bit 4:31 reserved */ - -#define CORE_ID_mskCOREID ( 0xF << CORE_ID_offCOREID ) - -/****************************************************************************** - * cr6: FUCOP_EXIST (FPU and Coprocessor Existence Configuration Register) - *****************************************************************************/ -#define FUCOP_EXIST_offCP0EX 0 -#define FUCOP_EXIST_offCP1EX 1 -#define FUCOP_EXIST_offCP2EX 2 -#define FUCOP_EXIST_offCP3EX 3 -#define FUCOP_EXIST_offCP0ISFPU 31 - -#define FUCOP_EXIST_mskCP0EX ( 0x1 << FUCOP_EXIST_offCP0EX ) -#define FUCOP_EXIST_mskCP1EX ( 0x1 << FUCOP_EXIST_offCP1EX ) -#define FUCOP_EXIST_mskCP2EX ( 0x1 << FUCOP_EXIST_offCP2EX ) -#define FUCOP_EXIST_mskCP3EX ( 0x1 << FUCOP_EXIST_offCP3EX ) -#define FUCOP_EXIST_mskCP0ISFPU ( 0x1 << FUCOP_EXIST_offCP0ISFPU ) - -/****************************************************************************** - * ir0: PSW (Processor Status Word Register) - * ir1: IPSW (Interruption PSW Register) - * ir2: P_IPSW (Previous IPSW Register) - *****************************************************************************/ -#define PSW_offGIE 0 /* Global Interrupt Enable */ -#define PSW_offINTL 1 /* Interruption Stack Level */ -#define PSW_offPOM 3 /* Processor Operation Mode, User/Superuser */ -#define PSW_offBE 5 /* Endianness for data memory access, 1:MSB, 0:LSB */ -#define PSW_offIT 6 /* Enable instruction address translation */ -#define PSW_offDT 7 /* Enable data address translation */ -#define PSW_offIME 8 /* Instruction Machine Error flag */ -#define PSW_offDME 9 /* Data Machine Error flag */ -#define PSW_offDEX 10 /* Debug Exception */ -#define PSW_offHSS 11 /* Hardware Single Stepping */ -#define PSW_offDRBE 12 /* Device Register Endian Mode */ -#define PSW_offAEN 13 /* Audio ISA special feature */ -#define PSW_offWBNA 14 /* Write Back Non-Allocate */ -#define PSW_offIFCON 15 /* IFC On */ -#define PSW_offCPL 16 /* Current Priority Level */ -/* bit 19:31 reserved */ - -#define PSW_mskGIE ( 0x1 << PSW_offGIE ) -#define PSW_mskINTL ( 0x3 << PSW_offINTL ) -#define PSW_mskPOM ( 0x3 << PSW_offPOM ) -#define PSW_mskBE ( 0x1 << PSW_offBE ) -#define PSW_mskIT ( 0x1 << PSW_offIT ) -#define PSW_mskDT ( 0x1 << PSW_offDT ) -#define PSW_mskIME ( 0x1 << PSW_offIME ) -#define PSW_mskDME ( 0x1 << PSW_offDME ) -#define PSW_mskDEX ( 0x1 << PSW_offDEX ) -#define PSW_mskHSS ( 0x1 << PSW_offHSS ) -#define PSW_mskDRBE ( 0x1 << PSW_offDRBE ) -#define PSW_mskAEN ( 0x1 << PSW_offAEN ) -#define PSW_mskWBNA ( 0x1 << PSW_offWBNA ) -#define PSW_mskIFCON ( 0x1 << PSW_offIFCON ) -#define PSW_mskCPL ( 0x7 << PSW_offCPL ) - -#define PSW_SYSTEM ( 1 << PSW_offPOM ) -#define PSW_INTL_1 ( 1 << PSW_offINTL ) -#define PSW_CPL_NO ( 0 << PSW_offCPL ) -#define PSW_CPL_ANY ( 7 << PSW_offCPL ) - -#define PSW_clr (PSW_mskGIE|PSW_mskINTL|PSW_mskPOM|PSW_mskIT|PSW_mskDT|PSW_mskIME|PSW_mskWBNA) -#ifdef __NDS32_EB__ -#ifdef CONFIG_WBNA -#define PSW_init (PSW_mskWBNA|(1< - -#define PG_dcache_dirty PG_arch_1 - -void flush_icache_range(unsigned long start, unsigned long end); -#define flush_icache_range flush_icache_range - -void flush_icache_page(struct vm_area_struct *vma, struct page *page); -#define flush_icache_page flush_icache_page - -#ifdef CONFIG_CPU_CACHE_ALIASING -void flush_cache_mm(struct mm_struct *mm); -void flush_cache_dup_mm(struct mm_struct *mm); -void flush_cache_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end); -void flush_cache_page(struct vm_area_struct *vma, - unsigned long addr, unsigned long pfn); -void flush_cache_kmaps(void); -void flush_cache_vmap(unsigned long start, unsigned long end); -void flush_cache_vunmap(unsigned long start, unsigned long end); - -#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 -void flush_dcache_page(struct page *page); -void copy_to_user_page(struct vm_area_struct *vma, struct page *page, - unsigned long vaddr, void *dst, void *src, int len); -void copy_from_user_page(struct vm_area_struct *vma, struct page *page, - unsigned long vaddr, void *dst, void *src, int len); - -#define ARCH_HAS_FLUSH_ANON_PAGE -void flush_anon_page(struct vm_area_struct *vma, - struct page *page, unsigned long vaddr); - -#define ARCH_IMPLEMENTS_FLUSH_KERNEL_VMAP_RANGE 1 -void flush_kernel_vmap_range(void *addr, int size); -void invalidate_kernel_vmap_range(void *addr, int size); -#define flush_dcache_mmap_lock(mapping) xa_lock_irq(&(mapping)->i_pages) -#define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&(mapping)->i_pages) - -#else -void flush_icache_user_page(struct vm_area_struct *vma, struct page *page, - unsigned long addr, int len); -#define flush_icache_user_page flush_icache_user_page - -#include -#endif - -#endif /* __NDS32_CACHEFLUSH_H__ */ diff --git a/arch/nds32/include/asm/current.h b/arch/nds32/include/asm/current.h deleted file mode 100644 index 65d30096142b..000000000000 --- a/arch/nds32/include/asm/current.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef _ASM_NDS32_CURRENT_H -#define _ASM_NDS32_CURRENT_H - -#ifndef __ASSEMBLY__ -register struct task_struct *current asm("$r25"); -#endif /* __ASSEMBLY__ */ -#define tsk $r25 - -#endif /* _ASM_NDS32_CURRENT_H */ diff --git a/arch/nds32/include/asm/delay.h b/arch/nds32/include/asm/delay.h deleted file mode 100644 index 56ea3894f8f8..000000000000 --- a/arch/nds32/include/asm/delay.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __NDS32_DELAY_H__ -#define __NDS32_DELAY_H__ - -#include - -/* There is no clocksource cycle counter in the CPU. */ -static inline void __delay(unsigned long loops) -{ - __asm__ __volatile__(".align 2\n" - "1:\n" - "\taddi\t%0, %0, -1\n" - "\tbgtz\t%0, 1b\n" - :"=r"(loops) - :"0"(loops)); -} - -static inline void __udelay(unsigned long usecs, unsigned long lpj) -{ - usecs *= (unsigned long)(((0x8000000000000000ULL / (500000 / HZ)) + - 0x80000000ULL) >> 32); - usecs = (unsigned long)(((unsigned long long)usecs * lpj) >> 32); - __delay(usecs); -} - -#define udelay(usecs) __udelay((usecs), loops_per_jiffy) - -/* make sure "usecs *= ..." in udelay do not overflow. */ -#if HZ >= 1000 -#define MAX_UDELAY_MS 1 -#elif HZ <= 200 -#define MAX_UDELAY_MS 5 -#else -#define MAX_UDELAY_MS (1000 / HZ) -#endif - -#endif diff --git a/arch/nds32/include/asm/elf.h b/arch/nds32/include/asm/elf.h deleted file mode 100644 index 1853dc89b8ac..000000000000 --- a/arch/nds32/include/asm/elf.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASMNDS32_ELF_H -#define __ASMNDS32_ELF_H - -/* - * ELF register definitions.. - */ - -#include -#include -#include - -typedef unsigned long elf_greg_t; -typedef unsigned long elf_freg_t[3]; - -extern unsigned int elf_hwcap; - -#define R_NDS32_NONE 0 -#define R_NDS32_16_RELA 19 -#define R_NDS32_32_RELA 20 -#define R_NDS32_9_PCREL_RELA 22 -#define R_NDS32_15_PCREL_RELA 23 -#define R_NDS32_17_PCREL_RELA 24 -#define R_NDS32_25_PCREL_RELA 25 -#define R_NDS32_HI20_RELA 26 -#define R_NDS32_LO12S3_RELA 27 -#define R_NDS32_LO12S2_RELA 28 -#define R_NDS32_LO12S1_RELA 29 -#define R_NDS32_LO12S0_RELA 30 -#define R_NDS32_SDA15S3_RELA 31 -#define R_NDS32_SDA15S2_RELA 32 -#define R_NDS32_SDA15S1_RELA 33 -#define R_NDS32_SDA15S0_RELA 34 -#define R_NDS32_GOT20 37 -#define R_NDS32_25_PLTREL 38 -#define R_NDS32_COPY 39 -#define R_NDS32_GLOB_DAT 40 -#define R_NDS32_JMP_SLOT 41 -#define R_NDS32_RELATIVE 42 -#define R_NDS32_GOTOFF 43 -#define R_NDS32_GOTPC20 44 -#define R_NDS32_GOT_HI20 45 -#define R_NDS32_GOT_LO12 46 -#define R_NDS32_GOTPC_HI20 47 -#define R_NDS32_GOTPC_LO12 48 -#define R_NDS32_GOTOFF_HI20 49 -#define R_NDS32_GOTOFF_LO12 50 -#define R_NDS32_INSN16 51 -#define R_NDS32_LABEL 52 -#define R_NDS32_LONGCALL1 53 -#define R_NDS32_LONGCALL2 54 -#define R_NDS32_LONGCALL3 55 -#define R_NDS32_LONGJUMP1 56 -#define R_NDS32_LONGJUMP2 57 -#define R_NDS32_LONGJUMP3 58 -#define R_NDS32_LOADSTORE 59 -#define R_NDS32_9_FIXED_RELA 60 -#define R_NDS32_15_FIXED_RELA 61 -#define R_NDS32_17_FIXED_RELA 62 -#define R_NDS32_25_FIXED_RELA 63 -#define R_NDS32_PLTREL_HI20 64 -#define R_NDS32_PLTREL_LO12 65 -#define R_NDS32_PLT_GOTREL_HI20 66 -#define R_NDS32_PLT_GOTREL_LO12 67 -#define R_NDS32_LO12S0_ORI_RELA 72 -#define R_NDS32_DWARF2_OP1_RELA 77 -#define R_NDS32_DWARF2_OP2_RELA 78 -#define R_NDS32_DWARF2_LEB_RELA 79 -#define R_NDS32_WORD_9_PCREL_RELA 94 -#define R_NDS32_LONGCALL4 107 -#define R_NDS32_RELA_NOP_MIX 192 -#define R_NDS32_RELA_NOP_MAX 255 - -#define ELF_NGREG (sizeof (struct user_pt_regs) / sizeof(elf_greg_t)) -#define ELF_CORE_COPY_REGS(dest, regs) \ - *(struct user_pt_regs *)&(dest) = (regs)->user_regs; - -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -/* Core file format: The core file is written in such a way that gdb - can understand it and provide useful information to the user (under - linux we use the 'trad-core' bfd). There are quite a number of - obstacles to being able to view the contents of the floating point - registers, and until these are solved you will not be able to view the - contents of them. Actually, you can read in the core file and look at - the contents of the user struct to find out what the floating point - registers contain. - The actual file contents are as follows: - UPAGE: 1 page consisting of a user struct that tells gdb what is present - in the file. Directly after this is a copy of the task_struct, which - is currently not used by gdb, but it may come in useful at some point. - All of the registers are stored as part of the upage. The upage should - always be only one page. - DATA: The data area is stored. We use current->end_text to - current->brk to pick up all of the user variables, plus any memory - that may have been malloced. No attempt is made to determine if a page - is demand-zero or if a page is totally unused, we just cover the entire - range. All of the addresses are rounded in such a way that an integral - number of pages is written. - STACK: We need the stack information in order to get a meaningful - backtrace. We need to write the data from (esp) to - current->start_stack, so we round each of these off in order to be able - to write an integer number of pages. - The minimum core file size is 3 pages, or 12288 bytes. -*/ - -struct user_fp { - unsigned long long fd_regs[32]; - unsigned long fpcsr; -}; - -typedef struct user_fp elf_fpregset_t; - -struct elf32_hdr; -#define elf_check_arch(x) ((x)->e_machine == EM_NDS32) - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#ifdef __NDS32_EB__ -#define ELF_DATA ELFDATA2MSB -#else -#define ELF_DATA ELFDATA2LSB -#endif -#define ELF_ARCH EM_NDS32 -#define ELF_EXEC_PAGESIZE PAGE_SIZE - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) - -/* When the program starts, a1 contains a pointer to a function to be - registered with atexit, as per the SVR4 ABI. A value of 0 means we - have no such handler. */ -#define ELF_PLAT_INIT(_r, load_addr) (_r)->uregs[0] = 0 - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. */ - -#define ELF_HWCAP (elf_hwcap) - -#ifdef __KERNEL__ - -#define ELF_PLATFORM (NULL) - -/* Old NetWinder binaries were compiled in such a way that the iBCS - heuristic always trips on them. Until these binaries become uncommon - enough not to care, don't trust the `ibcs' flag here. In any case - there is no other ELF system currently supported by iBCS. - @@ Could print a warning message to encourage users to upgrade. */ -#define SET_PERSONALITY(ex) set_personality(PER_LINUX) - -#endif - - -#if IS_ENABLED(CONFIG_FPU) -#define FPU_AUX_ENT NEW_AUX_ENT(AT_FPUCW, FPCSR_INIT) -#else -#define FPU_AUX_ENT NEW_AUX_ENT(AT_IGNORE, 0) -#endif - -#define ARCH_DLINFO \ -do { \ - /* Optional FPU initialization */ \ - FPU_AUX_ENT; \ - \ - NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (elf_addr_t)current->mm->context.vdso); \ -} while (0) -#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1 -struct linux_binprm; -int arch_setup_additional_pages(struct linux_binprm *, int); - -#endif diff --git a/arch/nds32/include/asm/fixmap.h b/arch/nds32/include/asm/fixmap.h deleted file mode 100644 index 2fa09a2de428..000000000000 --- a/arch/nds32/include/asm/fixmap.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_NDS32_FIXMAP_H -#define __ASM_NDS32_FIXMAP_H - -#ifdef CONFIG_HIGHMEM -#include -#include -#endif - -enum fixed_addresses { - FIX_HOLE, - FIX_KMAP_RESERVED, - FIX_KMAP_BEGIN, -#ifdef CONFIG_HIGHMEM - FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_MAX_IDX * NR_CPUS) - 1, -#endif - FIX_EARLYCON_MEM_BASE, - __end_of_fixed_addresses -}; -#define FIXADDR_TOP ((unsigned long) (-(16 * PAGE_SIZE))) -#define FIXADDR_SIZE ((__end_of_fixed_addresses) << PAGE_SHIFT) -#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) -#define FIXMAP_PAGE_IO __pgprot(PAGE_DEVICE) -void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot); - -#include -#endif /* __ASM_NDS32_FIXMAP_H */ diff --git a/arch/nds32/include/asm/fpu.h b/arch/nds32/include/asm/fpu.h deleted file mode 100644 index 8294ed4aaa2c..000000000000 --- a/arch/nds32/include/asm/fpu.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (C) 2005-2018 Andes Technology Corporation */ - -#ifndef __ASM_NDS32_FPU_H -#define __ASM_NDS32_FPU_H - -#if IS_ENABLED(CONFIG_FPU) -#ifndef __ASSEMBLY__ -#include -#include -#include - -extern bool has_fpu; - -extern void save_fpu(struct task_struct *__tsk); -extern void load_fpu(const struct fpu_struct *fpregs); -extern bool do_fpu_exception(unsigned int subtype, struct pt_regs *regs); -extern int do_fpuemu(struct pt_regs *regs, struct fpu_struct *fpu); - -#define test_tsk_fpu(regs) (regs->fucop_ctl & FUCOP_CTL_mskCP0EN) - -/* - * Initially load the FPU with signalling NANS. This bit pattern - * has the property that no matter whether considered as single or as - * double precision, it still represents a signalling NAN. - */ - -#define sNAN64 0xFFFFFFFFFFFFFFFFULL -#define sNAN32 0xFFFFFFFFUL - -#if IS_ENABLED(CONFIG_SUPPORT_DENORMAL_ARITHMETIC) -/* - * Denormalized number is unsupported by nds32 FPU. Hence the operation - * is treated as underflow cases when the final result is a denormalized - * number. To enhance precision, underflow exception trap should be - * enabled by default and kerenl will re-execute it by fpu emulator - * when getting underflow exception. - */ -#define FPCSR_INIT (FPCSR_mskUDFE | FPCSR_mskIEXE) -#else -#define FPCSR_INIT 0x0UL -#endif - -extern const struct fpu_struct init_fpuregs; - -static inline void disable_ptreg_fpu(struct pt_regs *regs) -{ - regs->fucop_ctl &= ~FUCOP_CTL_mskCP0EN; -} - -static inline void enable_ptreg_fpu(struct pt_regs *regs) -{ - regs->fucop_ctl |= FUCOP_CTL_mskCP0EN; -} - -static inline void enable_fpu(void) -{ - unsigned long fucop_ctl; - - fucop_ctl = __nds32__mfsr(NDS32_SR_FUCOP_CTL) | FUCOP_CTL_mskCP0EN; - __nds32__mtsr(fucop_ctl, NDS32_SR_FUCOP_CTL); - __nds32__isb(); -} - -static inline void disable_fpu(void) -{ - unsigned long fucop_ctl; - - fucop_ctl = __nds32__mfsr(NDS32_SR_FUCOP_CTL) & ~FUCOP_CTL_mskCP0EN; - __nds32__mtsr(fucop_ctl, NDS32_SR_FUCOP_CTL); - __nds32__isb(); -} - -static inline void lose_fpu(void) -{ - preempt_disable(); -#if IS_ENABLED(CONFIG_LAZY_FPU) - if (last_task_used_math == current) { - last_task_used_math = NULL; -#else - if (test_tsk_fpu(task_pt_regs(current))) { -#endif - save_fpu(current); - } - disable_ptreg_fpu(task_pt_regs(current)); - preempt_enable(); -} - -static inline void own_fpu(void) -{ - preempt_disable(); -#if IS_ENABLED(CONFIG_LAZY_FPU) - if (last_task_used_math != current) { - if (last_task_used_math != NULL) - save_fpu(last_task_used_math); - load_fpu(¤t->thread.fpu); - last_task_used_math = current; - } -#else - if (!test_tsk_fpu(task_pt_regs(current))) { - load_fpu(¤t->thread.fpu); - } -#endif - enable_ptreg_fpu(task_pt_regs(current)); - preempt_enable(); -} - -#if !IS_ENABLED(CONFIG_LAZY_FPU) -static inline void unlazy_fpu(struct task_struct *tsk) -{ - preempt_disable(); - if (test_tsk_fpu(task_pt_regs(tsk))) - save_fpu(tsk); - preempt_enable(); -} -#endif /* !CONFIG_LAZY_FPU */ -static inline void clear_fpu(struct pt_regs *regs) -{ - preempt_disable(); - if (test_tsk_fpu(regs)) - disable_ptreg_fpu(regs); - preempt_enable(); -} -#endif /* CONFIG_FPU */ -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_NDS32_FPU_H */ diff --git a/arch/nds32/include/asm/fpuemu.h b/arch/nds32/include/asm/fpuemu.h deleted file mode 100644 index 63e7ef5f7969..000000000000 --- a/arch/nds32/include/asm/fpuemu.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (C) 2005-2018 Andes Technology Corporation */ - -#ifndef __ARCH_NDS32_FPUEMU_H -#define __ARCH_NDS32_FPUEMU_H - -/* - * single precision - */ - -void fadds(void *ft, void *fa, void *fb); -void fsubs(void *ft, void *fa, void *fb); -void fmuls(void *ft, void *fa, void *fb); -void fdivs(void *ft, void *fa, void *fb); -void fs2d(void *ft, void *fa); -void fs2si(void *ft, void *fa); -void fs2si_z(void *ft, void *fa); -void fs2ui(void *ft, void *fa); -void fs2ui_z(void *ft, void *fa); -void fsi2s(void *ft, void *fa); -void fui2s(void *ft, void *fa); -void fsqrts(void *ft, void *fa); -void fnegs(void *ft, void *fa); -int fcmps(void *ft, void *fa, void *fb, int cop); - -/* - * double precision - */ -void faddd(void *ft, void *fa, void *fb); -void fsubd(void *ft, void *fa, void *fb); -void fmuld(void *ft, void *fa, void *fb); -void fdivd(void *ft, void *fa, void *fb); -void fsqrtd(void *ft, void *fa); -void fd2s(void *ft, void *fa); -void fd2si(void *ft, void *fa); -void fd2si_z(void *ft, void *fa); -void fd2ui(void *ft, void *fa); -void fd2ui_z(void *ft, void *fa); -void fsi2d(void *ft, void *fa); -void fui2d(void *ft, void *fa); -void fnegd(void *ft, void *fa); -int fcmpd(void *ft, void *fa, void *fb, int cop); - -#endif /* __ARCH_NDS32_FPUEMU_H */ diff --git a/arch/nds32/include/asm/ftrace.h b/arch/nds32/include/asm/ftrace.h deleted file mode 100644 index 2f96cc96aa35..000000000000 --- a/arch/nds32/include/asm/ftrace.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef __ASM_NDS32_FTRACE_H -#define __ASM_NDS32_FTRACE_H - -#ifdef CONFIG_FUNCTION_TRACER - -#define HAVE_FUNCTION_GRAPH_FP_TEST - -#define MCOUNT_ADDR ((unsigned long)(_mcount)) -/* mcount call is composed of three instructions: - * sethi + ori + jral - */ -#define MCOUNT_INSN_SIZE 12 - -extern void _mcount(unsigned long parent_ip); - -#ifdef CONFIG_DYNAMIC_FTRACE - -#define FTRACE_ADDR ((unsigned long)_ftrace_caller) - -#ifdef __NDS32_EL__ -#define INSN_NOP 0x09000040 -#define INSN_SIZE(insn) (((insn & 0x00000080) == 0) ? 4 : 2) -#define IS_SETHI(insn) ((insn & 0x000000fe) == 0x00000046) -#define ENDIAN_CONVERT(insn) be32_to_cpu(insn) -#else /* __NDS32_EB__ */ -#define INSN_NOP 0x40000009 -#define INSN_SIZE(insn) (((insn & 0x80000000) == 0) ? 4 : 2) -#define IS_SETHI(insn) ((insn & 0xfe000000) == 0x46000000) -#define ENDIAN_CONVERT(insn) (insn) -#endif - -extern void _ftrace_caller(unsigned long parent_ip); -static inline unsigned long ftrace_call_adjust(unsigned long addr) -{ - return addr; -} -struct dyn_arch_ftrace { -}; - -#endif /* CONFIG_DYNAMIC_FTRACE */ - -#endif /* CONFIG_FUNCTION_TRACER */ - -#endif /* __ASM_NDS32_FTRACE_H */ diff --git a/arch/nds32/include/asm/futex.h b/arch/nds32/include/asm/futex.h deleted file mode 100644 index 4223f473bd36..000000000000 --- a/arch/nds32/include/asm/futex.h +++ /dev/null @@ -1,101 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __NDS32_FUTEX_H__ -#define __NDS32_FUTEX_H__ - -#include -#include -#include - -#define __futex_atomic_ex_table(err_reg) \ - " .pushsection __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 4f\n" \ - " .long 2b, 4f\n" \ - " .popsection\n" \ - " .pushsection .fixup,\"ax\"\n" \ - "4: move %0, " err_reg "\n" \ - " b 3b\n" \ - " .popsection" - -#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ - smp_mb(); \ - asm volatile( \ - " movi $ta, #0\n" \ - "1: llw %1, [%2+$ta]\n" \ - " " insn "\n" \ - "2: scw %0, [%2+$ta]\n" \ - " beqz %0, 1b\n" \ - " movi %0, #0\n" \ - "3:\n" \ - __futex_atomic_ex_table("%4") \ - : "=&r" (ret), "=&r" (oldval) \ - : "r" (uaddr), "r" (oparg), "i" (-EFAULT) \ - : "cc", "memory") -static inline int -futex_atomic_cmpxchg_inatomic(u32 * uval, u32 __user * uaddr, - u32 oldval, u32 newval) -{ - int ret = 0; - u32 val, tmp, flags; - - if (!access_ok(uaddr, sizeof(u32))) - return -EFAULT; - - smp_mb(); - asm volatile (" movi $ta, #0\n" - "1: llw %1, [%6 + $ta]\n" - " sub %3, %1, %4\n" - " cmovz %2, %5, %3\n" - " cmovn %2, %1, %3\n" - "2: scw %2, [%6 + $ta]\n" - " beqz %2, 1b\n" - "3:\n " __futex_atomic_ex_table("%7") - :"+&r"(ret), "=&r"(val), "=&r"(tmp), "=&r"(flags) - :"r"(oldval), "r"(newval), "r"(uaddr), "i"(-EFAULT) - :"$ta", "memory"); - smp_mb(); - - *uval = val; - return ret; -} - -static inline int -arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *uaddr) -{ - int oldval = 0, ret; - - if (!access_ok(uaddr, sizeof(u32))) - return -EFAULT; - switch (op) { - case FUTEX_OP_SET: - __futex_atomic_op("move %0, %3", ret, oldval, tmp, uaddr, - oparg); - break; - case FUTEX_OP_ADD: - __futex_atomic_op("add %0, %1, %3", ret, oldval, tmp, uaddr, - oparg); - break; - case FUTEX_OP_OR: - __futex_atomic_op("or %0, %1, %3", ret, oldval, tmp, uaddr, - oparg); - break; - case FUTEX_OP_ANDN: - __futex_atomic_op("and %0, %1, %3", ret, oldval, tmp, uaddr, - ~oparg); - break; - case FUTEX_OP_XOR: - __futex_atomic_op("xor %0, %1, %3", ret, oldval, tmp, uaddr, - oparg); - break; - default: - ret = -ENOSYS; - } - - if (!ret) - *oval = oldval; - - return ret; -} -#endif /* __NDS32_FUTEX_H__ */ diff --git a/arch/nds32/include/asm/highmem.h b/arch/nds32/include/asm/highmem.h deleted file mode 100644 index 16159a8716f2..000000000000 --- a/arch/nds32/include/asm/highmem.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef _ASM_HIGHMEM_H -#define _ASM_HIGHMEM_H - -#include -#include - -/* - * Right now we initialize only a single pte table. It can be extended - * easily, subsequent pte tables have to be allocated in one physical - * chunk of RAM. - */ -/* - * Ordering is (from lower to higher memory addresses): - * - * high_memory - * Persistent kmap area - * PKMAP_BASE - * fixed_addresses - * FIXADDR_START - * FIXADDR_TOP - * Vmalloc area - * VMALLOC_START - * VMALLOC_END - */ -#define PKMAP_BASE ((FIXADDR_START - PGDIR_SIZE) & (PGDIR_MASK)) -#define LAST_PKMAP PTRS_PER_PTE -#define LAST_PKMAP_MASK (LAST_PKMAP - 1) -#define PKMAP_NR(virt) (((virt) - (PKMAP_BASE)) >> PAGE_SHIFT) -#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) - -static inline void flush_cache_kmaps(void) -{ - cpu_dcache_wbinval_all(); -} - -/* declarations for highmem.c */ -extern unsigned long highstart_pfn, highend_pfn; - -extern pte_t *pkmap_page_table; - -extern void kmap_init(void); - -/* - * FIXME: The below looks broken vs. a kmap_atomic() in task context which - * is interupted and another kmap_atomic() happens in interrupt context. - * But what do I know about nds32. -- tglx - */ -#define arch_kmap_local_post_map(vaddr, pteval) \ - do { \ - __nds32__tlbop_inv(vaddr); \ - __nds32__mtsr_dsb(vaddr, NDS32_SR_TLB_VPN); \ - __nds32__tlbop_rwr(pteval); \ - __nds32__isb(); \ - } while (0) - -#define arch_kmap_local_pre_unmap(vaddr) \ - do { \ - __nds32__tlbop_inv(vaddr); \ - __nds32__isb(); \ - } while (0) - -#endif diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h deleted file mode 100644 index e57378d04006..000000000000 --- a/arch/nds32/include/asm/io.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_NDS32_IO_H -#define __ASM_NDS32_IO_H - -#include - -#define __raw_writeb __raw_writeb -static inline void __raw_writeb(u8 val, volatile void __iomem *addr) -{ - asm volatile("sbi %0, [%1]" : : "r" (val), "r" (addr)); -} - -#define __raw_writew __raw_writew -static inline void __raw_writew(u16 val, volatile void __iomem *addr) -{ - asm volatile("shi %0, [%1]" : : "r" (val), "r" (addr)); -} - -#define __raw_writel __raw_writel -static inline void __raw_writel(u32 val, volatile void __iomem *addr) -{ - asm volatile("swi %0, [%1]" : : "r" (val), "r" (addr)); -} - -#define __raw_readb __raw_readb -static inline u8 __raw_readb(const volatile void __iomem *addr) -{ - u8 val; - - asm volatile("lbi %0, [%1]" : "=r" (val) : "r" (addr)); - return val; -} - -#define __raw_readw __raw_readw -static inline u16 __raw_readw(const volatile void __iomem *addr) -{ - u16 val; - - asm volatile("lhi %0, [%1]" : "=r" (val) : "r" (addr)); - return val; -} - -#define __raw_readl __raw_readl -static inline u32 __raw_readl(const volatile void __iomem *addr) -{ - u32 val; - - asm volatile("lwi %0, [%1]" : "=r" (val) : "r" (addr)); - return val; -} - -#define __iormb() rmb() -#define __iowmb() wmb() - -/* - * {read,write}{b,w,l,q}_relaxed() are like the regular version, but - * are not guaranteed to provide ordering against spinlocks or memory - * accesses. - */ - -#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; }) -#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; }) -#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; }) -#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) -#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) -#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) - -/* - * {read,write}{b,w,l,q}() access little endian memory and return result in - * native endianness. - */ -#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) -#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) -#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) - -#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); }) -#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); }) -#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) - -#include - -#endif /* __ASM_NDS32_IO_H */ diff --git a/arch/nds32/include/asm/irqflags.h b/arch/nds32/include/asm/irqflags.h deleted file mode 100644 index 51ef800bb301..000000000000 --- a/arch/nds32/include/asm/irqflags.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include - -#define arch_local_irq_disable() \ - GIE_DISABLE(); - -#define arch_local_irq_enable() \ - GIE_ENABLE(); -static inline unsigned long arch_local_irq_save(void) -{ - unsigned long flags; - flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE; - GIE_DISABLE(); - return flags; -} - -static inline unsigned long arch_local_save_flags(void) -{ - unsigned long flags; - flags = __nds32__mfsr(NDS32_SR_PSW) & PSW_mskGIE; - return flags; -} - -static inline void arch_local_irq_restore(unsigned long flags) -{ - if(flags) - GIE_ENABLE(); -} - -static inline int arch_irqs_disabled_flags(unsigned long flags) -{ - return !flags; -} - -static inline int arch_irqs_disabled(void) -{ - return arch_irqs_disabled_flags(arch_local_save_flags()); -} diff --git a/arch/nds32/include/asm/l2_cache.h b/arch/nds32/include/asm/l2_cache.h deleted file mode 100644 index 3ea48e19e6de..000000000000 --- a/arch/nds32/include/asm/l2_cache.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef L2_CACHE_H -#define L2_CACHE_H - -/* CCTL_CMD_OP */ -#define L2_CA_CONF_OFF 0x0 -#define L2_IF_CONF_OFF 0x4 -#define L2CC_SETUP_OFF 0x8 -#define L2CC_PROT_OFF 0xC -#define L2CC_CTRL_OFF 0x10 -#define L2_INT_EN_OFF 0x20 -#define L2_STA_OFF 0x24 -#define RDERR_ADDR_OFF 0x28 -#define WRERR_ADDR_OFF 0x2c -#define EVDPTERR_ADDR_OFF 0x30 -#define IMPL3ERR_ADDR_OFF 0x34 -#define L2_CNT0_CTRL_OFF 0x40 -#define L2_EVNT_CNT0_OFF 0x44 -#define L2_CNT1_CTRL_OFF 0x48 -#define L2_EVNT_CNT1_OFF 0x4c -#define L2_CCTL_CMD_OFF 0x60 -#define L2_CCTL_STATUS_OFF 0x64 -#define L2_LINE_TAG_OFF 0x68 -#define L2_LINE_DPT_OFF 0x70 - -#define CCTL_CMD_L2_IX_INVAL 0x0 -#define CCTL_CMD_L2_PA_INVAL 0x1 -#define CCTL_CMD_L2_IX_WB 0x2 -#define CCTL_CMD_L2_PA_WB 0x3 -#define CCTL_CMD_L2_PA_WBINVAL 0x5 -#define CCTL_CMD_L2_SYNC 0xa - -/* CCTL_CMD_TYPE */ -#define CCTL_SINGLE_CMD 0 -#define CCTL_BLOCK_CMD 0x10 -#define CCTL_ALL_CMD 0x10 - -/****************************************************************************** - * L2_CA_CONF (Cache architecture configuration) - *****************************************************************************/ -#define L2_CA_CONF_offL2SET 0 -#define L2_CA_CONF_offL2WAY 4 -#define L2_CA_CONF_offL2CLSZ 8 -#define L2_CA_CONF_offL2DW 11 -#define L2_CA_CONF_offL2PT 14 -#define L2_CA_CONF_offL2VER 16 - -#define L2_CA_CONF_mskL2SET (0xFUL << L2_CA_CONF_offL2SET) -#define L2_CA_CONF_mskL2WAY (0xFUL << L2_CA_CONF_offL2WAY) -#define L2_CA_CONF_mskL2CLSZ (0x7UL << L2_CA_CONF_offL2CLSZ) -#define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW) -#define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT) -#define L2_CA_CONF_mskL2VER (0xFFFFUL << L2_CA_CONF_offL2VER) - -/****************************************************************************** - * L2CC_SETUP (L2CC Setup register) - *****************************************************************************/ -#define L2CC_SETUP_offPART 0 -#define L2CC_SETUP_mskPART (0x3UL << L2CC_SETUP_offPART) -#define L2CC_SETUP_offDDLATC 4 -#define L2CC_SETUP_mskDDLATC (0x3UL << L2CC_SETUP_offDDLATC) -#define L2CC_SETUP_offTDLATC 8 -#define L2CC_SETUP_mskTDLATC (0x3UL << L2CC_SETUP_offTDLATC) - -/****************************************************************************** - * L2CC_PROT (L2CC Protect register) - *****************************************************************************/ -#define L2CC_PROT_offMRWEN 31 -#define L2CC_PROT_mskMRWEN (0x1UL << L2CC_PROT_offMRWEN) - -/****************************************************************************** - * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n) - *****************************************************************************/ -#define L2CC_CTRL_offEN 31 -#define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN) - -/****************************************************************************** - * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n) - *****************************************************************************/ -#define L2_CCTL_STATUS_offCMD_COMP 31 -#define L2_CCTL_STATUS_mskCMD_COMP (0x1 << L2_CCTL_STATUS_offCMD_COMP) - -extern void __iomem *atl2c_base; -#include -#include -#include - -#define L2C_R_REG(offset) readl(atl2c_base + offset) -#define L2C_W_REG(offset, value) writel(value, atl2c_base + offset) - -#define L2_CMD_RDY() \ - do{;}while((L2C_R_REG(L2_CCTL_STATUS_OFF) & L2_CCTL_STATUS_mskCMD_COMP) == 0) - -static inline unsigned long L2_CACHE_SET(void) -{ - return 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >> - L2_CA_CONF_offL2SET); -} - -static inline unsigned long L2_CACHE_WAY(void) -{ - return 1 + - ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2WAY) >> - L2_CA_CONF_offL2WAY); -} - -static inline unsigned long L2_CACHE_LINE_SIZE(void) -{ - - return 4 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2CLSZ) >> - L2_CA_CONF_offL2CLSZ); -} - -static inline unsigned long GET_L2CC_CTRL_CPU(unsigned long cpu) -{ - if (cpu == smp_processor_id()) - return L2C_R_REG(L2CC_CTRL_OFF); - return L2C_R_REG(L2CC_CTRL_OFF + (cpu << 8)); -} - -static inline void SET_L2CC_CTRL_CPU(unsigned long cpu, unsigned long val) -{ - if (cpu == smp_processor_id()) - L2C_W_REG(L2CC_CTRL_OFF, val); - else - L2C_W_REG(L2CC_CTRL_OFF + (cpu << 8), val); -} - -static inline unsigned long GET_L2CC_STATUS_CPU(unsigned long cpu) -{ - if (cpu == smp_processor_id()) - return L2C_R_REG(L2_CCTL_STATUS_OFF); - return L2C_R_REG(L2_CCTL_STATUS_OFF + (cpu << 8)); -} -#endif diff --git a/arch/nds32/include/asm/linkage.h b/arch/nds32/include/asm/linkage.h deleted file mode 100644 index a696469abb70..000000000000 --- a/arch/nds32/include/asm/linkage.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_LINKAGE_H -#define __ASM_LINKAGE_H - -/* This file is required by include/linux/linkage.h */ -#define __ALIGN .align 2 -#define __ALIGN_STR ".align 2" - -#endif diff --git a/arch/nds32/include/asm/memory.h b/arch/nds32/include/asm/memory.h deleted file mode 100644 index 62faafbc28e4..000000000000 --- a/arch/nds32/include/asm/memory.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_NDS32_MEMORY_H -#define __ASM_NDS32_MEMORY_H - -#include -#include - -#ifndef __ASSEMBLY__ -#include -#endif - -#ifndef PHYS_OFFSET -#define PHYS_OFFSET (0x0) -#endif - -/* - * TASK_SIZE - the maximum size of a user space task. - * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area - */ -#define TASK_SIZE ((CONFIG_PAGE_OFFSET) - (SZ_32M)) -#define TASK_UNMAPPED_BASE ALIGN(TASK_SIZE / 3, SZ_32M) -#define PAGE_OFFSET (CONFIG_PAGE_OFFSET) - -/* - * Physical vs virtual RAM address space conversion. These are - * private definitions which should NOT be used outside memory.h - * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. - */ -#ifndef __virt_to_phys -#define __virt_to_phys(x) ((x) - PAGE_OFFSET + PHYS_OFFSET) -#define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) -#endif - -/* - * The module space lives between the addresses given by TASK_SIZE - * and PAGE_OFFSET - it must be within 32MB of the kernel text. - */ -#define MODULES_END (PAGE_OFFSET) -#define MODULES_VADDR (MODULES_END - SZ_32M) - -#if TASK_SIZE > MODULES_VADDR -#error Top of user space clashes with start of module space -#endif - -#ifndef __ASSEMBLY__ - -/* - * PFNs are used to describe any physical page; this means - * PFN 0 == physical address 0. - * - * This is the PFN of the first RAM page in the kernel - * direct-mapped view. We assume this is the first page - * of RAM in the mem_map as well. - */ -#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT) - -/* - * Drivers should NOT use these either. - */ -#define __pa(x) __virt_to_phys((unsigned long)(x)) -#define __va(x) ((void *)__phys_to_virt((unsigned long)(x))) - -/* - * Conversion between a struct page and a physical address. - * - * Note: when converting an unknown physical address to a - * struct page, the resulting pointer must be validated - * using VALID_PAGE(). It must return an invalid struct page - * for any physical address not corresponding to a system - * RAM address. - * - * pfn_valid(pfn) indicates whether a PFN number is valid - * - * virt_to_page(k) convert a _valid_ virtual address to struct page * - * virt_addr_valid(k) indicates whether a virtual address is valid - */ -#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET -#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr)) - -#define virt_to_page(kaddr) (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)) -#define virt_addr_valid(kaddr) ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory) - -#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) - -#endif - -#include - -#endif diff --git a/arch/nds32/include/asm/mmu.h b/arch/nds32/include/asm/mmu.h deleted file mode 100644 index 89d63afee455..000000000000 --- a/arch/nds32/include/asm/mmu.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __NDS32_MMU_H -#define __NDS32_MMU_H - -typedef struct { - unsigned int id; - void *vdso; -} mm_context_t; - -#endif diff --git a/arch/nds32/include/asm/mmu_context.h b/arch/nds32/include/asm/mmu_context.h deleted file mode 100644 index c651bc8cacdc..000000000000 --- a/arch/nds32/include/asm/mmu_context.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_NDS32_MMU_CONTEXT_H -#define __ASM_NDS32_MMU_CONTEXT_H - -#include -#include -#include -#include - -#define init_new_context init_new_context -static inline int -init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ - mm->context.id = 0; - return 0; -} - -#define CID_BITS 9 -extern spinlock_t cid_lock; -extern unsigned int cpu_last_cid; - -static inline void __new_context(struct mm_struct *mm) -{ - unsigned int cid; - unsigned long flags; - - spin_lock_irqsave(&cid_lock, flags); - cid = cpu_last_cid; - cpu_last_cid += 1 << TLB_MISC_offCID; - if (cpu_last_cid == 0) - cpu_last_cid = 1 << TLB_MISC_offCID << CID_BITS; - - if ((cid & TLB_MISC_mskCID) == 0) - flush_tlb_all(); - spin_unlock_irqrestore(&cid_lock, flags); - - mm->context.id = cid; -} - -static inline void check_context(struct mm_struct *mm) -{ - if (unlikely - ((mm->context.id ^ cpu_last_cid) >> TLB_MISC_offCID >> CID_BITS)) - __new_context(mm); -} - -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, - struct task_struct *tsk) -{ - unsigned int cpu = smp_processor_id(); - - if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) { - check_context(next); - cpu_switch_mm(next); - } -} - -#include - -#endif diff --git a/arch/nds32/include/asm/nds32.h b/arch/nds32/include/asm/nds32.h deleted file mode 100644 index 4994f6a9e0a0..000000000000 --- a/arch/nds32/include/asm/nds32.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef _ASM_NDS32_NDS32_H_ -#define _ASM_NDS32_NDS32_H_ - -#include -#include - -#ifndef __ASSEMBLY__ -#include -#include -#include - -#ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE -#define FP_OFFSET (-3) -#else -#define FP_OFFSET (-2) -#endif -#define LP_OFFSET (-1) - -extern void __init early_trap_init(void); -static inline void GIE_ENABLE(void) -{ - mb(); - __nds32__gie_en(); -} - -static inline void GIE_DISABLE(void) -{ - mb(); - __nds32__gie_dis(); -} - -static inline unsigned long CACHE_SET(unsigned char cache) -{ - - if (cache == ICACHE) - return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >> - ICM_CFG_offISET); - else - return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >> - DCM_CFG_offDSET); -} - -static inline unsigned long CACHE_WAY(unsigned char cache) -{ - - if (cache == ICACHE) - return 1 + - ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY); - else - return 1 + - ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY); -} - -static inline unsigned long CACHE_LINE_SIZE(unsigned char cache) -{ - - if (cache == ICACHE) - return 8 << - (((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1); - else - return 8 << - (((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1); -} - -#endif /* __ASSEMBLY__ */ - -#define IVB_BASE PHYS_OFFSET /* in user space for intr/exc/trap/break table base, 64KB aligned - * We defined at the start of the physical memory */ - -/* dispatched sub-entry exception handler numbering */ -#define RD_PROT 0 /* read protrection */ -#define WRT_PROT 1 /* write protection */ -#define NOEXEC 2 /* non executable */ -#define PAGE_MODIFY 3 /* page modified */ -#define ACC_BIT 4 /* access bit */ -#define RESVED_PTE 5 /* reserved PTE attribute */ -/* reserved 6 ~ 16 */ - -#endif /* _ASM_NDS32_NDS32_H_ */ diff --git a/arch/nds32/include/asm/nds32_fpu_inst.h b/arch/nds32/include/asm/nds32_fpu_inst.h deleted file mode 100644 index 1e4b86a90a48..000000000000 --- a/arch/nds32/include/asm/nds32_fpu_inst.h +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (C) 2005-2018 Andes Technology Corporation */ - -#ifndef __NDS32_FPU_INST_H -#define __NDS32_FPU_INST_H - -#define cop0_op 0x35 - -/* - * COP0 field of opcodes. - */ -#define fs1_op 0x0 -#define fs2_op 0x4 -#define fd1_op 0x8 -#define fd2_op 0xc - -/* - * FS1 opcode. - */ -enum fs1 { - fadds_op, fsubs_op, fcpynss_op, fcpyss_op, - fmadds_op, fmsubs_op, fcmovns_op, fcmovzs_op, - fnmadds_op, fnmsubs_op, - fmuls_op = 0xc, fdivs_op, - fs1_f2op_op = 0xf -}; - -/* - * FS1/F2OP opcode. - */ -enum fs1_f2 { - fs2d_op, fsqrts_op, - fui2s_op = 0x8, fsi2s_op = 0xc, - fs2ui_op = 0x10, fs2ui_z_op = 0x14, - fs2si_op = 0x18, fs2si_z_op = 0x1c -}; - -/* - * FS2 opcode. - */ -enum fs2 { - fcmpeqs_op, fcmpeqs_e_op, fcmplts_op, fcmplts_e_op, - fcmples_op, fcmples_e_op, fcmpuns_op, fcmpuns_e_op -}; - -/* - * FD1 opcode. - */ -enum fd1 { - faddd_op, fsubd_op, fcpynsd_op, fcpysd_op, - fmaddd_op, fmsubd_op, fcmovnd_op, fcmovzd_op, - fnmaddd_op, fnmsubd_op, - fmuld_op = 0xc, fdivd_op, fd1_f2op_op = 0xf -}; - -/* - * FD1/F2OP opcode. - */ -enum fd1_f2 { - fd2s_op, fsqrtd_op, - fui2d_op = 0x8, fsi2d_op = 0xc, - fd2ui_op = 0x10, fd2ui_z_op = 0x14, - fd2si_op = 0x18, fd2si_z_op = 0x1c -}; - -/* - * FD2 opcode. - */ -enum fd2 { - fcmpeqd_op, fcmpeqd_e_op, fcmpltd_op, fcmpltd_e_op, - fcmpled_op, fcmpled_e_op, fcmpund_op, fcmpund_e_op -}; - -#define NDS32Insn(x) x - -#define I_OPCODE_off 25 -#define NDS32Insn_OPCODE(x) (NDS32Insn(x) >> I_OPCODE_off) - -#define I_OPCODE_offRt 20 -#define I_OPCODE_mskRt (0x1fUL << I_OPCODE_offRt) -#define NDS32Insn_OPCODE_Rt(x) \ - ((NDS32Insn(x) & I_OPCODE_mskRt) >> I_OPCODE_offRt) - -#define I_OPCODE_offRa 15 -#define I_OPCODE_mskRa (0x1fUL << I_OPCODE_offRa) -#define NDS32Insn_OPCODE_Ra(x) \ - ((NDS32Insn(x) & I_OPCODE_mskRa) >> I_OPCODE_offRa) - -#define I_OPCODE_offRb 10 -#define I_OPCODE_mskRb (0x1fUL << I_OPCODE_offRb) -#define NDS32Insn_OPCODE_Rb(x) \ - ((NDS32Insn(x) & I_OPCODE_mskRb) >> I_OPCODE_offRb) - -#define I_OPCODE_offbit1014 10 -#define I_OPCODE_mskbit1014 (0x1fUL << I_OPCODE_offbit1014) -#define NDS32Insn_OPCODE_BIT1014(x) \ - ((NDS32Insn(x) & I_OPCODE_mskbit1014) >> I_OPCODE_offbit1014) - -#define I_OPCODE_offbit69 6 -#define I_OPCODE_mskbit69 (0xfUL << I_OPCODE_offbit69) -#define NDS32Insn_OPCODE_BIT69(x) \ - ((NDS32Insn(x) & I_OPCODE_mskbit69) >> I_OPCODE_offbit69) - -#define I_OPCODE_offCOP0 0 -#define I_OPCODE_mskCOP0 (0x3fUL << I_OPCODE_offCOP0) -#define NDS32Insn_OPCODE_COP0(x) \ - ((NDS32Insn(x) & I_OPCODE_mskCOP0) >> I_OPCODE_offCOP0) - -#endif /* __NDS32_FPU_INST_H */ diff --git a/arch/nds32/include/asm/page.h b/arch/nds32/include/asm/page.h deleted file mode 100644 index add33a7f02c8..000000000000 --- a/arch/nds32/include/asm/page.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2005-2017 Andes Technology Corporation - */ - -#ifndef _ASMNDS32_PAGE_H -#define _ASMNDS32_PAGE_H - -#ifdef CONFIG_ANDES_PAGE_SIZE_4KB -#define PAGE_SHIFT 12 -#endif -#ifdef CONFIG_ANDES_PAGE_SIZE_8KB -#define PAGE_SHIFT 13 -#endif -#include -#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ - -struct page; -struct vm_area_struct; -#ifdef CONFIG_CPU_CACHE_ALIASING -extern void copy_user_highpage(struct page *to, struct page *from, - unsigned long vaddr, struct vm_area_struct *vma); -extern void clear_user_highpage(struct page *page, unsigned long vaddr); - -void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, - struct page *to); -void clear_user_page(void *addr, unsigned long vaddr, struct page *page); -#define __HAVE_ARCH_COPY_USER_HIGHPAGE -#define clear_user_highpage clear_user_highpage -#else -#define clear_user_page(page, vaddr, pg) clear_page(page) -#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) -#endif - -void clear_page(void *page); -void copy_page(void *to, void *from); - -typedef unsigned long pte_t; -typedef unsigned long pgd_t; -typedef unsigned long pgprot_t; - -#define pte_val(x) (x) -#define pgd_val(x) (x) -#define pgprot_val(x) (x) - -#define __pte(x) (x) -#define __pgd(x) (x) -#define __pgprot(x) (x) - -typedef struct page *pgtable_t; - -#include -#include - -#endif /* !__ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif diff --git a/arch/nds32/include/asm/perf_event.h b/arch/nds32/include/asm/perf_event.h deleted file mode 100644 index fcdff02acc14..000000000000 --- a/arch/nds32/include/asm/perf_event.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (C) 2008-2018 Andes Technology Corporation */ - -#ifndef __ASM_PERF_EVENT_H -#define __ASM_PERF_EVENT_H - -/* - * This file is request by Perf, - * please refer to tools/perf/design.txt for more details - */ -struct pt_regs; -unsigned long perf_instruction_pointer(struct pt_regs *regs); -unsigned long perf_misc_flags(struct pt_regs *regs); -#define perf_misc_flags(regs) perf_misc_flags(regs) - -#endif diff --git a/arch/nds32/include/asm/pgalloc.h b/arch/nds32/include/asm/pgalloc.h deleted file mode 100644 index a08e1ebca70e..000000000000 --- a/arch/nds32/include/asm/pgalloc.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef _ASMNDS32_PGALLOC_H -#define _ASMNDS32_PGALLOC_H - -#include -#include -#include -#include - -#define __HAVE_ARCH_PTE_ALLOC_ONE -#include /* for pte_{alloc,free}_one */ - -extern pgd_t *pgd_alloc(struct mm_struct *mm); -extern void pgd_free(struct mm_struct *mm, pgd_t * pgd); - -static inline pgtable_t pte_alloc_one(struct mm_struct *mm) -{ - pgtable_t pte; - - pte = __pte_alloc_one(mm, GFP_PGTABLE_USER); - if (pte) - cpu_dcache_wb_page((unsigned long)page_address(pte)); - - return pte; -} - -/* - * Populate the pmdp entry with a pointer to the pte. This pmd is part - * of the mm address space. - * - * Ensure that we always set both PMD entries. - */ -static inline void -pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmdp, pte_t * ptep) -{ - unsigned long pte_ptr = (unsigned long)ptep; - unsigned long pmdval; - - BUG_ON(mm != &init_mm); - - /* - * The pmd must be loaded with the physical - * address of the PTE table - */ - pmdval = __pa(pte_ptr) | _PAGE_KERNEL_TABLE; - set_pmd(pmdp, __pmd(pmdval)); -} - -static inline void -pmd_populate(struct mm_struct *mm, pmd_t * pmdp, pgtable_t ptep) -{ - unsigned long pmdval; - - BUG_ON(mm == &init_mm); - - pmdval = page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE; - set_pmd(pmdp, __pmd(pmdval)); -} - -#endif diff --git a/arch/nds32/include/asm/pgtable.h b/arch/nds32/include/asm/pgtable.h deleted file mode 100644 index 7ff144467b29..000000000000 --- a/arch/nds32/include/asm/pgtable.h +++ /dev/null @@ -1,378 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef _ASMNDS32_PGTABLE_H -#define _ASMNDS32_PGTABLE_H - -#include -#include - -#include -#include -#ifndef __ASSEMBLY__ -#include -#include -#endif - -#ifdef CONFIG_ANDES_PAGE_SIZE_4KB -#define PGDIR_SHIFT 22 -#define PTRS_PER_PGD 1024 -#define PTRS_PER_PTE 1024 -#endif - -#ifdef CONFIG_ANDES_PAGE_SIZE_8KB -#define PGDIR_SHIFT 24 -#define PTRS_PER_PGD 256 -#define PTRS_PER_PTE 2048 -#endif - -#ifndef __ASSEMBLY__ -extern void __pte_error(const char *file, int line, unsigned long val); -extern void __pgd_error(const char *file, int line, unsigned long val); - -#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) -#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) -#endif /* !__ASSEMBLY__ */ - -#define PMD_SIZE (1UL << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE-1)) -#define PGDIR_SIZE (1UL << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE-1)) - -/* - * This is the lowest virtual address we can permit any user space - * mapping to be mapped at. This is particularly important for - * non-high vector CPUs. - */ -#define FIRST_USER_ADDRESS 0x8000 - -#ifdef CONFIG_HIGHMEM -#define CONSISTENT_BASE ((PKMAP_BASE) - (SZ_2M)) -#define CONSISTENT_END (PKMAP_BASE) -#else -#define CONSISTENT_BASE (FIXADDR_START - SZ_2M) -#define CONSISTENT_END (FIXADDR_START) -#endif -#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) - -#ifdef CONFIG_HIGHMEM -#ifndef __ASSEMBLY__ -#include -#endif -#endif - -#define VMALLOC_RESERVE SZ_128M -#define VMALLOC_END (CONSISTENT_BASE - PAGE_SIZE) -#define VMALLOC_START ((VMALLOC_END) - VMALLOC_RESERVE) -#define VMALLOC_VMADDR(x) ((unsigned long)(x)) -#define MAXMEM __pa(VMALLOC_START) -#define MAXMEM_PFN PFN_DOWN(MAXMEM) - -#define FIRST_USER_PGD_NR 0 -#define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) + FIRST_USER_PGD_NR) - -/* L2 PTE */ -#define _PAGE_V (1UL << 0) - -#define _PAGE_M_XKRW (0UL << 1) -#define _PAGE_M_UR_KR (1UL << 1) -#define _PAGE_M_UR_KRW (2UL << 1) -#define _PAGE_M_URW_KRW (3UL << 1) -#define _PAGE_M_KR (5UL << 1) -#define _PAGE_M_KRW (7UL << 1) - -#define _PAGE_D (1UL << 4) -#define _PAGE_E (1UL << 5) -#define _PAGE_A (1UL << 6) -#define _PAGE_G (1UL << 7) - -#define _PAGE_C_DEV (0UL << 8) -#define _PAGE_C_DEV_WB (1UL << 8) -#define _PAGE_C_MEM (2UL << 8) -#define _PAGE_C_MEM_SHRD_WB (4UL << 8) -#define _PAGE_C_MEM_SHRD_WT (5UL << 8) -#define _PAGE_C_MEM_WB (6UL << 8) -#define _PAGE_C_MEM_WT (7UL << 8) - -#define _PAGE_L (1UL << 11) - -#define _HAVE_PAGE_L (_PAGE_L) -#define _PAGE_FILE (1UL << 1) -#define _PAGE_YOUNG 0 -#define _PAGE_M_MASK _PAGE_M_KRW -#define _PAGE_C_MASK _PAGE_C_MEM_WT - -#ifdef CONFIG_SMP -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -#define _PAGE_CACHE_SHRD _PAGE_C_MEM_SHRD_WT -#else -#define _PAGE_CACHE_SHRD _PAGE_C_MEM_SHRD_WB -#endif -#else -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -#define _PAGE_CACHE_SHRD _PAGE_C_MEM_WT -#else -#define _PAGE_CACHE_SHRD _PAGE_C_MEM_WB -#endif -#endif - -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -#define _PAGE_CACHE _PAGE_C_MEM_WT -#else -#define _PAGE_CACHE _PAGE_C_MEM_WB -#endif - -#define _PAGE_IOREMAP \ - (_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_G | _PAGE_C_DEV) - -/* - * + Level 1 descriptor (PMD) - */ -#define PMD_TYPE_TABLE 0 - -#ifndef __ASSEMBLY__ - -#define _PAGE_USER_TABLE PMD_TYPE_TABLE -#define _PAGE_KERNEL_TABLE PMD_TYPE_TABLE - -#define PAGE_EXEC __pgprot(_PAGE_V | _PAGE_M_XKRW | _PAGE_E) -#define PAGE_NONE __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_A) -#define PAGE_READ __pgprot(_PAGE_V | _PAGE_M_UR_KR) -#define PAGE_RDWR __pgprot(_PAGE_V | _PAGE_M_URW_KRW | _PAGE_D) -#define PAGE_COPY __pgprot(_PAGE_V | _PAGE_M_UR_KR) - -#define PAGE_UXKRWX_V1 __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD) -#define PAGE_UXKRWX_V2 __pgprot(_PAGE_V | _PAGE_M_XKRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD) -#define PAGE_URXKRWX_V2 __pgprot(_PAGE_V | _PAGE_M_UR_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD) -#define PAGE_CACHE_L1 __pgprot(_HAVE_PAGE_L | _PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE) -#define PAGE_MEMORY __pgprot(_HAVE_PAGE_L | _PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD) -#define PAGE_KERNEL __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_E | _PAGE_G | _PAGE_CACHE_SHRD) -#define PAGE_SHARED __pgprot(_PAGE_V | _PAGE_M_URW_KRW | _PAGE_D | _PAGE_CACHE_SHRD) -#define PAGE_DEVICE __pgprot(_PAGE_V | _PAGE_M_KRW | _PAGE_D | _PAGE_G | _PAGE_C_DEV) -#endif /* __ASSEMBLY__ */ - -/* xwr */ -#define __P000 (PAGE_NONE | _PAGE_CACHE_SHRD) -#define __P001 (PAGE_READ | _PAGE_CACHE_SHRD) -#define __P010 (PAGE_COPY | _PAGE_CACHE_SHRD) -#define __P011 (PAGE_COPY | _PAGE_CACHE_SHRD) -#define __P100 (PAGE_EXEC | _PAGE_CACHE_SHRD) -#define __P101 (PAGE_READ | _PAGE_E | _PAGE_CACHE_SHRD) -#define __P110 (PAGE_COPY | _PAGE_E | _PAGE_CACHE_SHRD) -#define __P111 (PAGE_COPY | _PAGE_E | _PAGE_CACHE_SHRD) - -#define __S000 (PAGE_NONE | _PAGE_CACHE_SHRD) -#define __S001 (PAGE_READ | _PAGE_CACHE_SHRD) -#define __S010 (PAGE_RDWR | _PAGE_CACHE_SHRD) -#define __S011 (PAGE_RDWR | _PAGE_CACHE_SHRD) -#define __S100 (PAGE_EXEC | _PAGE_CACHE_SHRD) -#define __S101 (PAGE_READ | _PAGE_E | _PAGE_CACHE_SHRD) -#define __S110 (PAGE_RDWR | _PAGE_E | _PAGE_CACHE_SHRD) -#define __S111 (PAGE_RDWR | _PAGE_E | _PAGE_CACHE_SHRD) - -#ifndef __ASSEMBLY__ -/* - * ZERO_PAGE is a global shared page that is always zero: used - * for zero-mapped memory areas etc.. - */ -extern struct page *empty_zero_page; -extern void paging_init(void); -#define ZERO_PAGE(vaddr) (empty_zero_page) - -#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) -#define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))) - -#define pte_none(pte) !(pte_val(pte)) -#define pte_clear(mm,addr,ptep) set_pte_at((mm),(addr),(ptep), __pte(0)) -#define pte_page(pte) (pfn_to_page(pte_pfn(pte))) - -static unsigned long pmd_page_vaddr(pmd_t pmd) -{ - return ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)); -} - -#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) -/* - * Set a level 1 translation table entry, and clean it out of - * any caches such that the MMUs can load it correctly. - */ -static inline void set_pmd(pmd_t * pmdp, pmd_t pmd) -{ - - *pmdp = pmd; -#if !defined(CONFIG_CPU_DCACHE_DISABLE) && !defined(CONFIG_CPU_DCACHE_WRITETHROUGH) - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (pmdp):"memory"); - __nds32__msync_all(); - __nds32__dsb(); -#endif -} - -/* - * Set a PTE and flush it out - */ -static inline void set_pte(pte_t * ptep, pte_t pte) -{ - - *ptep = pte; -#if !defined(CONFIG_CPU_DCACHE_DISABLE) && !defined(CONFIG_CPU_DCACHE_WRITETHROUGH) - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (ptep):"memory"); - __nds32__msync_all(); - __nds32__dsb(); -#endif -} - -/* - * The following only work if pte_present() is true. - * Undefined behaviour if not.. - */ - -/* - * pte_write: this page is writeable for user mode - * pte_read: this page is readable for user mode - * pte_kernel_write: this page is writeable for kernel mode - * - * We don't have pte_kernel_read because kernel always can read. - * - * */ - -#define pte_present(pte) (pte_val(pte) & _PAGE_V) -#define pte_write(pte) ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW) -#define pte_read(pte) (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KR) || \ - ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KRW) || \ - ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW)) -#define pte_kernel_write(pte) (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_URW_KRW) || \ - ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_UR_KRW) || \ - ((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_KRW) || \ - (((pte_val(pte) & _PAGE_M_MASK) == _PAGE_M_XKRW) && pte_exec(pte))) -#define pte_exec(pte) (pte_val(pte) & _PAGE_E) -#define pte_dirty(pte) (pte_val(pte) & _PAGE_D) -#define pte_young(pte) (pte_val(pte) & _PAGE_YOUNG) - -/* - * The following only works if pte_present() is not true. - */ -#define pte_file(pte) (pte_val(pte) & _PAGE_FILE) -#define pte_to_pgoff(x) (pte_val(x) >> 2) -#define pgoff_to_pte(x) __pte(((x) << 2) | _PAGE_FILE) - -#define PTE_FILE_MAX_BITS 29 - -#define PTE_BIT_FUNC(fn,op) \ -static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } - -static inline pte_t pte_wrprotect(pte_t pte) -{ - pte_val(pte) = pte_val(pte) & ~_PAGE_M_MASK; - pte_val(pte) = pte_val(pte) | _PAGE_M_UR_KR; - return pte; -} - -static inline pte_t pte_mkwrite(pte_t pte) -{ - pte_val(pte) = pte_val(pte) & ~_PAGE_M_MASK; - pte_val(pte) = pte_val(pte) | _PAGE_M_URW_KRW; - return pte; -} - -PTE_BIT_FUNC(exprotect, &=~_PAGE_E); -PTE_BIT_FUNC(mkexec, |=_PAGE_E); -PTE_BIT_FUNC(mkclean, &=~_PAGE_D); -PTE_BIT_FUNC(mkdirty, |=_PAGE_D); -PTE_BIT_FUNC(mkold, &=~_PAGE_YOUNG); -PTE_BIT_FUNC(mkyoung, |=_PAGE_YOUNG); - -/* - * Mark the prot value as uncacheable and unbufferable. - */ -#define pgprot_noncached(prot) __pgprot((pgprot_val(prot)&~_PAGE_C_MASK) | _PAGE_C_DEV) -#define pgprot_writecombine(prot) __pgprot((pgprot_val(prot)&~_PAGE_C_MASK) | _PAGE_C_DEV_WB) - -#define pmd_none(pmd) (pmd_val(pmd)&0x1) -#define pmd_present(pmd) (!pmd_none(pmd)) -#define pmd_bad(pmd) pmd_none(pmd) - -#define copy_pmd(pmdpd,pmdps) set_pmd((pmdpd), *(pmdps)) -#define pmd_clear(pmdp) set_pmd((pmdp), __pmd(1)) - -static inline pmd_t __mk_pmd(pte_t * ptep, unsigned long prot) -{ - unsigned long ptr = (unsigned long)ptep; - pmd_t pmd; - - /* - * The pmd must be loaded with the physical - * address of the PTE table - */ - - pmd_val(pmd) = __virt_to_phys(ptr) | prot; - return pmd; -} - -#define pmd_pfn(pmd) (pmd_val(pmd) >> PAGE_SHIFT) -#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd))) - -/* - * Permanent address of a page. We never have highmem, so this is trivial. - */ -#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT)) - -/* - * Conversion functions: convert a page and protection to a page entry, - * and a page entry and page directory to the page they refer to. - */ -#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) - -/* - * The "pgd_xxx()" functions here are trivial for a folded two-level - * setup: the pgd is never bad, and a pmd always exists (as it's folded - * into the pgd entry) - */ -#define pgd_none(pgd) (0) -#define pgd_bad(pgd) (0) -#define pgd_present(pgd) (1) -#define pgd_clear(pgdp) do { } while (0) - -#define page_pte_prot(page,prot) mk_pte(page, prot) -#define page_pte(page) mk_pte(page, __pgprot(0)) -/* - * L1PTE = $mr1 + ((virt >> PMD_SHIFT) << 2); - * L2PTE = (((virt >> PAGE_SHIFT) & (PTRS_PER_PTE -1 )) << 2); - * PPN = (phys & 0xfffff000); - * -*/ - -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ - const unsigned long mask = 0xfff; - pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); - return pte; -} - -extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; - -/* Encode and decode a swap entry. - * - * We support up to 32GB of swap on 4k machines - */ -#define __swp_type(x) (((x).val >> 2) & 0x7f) -#define __swp_offset(x) ((x).val >> 9) -#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) - -/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ -#define kern_addr_valid(addr) (1) - -/* - * We provide our own arch_get_unmapped_area to cope with VIPT caches. - */ -#define HAVE_ARCH_UNMAPPED_AREA - -/* - * remap a physical address `phys' of size `size' with page protection `prot' - * into virtual address `from' - */ - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASMNDS32_PGTABLE_H */ diff --git a/arch/nds32/include/asm/pmu.h b/arch/nds32/include/asm/pmu.h deleted file mode 100644 index e1ac0b0b8bcf..000000000000 --- a/arch/nds32/include/asm/pmu.h +++ /dev/null @@ -1,386 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (C) 2008-2018 Andes Technology Corporation */ - -#ifndef __ASM_PMU_H -#define __ASM_PMU_H - -#include -#include -#include -#include - -/* Has special meaning for perf core implementation */ -#define HW_OP_UNSUPPORTED 0x0 -#define C(_x) PERF_COUNT_HW_CACHE_##_x -#define CACHE_OP_UNSUPPORTED 0x0 - -/* Enough for both software and hardware defined events */ -#define SOFTWARE_EVENT_MASK 0xFF - -#define PFM_OFFSET_MAGIC_0 2 /* DO NOT START FROM 0 */ -#define PFM_OFFSET_MAGIC_1 (PFM_OFFSET_MAGIC_0 + 36) -#define PFM_OFFSET_MAGIC_2 (PFM_OFFSET_MAGIC_1 + 36) - -enum { PFMC0, PFMC1, PFMC2, MAX_COUNTERS }; - -u32 PFM_CTL_OVF[3] = { PFM_CTL_mskOVF0, PFM_CTL_mskOVF1, - PFM_CTL_mskOVF2 }; -u32 PFM_CTL_EN[3] = { PFM_CTL_mskEN0, PFM_CTL_mskEN1, - PFM_CTL_mskEN2 }; -u32 PFM_CTL_OFFSEL[3] = { PFM_CTL_offSEL0, PFM_CTL_offSEL1, - PFM_CTL_offSEL2 }; -u32 PFM_CTL_IE[3] = { PFM_CTL_mskIE0, PFM_CTL_mskIE1, PFM_CTL_mskIE2 }; -u32 PFM_CTL_KS[3] = { PFM_CTL_mskKS0, PFM_CTL_mskKS1, PFM_CTL_mskKS2 }; -u32 PFM_CTL_KU[3] = { PFM_CTL_mskKU0, PFM_CTL_mskKU1, PFM_CTL_mskKU2 }; -u32 PFM_CTL_SEL[3] = { PFM_CTL_mskSEL0, PFM_CTL_mskSEL1, PFM_CTL_mskSEL2 }; -/* - * Perf Events' indices - */ -#define NDS32_IDX_CYCLE_COUNTER 0 -#define NDS32_IDX_COUNTER0 1 -#define NDS32_IDX_COUNTER1 2 - -/* The events for a given PMU register set. */ -struct pmu_hw_events { - /* - * The events that are active on the PMU for the given index. - */ - struct perf_event *events[MAX_COUNTERS]; - - /* - * A 1 bit for an index indicates that the counter is being used for - * an event. A 0 means that the counter can be used. - */ - unsigned long used_mask[BITS_TO_LONGS(MAX_COUNTERS)]; - - /* - * Hardware lock to serialize accesses to PMU registers. Needed for the - * read/modify/write sequences. - */ - raw_spinlock_t pmu_lock; -}; - -struct nds32_pmu { - struct pmu pmu; - cpumask_t active_irqs; - char *name; - irqreturn_t (*handle_irq)(int irq_num, void *dev); - void (*enable)(struct perf_event *event); - void (*disable)(struct perf_event *event); - int (*get_event_idx)(struct pmu_hw_events *hw_events, - struct perf_event *event); - int (*set_event_filter)(struct hw_perf_event *evt, - struct perf_event_attr *attr); - u32 (*read_counter)(struct perf_event *event); - void (*write_counter)(struct perf_event *event, u32 val); - void (*start)(struct nds32_pmu *nds32_pmu); - void (*stop)(struct nds32_pmu *nds32_pmu); - void (*reset)(void *data); - int (*request_irq)(struct nds32_pmu *nds32_pmu, irq_handler_t handler); - void (*free_irq)(struct nds32_pmu *nds32_pmu); - int (*map_event)(struct perf_event *event); - int num_events; - atomic_t active_events; - u64 max_period; - struct platform_device *plat_device; - struct pmu_hw_events *(*get_hw_events)(void); -}; - -#define to_nds32_pmu(p) (container_of(p, struct nds32_pmu, pmu)) - -int nds32_pmu_register(struct nds32_pmu *nds32_pmu, int type); - -u64 nds32_pmu_event_update(struct perf_event *event); - -int nds32_pmu_event_set_period(struct perf_event *event); - -/* - * Common NDS32 SPAv3 event types - * - * Note: An implementation may not be able to count all of these events - * but the encodings are considered to be `reserved' in the case that - * they are not available. - * - * SEL_TOTAL_CYCLES will add an offset is due to ZERO is defined as - * NOT_SUPPORTED EVENT mapping in generic perf code. - * You will need to deal it in the event writing implementation. - */ -enum spav3_counter_0_perf_types { - SPAV3_0_SEL_BASE = -1 + PFM_OFFSET_MAGIC_0, /* counting symbol */ - SPAV3_0_SEL_TOTAL_CYCLES = 0 + PFM_OFFSET_MAGIC_0, - SPAV3_0_SEL_COMPLETED_INSTRUCTION = 1 + PFM_OFFSET_MAGIC_0, - SPAV3_0_SEL_LAST /* counting symbol */ -}; - -enum spav3_counter_1_perf_types { - SPAV3_1_SEL_BASE = -1 + PFM_OFFSET_MAGIC_1, /* counting symbol */ - SPAV3_1_SEL_TOTAL_CYCLES = 0 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_COMPLETED_INSTRUCTION = 1 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_CONDITIONAL_BRANCH = 2 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_TAKEN_CONDITIONAL_BRANCH = 3 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_PREFETCH_INSTRUCTION = 4 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_RET_INST = 5 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_JR_INST = 6 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_JAL_JRAL_INST = 7 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_NOP_INST = 8 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_SCW_INST = 9 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_ISB_DSB_INST = 10 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_CCTL_INST = 11 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_TAKEN_INTERRUPTS = 12 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_LOADS_COMPLETED = 13 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_UITLB_ACCESS = 14 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_UDTLB_ACCESS = 15 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_MTLB_ACCESS = 16 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_CODE_CACHE_ACCESS = 17 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_DATA_DEPENDENCY_STALL_CYCLES = 18 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_DATA_CACHE_MISS_STALL_CYCLES = 19 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_DATA_CACHE_ACCESS = 20 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_DATA_CACHE_MISS = 21 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_LOAD_DATA_CACHE_ACCESS = 22 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_STORE_DATA_CACHE_ACCESS = 23 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_ILM_ACCESS = 24 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_LSU_BIU_CYCLES = 25 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_HPTWK_BIU_CYCLES = 26 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_DMA_BIU_CYCLES = 27 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_CODE_CACHE_FILL_BIU_CYCLES = 28 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_LEGAL_UNALIGN_DCACHE_ACCESS = 29 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_PUSH25 = 30 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_SYSCALLS_INST = 31 + PFM_OFFSET_MAGIC_1, - SPAV3_1_SEL_LAST /* counting symbol */ -}; - -enum spav3_counter_2_perf_types { - SPAV3_2_SEL_BASE = -1 + PFM_OFFSET_MAGIC_2, /* counting symbol */ - SPAV3_2_SEL_TOTAL_CYCLES = 0 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_COMPLETED_INSTRUCTION = 1 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_CONDITIONAL_BRANCH_MISPREDICT = 2 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_TAKEN_CONDITIONAL_BRANCH_MISPREDICT = - 3 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_PREFETCH_INSTRUCTION_CACHE_HIT = 4 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_RET_MISPREDICT = 5 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_IMMEDIATE_J_INST = 6 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_MULTIPLY_INST = 7 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_16_BIT_INST = 8 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_FAILED_SCW_INST = 9 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_LD_AFTER_ST_CONFLICT_REPLAYS = 10 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_TAKEN_EXCEPTIONS = 12 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_STORES_COMPLETED = 13 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_UITLB_MISS = 14 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_UDTLB_MISS = 15 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_MTLB_MISS = 16 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_CODE_CACHE_MISS = 17 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_EMPTY_INST_QUEUE_STALL_CYCLES = 18 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_DATA_WRITE_BACK = 19 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_DATA_CACHE_MISS = 21 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_LOAD_DATA_CACHE_MISS = 22 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_STORE_DATA_CACHE_MISS = 23 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_DLM_ACCESS = 24 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_LSU_BIU_REQUEST = 25 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_HPTWK_BIU_REQUEST = 26 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_DMA_BIU_REQUEST = 27 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_CODE_CACHE_FILL_BIU_REQUEST = 28 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_EXTERNAL_EVENTS = 29 + PFM_OFFSET_MAGIC_2, - SPAV3_1_SEL_POP25 = 30 + PFM_OFFSET_MAGIC_2, - SPAV3_2_SEL_LAST /* counting symbol */ -}; - -/* Get converted event counter index */ -static inline int get_converted_event_idx(unsigned long event) -{ - int idx; - - if ((event) > SPAV3_0_SEL_BASE && event < SPAV3_0_SEL_LAST) { - idx = 0; - } else if ((event) > SPAV3_1_SEL_BASE && event < SPAV3_1_SEL_LAST) { - idx = 1; - } else if ((event) > SPAV3_2_SEL_BASE && event < SPAV3_2_SEL_LAST) { - idx = 2; - } else { - pr_err("GET_CONVERTED_EVENT_IDX PFM counter range error\n"); - return -EPERM; - } - - return idx; -} - -/* Get converted hardware event number */ -static inline u32 get_converted_evet_hw_num(u32 event) -{ - if (event > SPAV3_0_SEL_BASE && event < SPAV3_0_SEL_LAST) - event -= PFM_OFFSET_MAGIC_0; - else if (event > SPAV3_1_SEL_BASE && event < SPAV3_1_SEL_LAST) - event -= PFM_OFFSET_MAGIC_1; - else if (event > SPAV3_2_SEL_BASE && event < SPAV3_2_SEL_LAST) - event -= PFM_OFFSET_MAGIC_2; - else if (event != 0) - pr_err("GET_CONVERTED_EVENT_HW_NUM PFM counter range error\n"); - - return event; -} - -/* - * NDS32 HW events mapping - * - * The hardware events that we support. We do support cache operations but - * we have harvard caches and no way to combine instruction and data - * accesses/misses in hardware. - */ -static const unsigned int nds32_pfm_perf_map[PERF_COUNT_HW_MAX] = { - [PERF_COUNT_HW_CPU_CYCLES] = SPAV3_0_SEL_TOTAL_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] = SPAV3_1_SEL_COMPLETED_INSTRUCTION, - [PERF_COUNT_HW_CACHE_REFERENCES] = SPAV3_1_SEL_DATA_CACHE_ACCESS, - [PERF_COUNT_HW_CACHE_MISSES] = SPAV3_2_SEL_DATA_CACHE_MISS, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = HW_OP_UNSUPPORTED, - [PERF_COUNT_HW_BRANCH_MISSES] = HW_OP_UNSUPPORTED, - [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, - [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED, - [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = HW_OP_UNSUPPORTED, - [PERF_COUNT_HW_REF_CPU_CYCLES] = HW_OP_UNSUPPORTED -}; - -static const unsigned int nds32_pfm_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { - [C(L1D)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = - SPAV3_1_SEL_LOAD_DATA_CACHE_ACCESS, - [C(RESULT_MISS)] = - SPAV3_2_SEL_LOAD_DATA_CACHE_MISS, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = - SPAV3_1_SEL_STORE_DATA_CACHE_ACCESS, - [C(RESULT_MISS)] = - SPAV3_2_SEL_STORE_DATA_CACHE_MISS, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = - CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = - CACHE_OP_UNSUPPORTED, - }, - }, - [C(L1I)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = - SPAV3_1_SEL_CODE_CACHE_ACCESS, - [C(RESULT_MISS)] = - SPAV3_2_SEL_CODE_CACHE_MISS, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = - SPAV3_1_SEL_CODE_CACHE_ACCESS, - [C(RESULT_MISS)] = - SPAV3_2_SEL_CODE_CACHE_MISS, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = - CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, - }, - }, - /* TODO: L2CC */ - [C(LL)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = - CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, - }, - }, - /* NDS32 PMU does not support TLB read/write hit/miss, - * However, it can count access/miss, which mixed with read and write. - * Therefore, only READ counter will use it. - * We do as possible as we can. - */ - [C(DTLB)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = - SPAV3_1_SEL_UDTLB_ACCESS, - [C(RESULT_MISS)] = - SPAV3_2_SEL_UDTLB_MISS, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = - CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = - CACHE_OP_UNSUPPORTED, - }, - }, - [C(ITLB)] = { - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = - SPAV3_1_SEL_UITLB_ACCESS, - [C(RESULT_MISS)] = - SPAV3_2_SEL_UITLB_MISS, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = - CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = - CACHE_OP_UNSUPPORTED, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = - CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = - CACHE_OP_UNSUPPORTED, - }, - }, - [C(BPU)] = { /* What is BPU? */ - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = - CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = - CACHE_OP_UNSUPPORTED, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = - CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = - CACHE_OP_UNSUPPORTED, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = - CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = - CACHE_OP_UNSUPPORTED, - }, - }, - [C(NODE)] = { /* What is NODE? */ - [C(OP_READ)] = { - [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, - }, - [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED, - }, - [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = - CACHE_OP_UNSUPPORTED, - [C(RESULT_MISS)] = - CACHE_OP_UNSUPPORTED, - }, - }, -}; - -int nds32_pmu_map_event(struct perf_event *event, - const unsigned int (*event_map)[PERF_COUNT_HW_MAX], - const unsigned int (*cache_map)[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX], u32 raw_event_mask); - -#endif /* __ASM_PMU_H */ diff --git a/arch/nds32/include/asm/proc-fns.h b/arch/nds32/include/asm/proc-fns.h deleted file mode 100644 index 27c617fa77af..000000000000 --- a/arch/nds32/include/asm/proc-fns.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __NDS32_PROCFNS_H__ -#define __NDS32_PROCFNS_H__ - -#ifdef __KERNEL__ -#include - -struct mm_struct; -struct vm_area_struct; -extern void cpu_proc_init(void); -extern void cpu_proc_fin(void); -extern void cpu_do_idle(void); -extern void cpu_reset(unsigned long reset); -extern void cpu_switch_mm(struct mm_struct *mm); - -extern void cpu_dcache_inval_all(void); -extern void cpu_dcache_wbinval_all(void); -extern void cpu_dcache_inval_page(unsigned long page); -extern void cpu_dcache_wb_page(unsigned long page); -extern void cpu_dcache_wbinval_page(unsigned long page); -extern void cpu_dcache_inval_range(unsigned long start, unsigned long end); -extern void cpu_dcache_wb_range(unsigned long start, unsigned long end); -extern void cpu_dcache_wbinval_range(unsigned long start, unsigned long end); - -extern void cpu_icache_inval_all(void); -extern void cpu_icache_inval_page(unsigned long page); -extern void cpu_icache_inval_range(unsigned long start, unsigned long end); - -extern void cpu_cache_wbinval_page(unsigned long page, int flushi); -extern void cpu_cache_wbinval_range(unsigned long start, - unsigned long end, int flushi); -extern void cpu_cache_wbinval_range_check(struct vm_area_struct *vma, - unsigned long start, - unsigned long end, bool flushi, - bool wbd); - -extern void cpu_dma_wb_range(unsigned long start, unsigned long end); -extern void cpu_dma_inval_range(unsigned long start, unsigned long end); -extern void cpu_dma_wbinval_range(unsigned long start, unsigned long end); - -#endif /* __KERNEL__ */ -#endif /* __NDS32_PROCFNS_H__ */ diff --git a/arch/nds32/include/asm/processor.h b/arch/nds32/include/asm/processor.h deleted file mode 100644 index e6bfc74972bb..000000000000 --- a/arch/nds32/include/asm/processor.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_NDS32_PROCESSOR_H -#define __ASM_NDS32_PROCESSOR_H - -#ifdef __KERNEL__ - -#include -#include -#include - -#define KERNEL_STACK_SIZE PAGE_SIZE -#define STACK_TOP TASK_SIZE -#define STACK_TOP_MAX TASK_SIZE - -struct cpu_context { - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long r14; - unsigned long fp; - unsigned long pc; - unsigned long sp; -}; - -struct thread_struct { - struct cpu_context cpu_context; /* cpu context */ - /* fault info */ - unsigned long address; - unsigned long trap_no; - unsigned long error_code; - - struct fpu_struct fpu; -}; - -#define INIT_THREAD { } - -#ifdef __NDS32_EB__ -#define PSW_DE PSW_mskBE -#else -#define PSW_DE 0x0 -#endif - -#ifdef CONFIG_WBNA -#define PSW_valWBNA PSW_mskWBNA -#else -#define PSW_valWBNA 0x0 -#endif - -#ifdef CONFIG_HWZOL -#define PSW_valINIT (PSW_CPL_ANY | PSW_mskAEN | PSW_valWBNA | PSW_mskDT | PSW_mskIT | PSW_DE | PSW_mskGIE) -#else -#define PSW_valINIT (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT | PSW_DE | PSW_mskGIE) -#endif - -#define start_thread(regs,pc,stack) \ -({ \ - memzero(regs, sizeof(struct pt_regs)); \ - forget_syscall(regs); \ - regs->ipsw = PSW_valINIT; \ - regs->ir0 = (PSW_CPL_ANY | PSW_valWBNA | PSW_mskDT | PSW_mskIT | PSW_DE | PSW_SYSTEM | PSW_INTL_1); \ - regs->ipc = pc; \ - regs->sp = stack; \ -}) - -/* Forward declaration, a strange C thing */ -struct task_struct; - -/* Free all resources held by a thread. */ -#define release_thread(thread) do { } while(0) -#if IS_ENABLED(CONFIG_FPU) -#if !IS_ENABLED(CONFIG_UNLAZU_FPU) -extern struct task_struct *last_task_used_math; -#endif -#endif - -/* Prepare to copy thread state - unlazy all lazy status */ -#define prepare_to_copy(tsk) do { } while (0) - -unsigned long __get_wchan(struct task_struct *p); - -#define cpu_relax() barrier() - -#define task_pt_regs(task) \ - ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ - - 8) - 1) - -/* - * Create a new kernel thread - */ -extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags); - -#define KSTK_EIP(tsk) instruction_pointer(task_pt_regs(tsk)) -#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk)) - -#endif - -#endif /* __ASM_NDS32_PROCESSOR_H */ diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h deleted file mode 100644 index 919ee223620c..000000000000 --- a/arch/nds32/include/asm/ptrace.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_NDS32_PTRACE_H -#define __ASM_NDS32_PTRACE_H - -#include - -/* - * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing - * a syscall -- i.e., its most recent entry into the kernel from - * userspace was not via syscall, or otherwise a tracer cancelled the - * syscall. - * - * This must have the value -1, for ABI compatibility with ptrace etc. - */ -#define NO_SYSCALL (-1) -#ifndef __ASSEMBLY__ -#include - -struct pt_regs { - union { - struct user_pt_regs user_regs; - struct { - long uregs[26]; - long fp; - long gp; - long lp; - long sp; - long ipc; -#if defined(CONFIG_HWZOL) - long lb; - long le; - long lc; -#else - long dummy[3]; -#endif - long syscallno; - }; - }; - long orig_r0; - long ir0; - long ipsw; - long pipsw; - long pipc; - long pp0; - long pp1; - long fucop_ctl; - long osp; -}; - -static inline bool in_syscall(struct pt_regs const *regs) -{ - return regs->syscallno != NO_SYSCALL; -} - -static inline void forget_syscall(struct pt_regs *regs) -{ - regs->syscallno = NO_SYSCALL; -} -static inline unsigned long regs_return_value(struct pt_regs *regs) -{ - return regs->uregs[0]; -} -extern void show_regs(struct pt_regs *); -/* Avoid circular header include via sched.h */ -struct task_struct; - -#define arch_has_single_step() (1) -#define user_mode(regs) (((regs)->ipsw & PSW_mskPOM) == 0) -#define interrupts_enabled(regs) (!!((regs)->ipsw & PSW_mskGIE)) -#define user_stack_pointer(regs) ((regs)->sp) -#define instruction_pointer(regs) ((regs)->ipc) -#define profile_pc(regs) instruction_pointer(regs) - -#endif /* __ASSEMBLY__ */ -#endif diff --git a/arch/nds32/include/asm/sfp-machine.h b/arch/nds32/include/asm/sfp-machine.h deleted file mode 100644 index b1a5caa332b5..000000000000 --- a/arch/nds32/include/asm/sfp-machine.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (C) 2005-2018 Andes Technology Corporation */ - -#include - -#define _FP_W_TYPE_SIZE 32 -#define _FP_W_TYPE unsigned long -#define _FP_WS_TYPE signed long -#define _FP_I_TYPE long - -#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2)) -#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1)) -#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2)) - -#define _FP_MUL_MEAT_S(R, X, Y) \ - _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S, R, X, Y, umul_ppmm) -#define _FP_MUL_MEAT_D(R, X, Y) \ - _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D, R, X, Y, umul_ppmm) -#define _FP_MUL_MEAT_Q(R, X, Y) \ - _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q, R, X, Y, umul_ppmm) - -#define _FP_MUL_MEAT_DW_S(R, X, Y) \ - _FP_MUL_MEAT_DW_1_wide(_FP_WFRACBITS_S, R, X, Y, umul_ppmm) -#define _FP_MUL_MEAT_DW_D(R, X, Y) \ - _FP_MUL_MEAT_DW_2_wide(_FP_WFRACBITS_D, R, X, Y, umul_ppmm) - -#define _FP_DIV_MEAT_S(R, X, Y) _FP_DIV_MEAT_1_udiv_norm(S, R, X, Y) -#define _FP_DIV_MEAT_D(R, X, Y) _FP_DIV_MEAT_2_udiv(D, R, X, Y) - -#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) -#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 -#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 -#define _FP_NANSIGN_S 0 -#define _FP_NANSIGN_D 0 -#define _FP_NANSIGN_Q 0 - -#define _FP_KEEPNANFRACP 1 -#define _FP_QNANNEGATEDP 0 - -#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ -do { \ - if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \ - && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) { \ - R##_s = Y##_s; \ - _FP_FRAC_COPY_##wc(R, Y); \ - } else { \ - R##_s = X##_s; \ - _FP_FRAC_COPY_##wc(R, X); \ - } \ - R##_c = FP_CLS_NAN; \ -} while (0) - -#define __FPU_FPCSR (current->thread.fpu.fpcsr) - -/* Obtain the current rounding mode. */ -#define FP_ROUNDMODE \ -({ \ - __FPU_FPCSR & FPCSR_mskRM; \ -}) - -#define FP_RND_NEAREST 0 -#define FP_RND_PINF 1 -#define FP_RND_MINF 2 -#define FP_RND_ZERO 3 - -#define FP_EX_INVALID FPCSR_mskIVO -#define FP_EX_DIVZERO FPCSR_mskDBZ -#define FP_EX_OVERFLOW FPCSR_mskOVF -#define FP_EX_UNDERFLOW FPCSR_mskUDF -#define FP_EX_INEXACT FPCSR_mskIEX - -#define SF_CEQ 2 -#define SF_CLT 1 -#define SF_CGT 3 -#define SF_CUN 4 - -#include - -#ifdef __BIG_ENDIAN__ -#define __BYTE_ORDER __BIG_ENDIAN -#define __LITTLE_ENDIAN 0 -#else -#define __BYTE_ORDER __LITTLE_ENDIAN -#define __BIG_ENDIAN 0 -#endif - -#define abort() do { } while (0) -#define umul_ppmm(w1, w0, u, v) \ -do { \ - UWtype __x0, __x1, __x2, __x3; \ - UHWtype __ul, __vl, __uh, __vh; \ - \ - __ul = __ll_lowpart(u); \ - __uh = __ll_highpart(u); \ - __vl = __ll_lowpart(v); \ - __vh = __ll_highpart(v); \ - \ - __x0 = (UWtype) __ul * __vl; \ - __x1 = (UWtype) __ul * __vh; \ - __x2 = (UWtype) __uh * __vl; \ - __x3 = (UWtype) __uh * __vh; \ - \ - __x1 += __ll_highpart(__x0); \ - __x1 += __x2; \ - if (__x1 < __x2) \ - __x3 += __ll_B; \ - \ - (w1) = __x3 + __ll_highpart(__x1); \ - (w0) = __ll_lowpart(__x1) * __ll_B + __ll_lowpart(__x0); \ -} while (0) - -#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ -do { \ - UWtype __x; \ - __x = (al) + (bl); \ - (sh) = (ah) + (bh) + (__x < (al)); \ - (sl) = __x; \ -} while (0) - -#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ -do { \ - UWtype __x; \ - __x = (al) - (bl); \ - (sh) = (ah) - (bh) - (__x > (al)); \ - (sl) = __x; \ -} while (0) - -#define udiv_qrnnd(q, r, n1, n0, d) \ -do { \ - UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \ - __d1 = __ll_highpart(d); \ - __d0 = __ll_lowpart(d); \ - \ - __r1 = (n1) % __d1; \ - __q1 = (n1) / __d1; \ - __m = (UWtype) __q1 * __d0; \ - __r1 = __r1 * __ll_B | __ll_highpart(n0); \ - if (__r1 < __m) { \ - __q1--, __r1 += (d); \ - if (__r1 >= (d)) \ - if (__r1 < __m) \ - __q1--, __r1 += (d); \ - } \ - __r1 -= __m; \ - __r0 = __r1 % __d1; \ - __q0 = __r1 / __d1; \ - __m = (UWtype) __q0 * __d0; \ - __r0 = __r0 * __ll_B | __ll_lowpart(n0); \ - if (__r0 < __m) { \ - __q0--, __r0 += (d); \ - if (__r0 >= (d)) \ - if (__r0 < __m) \ - __q0--, __r0 += (d); \ - } \ - __r0 -= __m; \ - (q) = (UWtype) __q1 * __ll_B | __q0; \ - (r) = __r0; \ -} while (0) diff --git a/arch/nds32/include/asm/shmparam.h b/arch/nds32/include/asm/shmparam.h deleted file mode 100644 index 3aeee946973d..000000000000 --- a/arch/nds32/include/asm/shmparam.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef _ASMNDS32_SHMPARAM_H -#define _ASMNDS32_SHMPARAM_H - -/* - * This should be the size of the virtually indexed cache/ways, - * whichever is greater since the cache aliases every size/ways - * bytes. - */ -#define SHMLBA (4 * SZ_8K) /* attach addr a multiple of this */ - -/* - * Enforce SHMLBA in shmat - */ -#define __ARCH_FORCE_SHMLBA - -#endif /* _ASMNDS32_SHMPARAM_H */ diff --git a/arch/nds32/include/asm/stacktrace.h b/arch/nds32/include/asm/stacktrace.h deleted file mode 100644 index 6bf7c777bda4..000000000000 --- a/arch/nds32/include/asm/stacktrace.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (C) 2008-2018 Andes Technology Corporation */ - -#ifndef __ASM_STACKTRACE_H -#define __ASM_STACKTRACE_H - -/* Kernel callchain */ -struct stackframe { - unsigned long fp; - unsigned long sp; - unsigned long lp; -}; - -/* - * struct frame_tail: User callchain - * IMPORTANT: - * This struct is used for call-stack walking, - * the order and types matters. - * Do not use array, it only stores sizeof(pointer) - * - * The details can refer to arch/arm/kernel/perf_event.c - */ -struct frame_tail { - unsigned long stack_fp; - unsigned long stack_lp; -}; - -/* For User callchain with optimize for size */ -struct frame_tail_opt_size { - unsigned long stack_r6; - unsigned long stack_fp; - unsigned long stack_gp; - unsigned long stack_lp; -}; - -extern void -get_real_ret_addr(unsigned long *addr, struct task_struct *tsk, int *graph); - -#endif /* __ASM_STACKTRACE_H */ diff --git a/arch/nds32/include/asm/string.h b/arch/nds32/include/asm/string.h deleted file mode 100644 index cae8fe16de98..000000000000 --- a/arch/nds32/include/asm/string.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_NDS32_STRING_H -#define __ASM_NDS32_STRING_H - -#define __HAVE_ARCH_MEMCPY -extern void *memcpy(void *, const void *, __kernel_size_t); - -#define __HAVE_ARCH_MEMMOVE -extern void *memmove(void *, const void *, __kernel_size_t); - -#define __HAVE_ARCH_MEMSET -extern void *memset(void *, int, __kernel_size_t); - -extern void *memzero(void *ptr, __kernel_size_t n); -#endif diff --git a/arch/nds32/include/asm/suspend.h b/arch/nds32/include/asm/suspend.h deleted file mode 100644 index 6ed2418af1ac..000000000000 --- a/arch/nds32/include/asm/suspend.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2008-2017 Andes Technology Corporation - -#ifndef __ASM_NDS32_SUSPEND_H -#define __ASM_NDS32_SUSPEND_H - -extern void suspend2ram(void); -extern void cpu_resume(void); -extern unsigned long wake_mask; - -#endif diff --git a/arch/nds32/include/asm/swab.h b/arch/nds32/include/asm/swab.h deleted file mode 100644 index 362a466f2976..000000000000 --- a/arch/nds32/include/asm/swab.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __NDS32_SWAB_H__ -#define __NDS32_SWAB_H__ - -#include -#include - -static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) -{ - __asm__("wsbh %0, %0\n\t" /* word swap byte within halfword */ - "rotri %0, %0, #16\n" - :"=r"(x) - :"0"(x)); - return x; -} - -static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) -{ - __asm__("wsbh %0, %0\n" /* word swap byte within halfword */ - :"=r"(x) - :"0"(x)); - return x; -} - -#define __arch_swab32(x) ___arch__swab32(x) -#define __arch_swab16(x) ___arch__swab16(x) - -#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) -#define __BYTEORDER_HAS_U64__ -#define __SWAB_64_THRU_32__ -#endif - -#endif /* __NDS32_SWAB_H__ */ diff --git a/arch/nds32/include/asm/syscall.h b/arch/nds32/include/asm/syscall.h deleted file mode 100644 index 90aa56c94af1..000000000000 --- a/arch/nds32/include/asm/syscall.h +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2008-2009 Red Hat, Inc. All rights reserved. -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef _ASM_NDS32_SYSCALL_H -#define _ASM_NDS32_SYSCALL_H 1 - -#include -#include -struct task_struct; -struct pt_regs; - -/** - * syscall_get_nr - find what system call a task is executing - * @task: task of interest, must be blocked - * @regs: task_pt_regs() of @task - * - * If @task is executing a system call or is at system call - * tracing about to attempt one, returns the system call number. - * If @task is not executing a system call, i.e. it's blocked - * inside the kernel for a fault or signal, returns -1. - * - * Note this returns int even on 64-bit machines. Only 32 bits of - * system call number can be meaningful. If the actual arch value - * is 64 bits, this truncates to 32 bits so 0xffffffff means -1. - * - * It's only valid to call this when @task is known to be blocked. - */ -static inline int -syscall_get_nr(struct task_struct *task, struct pt_regs *regs) -{ - return regs->syscallno; -} - -/** - * syscall_rollback - roll back registers after an aborted system call - * @task: task of interest, must be in system call exit tracing - * @regs: task_pt_regs() of @task - * - * It's only valid to call this when @task is stopped for system - * call exit tracing (due to TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT), - * after tracehook_report_syscall_entry() returned nonzero to prevent - * the system call from taking place. - * - * This rolls back the register state in @regs so it's as if the - * system call instruction was a no-op. The registers containing - * the system call number and arguments are as they were before the - * system call instruction. This may not be the same as what the - * register state looked like at system call entry tracing. - */ -static inline void -syscall_rollback(struct task_struct *task, struct pt_regs *regs) -{ - regs->uregs[0] = regs->orig_r0; -} - -/** - * syscall_get_error - check result of traced system call - * @task: task of interest, must be blocked - * @regs: task_pt_regs() of @task - * - * Returns 0 if the system call succeeded, or -ERRORCODE if it failed. - * - * It's only valid to call this when @task is stopped for tracing on exit - * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. - */ -static inline long -syscall_get_error(struct task_struct *task, struct pt_regs *regs) -{ - unsigned long error = regs->uregs[0]; - return IS_ERR_VALUE(error) ? error : 0; -} - -/** - * syscall_get_return_value - get the return value of a traced system call - * @task: task of interest, must be blocked - * @regs: task_pt_regs() of @task - * - * Returns the return value of the successful system call. - * This value is meaningless if syscall_get_error() returned nonzero. - * - * It's only valid to call this when @task is stopped for tracing on exit - * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. - */ -static inline long -syscall_get_return_value(struct task_struct *task, struct pt_regs *regs) -{ - return regs->uregs[0]; -} - -/** - * syscall_set_return_value - change the return value of a traced system call - * @task: task of interest, must be blocked - * @regs: task_pt_regs() of @task - * @error: negative error code, or zero to indicate success - * @val: user return value if @error is zero - * - * This changes the results of the system call that user mode will see. - * If @error is zero, the user sees a successful system call with a - * return value of @val. If @error is nonzero, it's a negated errno - * code; the user sees a failed system call with this errno code. - * - * It's only valid to call this when @task is stopped for tracing on exit - * from a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. - */ -static inline void -syscall_set_return_value(struct task_struct *task, struct pt_regs *regs, - int error, long val) -{ - regs->uregs[0] = (long)error ? error : val; -} - -/** - * syscall_get_arguments - extract system call parameter values - * @task: task of interest, must be blocked - * @regs: task_pt_regs() of @task - * @args: array filled with argument values - * - * Fetches 6 arguments to the system call (from 0 through 5). The first - * argument is stored in @args[0], and so on. - * - * It's only valid to call this when @task is stopped for tracing on - * entry to a system call, due to %TIF_SYSCALL_TRACE or %TIF_SYSCALL_AUDIT. - */ -#define SYSCALL_MAX_ARGS 6 -static inline void -syscall_get_arguments(struct task_struct *task, struct pt_regs *regs, - unsigned long *args) -{ - args[0] = regs->orig_r0; - args++; - memcpy(args, ®s->uregs[0] + 1, 5 * sizeof(args[0])); -} - -static inline int -syscall_get_arch(struct task_struct *task) -{ - return IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) - ? AUDIT_ARCH_NDS32BE : AUDIT_ARCH_NDS32; -} - -#endif /* _ASM_NDS32_SYSCALL_H */ diff --git a/arch/nds32/include/asm/syscalls.h b/arch/nds32/include/asm/syscalls.h deleted file mode 100644 index 4e7216082a67..000000000000 --- a/arch/nds32/include/asm/syscalls.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_NDS32_SYSCALLS_H -#define __ASM_NDS32_SYSCALLS_H - -asmlinkage long sys_cacheflush(unsigned long addr, unsigned long len, unsigned int op); -asmlinkage long sys_fadvise64_64_wrapper(int fd, int advice, loff_t offset, loff_t len); -asmlinkage long sys_rt_sigreturn_wrapper(void); -asmlinkage long sys_fp_udfiex_crtl(int cmd, int act); - -#include - -#endif /* __ASM_NDS32_SYSCALLS_H */ diff --git a/arch/nds32/include/asm/thread_info.h b/arch/nds32/include/asm/thread_info.h deleted file mode 100644 index d3967ad184f0..000000000000 --- a/arch/nds32/include/asm/thread_info.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_NDS32_THREAD_INFO_H -#define __ASM_NDS32_THREAD_INFO_H - -#ifdef __KERNEL__ - -#define THREAD_SIZE_ORDER (1) -#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) - -#ifndef __ASSEMBLY__ - -struct task_struct; - -#include -#include - -typedef unsigned long mm_segment_t; - -/* - * low level task data that entry.S needs immediate access to. - * __switch_to() assumes cpu_context follows immediately after cpu_domain. - */ -struct thread_info { - unsigned long flags; /* low level flags */ - __s32 preempt_count; /* 0 => preemptable, <0 => bug */ - mm_segment_t addr_limit; /* address limit */ -}; -#define INIT_THREAD_INFO(tsk) \ -{ \ - .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ -} -#define thread_saved_pc(tsk) ((unsigned long)(tsk->thread.cpu_context.pc)) -#define thread_saved_fp(tsk) ((unsigned long)(tsk->thread.cpu_context.fp)) -#endif - -/* - * thread information flags: - * TIF_SYSCALL_TRACE - syscall trace active - * TIF_SIGPENDING - signal pending - * TIF_NEED_RESCHED - rescheduling necessary - * TIF_NOTIFY_RESUME - callback before returning to user - * TIF_POLLING_NRFLAG - true if poll_idle() is polling TIF_NEED_RESCHED - */ -#define TIF_SIGPENDING 1 -#define TIF_NEED_RESCHED 2 -#define TIF_SINGLESTEP 3 -#define TIF_NOTIFY_RESUME 4 /* callback before returning to user */ -#define TIF_NOTIFY_SIGNAL 5 /* signal notifications exist */ -#define TIF_SYSCALL_TRACE 8 -#define TIF_POLLING_NRFLAG 17 -#define TIF_MEMDIE 18 -#define TIF_FREEZE 19 -#define TIF_RESTORE_SIGMASK 20 - -#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) -#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) -#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) -#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL) -#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP) -#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) -#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) -#define _TIF_FREEZE (1 << TIF_FREEZE) -#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) - -/* - * Change these and you break ASM code in entry-common.S - */ -#define _TIF_WORK_MASK 0x000000ff -#define _TIF_WORK_SYSCALL_ENTRY (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP) -#define _TIF_WORK_SYSCALL_LEAVE (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP) - -#endif /* __KERNEL__ */ -#endif /* __ASM_NDS32_THREAD_INFO_H */ diff --git a/arch/nds32/include/asm/tlb.h b/arch/nds32/include/asm/tlb.h deleted file mode 100644 index 672603804a3b..000000000000 --- a/arch/nds32/include/asm/tlb.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASMNDS32_TLB_H -#define __ASMNDS32_TLB_H - -#include - -#define __pte_free_tlb(tlb, pte, addr) pte_free((tlb)->mm, pte) - -#endif diff --git a/arch/nds32/include/asm/tlbflush.h b/arch/nds32/include/asm/tlbflush.h deleted file mode 100644 index 97155366ea01..000000000000 --- a/arch/nds32/include/asm/tlbflush.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef _ASMNDS32_TLBFLUSH_H -#define _ASMNDS32_TLBFLUSH_H - -#include -#include -#include - -static inline void local_flush_tlb_all(void) -{ - __nds32__tlbop_flua(); - __nds32__isb(); -} - -static inline void local_flush_tlb_mm(struct mm_struct *mm) -{ - __nds32__tlbop_flua(); - __nds32__isb(); -} - -static inline void local_flush_tlb_kernel_range(unsigned long start, - unsigned long end) -{ - while (start < end) { - __nds32__tlbop_inv(start); - __nds32__isb(); - start += PAGE_SIZE; - } -} - -void local_flush_tlb_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end); -void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr); - -#define flush_tlb_all local_flush_tlb_all -#define flush_tlb_mm local_flush_tlb_mm -#define flush_tlb_range local_flush_tlb_range -#define flush_tlb_page local_flush_tlb_page -#define flush_tlb_kernel_range local_flush_tlb_kernel_range - -void update_mmu_cache(struct vm_area_struct *vma, - unsigned long address, pte_t * pte); - -#endif diff --git a/arch/nds32/include/asm/uaccess.h b/arch/nds32/include/asm/uaccess.h deleted file mode 100644 index d4cbf069dc22..000000000000 --- a/arch/nds32/include/asm/uaccess.h +++ /dev/null @@ -1,286 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef _ASMANDES_UACCESS_H -#define _ASMANDES_UACCESS_H - -/* - * User space memory access functions - */ -#include -#include -#include -#include - -#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" - -/* - * The exception table consists of pairs of addresses: the first is the - * address of an instruction that is allowed to fault, and the second is - * the address at which the program should continue. No registers are - * modified, so it is entirely up to the continuation code to figure out - * what to do. - * - * All the routines below use bits of fixup code that are out of line - * with the main instruction path. This means when everything is well, - * we don't even have to jump over them. Further, they do not intrude - * on our cache or tlb entries. - */ - -struct exception_table_entry { - unsigned long insn, fixup; -}; - -extern int fixup_exception(struct pt_regs *regs); - -#define KERNEL_DS ((mm_segment_t) { ~0UL }) -#define USER_DS ((mm_segment_t) {TASK_SIZE - 1}) - -#define get_fs() (current_thread_info()->addr_limit) -#define user_addr_max get_fs - -static inline void set_fs(mm_segment_t fs) -{ - current_thread_info()->addr_limit = fs; -} - -#define uaccess_kernel() (get_fs() == KERNEL_DS) - -#define __range_ok(addr, size) (size <= get_fs() && addr <= (get_fs() -size)) - -#define access_ok(addr, size) \ - __range_ok((unsigned long)addr, (unsigned long)size) -/* - * Single-value transfer routines. They automatically use the right - * size if we just have the right pointer type. Note that the functions - * which read from user space (*get_*) need to take care not to leak - * kernel data even if the calling code is buggy and fails to check - * the return value. This means zeroing out the destination variable - * or buffer on error. Normally this is done out of line by the - * fixup code, but there are a few places where it intrudes on the - * main code path. When we only write to user space, there is no - * problem. - * - * The "__xxx" versions of the user access functions do not verify the - * address space - it must have been done previously with a separate - * "access_ok()" call. - * - * The "xxx_error" versions set the third argument to EFAULT if an - * error occurs, and leave it unchanged on success. Note that these - * versions are void (ie, don't return a value as such). - */ - -#define get_user __get_user \ - -#define __get_user(x, ptr) \ -({ \ - long __gu_err = 0; \ - __get_user_check((x), (ptr), __gu_err); \ - __gu_err; \ -}) - -#define __get_user_error(x, ptr, err) \ -({ \ - __get_user_check((x), (ptr), (err)); \ - (void)0; \ -}) - -#define __get_user_check(x, ptr, err) \ -({ \ - const __typeof__(*(ptr)) __user *__p = (ptr); \ - might_fault(); \ - if (access_ok(__p, sizeof(*__p))) { \ - __get_user_err((x), __p, (err)); \ - } else { \ - (x) = 0; (err) = -EFAULT; \ - } \ -}) - -#define __get_user_err(x, ptr, err) \ -do { \ - unsigned long __gu_val; \ - __chk_user_ptr(ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: \ - __get_user_asm("lbi", __gu_val, (ptr), (err)); \ - break; \ - case 2: \ - __get_user_asm("lhi", __gu_val, (ptr), (err)); \ - break; \ - case 4: \ - __get_user_asm("lwi", __gu_val, (ptr), (err)); \ - break; \ - case 8: \ - __get_user_asm_dword(__gu_val, (ptr), (err)); \ - break; \ - default: \ - BUILD_BUG(); \ - break; \ - } \ - (x) = (__force __typeof__(*(ptr)))__gu_val; \ -} while (0) - -#define __get_user_asm(inst, x, addr, err) \ - __asm__ __volatile__ ( \ - "1: "inst" %1,[%2]\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - " .align 2\n" \ - "3: move %0, %3\n" \ - " move %1, #0\n" \ - " b 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 3b\n" \ - " .previous" \ - : "+r" (err), "=&r" (x) \ - : "r" (addr), "i" (-EFAULT) \ - : "cc") - -#ifdef __NDS32_EB__ -#define __gu_reg_oper0 "%H1" -#define __gu_reg_oper1 "%L1" -#else -#define __gu_reg_oper0 "%L1" -#define __gu_reg_oper1 "%H1" -#endif - -#define __get_user_asm_dword(x, addr, err) \ - __asm__ __volatile__ ( \ - "\n1:\tlwi " __gu_reg_oper0 ",[%2]\n" \ - "\n2:\tlwi " __gu_reg_oper1 ",[%2+4]\n" \ - "3:\n" \ - " .section .fixup,\"ax\"\n" \ - " .align 2\n" \ - "4: move %0, %3\n" \ - " b 3b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 4b\n" \ - " .long 2b, 4b\n" \ - " .previous" \ - : "+r"(err), "=&r"(x) \ - : "r"(addr), "i"(-EFAULT) \ - : "cc") - -#define put_user __put_user \ - -#define __put_user(x, ptr) \ -({ \ - long __pu_err = 0; \ - __put_user_err((x), (ptr), __pu_err); \ - __pu_err; \ -}) - -#define __put_user_error(x, ptr, err) \ -({ \ - __put_user_err((x), (ptr), (err)); \ - (void)0; \ -}) - -#define __put_user_check(x, ptr, err) \ -({ \ - __typeof__(*(ptr)) __user *__p = (ptr); \ - might_fault(); \ - if (access_ok(__p, sizeof(*__p))) { \ - __put_user_err((x), __p, (err)); \ - } else { \ - (err) = -EFAULT; \ - } \ -}) - -#define __put_user_err(x, ptr, err) \ -do { \ - __typeof__(*(ptr)) __pu_val = (x); \ - __chk_user_ptr(ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: \ - __put_user_asm("sbi", __pu_val, (ptr), (err)); \ - break; \ - case 2: \ - __put_user_asm("shi", __pu_val, (ptr), (err)); \ - break; \ - case 4: \ - __put_user_asm("swi", __pu_val, (ptr), (err)); \ - break; \ - case 8: \ - __put_user_asm_dword(__pu_val, (ptr), (err)); \ - break; \ - default: \ - BUILD_BUG(); \ - break; \ - } \ -} while (0) - -#define __put_user_asm(inst, x, addr, err) \ - __asm__ __volatile__ ( \ - "1: "inst" %1,[%2]\n" \ - "2:\n" \ - " .section .fixup,\"ax\"\n" \ - " .align 2\n" \ - "3: move %0, %3\n" \ - " b 2b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 3b\n" \ - " .previous" \ - : "+r" (err) \ - : "r" (x), "r" (addr), "i" (-EFAULT) \ - : "cc") - -#ifdef __NDS32_EB__ -#define __pu_reg_oper0 "%H2" -#define __pu_reg_oper1 "%L2" -#else -#define __pu_reg_oper0 "%L2" -#define __pu_reg_oper1 "%H2" -#endif - -#define __put_user_asm_dword(x, addr, err) \ - __asm__ __volatile__ ( \ - "\n1:\tswi " __pu_reg_oper0 ",[%1]\n" \ - "\n2:\tswi " __pu_reg_oper1 ",[%1+4]\n" \ - "3:\n" \ - " .section .fixup,\"ax\"\n" \ - " .align 2\n" \ - "4: move %0, %3\n" \ - " b 3b\n" \ - " .previous\n" \ - " .section __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 4b\n" \ - " .long 2b, 4b\n" \ - " .previous" \ - : "+r"(err) \ - : "r"(addr), "r"(x), "i"(-EFAULT) \ - : "cc") - -extern unsigned long __arch_clear_user(void __user * addr, unsigned long n); -extern long strncpy_from_user(char *dest, const char __user * src, long count); -extern __must_check long strnlen_user(const char __user * str, long n); -extern unsigned long __arch_copy_from_user(void *to, const void __user * from, - unsigned long n); -extern unsigned long __arch_copy_to_user(void __user * to, const void *from, - unsigned long n); - -#define raw_copy_from_user __arch_copy_from_user -#define raw_copy_to_user __arch_copy_to_user - -#define INLINE_COPY_FROM_USER -#define INLINE_COPY_TO_USER -static inline unsigned long clear_user(void __user * to, unsigned long n) -{ - if (access_ok(to, n)) - n = __arch_clear_user(to, n); - return n; -} - -static inline unsigned long __clear_user(void __user * to, unsigned long n) -{ - return __arch_clear_user(to, n); -} - -#endif /* _ASMNDS32_UACCESS_H */ diff --git a/arch/nds32/include/asm/unistd.h b/arch/nds32/include/asm/unistd.h deleted file mode 100644 index bf5e2d440913..000000000000 --- a/arch/nds32/include/asm/unistd.h +++ /dev/null @@ -1,6 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#define __ARCH_WANT_SYS_CLONE - -#include diff --git a/arch/nds32/include/asm/vdso.h b/arch/nds32/include/asm/vdso.h deleted file mode 100644 index 89b113ffc3dc..000000000000 --- a/arch/nds32/include/asm/vdso.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2005-2017 Andes Technology Corporation - */ - -#ifndef __ASM_VDSO_H -#define __ASM_VDSO_H - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ - -#include - -#define VDSO_SYMBOL(base, name) \ -({ \ - (unsigned long)(vdso_offset_##name + (unsigned long)(base)); \ -}) - -#endif /* !__ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* __ASM_VDSO_H */ diff --git a/arch/nds32/include/asm/vdso_datapage.h b/arch/nds32/include/asm/vdso_datapage.h deleted file mode 100644 index 74c68802021e..000000000000 --- a/arch/nds32/include/asm/vdso_datapage.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2012 ARM Limited -// Copyright (C) 2005-2017 Andes Technology Corporation -#ifndef __ASM_VDSO_DATAPAGE_H -#define __ASM_VDSO_DATAPAGE_H - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ - -struct vdso_data { - bool cycle_count_down; /* timer cyclye counter is decrease with time */ - u32 cycle_count_offset; /* offset of timer cycle counter register */ - u32 seq_count; /* sequence count - odd during updates */ - u32 xtime_coarse_sec; /* coarse time */ - u32 xtime_coarse_nsec; - - u32 wtm_clock_sec; /* wall to monotonic offset */ - u32 wtm_clock_nsec; - u32 xtime_clock_sec; /* CLOCK_REALTIME - seconds */ - u32 cs_mult; /* clocksource multiplier */ - u32 cs_shift; /* Cycle to nanosecond divisor (power of two) */ - u32 hrtimer_res; /* hrtimer resolution */ - - u64 cs_cycle_last; /* last cycle value */ - u64 cs_mask; /* clocksource mask */ - - u64 xtime_clock_nsec; /* CLOCK_REALTIME sub-ns base */ - u32 tz_minuteswest; /* timezone info for gettimeofday(2) */ - u32 tz_dsttime; -}; - -#endif /* !__ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* __ASM_VDSO_DATAPAGE_H */ diff --git a/arch/nds32/include/asm/vdso_timer_info.h b/arch/nds32/include/asm/vdso_timer_info.h deleted file mode 100644 index 328439ce37db..000000000000 --- a/arch/nds32/include/asm/vdso_timer_info.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -extern struct timer_info_t timer_info; -#define EMPTY_VALUE ~(0UL) -#define EMPTY_TIMER_MAPPING EMPTY_VALUE -#define EMPTY_REG_OFFSET EMPTY_VALUE - -struct timer_info_t -{ - bool cycle_count_down; - unsigned long mapping_base; - unsigned long cycle_count_reg_offset; -}; diff --git a/arch/nds32/include/asm/vermagic.h b/arch/nds32/include/asm/vermagic.h deleted file mode 100644 index f772e7ba33f1..000000000000 --- a/arch/nds32/include/asm/vermagic.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef _ASM_VERMAGIC_H -#define _ASM_VERMAGIC_H - -#define MODULE_ARCH_VERMAGIC "NDS32v3" - -#endif /* _ASM_VERMAGIC_H */ diff --git a/arch/nds32/include/asm/vmalloc.h b/arch/nds32/include/asm/vmalloc.h deleted file mode 100644 index caeed3898419..000000000000 --- a/arch/nds32/include/asm/vmalloc.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _ASM_NDS32_VMALLOC_H -#define _ASM_NDS32_VMALLOC_H - -#endif /* _ASM_NDS32_VMALLOC_H */ diff --git a/arch/nds32/include/uapi/asm/Kbuild b/arch/nds32/include/uapi/asm/Kbuild deleted file mode 100644 index e78470141932..000000000000 --- a/arch/nds32/include/uapi/asm/Kbuild +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -generic-y += ucontext.h diff --git a/arch/nds32/include/uapi/asm/auxvec.h b/arch/nds32/include/uapi/asm/auxvec.h deleted file mode 100644 index bc0b92ab8c15..000000000000 --- a/arch/nds32/include/uapi/asm/auxvec.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_AUXVEC_H -#define __ASM_AUXVEC_H - -/* - * This entry gives some information about the FPU initialization - * performed by the kernel. - */ -#define AT_FPUCW 18 /* Used FPU control word. */ - - -/* VDSO location */ -#define AT_SYSINFO_EHDR 33 - -#define AT_VECTOR_SIZE_ARCH 1 - -#endif diff --git a/arch/nds32/include/uapi/asm/byteorder.h b/arch/nds32/include/uapi/asm/byteorder.h deleted file mode 100644 index c264ef12c49c..000000000000 --- a/arch/nds32/include/uapi/asm/byteorder.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __NDS32_BYTEORDER_H__ -#define __NDS32_BYTEORDER_H__ - -#ifdef __NDS32_EB__ -#include -#else -#include -#endif - -#endif /* __NDS32_BYTEORDER_H__ */ diff --git a/arch/nds32/include/uapi/asm/cachectl.h b/arch/nds32/include/uapi/asm/cachectl.h deleted file mode 100644 index 31b9b439d819..000000000000 --- a/arch/nds32/include/uapi/asm/cachectl.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -// Copyright (C) 1994, 1995, 1996 by Ralf Baechle -// Copyright (C) 2005-2017 Andes Technology Corporation -#ifndef _ASM_CACHECTL -#define _ASM_CACHECTL - -/* - * Options for cacheflush system call - */ -#define ICACHE 0 /* flush instruction cache */ -#define DCACHE 1 /* writeback and flush data cache */ -#define BCACHE 2 /* flush instruction cache + writeback and flush data cache */ - -#endif /* _ASM_CACHECTL */ diff --git a/arch/nds32/include/uapi/asm/fp_udfiex_crtl.h b/arch/nds32/include/uapi/asm/fp_udfiex_crtl.h deleted file mode 100644 index f17396db16ec..000000000000 --- a/arch/nds32/include/uapi/asm/fp_udfiex_crtl.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -/* Copyright (C) 2005-2019 Andes Technology Corporation */ -#ifndef _FP_UDF_IEX_CRTL_H -#define _FP_UDF_IEX_CRTL_H - -/* - * The cmd list of sys_fp_udfiex_crtl() - */ -/* Disable UDF or IEX trap based on the content of parameter act */ -#define DISABLE_UDF_IEX_TRAP 0 -/* Enable UDF or IEX trap based on the content of parameter act */ -#define ENABLE_UDF_IEX_TRAP 1 -/* Get current status of UDF and IEX trap */ -#define GET_UDF_IEX_TRAP 2 - -#endif /* _FP_UDF_IEX_CRTL_H */ diff --git a/arch/nds32/include/uapi/asm/param.h b/arch/nds32/include/uapi/asm/param.h deleted file mode 100644 index 48d00328d328..000000000000 --- a/arch/nds32/include/uapi/asm/param.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __ASM_NDS32_PARAM_H -#define __ASM_NDS32_PARAM_H - -#define EXEC_PAGESIZE 8192 - -#include - -#endif /* __ASM_NDS32_PARAM_H */ diff --git a/arch/nds32/include/uapi/asm/ptrace.h b/arch/nds32/include/uapi/asm/ptrace.h deleted file mode 100644 index d76217c7c010..000000000000 --- a/arch/nds32/include/uapi/asm/ptrace.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef __UAPI_ASM_NDS32_PTRACE_H -#define __UAPI_ASM_NDS32_PTRACE_H - -#ifndef __ASSEMBLY__ - -/* - * User structures for general purpose register. - */ -struct user_pt_regs { - long uregs[26]; - long fp; - long gp; - long lp; - long sp; - long ipc; - long lb; - long le; - long lc; - long syscallno; -}; -#endif -#endif diff --git a/arch/nds32/include/uapi/asm/sigcontext.h b/arch/nds32/include/uapi/asm/sigcontext.h deleted file mode 100644 index 6c1e6648878f..000000000000 --- a/arch/nds32/include/uapi/asm/sigcontext.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#ifndef _ASMNDS32_SIGCONTEXT_H -#define _ASMNDS32_SIGCONTEXT_H - -/* - * Signal context structure - contains all info to do with the state - * before the signal handler was invoked. Note: only add new entries - * to the end of the structure. - */ -struct fpu_struct { - unsigned long long fd_regs[32]; - unsigned long fpcsr; - /* - * When CONFIG_SUPPORT_DENORMAL_ARITHMETIC is defined, kernel prevents - * hardware from treating the denormalized output as an underflow case - * and rounding it to a normal number. Hence kernel enables the UDF and - * IEX trap in the fpcsr register to step in the calculation. - * However, the UDF and IEX trap enable bit in $fpcsr also lose - * their use. - * - * UDF_IEX_trap replaces the feature of UDF and IEX trap enable bit in - * $fpcsr to control the trap of underflow and inexact. The bit filed - * of UDF_IEX_trap is the same as $fpcsr, 10th bit is used to enable UDF - * exception trapping and 11th bit is used to enable IEX exception - * trapping. - * - * UDF_IEX_trap is only modified through fp_udfiex_crtl syscall. - * Therefore, UDF_IEX_trap needn't be saved and restored in each - * context switch. - */ - unsigned long UDF_IEX_trap; -}; - -struct zol_struct { - unsigned long nds32_lc; /* $LC */ - unsigned long nds32_le; /* $LE */ - unsigned long nds32_lb; /* $LB */ -}; - -struct sigcontext { - unsigned long trap_no; - unsigned long error_code; - unsigned long oldmask; - unsigned long nds32_r0; - unsigned long nds32_r1; - unsigned long nds32_r2; - unsigned long nds32_r3; - unsigned long nds32_r4; - unsigned long nds32_r5; - unsigned long nds32_r6; - unsigned long nds32_r7; - unsigned long nds32_r8; - unsigned long nds32_r9; - unsigned long nds32_r10; - unsigned long nds32_r11; - unsigned long nds32_r12; - unsigned long nds32_r13; - unsigned long nds32_r14; - unsigned long nds32_r15; - unsigned long nds32_r16; - unsigned long nds32_r17; - unsigned long nds32_r18; - unsigned long nds32_r19; - unsigned long nds32_r20; - unsigned long nds32_r21; - unsigned long nds32_r22; - unsigned long nds32_r23; - unsigned long nds32_r24; - unsigned long nds32_r25; - unsigned long nds32_fp; /* $r28 */ - unsigned long nds32_gp; /* $r29 */ - unsigned long nds32_lp; /* $r30 */ - unsigned long nds32_sp; /* $r31 */ - unsigned long nds32_ipc; - unsigned long fault_address; - unsigned long used_math_flag; - /* FPU Registers */ - struct fpu_struct fpu; - struct zol_struct zol; -}; - -#endif diff --git a/arch/nds32/include/uapi/asm/unistd.h b/arch/nds32/include/uapi/asm/unistd.h deleted file mode 100644 index 410795e280fe..000000000000 --- a/arch/nds32/include/uapi/asm/unistd.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -// Copyright (C) 2005-2017 Andes Technology Corporation - -#define __ARCH_WANT_STAT64 -#define __ARCH_WANT_SYNC_FILE_RANGE2 -#define __ARCH_WANT_SET_GET_RLIMIT -#define __ARCH_WANT_TIME32_SYSCALLS - -/* Use the standard ABI for syscalls */ -#include - -/* Additional NDS32 specific syscalls. */ -#define __NR_cacheflush (__NR_arch_specific_syscall) -#define __NR_fp_udfiex_crtl (__NR_arch_specific_syscall + 1) -__SYSCALL(__NR_cacheflush, sys_cacheflush) -__SYSCALL(__NR_fp_udfiex_crtl, sys_fp_udfiex_crtl) diff --git a/arch/nds32/kernel/.gitignore b/arch/nds32/kernel/.gitignore deleted file mode 100644 index bbb90f92d051..000000000000 --- a/arch/nds32/kernel/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -vmlinux.lds diff --git a/arch/nds32/kernel/Makefile b/arch/nds32/kernel/Makefile deleted file mode 100644 index 394df3f6442c..000000000000 --- a/arch/nds32/kernel/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for the linux kernel. -# - -CPPFLAGS_vmlinux.lds := -DTEXTADDR=$(TEXTADDR) -AFLAGS_head.o := -DTEXTADDR=$(TEXTADDR) -# Object file lists. - -obj-y := ex-entry.o ex-exit.o ex-scall.o irq.o \ - process.o ptrace.o setup.o signal.o \ - sys_nds32.o time.o traps.o cacheinfo.o \ - dma.o syscall_table.o vdso.o - -obj-$(CONFIG_MODULES) += nds32_ksyms.o module.o -obj-$(CONFIG_STACKTRACE) += stacktrace.o -obj-$(CONFIG_FPU) += fpu.o -obj-$(CONFIG_OF) += devtree.o -obj-$(CONFIG_CACHE_L2) += atl2c.o -obj-$(CONFIG_PERF_EVENTS) += perf_event_cpu.o -obj-$(CONFIG_PM) += pm.o sleep.o -extra-y := head.o vmlinux.lds - -CFLAGS_fpu.o += -mext-fpu-sp -mext-fpu-dp - - -obj-y += vdso/ - -obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o - -ifdef CONFIG_FUNCTION_TRACER -CFLAGS_REMOVE_ftrace.o = $(CC_FLAGS_FTRACE) -endif diff --git a/arch/nds32/kernel/asm-offsets.c b/arch/nds32/kernel/asm-offsets.c deleted file mode 100644 index 3541d5981de7..000000000000 --- a/arch/nds32/kernel/asm-offsets.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include - -int main(void) -{ - DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags)); - DEFINE(TSK_TI_PREEMPT, - offsetof(struct task_struct, thread_info.preempt_count)); - DEFINE(THREAD_CPU_CONTEXT, - offsetof(struct task_struct, thread.cpu_context)); - DEFINE(OSP_OFFSET, offsetof(struct pt_regs, osp)); - DEFINE(SP_OFFSET, offsetof(struct pt_regs, sp)); - DEFINE(FUCOP_CTL_OFFSET, offsetof(struct pt_regs, fucop_ctl)); - DEFINE(IPSW_OFFSET, offsetof(struct pt_regs, ipsw)); - DEFINE(SYSCALLNO_OFFSET, offsetof(struct pt_regs, syscallno)); - DEFINE(IPC_OFFSET, offsetof(struct pt_regs, ipc)); - DEFINE(R0_OFFSET, offsetof(struct pt_regs, uregs[0])); - DEFINE(R15_OFFSET, offsetof(struct pt_regs, uregs[15])); - DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC); - DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC); - return 0; -} diff --git a/arch/nds32/kernel/atl2c.c b/arch/nds32/kernel/atl2c.c deleted file mode 100644 index 0c5386e72098..000000000000 --- a/arch/nds32/kernel/atl2c.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include - -void __iomem *atl2c_base; -static const struct of_device_id atl2c_ids[] __initconst = { - {.compatible = "andestech,atl2c",}, - {} -}; - -static int __init atl2c_of_init(void) -{ - struct device_node *np; - struct resource res; - unsigned long tmp = 0; - unsigned long l2set, l2way, l2clsz; - - if (!(__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C)) - return -ENODEV; - - np = of_find_matching_node(NULL, atl2c_ids); - if (!np) - return -ENODEV; - - if (of_address_to_resource(np, 0, &res)) - return -ENODEV; - - atl2c_base = ioremap(res.start, resource_size(&res)); - if (!atl2c_base) - return -ENOMEM; - - l2set = - 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >> - L2_CA_CONF_offL2SET); - l2way = - 1 + - ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2WAY) >> - L2_CA_CONF_offL2WAY); - l2clsz = - 4 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2CLSZ) >> - L2_CA_CONF_offL2CLSZ); - pr_info("L2:%luKB/%luS/%luW/%luB\n", - l2set * l2way * l2clsz / 1024, l2set, l2way, l2clsz); - - tmp = L2C_R_REG(L2CC_PROT_OFF); - tmp &= ~L2CC_PROT_mskMRWEN; - L2C_W_REG(L2CC_PROT_OFF, tmp); - - tmp = L2C_R_REG(L2CC_SETUP_OFF); - tmp &= ~L2CC_SETUP_mskPART; - L2C_W_REG(L2CC_SETUP_OFF, tmp); - - tmp = L2C_R_REG(L2CC_CTRL_OFF); - tmp |= L2CC_CTRL_mskEN; - L2C_W_REG(L2CC_CTRL_OFF, tmp); - - return 0; -} - -subsys_initcall(atl2c_of_init); diff --git a/arch/nds32/kernel/cacheinfo.c b/arch/nds32/kernel/cacheinfo.c deleted file mode 100644 index aab98e447feb..000000000000 --- a/arch/nds32/kernel/cacheinfo.c +++ /dev/null @@ -1,49 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include - -static void ci_leaf_init(struct cacheinfo *this_leaf, - enum cache_type type, unsigned int level) -{ - char cache_type = (type & CACHE_TYPE_INST ? ICACHE : DCACHE); - - this_leaf->level = level; - this_leaf->type = type; - this_leaf->coherency_line_size = CACHE_LINE_SIZE(cache_type); - this_leaf->number_of_sets = CACHE_SET(cache_type); - this_leaf->ways_of_associativity = CACHE_WAY(cache_type); - this_leaf->size = this_leaf->number_of_sets * - this_leaf->coherency_line_size * this_leaf->ways_of_associativity; -#if defined(CONFIG_CPU_DCACHE_WRITETHROUGH) - this_leaf->attributes = CACHE_WRITE_THROUGH; -#else - this_leaf->attributes = CACHE_WRITE_BACK; -#endif -} - -int init_cache_level(unsigned int cpu) -{ - struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); - - /* Only 1 level and I/D cache seperate. */ - this_cpu_ci->num_levels = 1; - this_cpu_ci->num_leaves = 2; - return 0; -} - -int populate_cache_leaves(unsigned int cpu) -{ - unsigned int level, idx; - struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); - struct cacheinfo *this_leaf = this_cpu_ci->info_list; - - for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && - idx < this_cpu_ci->num_leaves; idx++, level++) { - ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); - ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); - } - return 0; -} diff --git a/arch/nds32/kernel/devtree.c b/arch/nds32/kernel/devtree.c deleted file mode 100644 index bdce0fe5af9f..000000000000 --- a/arch/nds32/kernel/devtree.c +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include - -void __init early_init_devtree(void *params) -{ - if (!params || !early_init_dt_scan(params)) { - pr_crit("\n" - "Error: invalid device tree blob at (virtual address 0x%p)\n" - "\nPlease check your bootloader.", params); - - BUG_ON(1); - } - - dump_stack_set_arch_desc("%s (DT)", of_flat_dt_get_machine_name()); -} diff --git a/arch/nds32/kernel/dma.c b/arch/nds32/kernel/dma.c deleted file mode 100644 index 2ac8e6c82a61..000000000000 --- a/arch/nds32/kernel/dma.c +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include - -static inline void cache_op(phys_addr_t paddr, size_t size, - void (*fn)(unsigned long start, unsigned long end)) -{ - struct page *page = pfn_to_page(paddr >> PAGE_SHIFT); - unsigned offset = paddr & ~PAGE_MASK; - size_t left = size; - unsigned long start; - - do { - size_t len = left; - - if (PageHighMem(page)) { - void *addr; - - if (offset + len > PAGE_SIZE) { - if (offset >= PAGE_SIZE) { - page += offset >> PAGE_SHIFT; - offset &= ~PAGE_MASK; - } - len = PAGE_SIZE - offset; - } - - addr = kmap_atomic(page); - start = (unsigned long)(addr + offset); - fn(start, start + len); - kunmap_atomic(addr); - } else { - start = (unsigned long)phys_to_virt(paddr); - fn(start, start + size); - } - offset = 0; - page++; - left -= len; - } while (left); -} - -void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, - enum dma_data_direction dir) -{ - switch (dir) { - case DMA_FROM_DEVICE: - break; - case DMA_TO_DEVICE: - case DMA_BIDIRECTIONAL: - cache_op(paddr, size, cpu_dma_wb_range); - break; - default: - BUG(); - } -} - -void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, - enum dma_data_direction dir) -{ - switch (dir) { - case DMA_TO_DEVICE: - break; - case DMA_FROM_DEVICE: - case DMA_BIDIRECTIONAL: - cache_op(paddr, size, cpu_dma_inval_range); - break; - default: - BUG(); - } -} - -void arch_dma_prep_coherent(struct page *page, size_t size) -{ - cache_op(page_to_phys(page), size, cpu_dma_wbinval_range); -} diff --git a/arch/nds32/kernel/ex-entry.S b/arch/nds32/kernel/ex-entry.S deleted file mode 100644 index 107d98a1d1b8..000000000000 --- a/arch/nds32/kernel/ex-entry.S +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_HWZOL - .macro push_zol - mfusr $r14, $LB - mfusr $r15, $LE - mfusr $r16, $LC - .endm -#endif - .macro skip_save_fucop_ctl -#if defined(CONFIG_FPU) -skip_fucop_ctl: - smw.adm $p0, [$sp], $p0, #0x1 - j fucop_ctl_done -#endif - .endm - - .macro save_user_regs -#if defined(CONFIG_FPU) - sethi $p0, hi20(has_fpu) - lbsi $p0, [$p0+lo12(has_fpu)] - beqz $p0, skip_fucop_ctl - mfsr $p0, $FUCOP_CTL - smw.adm $p0, [$sp], $p0, #0x1 - bclr $p0, $p0, #FUCOP_CTL_offCP0EN - mtsr $p0, $FUCOP_CTL -fucop_ctl_done: - /* move $SP to the bottom of pt_regs */ - addi $sp, $sp, -FUCOP_CTL_OFFSET -#else - smw.adm $sp, [$sp], $sp, #0x1 - /* move $SP to the bottom of pt_regs */ - addi $sp, $sp, -OSP_OFFSET -#endif - - /* push $r0 ~ $r25 */ - smw.bim $r0, [$sp], $r25 - /* push $fp, $gp, $lp */ - smw.bim $sp, [$sp], $sp, #0xe - - mfsr $r12, $SP_USR - mfsr $r13, $IPC -#ifdef CONFIG_HWZOL - push_zol -#endif - movi $r17, -1 - move $r18, $r0 - mfsr $r19, $PSW - mfsr $r20, $IPSW - mfsr $r21, $P_IPSW - mfsr $r22, $P_IPC - mfsr $r23, $P_P0 - mfsr $r24, $P_P1 - smw.bim $r12, [$sp], $r24, #0 - addi $sp, $sp, -FUCOP_CTL_OFFSET - - /* Initialize kernel space $fp */ - andi $p0, $r20, #PSW_mskPOM - movi $p1, #0x0 - cmovz $fp, $p1, $p0 - - andi $r16, $r19, #PSW_mskINTL - slti $r17, $r16, #4 - bnez $r17, 1f - addi $r17, $r19, #-2 - mtsr $r17, $PSW - isb -1: - /* If it was superuser mode, we don't need to update $r25 */ - bnez $p0, 2f - la $p0, __entry_task - lw $r25, [$p0] -2: - .endm - - .text - -/* - * Exception Vector - */ -exception_handlers: - .long unhandled_exceptions !Reset/NMI - .long unhandled_exceptions !TLB fill - .long do_page_fault !PTE not present - .long do_dispatch_tlb_misc !TLB misc - .long unhandled_exceptions !TLB VLPT - .long unhandled_exceptions !Machine Error - .long do_debug_trap !Debug related - .long do_dispatch_general !General exception - .long eh_syscall !Syscall - .long asm_do_IRQ !IRQ - - skip_save_fucop_ctl -common_exception_handler: - save_user_regs - mfsr $p0, $ITYPE - andi $p0, $p0, #ITYPE_mskVECTOR - srli $p0, $p0, #ITYPE_offVECTOR - andi $p1, $p0, #NDS32_VECTOR_mskNONEXCEPTION - bnez $p1, 1f - sethi $lp, hi20(ret_from_exception) - ori $lp, $lp, lo12(ret_from_exception) - sethi $p1, hi20(exception_handlers) - ori $p1, $p1, lo12(exception_handlers) - lw $p1, [$p1+$p0<<2] - move $r0, $p0 - mfsr $r1, $EVA - mfsr $r2, $ITYPE - move $r3, $sp - mfsr $r4, $OIPC - /* enable gie if it is enabled in IPSW. */ - mfsr $r21, $PSW - andi $r20, $r20, #PSW_mskGIE /* r20 is $IPSW*/ - or $r21, $r21, $r20 - mtsr $r21, $PSW - dsb - jr $p1 - /* syscall */ -1: - addi $p1, $p0, #-NDS32_VECTOR_offEXCEPTION - bnez $p1, 2f - sethi $lp, hi20(ret_from_exception) - ori $lp, $lp, lo12(ret_from_exception) - sethi $p1, hi20(exception_handlers) - ori $p1, $p1, lo12(exception_handlers) - lwi $p1, [$p1+#NDS32_VECTOR_offEXCEPTION<<2] - jr $p1 - - /* interrupt */ -2: -#ifdef CONFIG_TRACE_IRQFLAGS - jal __trace_hardirqs_off -#endif - move $r0, $sp - sethi $lp, hi20(ret_from_intr) - ori $lp, $lp, lo12(ret_from_intr) - sethi $p0, hi20(exception_handlers) - ori $p0, $p0, lo12(exception_handlers) - lwi $p0, [$p0+#NDS32_VECTOR_offINTERRUPT<<2] - jr $p0 - - .macro EXCEPTION_VECTOR_DEBUG - .align 4 - mfsr $p0, $EDM_CTL - andi $p0, $p0, EDM_CTL_mskV3_EDM_MODE - tnez $p0, SWID_RAISE_INTERRUPT_LEVEL - .endm - - .macro EXCEPTION_VECTOR - .align 4 - sethi $p0, hi20(common_exception_handler) - ori $p0, $p0, lo12(common_exception_handler) - jral.ton $p0, $p0 - .endm - - .section ".text.init", #alloc, #execinstr - .global exception_vector -exception_vector: -.rept 6 - EXCEPTION_VECTOR -.endr - EXCEPTION_VECTOR_DEBUG -.rept 121 - EXCEPTION_VECTOR -.endr - .align 4 - .global exception_vector_end -exception_vector_end: diff --git a/arch/nds32/kernel/ex-exit.S b/arch/nds32/kernel/ex-exit.S deleted file mode 100644 index b30699911b81..000000000000 --- a/arch/nds32/kernel/ex-exit.S +++ /dev/null @@ -1,193 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include - - - -#ifdef CONFIG_HWZOL - .macro pop_zol - mtusr $r14, $LB - mtusr $r15, $LE - mtusr $r16, $LC - .endm -#endif - - .macro restore_user_regs_first - setgie.d - isb -#if defined(CONFIG_FPU) - addi $sp, $sp, OSP_OFFSET - lmw.adm $r12, [$sp], $r25, #0x0 - sethi $p0, hi20(has_fpu) - lbsi $p0, [$p0+lo12(has_fpu)] - beqz $p0, 2f - mtsr $r25, $FUCOP_CTL -2: -#else - addi $sp, $sp, FUCOP_CTL_OFFSET - lmw.adm $r12, [$sp], $r24, #0x0 -#endif - mtsr $r12, $SP_USR - mtsr $r13, $IPC -#ifdef CONFIG_HWZOL - pop_zol -#endif - mtsr $r19, $PSW - mtsr $r20, $IPSW - mtsr $r21, $P_IPSW - mtsr $r22, $P_IPC - mtsr $r23, $P_P0 - mtsr $r24, $P_P1 - lmw.adm $sp, [$sp], $sp, #0xe - .endm - - .macro restore_user_regs_last - pop $p0 - cmovn $sp, $p0, $p0 - - iret - nop - - .endm - - .macro restore_user_regs - restore_user_regs_first - lmw.adm $r0, [$sp], $r25, #0x0 - addi $sp, $sp, OSP_OFFSET - restore_user_regs_last - .endm - - .macro fast_restore_user_regs - restore_user_regs_first - lmw.adm $r1, [$sp], $r25, #0x0 - addi $sp, $sp, OSP_OFFSET-4 - restore_user_regs_last - .endm - -#ifdef CONFIG_PREEMPTION - .macro preempt_stop - .endm -#else - .macro preempt_stop - setgie.d - isb - .endm -#define resume_kernel no_work_pending -#endif - -ENTRY(ret_from_exception) - preempt_stop -ENTRY(ret_from_intr) - -/* - * judge Kernel or user mode - * - */ - lwi $p0, [$sp+(#IPSW_OFFSET)] ! Check if in nested interrupt - andi $p0, $p0, #PSW_mskINTL - bnez $p0, resume_kernel ! done with iret - j resume_userspace - - -/* - * This is the fast syscall return path. We do as little as - * possible here, and this includes saving $r0 back into the SVC - * stack. - * fixed: tsk - $r25, syscall # - $r7, syscall table pointer - $r8 - */ -ENTRY(ret_fast_syscall) - gie_disable - lwi $r1, [tsk+#TSK_TI_FLAGS] - andi $p1, $r1, #_TIF_WORK_MASK - bnez $p1, fast_work_pending - fast_restore_user_regs ! iret - -/* - * Ok, we need to do extra processing, - * enter the slow path returning from syscall, while pending work. - */ -fast_work_pending: - swi $r0, [$sp+(#R0_OFFSET)] ! what is different from ret_from_exception -work_pending: - andi $p1, $r1, #_TIF_NEED_RESCHED - bnez $p1, work_resched - - andi $p1, $r1, #_TIF_SIGPENDING|#_TIF_NOTIFY_RESUME|#_TIF_NOTIFY_SIGNAL - beqz $p1, no_work_pending - - move $r0, $sp ! 'regs' - gie_enable - bal do_notify_resume - b ret_slow_syscall -work_resched: - bal schedule ! path, return to user mode - -/* - * "slow" syscall return path. - */ -ENTRY(resume_userspace) -ENTRY(ret_slow_syscall) - gie_disable - lwi $p0, [$sp+(#IPSW_OFFSET)] ! Check if in nested interrupt - andi $p0, $p0, #PSW_mskINTL - bnez $p0, no_work_pending ! done with iret - lwi $r1, [tsk+#TSK_TI_FLAGS] - andi $p1, $r1, #_TIF_WORK_MASK - bnez $p1, work_pending ! handle work_resched, sig_pend - -no_work_pending: -#ifdef CONFIG_TRACE_IRQFLAGS - lwi $p0, [$sp+(#IPSW_OFFSET)] - andi $p0, $p0, #0x1 - la $r10, __trace_hardirqs_off - la $r9, __trace_hardirqs_on - cmovz $r9, $p0, $r10 - jral $r9 -#endif - restore_user_regs ! return from iret - - -/* - * preemptive kernel - */ -#ifdef CONFIG_PREEMPTION -resume_kernel: - gie_disable - lwi $t0, [tsk+#TSK_TI_PREEMPT] - bnez $t0, no_work_pending - - lwi $t0, [tsk+#TSK_TI_FLAGS] - andi $p1, $t0, #_TIF_NEED_RESCHED - beqz $p1, no_work_pending - - lwi $t0, [$sp+(#IPSW_OFFSET)] ! Interrupts off? - andi $t0, $t0, #1 - beqz $t0, no_work_pending - - jal preempt_schedule_irq - b no_work_pending -#endif - -/* - * This is how we return from a fork. - */ -ENTRY(ret_from_fork) - bal schedule_tail - beqz $r6, 1f ! r6 stores fn for kernel thread - move $r0, $r7 ! prepare kernel thread arg - jral $r6 -1: - lwi $r1, [tsk+#TSK_TI_FLAGS] ! check for syscall tracing - andi $p1, $r1, #_TIF_WORK_SYSCALL_LEAVE ! are we tracing syscalls? - beqz $p1, ret_slow_syscall - move $r0, $sp - bal syscall_trace_leave - b ret_slow_syscall diff --git a/arch/nds32/kernel/ex-scall.S b/arch/nds32/kernel/ex-scall.S deleted file mode 100644 index 270050f1b7b1..000000000000 --- a/arch/nds32/kernel/ex-scall.S +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include - -/* - * $r0 = previous task_struct, - * $r1 = next task_struct, - * previous and next are guaranteed not to be the same. - */ - -ENTRY(__switch_to) - - la $p0, __entry_task - sw $r1, [$p0] - addi $p1, $r0, #THREAD_CPU_CONTEXT - smw.bi $r6, [$p1], $r14, #0xb ! push r6~r14, fp, lp, sp - move $r25, $r1 -#if defined(CONFIG_FPU) - call _switch_fpu -#endif - addi $r1, $r25, #THREAD_CPU_CONTEXT - lmw.bi $r6, [$r1], $r14, #0xb ! pop r6~r14, fp, lp, sp - ret - - -#define tbl $r8 - -/* - * $r7 will be writen as syscall nr - */ - .macro get_scno - lwi $r7, [$sp + R15_OFFSET] - swi $r7, [$sp + SYSCALLNO_OFFSET] - .endm - - .macro updateipc - addi $r17, $r13, #4 ! $r13 is $IPC - swi $r17, [$sp + IPC_OFFSET] - .endm - -ENTRY(eh_syscall) - updateipc - - get_scno - gie_enable - - lwi $p0, [tsk+#TSK_TI_FLAGS] ! check for syscall tracing - - andi $p1, $p0, #_TIF_WORK_SYSCALL_ENTRY ! are we tracing syscalls? - bnez $p1, __sys_trace - - la $lp, ret_fast_syscall ! return address -jmp_systbl: - addi $p1, $r7, #-__NR_syscalls ! syscall number of syscall instruction is guarded by addembler - bgez $p1, _SCNO_EXCEED ! call sys_* routine - la tbl, sys_call_table ! load syscall table pointer - slli $p1, $r7, #2 - add $p1, tbl, $p1 - lwi $p1, [$p1] - jr $p1 ! no return - -_SCNO_EXCEED: - ori $r0, $r7, #0 - ori $r1, $sp, #0 - b bad_syscall - -/* - * This is the really slow path. We're going to be doing - * context switches, and waiting for our parent to respond. - */ -__sys_trace: - move $r0, $sp - bal syscall_trace_enter - move $r7, $r0 - la $lp, __sys_trace_return ! return address - - addi $p1, $r7, #1 - beqz $p1, ret_slow_syscall ! fatal signal is pending - - addi $p1, $sp, #R0_OFFSET ! pointer to regs - lmw.bi $r0, [$p1], $r5 ! have to reload $r0 - $r5 - b jmp_systbl - -__sys_trace_return: - swi $r0, [$sp+#R0_OFFSET] ! T: save returned $r0 - move $r0, $sp ! set pt_regs for syscall_trace_leave - bal syscall_trace_leave - b ret_slow_syscall - -ENTRY(sys_rt_sigreturn_wrapper) - addi $r0, $sp, #0 - b sys_rt_sigreturn -ENDPROC(sys_rt_sigreturn_wrapper) diff --git a/arch/nds32/kernel/fpu.c b/arch/nds32/kernel/fpu.c deleted file mode 100644 index 701c09a668de..000000000000 --- a/arch/nds32/kernel/fpu.c +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include - -const struct fpu_struct init_fpuregs = { - .fd_regs = {[0 ... 31] = sNAN64}, - .fpcsr = FPCSR_INIT, -#if IS_ENABLED(CONFIG_SUPPORT_DENORMAL_ARITHMETIC) - .UDF_IEX_trap = 0 -#endif -}; - -void save_fpu(struct task_struct *tsk) -{ - unsigned int fpcfg, fpcsr; - - enable_fpu(); - fpcfg = ((__nds32__fmfcfg() & FPCFG_mskFREG) >> FPCFG_offFREG); - switch (fpcfg) { - case SP32_DP32_reg: - asm volatile ("fsdi $fd31, [%0+0xf8]\n\t" - "fsdi $fd30, [%0+0xf0]\n\t" - "fsdi $fd29, [%0+0xe8]\n\t" - "fsdi $fd28, [%0+0xe0]\n\t" - "fsdi $fd27, [%0+0xd8]\n\t" - "fsdi $fd26, [%0+0xd0]\n\t" - "fsdi $fd25, [%0+0xc8]\n\t" - "fsdi $fd24, [%0+0xc0]\n\t" - "fsdi $fd23, [%0+0xb8]\n\t" - "fsdi $fd22, [%0+0xb0]\n\t" - "fsdi $fd21, [%0+0xa8]\n\t" - "fsdi $fd20, [%0+0xa0]\n\t" - "fsdi $fd19, [%0+0x98]\n\t" - "fsdi $fd18, [%0+0x90]\n\t" - "fsdi $fd17, [%0+0x88]\n\t" - "fsdi $fd16, [%0+0x80]\n\t" - : /* no output */ - : "r" (&tsk->thread.fpu) - : "memory"); - fallthrough; - case SP32_DP16_reg: - asm volatile ("fsdi $fd15, [%0+0x78]\n\t" - "fsdi $fd14, [%0+0x70]\n\t" - "fsdi $fd13, [%0+0x68]\n\t" - "fsdi $fd12, [%0+0x60]\n\t" - "fsdi $fd11, [%0+0x58]\n\t" - "fsdi $fd10, [%0+0x50]\n\t" - "fsdi $fd9, [%0+0x48]\n\t" - "fsdi $fd8, [%0+0x40]\n\t" - : /* no output */ - : "r" (&tsk->thread.fpu) - : "memory"); - fallthrough; - case SP16_DP8_reg: - asm volatile ("fsdi $fd7, [%0+0x38]\n\t" - "fsdi $fd6, [%0+0x30]\n\t" - "fsdi $fd5, [%0+0x28]\n\t" - "fsdi $fd4, [%0+0x20]\n\t" - : /* no output */ - : "r" (&tsk->thread.fpu) - : "memory"); - fallthrough; - case SP8_DP4_reg: - asm volatile ("fsdi $fd3, [%1+0x18]\n\t" - "fsdi $fd2, [%1+0x10]\n\t" - "fsdi $fd1, [%1+0x8]\n\t" - "fsdi $fd0, [%1+0x0]\n\t" - "fmfcsr %0\n\t" - "swi %0, [%1+0x100]\n\t" - : "=&r" (fpcsr) - : "r"(&tsk->thread.fpu) - : "memory"); - } - disable_fpu(); -} - -void load_fpu(const struct fpu_struct *fpregs) -{ - unsigned int fpcfg, fpcsr; - - enable_fpu(); - fpcfg = ((__nds32__fmfcfg() & FPCFG_mskFREG) >> FPCFG_offFREG); - switch (fpcfg) { - case SP32_DP32_reg: - asm volatile ("fldi $fd31, [%0+0xf8]\n\t" - "fldi $fd30, [%0+0xf0]\n\t" - "fldi $fd29, [%0+0xe8]\n\t" - "fldi $fd28, [%0+0xe0]\n\t" - "fldi $fd27, [%0+0xd8]\n\t" - "fldi $fd26, [%0+0xd0]\n\t" - "fldi $fd25, [%0+0xc8]\n\t" - "fldi $fd24, [%0+0xc0]\n\t" - "fldi $fd23, [%0+0xb8]\n\t" - "fldi $fd22, [%0+0xb0]\n\t" - "fldi $fd21, [%0+0xa8]\n\t" - "fldi $fd20, [%0+0xa0]\n\t" - "fldi $fd19, [%0+0x98]\n\t" - "fldi $fd18, [%0+0x90]\n\t" - "fldi $fd17, [%0+0x88]\n\t" - "fldi $fd16, [%0+0x80]\n\t" - : /* no output */ - : "r" (fpregs)); - fallthrough; - case SP32_DP16_reg: - asm volatile ("fldi $fd15, [%0+0x78]\n\t" - "fldi $fd14, [%0+0x70]\n\t" - "fldi $fd13, [%0+0x68]\n\t" - "fldi $fd12, [%0+0x60]\n\t" - "fldi $fd11, [%0+0x58]\n\t" - "fldi $fd10, [%0+0x50]\n\t" - "fldi $fd9, [%0+0x48]\n\t" - "fldi $fd8, [%0+0x40]\n\t" - : /* no output */ - : "r" (fpregs)); - fallthrough; - case SP16_DP8_reg: - asm volatile ("fldi $fd7, [%0+0x38]\n\t" - "fldi $fd6, [%0+0x30]\n\t" - "fldi $fd5, [%0+0x28]\n\t" - "fldi $fd4, [%0+0x20]\n\t" - : /* no output */ - : "r" (fpregs)); - fallthrough; - case SP8_DP4_reg: - asm volatile ("fldi $fd3, [%1+0x18]\n\t" - "fldi $fd2, [%1+0x10]\n\t" - "fldi $fd1, [%1+0x8]\n\t" - "fldi $fd0, [%1+0x0]\n\t" - "lwi %0, [%1+0x100]\n\t" - "fmtcsr %0\n\t":"=&r" (fpcsr) - : "r"(fpregs)); - } - disable_fpu(); -} -void store_fpu_for_suspend(void) -{ -#ifdef CONFIG_LAZY_FPU - if (last_task_used_math != NULL) - save_fpu(last_task_used_math); - last_task_used_math = NULL; -#else - if (!used_math()) - return; - unlazy_fpu(current); -#endif - clear_fpu(task_pt_regs(current)); -} -inline void do_fpu_context_switch(struct pt_regs *regs) -{ - /* Enable to use FPU. */ - - if (!user_mode(regs)) { - pr_err("BUG: FPU is used in kernel mode.\n"); - BUG(); - return; - } - - enable_ptreg_fpu(regs); -#ifdef CONFIG_LAZY_FPU //Lazy FPU is used - if (last_task_used_math == current) - return; - if (last_task_used_math != NULL) - /* Other processes fpu state, save away */ - save_fpu(last_task_used_math); - last_task_used_math = current; -#endif - if (used_math()) { - load_fpu(¤t->thread.fpu); - } else { - /* First time FPU user. */ - load_fpu(&init_fpuregs); -#if IS_ENABLED(CONFIG_SUPPORT_DENORMAL_ARITHMETIC) - current->thread.fpu.UDF_IEX_trap = init_fpuregs.UDF_IEX_trap; -#endif - set_used_math(); - } - -} - -inline void fill_sigfpe_signo(unsigned int fpcsr, int *signo) -{ - if (fpcsr & FPCSR_mskOVFT) - *signo = FPE_FLTOVF; -#ifndef CONFIG_SUPPORT_DENORMAL_ARITHMETIC - else if (fpcsr & FPCSR_mskUDFT) - *signo = FPE_FLTUND; -#endif - else if (fpcsr & FPCSR_mskIVOT) - *signo = FPE_FLTINV; - else if (fpcsr & FPCSR_mskDBZT) - *signo = FPE_FLTDIV; - else if (fpcsr & FPCSR_mskIEXT) - *signo = FPE_FLTRES; -} - -inline void handle_fpu_exception(struct pt_regs *regs) -{ - unsigned int fpcsr; - int si_code = 0, si_signo = SIGFPE; -#if IS_ENABLED(CONFIG_SUPPORT_DENORMAL_ARITHMETIC) - unsigned long redo_except = FPCSR_mskDNIT|FPCSR_mskUDFT|FPCSR_mskIEXT; -#else - unsigned long redo_except = FPCSR_mskDNIT; -#endif - - lose_fpu(); - fpcsr = current->thread.fpu.fpcsr; - - if (fpcsr & redo_except) { - si_signo = do_fpuemu(regs, ¤t->thread.fpu); - fpcsr = current->thread.fpu.fpcsr; - if (!si_signo) { - current->thread.fpu.fpcsr &= ~(redo_except); - goto done; - } - } else if (fpcsr & FPCSR_mskRIT) { - if (!user_mode(regs)) - make_task_dead(SIGILL); - si_signo = SIGILL; - } - - switch (si_signo) { - case SIGFPE: - fill_sigfpe_signo(fpcsr, &si_code); - break; - case SIGILL: - show_regs(regs); - si_code = ILL_COPROC; - break; - case SIGBUS: - si_code = BUS_ADRERR; - break; - default: - break; - } - - force_sig_fault(si_signo, si_code, - (void __user *)instruction_pointer(regs)); -done: - own_fpu(); -} - -bool do_fpu_exception(unsigned int subtype, struct pt_regs *regs) -{ - int done = true; - /* Coprocessor disabled exception */ - if (subtype == FPU_DISABLE_EXCEPTION) { - preempt_disable(); - do_fpu_context_switch(regs); - preempt_enable(); - } - /* Coprocessor exception such as underflow and overflow */ - else if (subtype == FPU_EXCEPTION) - handle_fpu_exception(regs); - else - done = false; - return done; -} diff --git a/arch/nds32/kernel/ftrace.c b/arch/nds32/kernel/ftrace.c deleted file mode 100644 index 711bc8cd186d..000000000000 --- a/arch/nds32/kernel/ftrace.c +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#include -#include -#include - -#ifndef CONFIG_DYNAMIC_FTRACE -extern void (*ftrace_trace_function)(unsigned long, unsigned long, - struct ftrace_ops*, struct ftrace_regs*); -extern void ftrace_graph_caller(void); - -noinline void __naked ftrace_stub(unsigned long ip, unsigned long parent_ip, - struct ftrace_ops *op, struct ftrace_regs *fregs) -{ - __asm__ (""); /* avoid to optimize as pure function */ -} - -noinline void _mcount(unsigned long parent_ip) -{ - /* save all state by the compiler prologue */ - - unsigned long ip = (unsigned long)__builtin_return_address(0); - - if (ftrace_trace_function != ftrace_stub) - ftrace_trace_function(ip - MCOUNT_INSN_SIZE, parent_ip, - NULL, NULL); - -#ifdef CONFIG_FUNCTION_GRAPH_TRACER - if (ftrace_graph_return != (trace_func_graph_ret_t)ftrace_stub - || ftrace_graph_entry != ftrace_graph_entry_stub) - ftrace_graph_caller(); -#endif - - /* restore all state by the compiler epilogue */ -} -EXPORT_SYMBOL(_mcount); - -#else /* CONFIG_DYNAMIC_FTRACE */ - -noinline void __naked ftrace_stub(unsigned long ip, unsigned long parent_ip, - struct ftrace_ops *op, struct ftrace_regs *fregs) -{ - __asm__ (""); /* avoid to optimize as pure function */ -} - -noinline void __naked _mcount(unsigned long parent_ip) -{ - __asm__ (""); /* avoid to optimize as pure function */ -} -EXPORT_SYMBOL(_mcount); - -#define XSTR(s) STR(s) -#define STR(s) #s -void _ftrace_caller(unsigned long parent_ip) -{ - /* save all state needed by the compiler prologue */ - - /* - * prepare arguments for real tracing function - * first arg : __builtin_return_address(0) - MCOUNT_INSN_SIZE - * second arg : parent_ip - */ - __asm__ __volatile__ ( - "move $r1, %0 \n\t" - "addi $r0, %1, #-" XSTR(MCOUNT_INSN_SIZE) "\n\t" - : - : "r" (parent_ip), "r" (__builtin_return_address(0))); - - /* a placeholder for the call to a real tracing function */ - __asm__ __volatile__ ( - "ftrace_call: \n\t" - "nop \n\t" - "nop \n\t" - "nop \n\t"); - -#ifdef CONFIG_FUNCTION_GRAPH_TRACER - /* a placeholder for the call to ftrace_graph_caller */ - __asm__ __volatile__ ( - "ftrace_graph_call: \n\t" - "nop \n\t" - "nop \n\t" - "nop \n\t"); -#endif - /* restore all state needed by the compiler epilogue */ -} - -static unsigned long gen_sethi_insn(unsigned long addr) -{ - unsigned long opcode = 0x46000000; - unsigned long imm = addr >> 12; - unsigned long rt_num = 0xf << 20; - - return ENDIAN_CONVERT(opcode | rt_num | imm); -} - -static unsigned long gen_ori_insn(unsigned long addr) -{ - unsigned long opcode = 0x58000000; - unsigned long imm = addr & 0x0000fff; - unsigned long rt_num = 0xf << 20; - unsigned long ra_num = 0xf << 15; - - return ENDIAN_CONVERT(opcode | rt_num | ra_num | imm); -} - -static unsigned long gen_jral_insn(unsigned long addr) -{ - unsigned long opcode = 0x4a000001; - unsigned long rt_num = 0x1e << 20; - unsigned long rb_num = 0xf << 10; - - return ENDIAN_CONVERT(opcode | rt_num | rb_num); -} - -static void ftrace_gen_call_insn(unsigned long *call_insns, - unsigned long addr) -{ - call_insns[0] = gen_sethi_insn(addr); /* sethi $r15, imm20u */ - call_insns[1] = gen_ori_insn(addr); /* ori $r15, $r15, imm15u */ - call_insns[2] = gen_jral_insn(addr); /* jral $lp, $r15 */ -} - -static int __ftrace_modify_code(unsigned long pc, unsigned long *old_insn, - unsigned long *new_insn, bool validate) -{ - unsigned long orig_insn[3]; - - if (validate) { - if (copy_from_kernel_nofault(orig_insn, (void *)pc, - MCOUNT_INSN_SIZE)) - return -EFAULT; - if (memcmp(orig_insn, old_insn, MCOUNT_INSN_SIZE)) - return -EINVAL; - } - - if (copy_to_kernel_nofault((void *)pc, new_insn, MCOUNT_INSN_SIZE)) - return -EPERM; - - return 0; -} - -static int ftrace_modify_code(unsigned long pc, unsigned long *old_insn, - unsigned long *new_insn, bool validate) -{ - int ret; - - ret = __ftrace_modify_code(pc, old_insn, new_insn, validate); - if (ret) - return ret; - - flush_icache_range(pc, pc + MCOUNT_INSN_SIZE); - - return ret; -} - -int ftrace_update_ftrace_func(ftrace_func_t func) -{ - unsigned long pc = (unsigned long)&ftrace_call; - unsigned long old_insn[3] = {INSN_NOP, INSN_NOP, INSN_NOP}; - unsigned long new_insn[3] = {INSN_NOP, INSN_NOP, INSN_NOP}; - - if (func != ftrace_stub) - ftrace_gen_call_insn(new_insn, (unsigned long)func); - - return ftrace_modify_code(pc, old_insn, new_insn, false); -} - -int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) -{ - unsigned long pc = rec->ip; - unsigned long nop_insn[3] = {INSN_NOP, INSN_NOP, INSN_NOP}; - unsigned long call_insn[3] = {INSN_NOP, INSN_NOP, INSN_NOP}; - - ftrace_gen_call_insn(call_insn, addr); - - return ftrace_modify_code(pc, nop_insn, call_insn, true); -} - -int ftrace_make_nop(struct module *mod, struct dyn_ftrace *rec, - unsigned long addr) -{ - unsigned long pc = rec->ip; - unsigned long nop_insn[3] = {INSN_NOP, INSN_NOP, INSN_NOP}; - unsigned long call_insn[3] = {INSN_NOP, INSN_NOP, INSN_NOP}; - - ftrace_gen_call_insn(call_insn, addr); - - return ftrace_modify_code(pc, call_insn, nop_insn, true); -} -#endif /* CONFIG_DYNAMIC_FTRACE */ - -#ifdef CONFIG_FUNCTION_GRAPH_TRACER -void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr, - unsigned long frame_pointer) -{ - unsigned long return_hooker = (unsigned long)&return_to_handler; - unsigned long old; - - if (unlikely(atomic_read(¤t->tracing_graph_pause))) - return; - - old = *parent; - - if (!function_graph_enter(old, self_addr, frame_pointer, NULL)) - *parent = return_hooker; -} - -noinline void ftrace_graph_caller(void) -{ - unsigned long *parent_ip = - (unsigned long *)(__builtin_frame_address(2) - 4); - - unsigned long selfpc = - (unsigned long)(__builtin_return_address(1) - MCOUNT_INSN_SIZE); - - unsigned long frame_pointer = - (unsigned long)__builtin_frame_address(3); - - prepare_ftrace_return(parent_ip, selfpc, frame_pointer); -} - -extern unsigned long ftrace_return_to_handler(unsigned long frame_pointer); -void __naked return_to_handler(void) -{ - __asm__ __volatile__ ( - /* save state needed by the ABI */ - "smw.adm $r0,[$sp],$r1,#0x0 \n\t" - - /* get original return address */ - "move $r0, $fp \n\t" - "bal ftrace_return_to_handler\n\t" - "move $lp, $r0 \n\t" - - /* restore state needed by the ABI */ - "lmw.bim $r0,[$sp],$r1,#0x0 \n\t"); -} - -#ifdef CONFIG_DYNAMIC_FTRACE -extern unsigned long ftrace_graph_call; - -static int ftrace_modify_graph_caller(bool enable) -{ - unsigned long pc = (unsigned long)&ftrace_graph_call; - unsigned long nop_insn[3] = {INSN_NOP, INSN_NOP, INSN_NOP}; - unsigned long call_insn[3] = {INSN_NOP, INSN_NOP, INSN_NOP}; - - ftrace_gen_call_insn(call_insn, (unsigned long)ftrace_graph_caller); - - if (enable) - return ftrace_modify_code(pc, nop_insn, call_insn, true); - else - return ftrace_modify_code(pc, call_insn, nop_insn, true); -} - -int ftrace_enable_ftrace_graph_caller(void) -{ - return ftrace_modify_graph_caller(true); -} - -int ftrace_disable_ftrace_graph_caller(void) -{ - return ftrace_modify_graph_caller(false); -} -#endif /* CONFIG_DYNAMIC_FTRACE */ - -#endif /* CONFIG_FUNCTION_GRAPH_TRACER */ - - -#ifdef CONFIG_TRACE_IRQFLAGS -noinline void __trace_hardirqs_off(void) -{ - trace_hardirqs_off(); -} -noinline void __trace_hardirqs_on(void) -{ - trace_hardirqs_on(); -} -#endif /* CONFIG_TRACE_IRQFLAGS */ diff --git a/arch/nds32/kernel/head.S b/arch/nds32/kernel/head.S deleted file mode 100644 index 7347f00451a9..000000000000 --- a/arch/nds32/kernel/head.S +++ /dev/null @@ -1,197 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_CPU_BIG_ENDIAN -#define OF_DT_MAGIC 0xd00dfeed -#else -#define OF_DT_MAGIC 0xedfe0dd0 -#endif - - .globl swapper_pg_dir - .equ swapper_pg_dir, TEXTADDR - 0x4000 - -/* - * Kernel startup entry point. - */ - .section ".head.text", "ax" - .type _stext, %function -ENTRY(_stext) - setgie.d ! Disable interrupt - isb -/* - * Disable I/D-cache and enable it at a proper time - */ - mfsr $r0, $mr8 - li $r1, #~(CACHE_CTL_mskIC_EN|CACHE_CTL_mskDC_EN) - and $r0, $r0, $r1 - mtsr $r0, $mr8 - -/* - * Process device tree blob - */ - andi $r0,$r2,#0x3 - li $r10, 0 - bne $r0, $r10, _nodtb - lwi $r0, [$r2] - li $r1, OF_DT_MAGIC - bne $r0, $r1, _nodtb - move $r10, $r2 -_nodtb: - -/* - * Create a temporary mapping area for booting, before start_kernel - */ - sethi $r4, hi20(swapper_pg_dir) - li $p0, (PAGE_OFFSET - PHYS_OFFSET) - sub $r4, $r4, $p0 - tlbop FlushAll ! invalidate TLB\n" - isb - mtsr $r4, $L1_PPTB ! load page table pointer\n" - -#ifdef CONFIG_CPU_DCACHE_DISABLE - #define MMU_CTL_NTCC MMU_CTL_CACHEABLE_NON -#else - #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH - #define MMU_CTL_NTCC MMU_CTL_CACHEABLE_WT - #else - #define MMU_CTL_NTCC MMU_CTL_CACHEABLE_WB - #endif -#endif - -/* set NTC cacheability, mutliple page size in use */ - mfsr $r3, $MMU_CTL -#if CONFIG_MEMORY_START >= 0xc0000000 - ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC3) -#elif CONFIG_MEMORY_START >= 0x80000000 - ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC2) -#elif CONFIG_MEMORY_START >= 0x40000000 - ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC1) -#else - ori $r3, $r3, (MMU_CTL_NTCC << MMU_CTL_offNTC0) -#endif - -#ifdef CONFIG_ANDES_PAGE_SIZE_4KB - ori $r3, $r3, #(MMU_CTL_mskMPZIU) -#else - ori $r3, $r3, #(MMU_CTL_mskMPZIU|MMU_CTL_D8KB) -#endif -#ifdef CONFIG_HW_SUPPORT_UNALIGNMENT_ACCESS - li $r0, #MMU_CTL_UNA - or $r3, $r3, $r0 -#endif - mtsr $r3, $MMU_CTL - isb - -/* set page size and size of kernel image */ - mfsr $r0, $MMU_CFG - srli $r3, $r0, MMU_CFG_offfEPSZ - zeb $r3, $r3 - bnez $r3, _extra_page_size_support -#ifdef CONFIG_ANDES_PAGE_SIZE_4KB - li $r5, #SZ_4K ! Use 4KB page size -#else - li $r5, #SZ_8K ! Use 8KB page size - li $r3, #1 -#endif - mtsr $r3, $TLB_MISC - b _image_size_check - -_extra_page_size_support: ! Use epzs pages size - clz $r6, $r3 - subri $r2, $r6, #31 - li $r3, #1 - sll $r3, $r3, $r2 - /* MMU_CFG.EPSZ value -> meaning */ - mul $r5, $r3, $r3 - slli $r5, $r5, #14 - /* MMU_CFG.EPSZ -> TLB_MISC.ACC_PSZ */ - addi $r3, $r2, #0x2 - mtsr $r3, $TLB_MISC - -_image_size_check: - /* calculate the image maximum size accepted by TLB config */ - andi $r6, $r0, MMU_CFG_mskTBW - andi $r0, $r0, MMU_CFG_mskTBS - srli $r6, $r6, MMU_CFG_offTBW - srli $r0, $r0, MMU_CFG_offTBS - addi $r6, $r6, #0x1 ! MMU_CFG.TBW value -> meaning - addi $r0, $r0, #0x2 ! MMU_CFG.TBS value -> meaning - sll $r0, $r6, $r0 ! entries = k-way * n-set - mul $r6, $r0, $r5 ! max size = entries * page size - /* check kernel image size */ - la $r3, (_end - PAGE_OFFSET) - bgt $r3, $r6, __error - - li $r2, #(PHYS_OFFSET + TLB_DATA_kernel_text_attr) - li $r3, PAGE_OFFSET - add $r6, $r6, $r3 - -_tlb: - mtsr $r3, $TLB_VPN - dsb - tlbop $r2, RWR - isb - add $r3, $r3, $r5 - add $r2, $r2, $r5 - bgt $r6, $r3, _tlb - mfsr $r3, $TLB_MISC ! setup access page size - li $r2, #~0xf - and $r3, $r3, $r2 -#ifdef CONFIG_ANDES_PAGE_SIZE_8KB - ori $r3, $r3, #0x1 -#endif - mtsr $r3, $TLB_MISC - - mfsr $r0, $MISC_CTL ! Enable BTB, RTP, shadow sp, and HW_PRE - ori $r0, $r0, #MISC_init - mtsr $r0, $MISC_CTL - - mfsr $p1, $PSW - li $r15, #~PSW_clr ! clear WBNA|DME|IME|DT|IT|POM|INTL|GIE - and $p1, $p1, $r15 - ori $p1, $p1, #PSW_init - mtsr $p1, $IPSW ! when iret, it will automatically enable MMU - la $lp, __mmap_switched - mtsr $lp, $IPC - iret - nop - - .type __switch_data, %object -__switch_data: - .long __bss_start ! $r6 - .long _end ! $r7 - .long __atags_pointer ! $atag_pointer - .long init_task ! $r9, move to $r25 - .long init_thread_union + THREAD_SIZE ! $sp - - -/* - * The following fragment of code is executed with the MMU on in MMU mode, - * and uses absolute addresses; this is not position independent. - */ - .align - .type __mmap_switched, %function -__mmap_switched: - la $r3, __switch_data - lmw.bim $r6, [$r3], $r9, #0b0001 - move $r25, $r9 - move $fp, #0 ! Clear BSS (and zero $fp) - beq $r7, $r6, _RRT -1: swi.bi $fp, [$r6], #4 - bne $r7, $r6, 1b - swi $r10, [$r8] - -_RRT: - b start_kernel - -__error: - b __error diff --git a/arch/nds32/kernel/irq.c b/arch/nds32/kernel/irq.c deleted file mode 100644 index 6ff5a672be27..000000000000 --- a/arch/nds32/kernel/irq.c +++ /dev/null @@ -1,9 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include - -void __init init_IRQ(void) -{ - irqchip_init(); -} diff --git a/arch/nds32/kernel/module.c b/arch/nds32/kernel/module.c deleted file mode 100644 index 3897fd14a21d..000000000000 --- a/arch/nds32/kernel/module.c +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include - -void *module_alloc(unsigned long size) -{ - return __vmalloc_node_range(size, 1, MODULES_VADDR, MODULES_END, - GFP_KERNEL, PAGE_KERNEL, 0, NUMA_NO_NODE, - __builtin_return_address(0)); -} - -void module_free(struct module *module, void *region) -{ - vfree(region); -} - -int module_frob_arch_sections(Elf_Ehdr * hdr, - Elf_Shdr * sechdrs, - char *secstrings, struct module *mod) -{ - return 0; -} - -void do_reloc16(unsigned int val, unsigned int *loc, unsigned int val_mask, - unsigned int val_shift, unsigned int loc_mask, - unsigned int partial_in_place, unsigned int swap) -{ - unsigned int tmp = 0, tmp2 = 0; - - __asm__ __volatile__("\tlhi.bi\t%0, [%2], 0\n" - "\tbeqz\t%3, 1f\n" - "\twsbh\t%0, %1\n" - "1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap) - ); - - tmp2 = tmp & loc_mask; - if (partial_in_place) { - tmp &= (~loc_mask); - tmp = - tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask); - } else { - tmp = tmp2 | ((val & val_mask) >> val_shift); - } - - __asm__ __volatile__("\tbeqz\t%3, 2f\n" - "\twsbh\t%0, %1\n" - "2:\n" - "\tshi.bi\t%0, [%2], 0\n":"=r"(tmp):"0"(tmp), - "r"(loc), "r"(swap) - ); -} - -void do_reloc32(unsigned int val, unsigned int *loc, unsigned int val_mask, - unsigned int val_shift, unsigned int loc_mask, - unsigned int partial_in_place, unsigned int swap) -{ - unsigned int tmp = 0, tmp2 = 0; - - __asm__ __volatile__("\tlmw.bi\t%0, [%2], %0, 0\n" - "\tbeqz\t%3, 1f\n" - "\twsbh\t%0, %1\n" - "\trotri\t%0, %1, 16\n" - "1:\n":"=r"(tmp):"0"(tmp), "r"(loc), "r"(swap) - ); - - tmp2 = tmp & loc_mask; - if (partial_in_place) { - tmp &= (~loc_mask); - tmp = - tmp2 | ((tmp + ((val & val_mask) >> val_shift)) & val_mask); - } else { - tmp = tmp2 | ((val & val_mask) >> val_shift); - } - - __asm__ __volatile__("\tbeqz\t%3, 2f\n" - "\twsbh\t%0, %1\n" - "\trotri\t%0, %1, 16\n" - "2:\n" - "\tsmw.bi\t%0, [%2], %0, 0\n":"=r"(tmp):"0"(tmp), - "r"(loc), "r"(swap) - ); -} - -static inline int exceed_limit(int offset, unsigned int val_mask, - struct module *module, Elf32_Rela * rel, - unsigned int relindex, unsigned int reloc_order) -{ - int abs_off = offset < 0 ? ~offset : offset; - - if (abs_off & (~val_mask)) { - pr_err("\n%s: relocation type %d out of range.\n" - "please rebuild the kernel module with gcc option \"-Wa,-mno-small-text\".\n", - module->name, ELF32_R_TYPE(rel->r_info)); - pr_err("section %d reloc %d offset 0x%x relative 0x%x.\n", - relindex, reloc_order, rel->r_offset, offset); - return true; - } - return false; -} - -#ifdef __NDS32_EL__ -#define NEED_SWAP 1 -#else -#define NEED_SWAP 0 -#endif - -int -apply_relocate_add(Elf32_Shdr * sechdrs, const char *strtab, - unsigned int symindex, unsigned int relindex, - struct module *module) -{ - Elf32_Shdr *symsec = sechdrs + symindex; - Elf32_Shdr *relsec = sechdrs + relindex; - Elf32_Shdr *dstsec = sechdrs + relsec->sh_info; - Elf32_Rela *rel = (void *)relsec->sh_addr; - unsigned int i; - - for (i = 0; i < relsec->sh_size / sizeof(Elf32_Rela); i++, rel++) { - Elf32_Addr *loc; - Elf32_Sym *sym; - Elf32_Addr v; - s32 offset; - - offset = ELF32_R_SYM(rel->r_info); - if (offset < 0 - || offset > (symsec->sh_size / sizeof(Elf32_Sym))) { - pr_err("%s: bad relocation\n", module->name); - pr_err("section %d reloc %d\n", relindex, i); - return -ENOEXEC; - } - - sym = ((Elf32_Sym *) symsec->sh_addr) + offset; - - if (rel->r_offset < 0 - || rel->r_offset > dstsec->sh_size - sizeof(u16)) { - pr_err("%s: out of bounds relocation\n", module->name); - pr_err("section %d reloc %d offset 0x%0x size %d\n", - relindex, i, rel->r_offset, dstsec->sh_size); - return -ENOEXEC; - } - - loc = (Elf32_Addr *) (dstsec->sh_addr + rel->r_offset); - v = sym->st_value + rel->r_addend; - - switch (ELF32_R_TYPE(rel->r_info)) { - case R_NDS32_NONE: - case R_NDS32_INSN16: - case R_NDS32_LABEL: - case R_NDS32_LONGCALL1: - case R_NDS32_LONGCALL2: - case R_NDS32_LONGCALL3: - case R_NDS32_LONGCALL4: - case R_NDS32_LONGJUMP1: - case R_NDS32_LONGJUMP2: - case R_NDS32_LONGJUMP3: - case R_NDS32_9_FIXED_RELA: - case R_NDS32_15_FIXED_RELA: - case R_NDS32_17_FIXED_RELA: - case R_NDS32_25_FIXED_RELA: - case R_NDS32_LOADSTORE: - case R_NDS32_DWARF2_OP1_RELA: - case R_NDS32_DWARF2_OP2_RELA: - case R_NDS32_DWARF2_LEB_RELA: - case R_NDS32_RELA_NOP_MIX ... R_NDS32_RELA_NOP_MAX: - break; - - case R_NDS32_32_RELA: - do_reloc32(v, loc, 0xffffffff, 0, 0, 0, 0); - break; - - case R_NDS32_HI20_RELA: - do_reloc32(v, loc, 0xfffff000, 12, 0xfff00000, 0, - NEED_SWAP); - break; - - case R_NDS32_LO12S3_RELA: - do_reloc32(v, loc, 0x00000fff, 3, 0xfffff000, 0, - NEED_SWAP); - break; - - case R_NDS32_LO12S2_RELA: - do_reloc32(v, loc, 0x00000fff, 2, 0xfffff000, 0, - NEED_SWAP); - break; - - case R_NDS32_LO12S1_RELA: - do_reloc32(v, loc, 0x00000fff, 1, 0xfffff000, 0, - NEED_SWAP); - break; - - case R_NDS32_LO12S0_RELA: - case R_NDS32_LO12S0_ORI_RELA: - do_reloc32(v, loc, 0x00000fff, 0, 0xfffff000, 0, - NEED_SWAP); - break; - - case R_NDS32_9_PCREL_RELA: - if (exceed_limit - ((v - (Elf32_Addr) loc), 0x000000ff, module, rel, - relindex, i)) - return -ENOEXEC; - do_reloc16(v - (Elf32_Addr) loc, loc, 0x000001ff, 1, - 0xffffff00, 0, NEED_SWAP); - break; - - case R_NDS32_15_PCREL_RELA: - if (exceed_limit - ((v - (Elf32_Addr) loc), 0x00003fff, module, rel, - relindex, i)) - return -ENOEXEC; - do_reloc32(v - (Elf32_Addr) loc, loc, 0x00007fff, 1, - 0xffffc000, 0, NEED_SWAP); - break; - - case R_NDS32_17_PCREL_RELA: - if (exceed_limit - ((v - (Elf32_Addr) loc), 0x0000ffff, module, rel, - relindex, i)) - return -ENOEXEC; - do_reloc32(v - (Elf32_Addr) loc, loc, 0x0001ffff, 1, - 0xffff0000, 0, NEED_SWAP); - break; - - case R_NDS32_25_PCREL_RELA: - if (exceed_limit - ((v - (Elf32_Addr) loc), 0x00ffffff, module, rel, - relindex, i)) - return -ENOEXEC; - do_reloc32(v - (Elf32_Addr) loc, loc, 0x01ffffff, 1, - 0xff000000, 0, NEED_SWAP); - break; - case R_NDS32_WORD_9_PCREL_RELA: - if (exceed_limit - ((v - (Elf32_Addr) loc), 0x000000ff, module, rel, - relindex, i)) - return -ENOEXEC; - do_reloc32(v - (Elf32_Addr) loc, loc, 0x000001ff, 1, - 0xffffff00, 0, NEED_SWAP); - break; - - case R_NDS32_SDA15S3_RELA: - case R_NDS32_SDA15S2_RELA: - case R_NDS32_SDA15S1_RELA: - case R_NDS32_SDA15S0_RELA: - pr_err("%s: unsupported relocation type %d.\n", - module->name, ELF32_R_TYPE(rel->r_info)); - pr_err - ("Small data section access doesn't work in the kernel space; " - "please rebuild the kernel module with gcc option -mcmodel=large.\n"); - pr_err("section %d reloc %d offset 0x%x size %d\n", - relindex, i, rel->r_offset, dstsec->sh_size); - break; - - default: - pr_err("%s: unsupported relocation type %d.\n", - module->name, ELF32_R_TYPE(rel->r_info)); - pr_err("section %d reloc %d offset 0x%x size %d\n", - relindex, i, rel->r_offset, dstsec->sh_size); - } - } - return 0; -} - -int -module_finalize(const Elf32_Ehdr * hdr, const Elf_Shdr * sechdrs, - struct module *module) -{ - return 0; -} - -void module_arch_cleanup(struct module *mod) -{ -} diff --git a/arch/nds32/kernel/nds32_ksyms.c b/arch/nds32/kernel/nds32_ksyms.c deleted file mode 100644 index 20719e42ae36..000000000000 --- a/arch/nds32/kernel/nds32_ksyms.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* mem functions */ -EXPORT_SYMBOL(memset); -EXPORT_SYMBOL(memcpy); -EXPORT_SYMBOL(memmove); -EXPORT_SYMBOL(memzero); - -/* user mem (segment) */ -EXPORT_SYMBOL(__arch_copy_from_user); -EXPORT_SYMBOL(__arch_copy_to_user); -EXPORT_SYMBOL(__arch_clear_user); diff --git a/arch/nds32/kernel/perf_event_cpu.c b/arch/nds32/kernel/perf_event_cpu.c deleted file mode 100644 index a78a879e7ef1..000000000000 --- a/arch/nds32/kernel/perf_event_cpu.c +++ /dev/null @@ -1,1500 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2008-2017 Andes Technology Corporation - * - * Reference ARMv7: Jean Pihet - * 2010 (c) MontaVista Software, LLC. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -/* Set at runtime when we know what CPU type we are. */ -static struct nds32_pmu *cpu_pmu; - -static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); -static void nds32_pmu_start(struct nds32_pmu *cpu_pmu); -static void nds32_pmu_stop(struct nds32_pmu *cpu_pmu); -static struct platform_device_id cpu_pmu_plat_device_ids[] = { - {.name = "nds32-pfm"}, - {}, -}; - -static int nds32_pmu_map_cache_event(const unsigned int (*cache_map) - [PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX], u64 config) -{ - unsigned int cache_type, cache_op, cache_result, ret; - - cache_type = (config >> 0) & 0xff; - if (cache_type >= PERF_COUNT_HW_CACHE_MAX) - return -EINVAL; - - cache_op = (config >> 8) & 0xff; - if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) - return -EINVAL; - - cache_result = (config >> 16) & 0xff; - if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) - return -EINVAL; - - ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; - - if (ret == CACHE_OP_UNSUPPORTED) - return -ENOENT; - - return ret; -} - -static int -nds32_pmu_map_hw_event(const unsigned int (*event_map)[PERF_COUNT_HW_MAX], - u64 config) -{ - int mapping; - - if (config >= PERF_COUNT_HW_MAX) - return -ENOENT; - - mapping = (*event_map)[config]; - return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; -} - -static int nds32_pmu_map_raw_event(u32 raw_event_mask, u64 config) -{ - int ev_type = (int)(config & raw_event_mask); - int idx = config >> 8; - - switch (idx) { - case 0: - ev_type = PFM_OFFSET_MAGIC_0 + ev_type; - if (ev_type >= SPAV3_0_SEL_LAST || ev_type <= SPAV3_0_SEL_BASE) - return -ENOENT; - break; - case 1: - ev_type = PFM_OFFSET_MAGIC_1 + ev_type; - if (ev_type >= SPAV3_1_SEL_LAST || ev_type <= SPAV3_1_SEL_BASE) - return -ENOENT; - break; - case 2: - ev_type = PFM_OFFSET_MAGIC_2 + ev_type; - if (ev_type >= SPAV3_2_SEL_LAST || ev_type <= SPAV3_2_SEL_BASE) - return -ENOENT; - break; - default: - return -ENOENT; - } - - return ev_type; -} - -int -nds32_pmu_map_event(struct perf_event *event, - const unsigned int (*event_map)[PERF_COUNT_HW_MAX], - const unsigned int (*cache_map) - [PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX], u32 raw_event_mask) -{ - u64 config = event->attr.config; - - switch (event->attr.type) { - case PERF_TYPE_HARDWARE: - return nds32_pmu_map_hw_event(event_map, config); - case PERF_TYPE_HW_CACHE: - return nds32_pmu_map_cache_event(cache_map, config); - case PERF_TYPE_RAW: - return nds32_pmu_map_raw_event(raw_event_mask, config); - } - - return -ENOENT; -} - -static int nds32_spav3_map_event(struct perf_event *event) -{ - return nds32_pmu_map_event(event, &nds32_pfm_perf_map, - &nds32_pfm_perf_cache_map, SOFTWARE_EVENT_MASK); -} - -static inline u32 nds32_pfm_getreset_flags(void) -{ - /* Read overflow status */ - u32 val = __nds32__mfsr(NDS32_SR_PFM_CTL); - u32 old_val = val; - - /* Write overflow bit to clear status, and others keep it 0 */ - u32 ov_flag = PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]; - - __nds32__mtsr(val | ov_flag, NDS32_SR_PFM_CTL); - - return old_val; -} - -static inline int nds32_pfm_has_overflowed(u32 pfm) -{ - u32 ov_flag = PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]; - - return pfm & ov_flag; -} - -static inline int nds32_pfm_counter_has_overflowed(u32 pfm, int idx) -{ - u32 mask = 0; - - switch (idx) { - case 0: - mask = PFM_CTL_OVF[0]; - break; - case 1: - mask = PFM_CTL_OVF[1]; - break; - case 2: - mask = PFM_CTL_OVF[2]; - break; - default: - pr_err("%s index wrong\n", __func__); - break; - } - return pfm & mask; -} - -/* - * Set the next IRQ period, based on the hwc->period_left value. - * To be called with the event disabled in hw: - */ -int nds32_pmu_event_set_period(struct perf_event *event) -{ - struct nds32_pmu *nds32_pmu = to_nds32_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - s64 left = local64_read(&hwc->period_left); - s64 period = hwc->sample_period; - int ret = 0; - - /* The period may have been changed by PERF_EVENT_IOC_PERIOD */ - if (unlikely(period != hwc->last_period)) - left = period - (hwc->last_period - left); - - if (unlikely(left <= -period)) { - left = period; - local64_set(&hwc->period_left, left); - hwc->last_period = period; - ret = 1; - } - - if (unlikely(left <= 0)) { - left += period; - local64_set(&hwc->period_left, left); - hwc->last_period = period; - ret = 1; - } - - if (left > (s64)nds32_pmu->max_period) - left = nds32_pmu->max_period; - - /* - * The hw event starts counting from this event offset, - * mark it to be able to extract future "deltas": - */ - local64_set(&hwc->prev_count, (u64)(-left)); - - nds32_pmu->write_counter(event, (u64)(-left) & nds32_pmu->max_period); - - perf_event_update_userpage(event); - - return ret; -} - -static irqreturn_t nds32_pmu_handle_irq(int irq_num, void *dev) -{ - u32 pfm; - struct perf_sample_data data; - struct nds32_pmu *cpu_pmu = (struct nds32_pmu *)dev; - struct pmu_hw_events *cpuc = cpu_pmu->get_hw_events(); - struct pt_regs *regs; - int idx; - /* - * Get and reset the IRQ flags - */ - pfm = nds32_pfm_getreset_flags(); - - /* - * Did an overflow occur? - */ - if (!nds32_pfm_has_overflowed(pfm)) - return IRQ_NONE; - - /* - * Handle the counter(s) overflow(s) - */ - regs = get_irq_regs(); - - nds32_pmu_stop(cpu_pmu); - for (idx = 0; idx < cpu_pmu->num_events; ++idx) { - struct perf_event *event = cpuc->events[idx]; - struct hw_perf_event *hwc; - - /* Ignore if we don't have an event. */ - if (!event) - continue; - - /* - * We have a single interrupt for all counters. Check that - * each counter has overflowed before we process it. - */ - if (!nds32_pfm_counter_has_overflowed(pfm, idx)) - continue; - - hwc = &event->hw; - nds32_pmu_event_update(event); - perf_sample_data_init(&data, 0, hwc->last_period); - if (!nds32_pmu_event_set_period(event)) - continue; - - if (perf_event_overflow(event, &data, regs)) - cpu_pmu->disable(event); - } - nds32_pmu_start(cpu_pmu); - /* - * Handle the pending perf events. - * - * Note: this call *must* be run with interrupts disabled. For - * platforms that can have the PMU interrupts raised as an NMI, this - * will not work. - */ - irq_work_run(); - - return IRQ_HANDLED; -} - -static inline int nds32_pfm_counter_valid(struct nds32_pmu *cpu_pmu, int idx) -{ - return ((idx >= 0) && (idx < cpu_pmu->num_events)); -} - -static inline int nds32_pfm_disable_counter(int idx) -{ - unsigned int val = __nds32__mfsr(NDS32_SR_PFM_CTL); - u32 mask = 0; - - mask = PFM_CTL_EN[idx]; - val &= ~mask; - val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); - __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); - return idx; -} - -/* - * Add an event filter to a given event. - */ -static int nds32_pmu_set_event_filter(struct hw_perf_event *event, - struct perf_event_attr *attr) -{ - unsigned long config_base = 0; - int idx = event->idx; - unsigned long no_kernel_tracing = 0; - unsigned long no_user_tracing = 0; - /* If index is -1, do not do anything */ - if (idx == -1) - return 0; - - no_kernel_tracing = PFM_CTL_KS[idx]; - no_user_tracing = PFM_CTL_KU[idx]; - /* - * Default: enable both kernel and user mode tracing. - */ - if (attr->exclude_user) - config_base |= no_user_tracing; - - if (attr->exclude_kernel) - config_base |= no_kernel_tracing; - - /* - * Install the filter into config_base as this is used to - * construct the event type. - */ - event->config_base |= config_base; - return 0; -} - -static inline void nds32_pfm_write_evtsel(int idx, u32 evnum) -{ - u32 offset = 0; - u32 ori_val = __nds32__mfsr(NDS32_SR_PFM_CTL); - u32 ev_mask = 0; - u32 no_kernel_mask = 0; - u32 no_user_mask = 0; - u32 val; - - offset = PFM_CTL_OFFSEL[idx]; - /* Clear previous mode selection, and write new one */ - no_kernel_mask = PFM_CTL_KS[idx]; - no_user_mask = PFM_CTL_KU[idx]; - ori_val &= ~no_kernel_mask; - ori_val &= ~no_user_mask; - if (evnum & no_kernel_mask) - ori_val |= no_kernel_mask; - - if (evnum & no_user_mask) - ori_val |= no_user_mask; - - /* Clear previous event selection */ - ev_mask = PFM_CTL_SEL[idx]; - ori_val &= ~ev_mask; - evnum &= SOFTWARE_EVENT_MASK; - - /* undo the linear mapping */ - evnum = get_converted_evet_hw_num(evnum); - val = ori_val | (evnum << offset); - val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); - __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); -} - -static inline int nds32_pfm_enable_counter(int idx) -{ - unsigned int val = __nds32__mfsr(NDS32_SR_PFM_CTL); - u32 mask = 0; - - mask = PFM_CTL_EN[idx]; - val |= mask; - val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); - __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); - return idx; -} - -static inline int nds32_pfm_enable_intens(int idx) -{ - unsigned int val = __nds32__mfsr(NDS32_SR_PFM_CTL); - u32 mask = 0; - - mask = PFM_CTL_IE[idx]; - val |= mask; - val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); - __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); - return idx; -} - -static inline int nds32_pfm_disable_intens(int idx) -{ - unsigned int val = __nds32__mfsr(NDS32_SR_PFM_CTL); - u32 mask = 0; - - mask = PFM_CTL_IE[idx]; - val &= ~mask; - val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); - __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); - return idx; -} - -static int event_requires_mode_exclusion(struct perf_event_attr *attr) -{ - /* Other modes NDS32 does not support */ - return attr->exclude_user || attr->exclude_kernel; -} - -static void nds32_pmu_enable_event(struct perf_event *event) -{ - unsigned long flags; - unsigned int evnum = 0; - struct hw_perf_event *hwc = &event->hw; - struct nds32_pmu *cpu_pmu = to_nds32_pmu(event->pmu); - struct pmu_hw_events *events = cpu_pmu->get_hw_events(); - int idx = hwc->idx; - - if (!nds32_pfm_counter_valid(cpu_pmu, idx)) { - pr_err("CPU enabling wrong pfm counter IRQ enable\n"); - return; - } - - /* - * Enable counter and interrupt, and set the counter to count - * the event that we're interested in. - */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); - - /* - * Disable counter - */ - nds32_pfm_disable_counter(idx); - - /* - * Check whether we need to exclude the counter from certain modes. - */ - if ((!cpu_pmu->set_event_filter || - cpu_pmu->set_event_filter(hwc, &event->attr)) && - event_requires_mode_exclusion(&event->attr)) { - pr_notice - ("NDS32 performance counters do not support mode exclusion\n"); - hwc->config_base = 0; - } - /* Write event */ - evnum = hwc->config_base; - nds32_pfm_write_evtsel(idx, evnum); - - /* - * Enable interrupt for this counter - */ - nds32_pfm_enable_intens(idx); - - /* - * Enable counter - */ - nds32_pfm_enable_counter(idx); - - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); -} - -static void nds32_pmu_disable_event(struct perf_event *event) -{ - unsigned long flags; - struct hw_perf_event *hwc = &event->hw; - struct nds32_pmu *cpu_pmu = to_nds32_pmu(event->pmu); - struct pmu_hw_events *events = cpu_pmu->get_hw_events(); - int idx = hwc->idx; - - if (!nds32_pfm_counter_valid(cpu_pmu, idx)) { - pr_err("CPU disabling wrong pfm counter IRQ enable %d\n", idx); - return; - } - - /* - * Disable counter and interrupt - */ - raw_spin_lock_irqsave(&events->pmu_lock, flags); - - /* - * Disable counter - */ - nds32_pfm_disable_counter(idx); - - /* - * Disable interrupt for this counter - */ - nds32_pfm_disable_intens(idx); - - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); -} - -static inline u32 nds32_pmu_read_counter(struct perf_event *event) -{ - struct nds32_pmu *cpu_pmu = to_nds32_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - u32 count = 0; - - if (!nds32_pfm_counter_valid(cpu_pmu, idx)) { - pr_err("CPU reading wrong counter %d\n", idx); - } else { - switch (idx) { - case PFMC0: - count = __nds32__mfsr(NDS32_SR_PFMC0); - break; - case PFMC1: - count = __nds32__mfsr(NDS32_SR_PFMC1); - break; - case PFMC2: - count = __nds32__mfsr(NDS32_SR_PFMC2); - break; - default: - pr_err - ("%s: CPU has no performance counters %d\n", - __func__, idx); - } - } - return count; -} - -static inline void nds32_pmu_write_counter(struct perf_event *event, u32 value) -{ - struct nds32_pmu *cpu_pmu = to_nds32_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - if (!nds32_pfm_counter_valid(cpu_pmu, idx)) { - pr_err("CPU writing wrong counter %d\n", idx); - } else { - switch (idx) { - case PFMC0: - __nds32__mtsr_isb(value, NDS32_SR_PFMC0); - break; - case PFMC1: - __nds32__mtsr_isb(value, NDS32_SR_PFMC1); - break; - case PFMC2: - __nds32__mtsr_isb(value, NDS32_SR_PFMC2); - break; - default: - pr_err - ("%s: CPU has no performance counters %d\n", - __func__, idx); - } - } -} - -static int nds32_pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - int idx; - struct hw_perf_event *hwc = &event->hw; - /* - * Current implementation maps cycles, instruction count and cache-miss - * to specific counter. - * However, multiple of the 3 counters are able to count these events. - * - * - * SOFTWARE_EVENT_MASK mask for getting event num , - * This is defined by Jia-Rung, you can change the polocies. - * However, do not exceed 8 bits. This is hardware specific. - * The last number is SPAv3_2_SEL_LAST. - */ - unsigned long evtype = hwc->config_base & SOFTWARE_EVENT_MASK; - - idx = get_converted_event_idx(evtype); - /* - * Try to get the counter for correpsonding event - */ - if (evtype == SPAV3_0_SEL_TOTAL_CYCLES) { - if (!test_and_set_bit(idx, cpuc->used_mask)) - return idx; - if (!test_and_set_bit(NDS32_IDX_COUNTER0, cpuc->used_mask)) - return NDS32_IDX_COUNTER0; - if (!test_and_set_bit(NDS32_IDX_COUNTER1, cpuc->used_mask)) - return NDS32_IDX_COUNTER1; - } else if (evtype == SPAV3_1_SEL_COMPLETED_INSTRUCTION) { - if (!test_and_set_bit(idx, cpuc->used_mask)) - return idx; - else if (!test_and_set_bit(NDS32_IDX_COUNTER1, cpuc->used_mask)) - return NDS32_IDX_COUNTER1; - else if (!test_and_set_bit - (NDS32_IDX_CYCLE_COUNTER, cpuc->used_mask)) - return NDS32_IDX_CYCLE_COUNTER; - } else { - if (!test_and_set_bit(idx, cpuc->used_mask)) - return idx; - } - return -EAGAIN; -} - -static void nds32_pmu_start(struct nds32_pmu *cpu_pmu) -{ - unsigned long flags; - unsigned int val; - struct pmu_hw_events *events = cpu_pmu->get_hw_events(); - - raw_spin_lock_irqsave(&events->pmu_lock, flags); - - /* Enable all counters , NDS PFM has 3 counters */ - val = __nds32__mfsr(NDS32_SR_PFM_CTL); - val |= (PFM_CTL_EN[0] | PFM_CTL_EN[1] | PFM_CTL_EN[2]); - val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); - __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); - - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); -} - -static void nds32_pmu_stop(struct nds32_pmu *cpu_pmu) -{ - unsigned long flags; - unsigned int val; - struct pmu_hw_events *events = cpu_pmu->get_hw_events(); - - raw_spin_lock_irqsave(&events->pmu_lock, flags); - - /* Disable all counters , NDS PFM has 3 counters */ - val = __nds32__mfsr(NDS32_SR_PFM_CTL); - val &= ~(PFM_CTL_EN[0] | PFM_CTL_EN[1] | PFM_CTL_EN[2]); - val &= ~(PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); - __nds32__mtsr_isb(val, NDS32_SR_PFM_CTL); - - raw_spin_unlock_irqrestore(&events->pmu_lock, flags); -} - -static void nds32_pmu_reset(void *info) -{ - u32 val = 0; - - val |= (PFM_CTL_OVF[0] | PFM_CTL_OVF[1] | PFM_CTL_OVF[2]); - __nds32__mtsr(val, NDS32_SR_PFM_CTL); - __nds32__mtsr(0, NDS32_SR_PFM_CTL); - __nds32__mtsr(0, NDS32_SR_PFMC0); - __nds32__mtsr(0, NDS32_SR_PFMC1); - __nds32__mtsr(0, NDS32_SR_PFMC2); -} - -static void nds32_pmu_init(struct nds32_pmu *cpu_pmu) -{ - cpu_pmu->handle_irq = nds32_pmu_handle_irq; - cpu_pmu->enable = nds32_pmu_enable_event; - cpu_pmu->disable = nds32_pmu_disable_event; - cpu_pmu->read_counter = nds32_pmu_read_counter; - cpu_pmu->write_counter = nds32_pmu_write_counter; - cpu_pmu->get_event_idx = nds32_pmu_get_event_idx; - cpu_pmu->start = nds32_pmu_start; - cpu_pmu->stop = nds32_pmu_stop; - cpu_pmu->reset = nds32_pmu_reset; - cpu_pmu->max_period = 0xFFFFFFFF; /* Maximum counts */ -}; - -static u32 nds32_read_num_pfm_events(void) -{ - /* NDS32 SPAv3 PMU support 3 counter */ - return 3; -} - -static int device_pmu_init(struct nds32_pmu *cpu_pmu) -{ - nds32_pmu_init(cpu_pmu); - /* - * This name should be devive-specific name, whatever you like :) - * I think "PMU" will be a good generic name. - */ - cpu_pmu->name = "nds32v3-pmu"; - cpu_pmu->map_event = nds32_spav3_map_event; - cpu_pmu->num_events = nds32_read_num_pfm_events(); - cpu_pmu->set_event_filter = nds32_pmu_set_event_filter; - return 0; -} - -/* - * CPU PMU identification and probing. - */ -static int probe_current_pmu(struct nds32_pmu *pmu) -{ - int ret; - - get_cpu(); - ret = -ENODEV; - /* - * If ther are various CPU types with its own PMU, initialize with - * - * the corresponding one - */ - device_pmu_init(pmu); - put_cpu(); - return ret; -} - -static void nds32_pmu_enable(struct pmu *pmu) -{ - struct nds32_pmu *nds32_pmu = to_nds32_pmu(pmu); - struct pmu_hw_events *hw_events = nds32_pmu->get_hw_events(); - int enabled = bitmap_weight(hw_events->used_mask, - nds32_pmu->num_events); - - if (enabled) - nds32_pmu->start(nds32_pmu); -} - -static void nds32_pmu_disable(struct pmu *pmu) -{ - struct nds32_pmu *nds32_pmu = to_nds32_pmu(pmu); - - nds32_pmu->stop(nds32_pmu); -} - -static void nds32_pmu_release_hardware(struct nds32_pmu *nds32_pmu) -{ - nds32_pmu->free_irq(nds32_pmu); - pm_runtime_put_sync(&nds32_pmu->plat_device->dev); -} - -static irqreturn_t nds32_pmu_dispatch_irq(int irq, void *dev) -{ - struct nds32_pmu *nds32_pmu = (struct nds32_pmu *)dev; - int ret; - u64 start_clock, finish_clock; - - start_clock = local_clock(); - ret = nds32_pmu->handle_irq(irq, dev); - finish_clock = local_clock(); - - perf_sample_event_took(finish_clock - start_clock); - return ret; -} - -static int nds32_pmu_reserve_hardware(struct nds32_pmu *nds32_pmu) -{ - int err; - struct platform_device *pmu_device = nds32_pmu->plat_device; - - if (!pmu_device) - return -ENODEV; - - pm_runtime_get_sync(&pmu_device->dev); - err = nds32_pmu->request_irq(nds32_pmu, nds32_pmu_dispatch_irq); - if (err) { - nds32_pmu_release_hardware(nds32_pmu); - return err; - } - - return 0; -} - -static int -validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events, - struct perf_event *event) -{ - struct nds32_pmu *nds32_pmu = to_nds32_pmu(event->pmu); - - if (is_software_event(event)) - return 1; - - if (event->pmu != pmu) - return 0; - - if (event->state < PERF_EVENT_STATE_OFF) - return 1; - - if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) - return 1; - - return nds32_pmu->get_event_idx(hw_events, event) >= 0; -} - -static int validate_group(struct perf_event *event) -{ - struct perf_event *sibling, *leader = event->group_leader; - struct pmu_hw_events fake_pmu; - DECLARE_BITMAP(fake_used_mask, MAX_COUNTERS); - /* - * Initialize the fake PMU. We only need to populate the - * used_mask for the purposes of validation. - */ - memset(fake_used_mask, 0, sizeof(fake_used_mask)); - - if (!validate_event(event->pmu, &fake_pmu, leader)) - return -EINVAL; - - for_each_sibling_event(sibling, leader) { - if (!validate_event(event->pmu, &fake_pmu, sibling)) - return -EINVAL; - } - - if (!validate_event(event->pmu, &fake_pmu, event)) - return -EINVAL; - - return 0; -} - -static int __hw_perf_event_init(struct perf_event *event) -{ - struct nds32_pmu *nds32_pmu = to_nds32_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - int mapping; - - mapping = nds32_pmu->map_event(event); - - if (mapping < 0) { - pr_debug("event %x:%llx not supported\n", event->attr.type, - event->attr.config); - return mapping; - } - - /* - * We don't assign an index until we actually place the event onto - * hardware. Use -1 to signify that we haven't decided where to put it - * yet. For SMP systems, each core has it's own PMU so we can't do any - * clever allocation or constraints checking at this point. - */ - hwc->idx = -1; - hwc->config_base = 0; - hwc->config = 0; - hwc->event_base = 0; - - /* - * Check whether we need to exclude the counter from certain modes. - */ - if ((!nds32_pmu->set_event_filter || - nds32_pmu->set_event_filter(hwc, &event->attr)) && - event_requires_mode_exclusion(&event->attr)) { - pr_debug - ("NDS performance counters do not support mode exclusion\n"); - return -EOPNOTSUPP; - } - - /* - * Store the event encoding into the config_base field. - */ - hwc->config_base |= (unsigned long)mapping; - - if (!hwc->sample_period) { - /* - * For non-sampling runs, limit the sample_period to half - * of the counter width. That way, the new counter value - * is far less likely to overtake the previous one unless - * you have some serious IRQ latency issues. - */ - hwc->sample_period = nds32_pmu->max_period >> 1; - hwc->last_period = hwc->sample_period; - local64_set(&hwc->period_left, hwc->sample_period); - } - - if (event->group_leader != event) { - if (validate_group(event) != 0) - return -EINVAL; - } - - return 0; -} - -static int nds32_pmu_event_init(struct perf_event *event) -{ - struct nds32_pmu *nds32_pmu = to_nds32_pmu(event->pmu); - int err = 0; - atomic_t *active_events = &nds32_pmu->active_events; - - /* does not support taken branch sampling */ - if (has_branch_stack(event)) - return -EOPNOTSUPP; - - if (nds32_pmu->map_event(event) == -ENOENT) - return -ENOENT; - - if (!atomic_inc_not_zero(active_events)) { - if (atomic_read(active_events) == 0) { - /* Register irq handler */ - err = nds32_pmu_reserve_hardware(nds32_pmu); - } - - if (!err) - atomic_inc(active_events); - } - - if (err) - return err; - - err = __hw_perf_event_init(event); - - return err; -} - -static void nds32_start(struct perf_event *event, int flags) -{ - struct nds32_pmu *nds32_pmu = to_nds32_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - /* - * NDS pmu always has to reprogram the period, so ignore - * PERF_EF_RELOAD, see the comment below. - */ - if (flags & PERF_EF_RELOAD) - WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); - - hwc->state = 0; - /* Set the period for the event. */ - nds32_pmu_event_set_period(event); - - nds32_pmu->enable(event); -} - -static int nds32_pmu_add(struct perf_event *event, int flags) -{ - struct nds32_pmu *nds32_pmu = to_nds32_pmu(event->pmu); - struct pmu_hw_events *hw_events = nds32_pmu->get_hw_events(); - struct hw_perf_event *hwc = &event->hw; - int idx; - int err = 0; - - perf_pmu_disable(event->pmu); - - /* If we don't have a space for the counter then finish early. */ - idx = nds32_pmu->get_event_idx(hw_events, event); - if (idx < 0) { - err = idx; - goto out; - } - - /* - * If there is an event in the counter we are going to use then make - * sure it is disabled. - */ - event->hw.idx = idx; - nds32_pmu->disable(event); - hw_events->events[idx] = event; - - hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; - if (flags & PERF_EF_START) - nds32_start(event, PERF_EF_RELOAD); - - /* Propagate our changes to the userspace mapping. */ - perf_event_update_userpage(event); - -out: - perf_pmu_enable(event->pmu); - return err; -} - -u64 nds32_pmu_event_update(struct perf_event *event) -{ - struct nds32_pmu *nds32_pmu = to_nds32_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - u64 delta, prev_raw_count, new_raw_count; - -again: - prev_raw_count = local64_read(&hwc->prev_count); - new_raw_count = nds32_pmu->read_counter(event); - - if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, - new_raw_count) != prev_raw_count) { - goto again; - } - /* - * Whether overflow or not, "unsigned substraction" - * will always get their delta - */ - delta = (new_raw_count - prev_raw_count) & nds32_pmu->max_period; - - local64_add(delta, &event->count); - local64_sub(delta, &hwc->period_left); - - return new_raw_count; -} - -static void nds32_stop(struct perf_event *event, int flags) -{ - struct nds32_pmu *nds32_pmu = to_nds32_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - /* - * NDS pmu always has to update the counter, so ignore - * PERF_EF_UPDATE, see comments in nds32_start(). - */ - if (!(hwc->state & PERF_HES_STOPPED)) { - nds32_pmu->disable(event); - nds32_pmu_event_update(event); - hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; - } -} - -static void nds32_pmu_del(struct perf_event *event, int flags) -{ - struct nds32_pmu *nds32_pmu = to_nds32_pmu(event->pmu); - struct pmu_hw_events *hw_events = nds32_pmu->get_hw_events(); - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - nds32_stop(event, PERF_EF_UPDATE); - hw_events->events[idx] = NULL; - clear_bit(idx, hw_events->used_mask); - - perf_event_update_userpage(event); -} - -static void nds32_pmu_read(struct perf_event *event) -{ - nds32_pmu_event_update(event); -} - -/* Please refer to SPAv3 for more hardware specific details */ -PMU_FORMAT_ATTR(event, "config:0-63"); - -static struct attribute *nds32_arch_formats_attr[] = { - &format_attr_event.attr, - NULL, -}; - -static struct attribute_group nds32_pmu_format_group = { - .name = "format", - .attrs = nds32_arch_formats_attr, -}; - -static ssize_t nds32_pmu_cpumask_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - return 0; -} - -static DEVICE_ATTR(cpus, 0444, nds32_pmu_cpumask_show, NULL); - -static struct attribute *nds32_pmu_common_attrs[] = { - &dev_attr_cpus.attr, - NULL, -}; - -static struct attribute_group nds32_pmu_common_group = { - .attrs = nds32_pmu_common_attrs, -}; - -static const struct attribute_group *nds32_pmu_attr_groups[] = { - &nds32_pmu_format_group, - &nds32_pmu_common_group, - NULL, -}; - -static void nds32_init(struct nds32_pmu *nds32_pmu) -{ - atomic_set(&nds32_pmu->active_events, 0); - - nds32_pmu->pmu = (struct pmu) { - .pmu_enable = nds32_pmu_enable, - .pmu_disable = nds32_pmu_disable, - .attr_groups = nds32_pmu_attr_groups, - .event_init = nds32_pmu_event_init, - .add = nds32_pmu_add, - .del = nds32_pmu_del, - .start = nds32_start, - .stop = nds32_stop, - .read = nds32_pmu_read, - }; -} - -int nds32_pmu_register(struct nds32_pmu *nds32_pmu, int type) -{ - nds32_init(nds32_pmu); - pm_runtime_enable(&nds32_pmu->plat_device->dev); - pr_info("enabled with %s PMU driver, %d counters available\n", - nds32_pmu->name, nds32_pmu->num_events); - return perf_pmu_register(&nds32_pmu->pmu, nds32_pmu->name, type); -} - -static struct pmu_hw_events *cpu_pmu_get_cpu_events(void) -{ - return this_cpu_ptr(&cpu_hw_events); -} - -static int cpu_pmu_request_irq(struct nds32_pmu *cpu_pmu, irq_handler_t handler) -{ - int err, irq, irqs; - struct platform_device *pmu_device = cpu_pmu->plat_device; - - if (!pmu_device) - return -ENODEV; - - irqs = min(pmu_device->num_resources, num_possible_cpus()); - if (irqs < 1) { - pr_err("no irqs for PMUs defined\n"); - return -ENODEV; - } - - irq = platform_get_irq(pmu_device, 0); - err = request_irq(irq, handler, IRQF_NOBALANCING, "nds32-pfm", - cpu_pmu); - if (err) { - pr_err("unable to request IRQ%d for NDS PMU counters\n", - irq); - return err; - } - return 0; -} - -static void cpu_pmu_free_irq(struct nds32_pmu *cpu_pmu) -{ - int irq; - struct platform_device *pmu_device = cpu_pmu->plat_device; - - irq = platform_get_irq(pmu_device, 0); - if (irq >= 0) - free_irq(irq, cpu_pmu); -} - -static void cpu_pmu_init(struct nds32_pmu *cpu_pmu) -{ - int cpu; - struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu); - - raw_spin_lock_init(&events->pmu_lock); - - cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events; - cpu_pmu->request_irq = cpu_pmu_request_irq; - cpu_pmu->free_irq = cpu_pmu_free_irq; - - /* Ensure the PMU has sane values out of reset. */ - if (cpu_pmu->reset) - on_each_cpu(cpu_pmu->reset, cpu_pmu, 1); -} - -static const struct of_device_id cpu_pmu_of_device_ids[] = { - {.compatible = "andestech,nds32v3-pmu", - .data = device_pmu_init}, - {}, -}; - -static int cpu_pmu_device_probe(struct platform_device *pdev) -{ - const struct of_device_id *of_id; - int (*init_fn)(struct nds32_pmu *nds32_pmu); - struct device_node *node = pdev->dev.of_node; - struct nds32_pmu *pmu; - int ret = -ENODEV; - - if (cpu_pmu) { - pr_notice("[perf] attempt to register multiple PMU devices!\n"); - return -ENOSPC; - } - - pmu = kzalloc(sizeof(*pmu), GFP_KERNEL); - if (!pmu) - return -ENOMEM; - - of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node); - if (node && of_id) { - init_fn = of_id->data; - ret = init_fn(pmu); - } else { - ret = probe_current_pmu(pmu); - } - - if (ret) { - pr_notice("[perf] failed to probe PMU!\n"); - goto out_free; - } - - cpu_pmu = pmu; - cpu_pmu->plat_device = pdev; - cpu_pmu_init(cpu_pmu); - ret = nds32_pmu_register(cpu_pmu, PERF_TYPE_RAW); - - if (!ret) - return 0; - -out_free: - pr_notice("[perf] failed to register PMU devices!\n"); - kfree(pmu); - return ret; -} - -static struct platform_driver cpu_pmu_driver = { - .driver = { - .name = "nds32-pfm", - .of_match_table = cpu_pmu_of_device_ids, - }, - .probe = cpu_pmu_device_probe, - .id_table = cpu_pmu_plat_device_ids, -}; - -static int __init register_pmu_driver(void) -{ - int err = 0; - - err = platform_driver_register(&cpu_pmu_driver); - if (err) - pr_notice("[perf] PMU initialization failed\n"); - else - pr_notice("[perf] PMU initialization done\n"); - - return err; -} - -device_initcall(register_pmu_driver); - -/* - * References: arch/nds32/kernel/traps.c:__dump() - * You will need to know the NDS ABI first. - */ -static int unwind_frame_kernel(struct stackframe *frame) -{ - int graph = 0; -#ifdef CONFIG_FRAME_POINTER - /* 0x3 means misalignment */ - if (!kstack_end((void *)frame->fp) && - !((unsigned long)frame->fp & 0x3) && - ((unsigned long)frame->fp >= TASK_SIZE)) { - /* - * The array index is based on the ABI, the below graph - * illustrate the reasons. - * Function call procedure: "smw" and "lmw" will always - * update SP and FP for you automatically. - * - * Stack Relative Address - * | | 0 - * ---- - * |LP| <-- SP(before smw) <-- FP(after smw) -1 - * ---- - * |FP| -2 - * ---- - * | | <-- SP(after smw) -3 - */ - frame->lp = ((unsigned long *)frame->fp)[-1]; - frame->fp = ((unsigned long *)frame->fp)[FP_OFFSET]; - /* make sure CONFIG_FUNCTION_GRAPH_TRACER is turned on */ - if (__kernel_text_address(frame->lp)) - frame->lp = ftrace_graph_ret_addr - (NULL, &graph, frame->lp, NULL); - - return 0; - } else { - return -EPERM; - } -#else - /* - * You can refer to arch/nds32/kernel/traps.c:__dump() - * Treat "sp" as "fp", but the "sp" is one frame ahead of "fp". - * And, the "sp" is not always correct. - * - * Stack Relative Address - * | | 0 - * ---- - * |LP| <-- SP(before smw) -1 - * ---- - * | | <-- SP(after smw) -2 - * ---- - */ - if (!kstack_end((void *)frame->sp)) { - frame->lp = ((unsigned long *)frame->sp)[1]; - /* TODO: How to deal with the value in first - * "sp" is not correct? - */ - if (__kernel_text_address(frame->lp)) - frame->lp = ftrace_graph_ret_addr - (tsk, &graph, frame->lp, NULL); - - frame->sp = ((unsigned long *)frame->sp) + 1; - - return 0; - } else { - return -EPERM; - } -#endif -} - -static void notrace -walk_stackframe(struct stackframe *frame, - int (*fn_record)(struct stackframe *, void *), - void *data) -{ - while (1) { - int ret; - - if (fn_record(frame, data)) - break; - - ret = unwind_frame_kernel(frame); - if (ret < 0) - break; - } -} - -/* - * Gets called by walk_stackframe() for every stackframe. This will be called - * whist unwinding the stackframe and is like a subroutine return so we use - * the PC. - */ -static int callchain_trace(struct stackframe *fr, void *data) -{ - struct perf_callchain_entry_ctx *entry = data; - - perf_callchain_store(entry, fr->lp); - return 0; -} - -/* - * Get the return address for a single stackframe and return a pointer to the - * next frame tail. - */ -static unsigned long -user_backtrace(struct perf_callchain_entry_ctx *entry, unsigned long fp) -{ - struct frame_tail buftail; - unsigned long lp = 0; - unsigned long *user_frame_tail = - (unsigned long *)(fp - (unsigned long)sizeof(buftail)); - - /* Check accessibility of one struct frame_tail beyond */ - if (!access_ok(user_frame_tail, sizeof(buftail))) - return 0; - if (__copy_from_user_inatomic - (&buftail, user_frame_tail, sizeof(buftail))) - return 0; - - /* - * Refer to unwind_frame_kernel() for more illurstration - */ - lp = buftail.stack_lp; /* ((unsigned long *)fp)[-1] */ - fp = buftail.stack_fp; /* ((unsigned long *)fp)[FP_OFFSET] */ - perf_callchain_store(entry, lp); - return fp; -} - -static unsigned long -user_backtrace_opt_size(struct perf_callchain_entry_ctx *entry, - unsigned long fp) -{ - struct frame_tail_opt_size buftail; - unsigned long lp = 0; - - unsigned long *user_frame_tail = - (unsigned long *)(fp - (unsigned long)sizeof(buftail)); - - /* Check accessibility of one struct frame_tail beyond */ - if (!access_ok(user_frame_tail, sizeof(buftail))) - return 0; - if (__copy_from_user_inatomic - (&buftail, user_frame_tail, sizeof(buftail))) - return 0; - - /* - * Refer to unwind_frame_kernel() for more illurstration - */ - lp = buftail.stack_lp; /* ((unsigned long *)fp)[-1] */ - fp = buftail.stack_fp; /* ((unsigned long *)fp)[FP_OFFSET] */ - - perf_callchain_store(entry, lp); - return fp; -} - -/* - * This will be called when the target is in user mode - * This function will only be called when we use - * "PERF_SAMPLE_CALLCHAIN" in - * kernel/events/core.c:perf_prepare_sample() - * - * How to trigger perf_callchain_[user/kernel] : - * $ perf record -e cpu-clock --call-graph fp ./program - * $ perf report --call-graph - */ -unsigned long leaf_fp; -void -perf_callchain_user(struct perf_callchain_entry_ctx *entry, - struct pt_regs *regs) -{ - unsigned long fp = 0; - unsigned long gp = 0; - unsigned long lp = 0; - unsigned long sp = 0; - unsigned long *user_frame_tail; - - leaf_fp = 0; - - perf_callchain_store(entry, regs->ipc); - fp = regs->fp; - gp = regs->gp; - lp = regs->lp; - sp = regs->sp; - if (entry->nr < PERF_MAX_STACK_DEPTH && - (unsigned long)fp && !((unsigned long)fp & 0x7) && fp > sp) { - user_frame_tail = - (unsigned long *)(fp - (unsigned long)sizeof(fp)); - - if (!access_ok(user_frame_tail, sizeof(fp))) - return; - - if (__copy_from_user_inatomic - (&leaf_fp, user_frame_tail, sizeof(fp))) - return; - - if (leaf_fp == lp) { - /* - * Maybe this is non leaf function - * with optimize for size, - * or maybe this is the function - * with optimize for size - */ - struct frame_tail buftail; - - user_frame_tail = - (unsigned long *)(fp - - (unsigned long)sizeof(buftail)); - - if (!access_ok(user_frame_tail, sizeof(buftail))) - return; - - if (__copy_from_user_inatomic - (&buftail, user_frame_tail, sizeof(buftail))) - return; - - if (buftail.stack_fp == gp) { - /* non leaf function with optimize - * for size condition - */ - struct frame_tail_opt_size buftail_opt_size; - - user_frame_tail = - (unsigned long *)(fp - (unsigned long) - sizeof(buftail_opt_size)); - - if (!access_ok(user_frame_tail, - sizeof(buftail_opt_size))) - return; - - if (__copy_from_user_inatomic - (&buftail_opt_size, user_frame_tail, - sizeof(buftail_opt_size))) - return; - - perf_callchain_store(entry, lp); - fp = buftail_opt_size.stack_fp; - - while ((entry->nr < PERF_MAX_STACK_DEPTH) && - (unsigned long)fp && - !((unsigned long)fp & 0x7) && - fp > sp) { - sp = fp; - fp = user_backtrace_opt_size(entry, fp); - } - - } else { - /* this is the function - * without optimize for size - */ - fp = buftail.stack_fp; - perf_callchain_store(entry, lp); - while ((entry->nr < PERF_MAX_STACK_DEPTH) && - (unsigned long)fp && - !((unsigned long)fp & 0x7) && - fp > sp) { - sp = fp; - fp = user_backtrace(entry, fp); - } - } - } else { - /* this is leaf function */ - fp = leaf_fp; - perf_callchain_store(entry, lp); - - /* previous function callcahin */ - while ((entry->nr < PERF_MAX_STACK_DEPTH) && - (unsigned long)fp && - !((unsigned long)fp & 0x7) && fp > sp) { - sp = fp; - fp = user_backtrace(entry, fp); - } - } - return; - } -} - -/* This will be called when the target is in kernel mode */ -void -perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, - struct pt_regs *regs) -{ - struct stackframe fr; - - fr.fp = regs->fp; - fr.lp = regs->lp; - fr.sp = regs->sp; - walk_stackframe(&fr, callchain_trace, entry); -} - -unsigned long perf_instruction_pointer(struct pt_regs *regs) -{ - return instruction_pointer(regs); -} - -unsigned long perf_misc_flags(struct pt_regs *regs) -{ - int misc = 0; - - if (user_mode(regs)) - misc |= PERF_RECORD_MISC_USER; - else - misc |= PERF_RECORD_MISC_KERNEL; - - return misc; -} diff --git a/arch/nds32/kernel/pm.c b/arch/nds32/kernel/pm.c deleted file mode 100644 index e25700e125d8..000000000000 --- a/arch/nds32/kernel/pm.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2008-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include - -unsigned int resume_addr; -unsigned int *phy_addr_sp_tmp; - -static void nds32_suspend2ram(void) -{ - pgd_t *pgdv; - p4d_t *p4dv; - pud_t *pudv; - pmd_t *pmdv; - pte_t *ptev; - - pgdv = (pgd_t *)__va((__nds32__mfsr(NDS32_SR_L1_PPTB) & - L1_PPTB_mskBASE)) + pgd_index((unsigned int)cpu_resume); - - p4dv = p4d_offset(pgdv, (unsigned int)cpu_resume); - pudv = pud_offset(p4dv, (unsigned int)cpu_resume); - pmdv = pmd_offset(pudv, (unsigned int)cpu_resume); - ptev = pte_offset_map(pmdv, (unsigned int)cpu_resume); - - resume_addr = ((*ptev) & TLB_DATA_mskPPN) - | ((unsigned int)cpu_resume & 0x00000fff); - - suspend2ram(); -} - -static void nds32_suspend_cpu(void) -{ - while (!(__nds32__mfsr(NDS32_SR_INT_PEND) & wake_mask)) - __asm__ volatile ("standby no_wake_grant\n\t"); -} - -static int nds32_pm_valid(suspend_state_t state) -{ - switch (state) { - case PM_SUSPEND_ON: - case PM_SUSPEND_STANDBY: - case PM_SUSPEND_MEM: - return 1; - default: - return 0; - } -} - -static int nds32_pm_enter(suspend_state_t state) -{ - pr_debug("%s:state:%d\n", __func__, state); - switch (state) { - case PM_SUSPEND_STANDBY: - nds32_suspend_cpu(); - return 0; - case PM_SUSPEND_MEM: - nds32_suspend2ram(); - return 0; - default: - return -EINVAL; - } -} - -static const struct platform_suspend_ops nds32_pm_ops = { - .valid = nds32_pm_valid, - .enter = nds32_pm_enter, -}; - -static int __init nds32_pm_init(void) -{ - pr_debug("Enter %s\n", __func__); - suspend_set_ops(&nds32_pm_ops); - return 0; -} -late_initcall(nds32_pm_init); diff --git a/arch/nds32/kernel/process.c b/arch/nds32/kernel/process.c deleted file mode 100644 index 49fab9e39cbf..000000000000 --- a/arch/nds32/kernel/process.c +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if IS_ENABLED(CONFIG_LAZY_FPU) -struct task_struct *last_task_used_math; -#endif - -extern void setup_mm_for_reboot(char mode); - -extern inline void arch_reset(char mode) -{ - if (mode == 's') { - /* Use cpu handler, jump to 0 */ - cpu_reset(0); - } -} - -void (*pm_power_off) (void); -EXPORT_SYMBOL(pm_power_off); - -static char reboot_mode_nds32 = 'h'; - -int __init reboot_setup(char *str) -{ - reboot_mode_nds32 = str[0]; - return 1; -} - -static int cpub_pwroff(void) -{ - return 0; -} - -__setup("reboot=", reboot_setup); - -void machine_halt(void) -{ - cpub_pwroff(); -} - -EXPORT_SYMBOL(machine_halt); - -void machine_power_off(void) -{ - if (pm_power_off) - pm_power_off(); -} - -EXPORT_SYMBOL(machine_power_off); - -void machine_restart(char *cmd) -{ - /* - * Clean and disable cache, and turn off interrupts - */ - cpu_proc_fin(); - - /* - * Tell the mm system that we are going to reboot - - * we may need it to insert some 1:1 mappings so that - * soft boot works. - */ - setup_mm_for_reboot(reboot_mode_nds32); - - /* Execute kernel restart handler call chain */ - do_kernel_restart(cmd); - - /* - * Now call the architecture specific reboot code. - */ - arch_reset(reboot_mode_nds32); - - /* - * Whoops - the architecture was unable to reboot. - * Tell the user! - */ - mdelay(1000); - pr_info("Reboot failed -- System halted\n"); - while (1) ; -} - -EXPORT_SYMBOL(machine_restart); - -void show_regs(struct pt_regs *regs) -{ - printk("PC is at %pS\n", (void *)instruction_pointer(regs)); - printk("LP is at %pS\n", (void *)regs->lp); - pr_info("pc : [<%08lx>] lp : [<%08lx>] %s\n" - "sp : %08lx fp : %08lx gp : %08lx\n", - instruction_pointer(regs), - regs->lp, print_tainted(), regs->sp, regs->fp, regs->gp); - pr_info("r25: %08lx r24: %08lx\n", regs->uregs[25], regs->uregs[24]); - - pr_info("r23: %08lx r22: %08lx r21: %08lx r20: %08lx\n", - regs->uregs[23], regs->uregs[22], - regs->uregs[21], regs->uregs[20]); - pr_info("r19: %08lx r18: %08lx r17: %08lx r16: %08lx\n", - regs->uregs[19], regs->uregs[18], - regs->uregs[17], regs->uregs[16]); - pr_info("r15: %08lx r14: %08lx r13: %08lx r12: %08lx\n", - regs->uregs[15], regs->uregs[14], - regs->uregs[13], regs->uregs[12]); - pr_info("r11: %08lx r10: %08lx r9 : %08lx r8 : %08lx\n", - regs->uregs[11], regs->uregs[10], - regs->uregs[9], regs->uregs[8]); - pr_info("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", - regs->uregs[7], regs->uregs[6], regs->uregs[5], regs->uregs[4]); - pr_info("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", - regs->uregs[3], regs->uregs[2], regs->uregs[1], regs->uregs[0]); - pr_info(" IRQs o%s Segment %s\n", - interrupts_enabled(regs) ? "n" : "ff", - uaccess_kernel() ? "kernel" : "user"); -} - -EXPORT_SYMBOL(show_regs); - -void exit_thread(struct task_struct *tsk) -{ -#if defined(CONFIG_FPU) && defined(CONFIG_LAZY_FPU) - if (last_task_used_math == tsk) - last_task_used_math = NULL; -#endif -} - -void flush_thread(void) -{ -#if defined(CONFIG_FPU) - clear_fpu(task_pt_regs(current)); - clear_used_math(); -# ifdef CONFIG_LAZY_FPU - if (last_task_used_math == current) - last_task_used_math = NULL; -# endif -#endif -} - -DEFINE_PER_CPU(struct task_struct *, __entry_task); - -asmlinkage void ret_from_fork(void) __asm__("ret_from_fork"); -int copy_thread(unsigned long clone_flags, unsigned long stack_start, - unsigned long stk_sz, struct task_struct *p, unsigned long tls) -{ - struct pt_regs *childregs = task_pt_regs(p); - - memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context)); - - if (unlikely(p->flags & (PF_KTHREAD | PF_IO_WORKER))) { - memset(childregs, 0, sizeof(struct pt_regs)); - /* kernel thread fn */ - p->thread.cpu_context.r6 = stack_start; - /* kernel thread argument */ - p->thread.cpu_context.r7 = stk_sz; - } else { - *childregs = *current_pt_regs(); - if (stack_start) - childregs->sp = stack_start; - /* child get zero as ret. */ - childregs->uregs[0] = 0; - childregs->osp = 0; - if (clone_flags & CLONE_SETTLS) - childregs->uregs[25] = tls; - } - /* cpu context switching */ - p->thread.cpu_context.pc = (unsigned long)ret_from_fork; - p->thread.cpu_context.sp = (unsigned long)childregs; - -#if IS_ENABLED(CONFIG_FPU) - if (used_math()) { -# if !IS_ENABLED(CONFIG_LAZY_FPU) - unlazy_fpu(current); -# else - preempt_disable(); - if (last_task_used_math == current) - save_fpu(current); - preempt_enable(); -# endif - p->thread.fpu = current->thread.fpu; - clear_fpu(task_pt_regs(p)); - set_stopped_child_used_math(p); - } -#endif - -#ifdef CONFIG_HWZOL - childregs->lb = 0; - childregs->le = 0; - childregs->lc = 0; -#endif - - return 0; -} - -#if IS_ENABLED(CONFIG_FPU) -struct task_struct *_switch_fpu(struct task_struct *prev, struct task_struct *next) -{ -#if !IS_ENABLED(CONFIG_LAZY_FPU) - unlazy_fpu(prev); -#endif - if (!(next->flags & PF_KTHREAD)) - clear_fpu(task_pt_regs(next)); - return prev; -} -#endif - -/* - * fill in the fpe structure for a core dump... - */ -int dump_fpu(struct pt_regs *regs, elf_fpregset_t * fpu) -{ - int fpvalid = 0; -#if IS_ENABLED(CONFIG_FPU) - struct task_struct *tsk = current; - - fpvalid = tsk_used_math(tsk); - if (fpvalid) { - lose_fpu(); - memcpy(fpu, &tsk->thread.fpu, sizeof(*fpu)); - } -#endif - return fpvalid; -} - -EXPORT_SYMBOL(dump_fpu); - -unsigned long __get_wchan(struct task_struct *p) -{ - unsigned long fp, lr; - unsigned long stack_start, stack_end; - int count = 0; - - if (IS_ENABLED(CONFIG_FRAME_POINTER)) { - stack_start = (unsigned long)end_of_stack(p); - stack_end = (unsigned long)task_stack_page(p) + THREAD_SIZE; - - fp = thread_saved_fp(p); - do { - if (fp < stack_start || fp > stack_end) - return 0; - lr = ((unsigned long *)fp)[0]; - if (!in_sched_functions(lr)) - return lr; - fp = *(unsigned long *)(fp + 4); - } while (count++ < 16); - } - return 0; -} diff --git a/arch/nds32/kernel/ptrace.c b/arch/nds32/kernel/ptrace.c deleted file mode 100644 index d0eda870fbc2..000000000000 --- a/arch/nds32/kernel/ptrace.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include - -enum nds32_regset { - REGSET_GPR, -}; - -static int gpr_get(struct task_struct *target, - const struct user_regset *regset, - struct membuf to) -{ - return membuf_write(&to, &task_pt_regs(target)->user_regs, - sizeof(struct user_pt_regs)); -} - -static int gpr_set(struct task_struct *target, const struct user_regset *regset, - unsigned int pos, unsigned int count, - const void *kbuf, const void __user * ubuf) -{ - int err; - struct user_pt_regs newregs = task_pt_regs(target)->user_regs; - - err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &newregs, 0, -1); - if (err) - return err; - - task_pt_regs(target)->user_regs = newregs; - return 0; -} - -static const struct user_regset nds32_regsets[] = { - [REGSET_GPR] = { - .core_note_type = NT_PRSTATUS, - .n = sizeof(struct user_pt_regs) / sizeof(u32), - .size = sizeof(elf_greg_t), - .align = sizeof(elf_greg_t), - .regset_get = gpr_get, - .set = gpr_set} -}; - -static const struct user_regset_view nds32_user_view = { - .name = "nds32", - .e_machine = EM_NDS32, - .regsets = nds32_regsets, - .n = ARRAY_SIZE(nds32_regsets) -}; - -const struct user_regset_view *task_user_regset_view(struct task_struct *task) -{ - return &nds32_user_view; -} - -void ptrace_disable(struct task_struct *child) -{ - user_disable_single_step(child); -} - -/* do_ptrace() - * - * Provide ptrace defined service. - */ -long arch_ptrace(struct task_struct *child, long request, unsigned long addr, - unsigned long data) -{ - int ret = -EIO; - - switch (request) { - default: - ret = ptrace_request(child, request, addr, data); - break; - } - - return ret; -} - -void user_enable_single_step(struct task_struct *child) -{ - struct pt_regs *regs; - regs = task_pt_regs(child); - regs->ipsw |= PSW_mskHSS; - set_tsk_thread_flag(child, TIF_SINGLESTEP); -} - -void user_disable_single_step(struct task_struct *child) -{ - struct pt_regs *regs; - regs = task_pt_regs(child); - regs->ipsw &= ~PSW_mskHSS; - clear_tsk_thread_flag(child, TIF_SINGLESTEP); -} - -/* sys_trace() - * - * syscall trace handler. - */ - -asmlinkage int syscall_trace_enter(struct pt_regs *regs) -{ - if (test_thread_flag(TIF_SYSCALL_TRACE)) { - if (tracehook_report_syscall_entry(regs)) - forget_syscall(regs); - } - return regs->syscallno; -} - -asmlinkage void syscall_trace_leave(struct pt_regs *regs) -{ - int step = test_thread_flag(TIF_SINGLESTEP); - if (step || test_thread_flag(TIF_SYSCALL_TRACE)) - tracehook_report_syscall_exit(regs, step); - -} diff --git a/arch/nds32/kernel/setup.c b/arch/nds32/kernel/setup.c deleted file mode 100644 index b3d34d646652..000000000000 --- a/arch/nds32/kernel/setup.c +++ /dev/null @@ -1,369 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define HWCAP_MFUSR_PC 0x000001 -#define HWCAP_EXT 0x000002 -#define HWCAP_EXT2 0x000004 -#define HWCAP_FPU 0x000008 -#define HWCAP_AUDIO 0x000010 -#define HWCAP_BASE16 0x000020 -#define HWCAP_STRING 0x000040 -#define HWCAP_REDUCED_REGS 0x000080 -#define HWCAP_VIDEO 0x000100 -#define HWCAP_ENCRYPT 0x000200 -#define HWCAP_EDM 0x000400 -#define HWCAP_LMDMA 0x000800 -#define HWCAP_PFM 0x001000 -#define HWCAP_HSMP 0x002000 -#define HWCAP_TRACE 0x004000 -#define HWCAP_DIV 0x008000 -#define HWCAP_MAC 0x010000 -#define HWCAP_L2C 0x020000 -#define HWCAP_FPU_DP 0x040000 -#define HWCAP_V2 0x080000 -#define HWCAP_DX_REGS 0x100000 -#define HWCAP_HWPRE 0x200000 - -unsigned long cpu_id, cpu_rev, cpu_cfgid; -bool has_fpu = false; -char cpu_series; -char *endianness = NULL; - -unsigned int __atags_pointer __initdata; -unsigned int elf_hwcap; -EXPORT_SYMBOL(elf_hwcap); - -/* - * The following string table, must sync with HWCAP_xx bitmask, - * which is defined above - */ -static const char *hwcap_str[] = { - "mfusr_pc", - "perf1", - "perf2", - "fpu", - "audio", - "16b", - "string", - "reduced_regs", - "video", - "encrypt", - "edm", - "lmdma", - "pfm", - "hsmp", - "trace", - "div", - "mac", - "l2c", - "fpu_dp", - "v2", - "dx_regs", - "hw_pre", - NULL, -}; - -#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH -#define WRITE_METHOD "write through" -#else -#define WRITE_METHOD "write back" -#endif - -struct cache_info L1_cache_info[2]; -static void __init dump_cpu_info(int cpu) -{ - int i, p = 0; - char str[sizeof(hwcap_str) + 16]; - - for (i = 0; hwcap_str[i]; i++) { - if (elf_hwcap & (1 << i)) { - sprintf(str + p, "%s ", hwcap_str[i]); - p += strlen(hwcap_str[i]) + 1; - } - } - - pr_info("CPU%d Features: %s\n", cpu, str); - - L1_cache_info[ICACHE].ways = CACHE_WAY(ICACHE); - L1_cache_info[ICACHE].line_size = CACHE_LINE_SIZE(ICACHE); - L1_cache_info[ICACHE].sets = CACHE_SET(ICACHE); - L1_cache_info[ICACHE].size = - L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].line_size * - L1_cache_info[ICACHE].sets / 1024; - pr_info("L1I:%dKB/%dS/%dW/%dB\n", L1_cache_info[ICACHE].size, - L1_cache_info[ICACHE].sets, L1_cache_info[ICACHE].ways, - L1_cache_info[ICACHE].line_size); - L1_cache_info[DCACHE].ways = CACHE_WAY(DCACHE); - L1_cache_info[DCACHE].line_size = CACHE_LINE_SIZE(DCACHE); - L1_cache_info[DCACHE].sets = CACHE_SET(DCACHE); - L1_cache_info[DCACHE].size = - L1_cache_info[DCACHE].ways * L1_cache_info[DCACHE].line_size * - L1_cache_info[DCACHE].sets / 1024; - pr_info("L1D:%dKB/%dS/%dW/%dB\n", L1_cache_info[DCACHE].size, - L1_cache_info[DCACHE].sets, L1_cache_info[DCACHE].ways, - L1_cache_info[DCACHE].line_size); - pr_info("L1 D-Cache is %s\n", WRITE_METHOD); - if (L1_cache_info[DCACHE].size != L1_CACHE_BYTES) - pr_crit - ("The cache line size(%d) of this processor is not the same as L1_CACHE_BYTES(%d).\n", - L1_cache_info[DCACHE].size, L1_CACHE_BYTES); -#ifdef CONFIG_CPU_CACHE_ALIASING - { - int aliasing_num; - aliasing_num = - L1_cache_info[ICACHE].size * 1024 / PAGE_SIZE / - L1_cache_info[ICACHE].ways; - L1_cache_info[ICACHE].aliasing_num = aliasing_num; - L1_cache_info[ICACHE].aliasing_mask = - (aliasing_num - 1) << PAGE_SHIFT; - aliasing_num = - L1_cache_info[DCACHE].size * 1024 / PAGE_SIZE / - L1_cache_info[DCACHE].ways; - L1_cache_info[DCACHE].aliasing_num = aliasing_num; - L1_cache_info[DCACHE].aliasing_mask = - (aliasing_num - 1) << PAGE_SHIFT; - } -#endif -#ifdef CONFIG_FPU - /* Disable fpu and enable when it is used. */ - if (has_fpu) - disable_fpu(); -#endif -} - -static void __init setup_cpuinfo(void) -{ - unsigned long tmp = 0, cpu_name; - - cpu_dcache_inval_all(); - cpu_icache_inval_all(); - __nds32__isb(); - - cpu_id = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCPUID) >> CPU_VER_offCPUID; - cpu_name = ((cpu_id) & 0xf0) >> 4; - cpu_series = cpu_name ? cpu_name - 10 + 'A' : 'N'; - cpu_id = cpu_id & 0xf; - cpu_rev = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskREV) >> CPU_VER_offREV; - cpu_cfgid = (__nds32__mfsr(NDS32_SR_CPU_VER) & CPU_VER_mskCFGID) >> CPU_VER_offCFGID; - - pr_info("CPU:%c%ld, CPU_VER 0x%08x(id %lu, rev %lu, cfg %lu)\n", - cpu_series, cpu_id, __nds32__mfsr(NDS32_SR_CPU_VER), cpu_id, cpu_rev, cpu_cfgid); - - elf_hwcap |= HWCAP_MFUSR_PC; - - if (((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskBASEV) >> MSC_CFG_offBASEV) == 0) { - if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskDIV) - elf_hwcap |= HWCAP_DIV; - - if ((__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskMAC) - || (cpu_id == 12 && cpu_rev < 4)) - elf_hwcap |= HWCAP_MAC; - } else { - elf_hwcap |= HWCAP_V2; - elf_hwcap |= HWCAP_DIV; - elf_hwcap |= HWCAP_MAC; - } - - if (cpu_cfgid & 0x0001) - elf_hwcap |= HWCAP_EXT; - - if (cpu_cfgid & 0x0002) - elf_hwcap |= HWCAP_BASE16; - - if (cpu_cfgid & 0x0004) - elf_hwcap |= HWCAP_EXT2; - - if (cpu_cfgid & 0x0008) { - elf_hwcap |= HWCAP_FPU; - has_fpu = true; - } - if (cpu_cfgid & 0x0010) - elf_hwcap |= HWCAP_STRING; - - if (__nds32__mfsr(NDS32_SR_MMU_CFG) & MMU_CFG_mskDE) - endianness = "MSB"; - else - endianness = "LSB"; - - if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskEDM) - elf_hwcap |= HWCAP_EDM; - - if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskLMDMA) - elf_hwcap |= HWCAP_LMDMA; - - if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskPFM) - elf_hwcap |= HWCAP_PFM; - - if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskHSMP) - elf_hwcap |= HWCAP_HSMP; - - if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskTRACE) - elf_hwcap |= HWCAP_TRACE; - - if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskAUDIO) - elf_hwcap |= HWCAP_AUDIO; - - if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C) - elf_hwcap |= HWCAP_L2C; - -#ifdef CONFIG_HW_PRE - if (__nds32__mfsr(NDS32_SR_MISC_CTL) & MISC_CTL_makHWPRE_EN) - elf_hwcap |= HWCAP_HWPRE; -#endif - - tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL); - if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE)) - tmp |= CACHE_CTL_mskDC_EN; - - if (!IS_ENABLED(CONFIG_CPU_ICACHE_DISABLE)) - tmp |= CACHE_CTL_mskIC_EN; - __nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL); - - dump_cpu_info(smp_processor_id()); -} - -static void __init setup_memory(void) -{ - unsigned long ram_start_pfn; - unsigned long free_ram_start_pfn; - phys_addr_t memory_start, memory_end; - - memory_end = memory_start = 0; - - /* Find main memory where is the kernel */ - memory_start = memblock_start_of_DRAM(); - memory_end = memblock_end_of_DRAM(); - - if (!memory_end) { - panic("No memory!"); - } - - ram_start_pfn = PFN_UP(memblock_start_of_DRAM()); - /* free_ram_start_pfn is first page after kernel */ - free_ram_start_pfn = PFN_UP(__pa(&_end)); - max_pfn = PFN_DOWN(memblock_end_of_DRAM()); - /* it could update max_pfn */ - if (max_pfn - ram_start_pfn <= MAXMEM_PFN) - max_low_pfn = max_pfn; - else { - max_low_pfn = MAXMEM_PFN + ram_start_pfn; - if (!IS_ENABLED(CONFIG_HIGHMEM)) - max_pfn = MAXMEM_PFN + ram_start_pfn; - } - /* high_memory is related with VMALLOC */ - high_memory = (void *)__va(max_low_pfn * PAGE_SIZE); - min_low_pfn = free_ram_start_pfn; - - /* - * initialize the boot-time allocator (with low memory only). - * - * This makes the memory from the end of the kernel to the end of - * RAM usable. - */ - memblock_set_bottom_up(true); - memblock_reserve(PFN_PHYS(ram_start_pfn), PFN_PHYS(free_ram_start_pfn - ram_start_pfn)); - - early_init_fdt_reserve_self(); - early_init_fdt_scan_reserved_mem(); - - memblock_dump_all(); -} - -void __init setup_arch(char **cmdline_p) -{ - early_init_devtree(__atags_pointer ? \ - phys_to_virt(__atags_pointer) : __dtb_start); - - setup_cpuinfo(); - - setup_initial_init_mm(_stext, _etext, _edata, _end); - - /* setup bootmem allocator */ - setup_memory(); - - /* paging_init() sets up the MMU and marks all pages as reserved */ - paging_init(); - - /* invalidate all TLB entries because the new mapping is created */ - __nds32__tlbop_flua(); - - /* use generic way to parse */ - parse_early_param(); - - unflatten_and_copy_device_tree(); - - *cmdline_p = boot_command_line; - early_trap_init(); -} - -static int c_show(struct seq_file *m, void *v) -{ - int i; - - seq_printf(m, "Processor\t: %c%ld (id %lu, rev %lu, cfg %lu)\n", - cpu_series, cpu_id, cpu_id, cpu_rev, cpu_cfgid); - - seq_printf(m, "L1I\t\t: %luKB/%luS/%luW/%luB\n", - CACHE_SET(ICACHE) * CACHE_WAY(ICACHE) * - CACHE_LINE_SIZE(ICACHE) / 1024, CACHE_SET(ICACHE), - CACHE_WAY(ICACHE), CACHE_LINE_SIZE(ICACHE)); - - seq_printf(m, "L1D\t\t: %luKB/%luS/%luW/%luB\n", - CACHE_SET(DCACHE) * CACHE_WAY(DCACHE) * - CACHE_LINE_SIZE(DCACHE) / 1024, CACHE_SET(DCACHE), - CACHE_WAY(DCACHE), CACHE_LINE_SIZE(DCACHE)); - - seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", - loops_per_jiffy / (500000 / HZ), - (loops_per_jiffy / (5000 / HZ)) % 100); - - /* dump out the processor features */ - seq_puts(m, "Features\t: "); - - for (i = 0; hwcap_str[i]; i++) - if (elf_hwcap & (1 << i)) - seq_printf(m, "%s ", hwcap_str[i]); - - seq_puts(m, "\n\n"); - - return 0; -} - -static void *c_start(struct seq_file *m, loff_t * pos) -{ - return *pos < 1 ? (void *)1 : NULL; -} - -static void *c_next(struct seq_file *m, void *v, loff_t * pos) -{ - ++*pos; - return NULL; -} - -static void c_stop(struct seq_file *m, void *v) -{ -} - -struct seq_operations cpuinfo_op = { - .start = c_start, - .next = c_next, - .stop = c_stop, - .show = c_show -}; diff --git a/arch/nds32/kernel/signal.c b/arch/nds32/kernel/signal.c deleted file mode 100644 index 7e3ca430a223..000000000000 --- a/arch/nds32/kernel/signal.c +++ /dev/null @@ -1,384 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -struct rt_sigframe { - struct siginfo info; - struct ucontext uc; -}; -#if IS_ENABLED(CONFIG_FPU) -static inline int restore_sigcontext_fpu(struct pt_regs *regs, - struct sigcontext __user *sc) -{ - struct task_struct *tsk = current; - unsigned long used_math_flag; - int ret = 0; - - clear_used_math(); - __get_user_error(used_math_flag, &sc->used_math_flag, ret); - - if (!used_math_flag) - return 0; - set_used_math(); - -#if IS_ENABLED(CONFIG_LAZY_FPU) - preempt_disable(); - if (current == last_task_used_math) { - last_task_used_math = NULL; - disable_ptreg_fpu(regs); - } - preempt_enable(); -#else - clear_fpu(regs); -#endif - - return __copy_from_user(&tsk->thread.fpu, &sc->fpu, - sizeof(struct fpu_struct)); -} - -static inline int setup_sigcontext_fpu(struct pt_regs *regs, - struct sigcontext __user *sc) -{ - struct task_struct *tsk = current; - int ret = 0; - - __put_user_error(used_math(), &sc->used_math_flag, ret); - - if (!used_math()) - return ret; - - preempt_disable(); -#if IS_ENABLED(CONFIG_LAZY_FPU) - if (last_task_used_math == tsk) - save_fpu(last_task_used_math); -#else - unlazy_fpu(tsk); -#endif - ret = __copy_to_user(&sc->fpu, &tsk->thread.fpu, - sizeof(struct fpu_struct)); - preempt_enable(); - return ret; -} -#endif - -static int restore_sigframe(struct pt_regs *regs, - struct rt_sigframe __user * sf) -{ - sigset_t set; - int err; - - err = __copy_from_user(&set, &sf->uc.uc_sigmask, sizeof(set)); - if (err == 0) { - set_current_blocked(&set); - } - - __get_user_error(regs->uregs[0], &sf->uc.uc_mcontext.nds32_r0, err); - __get_user_error(regs->uregs[1], &sf->uc.uc_mcontext.nds32_r1, err); - __get_user_error(regs->uregs[2], &sf->uc.uc_mcontext.nds32_r2, err); - __get_user_error(regs->uregs[3], &sf->uc.uc_mcontext.nds32_r3, err); - __get_user_error(regs->uregs[4], &sf->uc.uc_mcontext.nds32_r4, err); - __get_user_error(regs->uregs[5], &sf->uc.uc_mcontext.nds32_r5, err); - __get_user_error(regs->uregs[6], &sf->uc.uc_mcontext.nds32_r6, err); - __get_user_error(regs->uregs[7], &sf->uc.uc_mcontext.nds32_r7, err); - __get_user_error(regs->uregs[8], &sf->uc.uc_mcontext.nds32_r8, err); - __get_user_error(regs->uregs[9], &sf->uc.uc_mcontext.nds32_r9, err); - __get_user_error(regs->uregs[10], &sf->uc.uc_mcontext.nds32_r10, err); - __get_user_error(regs->uregs[11], &sf->uc.uc_mcontext.nds32_r11, err); - __get_user_error(regs->uregs[12], &sf->uc.uc_mcontext.nds32_r12, err); - __get_user_error(regs->uregs[13], &sf->uc.uc_mcontext.nds32_r13, err); - __get_user_error(regs->uregs[14], &sf->uc.uc_mcontext.nds32_r14, err); - __get_user_error(regs->uregs[15], &sf->uc.uc_mcontext.nds32_r15, err); - __get_user_error(regs->uregs[16], &sf->uc.uc_mcontext.nds32_r16, err); - __get_user_error(regs->uregs[17], &sf->uc.uc_mcontext.nds32_r17, err); - __get_user_error(regs->uregs[18], &sf->uc.uc_mcontext.nds32_r18, err); - __get_user_error(regs->uregs[19], &sf->uc.uc_mcontext.nds32_r19, err); - __get_user_error(regs->uregs[20], &sf->uc.uc_mcontext.nds32_r20, err); - __get_user_error(regs->uregs[21], &sf->uc.uc_mcontext.nds32_r21, err); - __get_user_error(regs->uregs[22], &sf->uc.uc_mcontext.nds32_r22, err); - __get_user_error(regs->uregs[23], &sf->uc.uc_mcontext.nds32_r23, err); - __get_user_error(regs->uregs[24], &sf->uc.uc_mcontext.nds32_r24, err); - __get_user_error(regs->uregs[25], &sf->uc.uc_mcontext.nds32_r25, err); - - __get_user_error(regs->fp, &sf->uc.uc_mcontext.nds32_fp, err); - __get_user_error(regs->gp, &sf->uc.uc_mcontext.nds32_gp, err); - __get_user_error(regs->lp, &sf->uc.uc_mcontext.nds32_lp, err); - __get_user_error(regs->sp, &sf->uc.uc_mcontext.nds32_sp, err); - __get_user_error(regs->ipc, &sf->uc.uc_mcontext.nds32_ipc, err); -#if defined(CONFIG_HWZOL) - __get_user_error(regs->lc, &sf->uc.uc_mcontext.zol.nds32_lc, err); - __get_user_error(regs->le, &sf->uc.uc_mcontext.zol.nds32_le, err); - __get_user_error(regs->lb, &sf->uc.uc_mcontext.zol.nds32_lb, err); -#endif -#if IS_ENABLED(CONFIG_FPU) - err |= restore_sigcontext_fpu(regs, &sf->uc.uc_mcontext); -#endif - /* - * Avoid sys_rt_sigreturn() restarting. - */ - forget_syscall(regs); - return err; -} - -asmlinkage long sys_rt_sigreturn(struct pt_regs *regs) -{ - struct rt_sigframe __user *frame; - - /* Always make any pending restarted system calls return -EINTR */ - current->restart_block.fn = do_no_restart_syscall; - - /* - * Since we stacked the signal on a 64-bit boundary, - * then 'sp' should be two-word aligned here. If it's - * not, then the user is trying to mess with us. - */ - if (regs->sp & 7) - goto badframe; - - frame = (struct rt_sigframe __user *)regs->sp; - - if (!access_ok(frame, sizeof(*frame))) - goto badframe; - - if (restore_sigframe(regs, frame)) - goto badframe; - - if (restore_altstack(&frame->uc.uc_stack)) - goto badframe; - - return regs->uregs[0]; - -badframe: - force_sig(SIGSEGV); - return 0; -} - -static int -setup_sigframe(struct rt_sigframe __user * sf, struct pt_regs *regs, - sigset_t * set) -{ - int err = 0; - - __put_user_error(regs->uregs[0], &sf->uc.uc_mcontext.nds32_r0, err); - __put_user_error(regs->uregs[1], &sf->uc.uc_mcontext.nds32_r1, err); - __put_user_error(regs->uregs[2], &sf->uc.uc_mcontext.nds32_r2, err); - __put_user_error(regs->uregs[3], &sf->uc.uc_mcontext.nds32_r3, err); - __put_user_error(regs->uregs[4], &sf->uc.uc_mcontext.nds32_r4, err); - __put_user_error(regs->uregs[5], &sf->uc.uc_mcontext.nds32_r5, err); - __put_user_error(regs->uregs[6], &sf->uc.uc_mcontext.nds32_r6, err); - __put_user_error(regs->uregs[7], &sf->uc.uc_mcontext.nds32_r7, err); - __put_user_error(regs->uregs[8], &sf->uc.uc_mcontext.nds32_r8, err); - __put_user_error(regs->uregs[9], &sf->uc.uc_mcontext.nds32_r9, err); - __put_user_error(regs->uregs[10], &sf->uc.uc_mcontext.nds32_r10, err); - __put_user_error(regs->uregs[11], &sf->uc.uc_mcontext.nds32_r11, err); - __put_user_error(regs->uregs[12], &sf->uc.uc_mcontext.nds32_r12, err); - __put_user_error(regs->uregs[13], &sf->uc.uc_mcontext.nds32_r13, err); - __put_user_error(regs->uregs[14], &sf->uc.uc_mcontext.nds32_r14, err); - __put_user_error(regs->uregs[15], &sf->uc.uc_mcontext.nds32_r15, err); - __put_user_error(regs->uregs[16], &sf->uc.uc_mcontext.nds32_r16, err); - __put_user_error(regs->uregs[17], &sf->uc.uc_mcontext.nds32_r17, err); - __put_user_error(regs->uregs[18], &sf->uc.uc_mcontext.nds32_r18, err); - __put_user_error(regs->uregs[19], &sf->uc.uc_mcontext.nds32_r19, err); - __put_user_error(regs->uregs[20], &sf->uc.uc_mcontext.nds32_r20, err); - - __put_user_error(regs->uregs[21], &sf->uc.uc_mcontext.nds32_r21, err); - __put_user_error(regs->uregs[22], &sf->uc.uc_mcontext.nds32_r22, err); - __put_user_error(regs->uregs[23], &sf->uc.uc_mcontext.nds32_r23, err); - __put_user_error(regs->uregs[24], &sf->uc.uc_mcontext.nds32_r24, err); - __put_user_error(regs->uregs[25], &sf->uc.uc_mcontext.nds32_r25, err); - __put_user_error(regs->fp, &sf->uc.uc_mcontext.nds32_fp, err); - __put_user_error(regs->gp, &sf->uc.uc_mcontext.nds32_gp, err); - __put_user_error(regs->lp, &sf->uc.uc_mcontext.nds32_lp, err); - __put_user_error(regs->sp, &sf->uc.uc_mcontext.nds32_sp, err); - __put_user_error(regs->ipc, &sf->uc.uc_mcontext.nds32_ipc, err); -#if defined(CONFIG_HWZOL) - __put_user_error(regs->lc, &sf->uc.uc_mcontext.zol.nds32_lc, err); - __put_user_error(regs->le, &sf->uc.uc_mcontext.zol.nds32_le, err); - __put_user_error(regs->lb, &sf->uc.uc_mcontext.zol.nds32_lb, err); -#endif -#if IS_ENABLED(CONFIG_FPU) - err |= setup_sigcontext_fpu(regs, &sf->uc.uc_mcontext); -#endif - - __put_user_error(current->thread.trap_no, &sf->uc.uc_mcontext.trap_no, - err); - __put_user_error(current->thread.error_code, - &sf->uc.uc_mcontext.error_code, err); - __put_user_error(current->thread.address, - &sf->uc.uc_mcontext.fault_address, err); - __put_user_error(set->sig[0], &sf->uc.uc_mcontext.oldmask, err); - - err |= __copy_to_user(&sf->uc.uc_sigmask, set, sizeof(*set)); - - return err; -} - -static inline void __user *get_sigframe(struct ksignal *ksig, - struct pt_regs *regs, int framesize) -{ - unsigned long sp; - - /* Default to using normal stack */ - sp = regs->sp; - - /* - * If we are on the alternate signal stack and would overflow it, don't. - * Return an always-bogus address instead so we will die with SIGSEGV. - */ - if (on_sig_stack(sp) && !likely(on_sig_stack(sp - framesize))) - return (void __user __force *)(-1UL); - - /* This is the X/Open sanctioned signal stack switching. */ - sp = (sigsp(sp, ksig) - framesize); - - /* - * nds32 mandates 8-byte alignment - */ - sp &= ~0x7UL; - - return (void __user *)sp; -} - -static int -setup_return(struct pt_regs *regs, struct ksignal *ksig, void __user * frame) -{ - unsigned long handler = (unsigned long)ksig->ka.sa.sa_handler; - unsigned long retcode; - - retcode = VDSO_SYMBOL(current->mm->context.vdso, rt_sigtramp); - regs->uregs[0] = ksig->sig; - regs->sp = (unsigned long)frame; - regs->lp = retcode; - regs->ipc = handler; - - return 0; -} - -static int -setup_rt_frame(struct ksignal *ksig, sigset_t * set, struct pt_regs *regs) -{ - struct rt_sigframe __user *frame = - get_sigframe(ksig, regs, sizeof(*frame)); - int err = 0; - - if (!access_ok(frame, sizeof(*frame))) - return -EFAULT; - - __put_user_error(0, &frame->uc.uc_flags, err); - __put_user_error(NULL, &frame->uc.uc_link, err); - - err |= __save_altstack(&frame->uc.uc_stack, regs->sp); - err |= setup_sigframe(frame, regs, set); - if (err == 0) { - setup_return(regs, ksig, frame); - if (ksig->ka.sa.sa_flags & SA_SIGINFO) { - err |= copy_siginfo_to_user(&frame->info, &ksig->info); - regs->uregs[1] = (unsigned long)&frame->info; - regs->uregs[2] = (unsigned long)&frame->uc; - } - } - return err; -} - -/* - * OK, we're invoking a handler - */ -static void handle_signal(struct ksignal *ksig, struct pt_regs *regs) -{ - int ret; - sigset_t *oldset = sigmask_to_save(); - - if (in_syscall(regs)) { - /* Avoid additional syscall restarting via ret_slow_syscall. */ - forget_syscall(regs); - - switch (regs->uregs[0]) { - case -ERESTART_RESTARTBLOCK: - case -ERESTARTNOHAND: - regs->uregs[0] = -EINTR; - break; - case -ERESTARTSYS: - if (!(ksig->ka.sa.sa_flags & SA_RESTART)) { - regs->uregs[0] = -EINTR; - break; - } - fallthrough; - case -ERESTARTNOINTR: - regs->uregs[0] = regs->orig_r0; - regs->ipc -= 4; - break; - } - } - /* - * Set up the stack frame - */ - ret = setup_rt_frame(ksig, oldset, regs); - - signal_setup_done(ret, ksig, 0); -} - -/* - * Note that 'init' is a special process: it doesn't get signals it doesn't - * want to handle. Thus you cannot kill init even with a SIGKILL even by - * mistake. - * - * Note that we go through the signals twice: once to check the signals that - * the kernel can handle, and then we build all the user-level signal handling - * stack-frames in one go after that. - */ -static void do_signal(struct pt_regs *regs) -{ - struct ksignal ksig; - - if (get_signal(&ksig)) { - handle_signal(&ksig, regs); - return; - } - - /* - * If we were from a system call, check for system call restarting... - */ - if (in_syscall(regs)) { - /* Restart the system call - no handlers present */ - - /* Avoid additional syscall restarting via ret_slow_syscall. */ - forget_syscall(regs); - - switch (regs->uregs[0]) { - case -ERESTART_RESTARTBLOCK: - regs->uregs[15] = __NR_restart_syscall; - fallthrough; - case -ERESTARTNOHAND: - case -ERESTARTSYS: - case -ERESTARTNOINTR: - regs->uregs[0] = regs->orig_r0; - regs->ipc -= 0x4; - break; - } - } - restore_saved_sigmask(); -} - -asmlinkage void -do_notify_resume(struct pt_regs *regs, unsigned int thread_flags) -{ - if (thread_flags & (_TIF_SIGPENDING | _TIF_NOTIFY_SIGNAL)) - do_signal(regs); - - if (thread_flags & _TIF_NOTIFY_RESUME) - tracehook_notify_resume(regs); -} diff --git a/arch/nds32/kernel/sleep.S b/arch/nds32/kernel/sleep.S deleted file mode 100644 index ca4e61f3656f..000000000000 --- a/arch/nds32/kernel/sleep.S +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (C) 2017 Andes Technology Corporation */ - -#include - -.data -.global sp_tmp -sp_tmp: -.long - -.text -.globl suspend2ram -.globl cpu_resume - -suspend2ram: - pushm $r0, $r31 -#if defined(CONFIG_HWZOL) - mfusr $r0, $lc - mfusr $r1, $le - mfusr $r2, $lb -#endif - mfsr $r3, $mr0 - mfsr $r4, $mr1 - mfsr $r5, $mr4 - mfsr $r6, $mr6 - mfsr $r7, $mr7 - mfsr $r8, $mr8 - mfsr $r9, $ir0 - mfsr $r10, $ir1 - mfsr $r11, $ir2 - mfsr $r12, $ir3 - mfsr $r13, $ir9 - mfsr $r14, $ir10 - mfsr $r15, $ir12 - mfsr $r16, $ir13 - mfsr $r17, $ir14 - mfsr $r18, $ir15 - pushm $r0, $r19 -#if defined(CONFIG_FPU) - jal store_fpu_for_suspend -#endif - tlbop FlushAll - isb - - // transfer $sp from va to pa - sethi $r0, hi20(PAGE_OFFSET) - ori $r0, $r0, lo12(PAGE_OFFSET) - movi $r2, PHYS_OFFSET - sub $r1, $sp, $r0 - add $r2, $r1, $r2 - - // store pa($sp) to sp_tmp - sethi $r1, hi20(sp_tmp) - swi $r2, [$r1 + lo12(sp_tmp)] - - pushm $r16, $r25 - pushm $r29, $r30 -#ifdef CONFIG_CACHE_L2 - jal dcache_wb_all_level -#else - jal cpu_dcache_wb_all -#endif - popm $r29, $r30 - popm $r16, $r25 - - // get wake_mask and loop in standby - la $r1, wake_mask - lwi $r1, [$r1] -self_loop: - standby wake_grant - mfsr $r2, $ir15 - and $r2, $r1, $r2 - beqz $r2, self_loop - - // set ipc to resume address - la $r1, resume_addr - lwi $r1, [$r1] - mtsr $r1, $ipc - isb - - // reset psw, turn off the address translation - li $r2, 0x7000a - mtsr $r2, $ipsw - isb - - iret -cpu_resume: - // translate the address of sp_tmp variable to pa - la $r1, sp_tmp - sethi $r0, hi20(PAGE_OFFSET) - ori $r0, $r0, lo12(PAGE_OFFSET) - movi $r2, PHYS_OFFSET - sub $r1, $r1, $r0 - add $r1, $r1, $r2 - - // access the sp_tmp to get stack pointer - lwi $sp, [$r1] - - popm $r0, $r19 -#if defined(CONFIG_HWZOL) - mtusr $r0, $lb - mtusr $r1, $lc - mtusr $r2, $le -#endif - mtsr $r3, $mr0 - mtsr $r4, $mr1 - mtsr $r5, $mr4 - mtsr $r6, $mr6 - mtsr $r7, $mr7 - mtsr $r8, $mr8 - // set original psw to ipsw - mtsr $r9, $ir1 - - mtsr $r11, $ir2 - mtsr $r12, $ir3 - - // set ipc to RR - la $r13, RR - mtsr $r13, $ir9 - - mtsr $r14, $ir10 - mtsr $r15, $ir12 - mtsr $r16, $ir13 - mtsr $r17, $ir14 - mtsr $r18, $ir15 - popm $r0, $r31 - - isb - iret -RR: - ret diff --git a/arch/nds32/kernel/stacktrace.c b/arch/nds32/kernel/stacktrace.c deleted file mode 100644 index d974c0c1c65f..000000000000 --- a/arch/nds32/kernel/stacktrace.c +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include - -void save_stack_trace(struct stack_trace *trace) -{ - save_stack_trace_tsk(current, trace); -} -EXPORT_SYMBOL_GPL(save_stack_trace); - -void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) -{ - unsigned long *fpn; - int skip = trace->skip; - int savesched; - int graph_idx = 0; - - if (tsk == current) { - __asm__ __volatile__("\tori\t%0, $fp, #0\n":"=r"(fpn)); - savesched = 1; - } else { - fpn = (unsigned long *)thread_saved_fp(tsk); - savesched = 0; - } - - while (!kstack_end(fpn) && !((unsigned long)fpn & 0x3) - && (fpn >= (unsigned long *)TASK_SIZE)) { - unsigned long lpp, fpp; - - lpp = fpn[LP_OFFSET]; - fpp = fpn[FP_OFFSET]; - if (!__kernel_text_address(lpp)) - break; - else - lpp = ftrace_graph_ret_addr(tsk, &graph_idx, lpp, NULL); - - if (savesched || !in_sched_functions(lpp)) { - if (skip) { - skip--; - } else { - trace->entries[trace->nr_entries++] = lpp; - if (trace->nr_entries >= trace->max_entries) - break; - } - } - fpn = (unsigned long *)fpp; - } -} -EXPORT_SYMBOL_GPL(save_stack_trace_tsk); diff --git a/arch/nds32/kernel/sys_nds32.c b/arch/nds32/kernel/sys_nds32.c deleted file mode 100644 index cb2d1e219bb3..000000000000 --- a/arch/nds32/kernel/sys_nds32.c +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include - -#include -#include -#include -#include - -SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, - unsigned long, prot, unsigned long, flags, - unsigned long, fd, unsigned long, pgoff) -{ - if (pgoff & (~PAGE_MASK >> 12)) - return -EINVAL; - - return sys_mmap_pgoff(addr, len, prot, flags, fd, - pgoff >> (PAGE_SHIFT - 12)); -} - -SYSCALL_DEFINE4(fadvise64_64_wrapper,int, fd, int, advice, loff_t, offset, - loff_t, len) -{ - return sys_fadvise64_64(fd, offset, len, advice); -} - -SYSCALL_DEFINE3(cacheflush, unsigned int, start, unsigned int, end, int, cache) -{ - struct vm_area_struct *vma; - bool flushi = true, wbd = true; - - vma = find_vma(current->mm, start); - if (!vma) - return -EFAULT; - switch (cache) { - case ICACHE: - wbd = false; - break; - case DCACHE: - flushi = false; - break; - case BCACHE: - break; - default: - return -EINVAL; - } - cpu_cache_wbinval_range_check(vma, start, end, flushi, wbd); - - return 0; -} - -SYSCALL_DEFINE2(fp_udfiex_crtl, unsigned int, cmd, unsigned int, act) -{ -#if IS_ENABLED(CONFIG_SUPPORT_DENORMAL_ARITHMETIC) - int old_udf_iex; - - if (!used_math()) { - load_fpu(&init_fpuregs); - current->thread.fpu.UDF_IEX_trap = init_fpuregs.UDF_IEX_trap; - set_used_math(); - } - - old_udf_iex = current->thread.fpu.UDF_IEX_trap; - act &= (FPCSR_mskUDFE | FPCSR_mskIEXE); - - switch (cmd) { - case DISABLE_UDF_IEX_TRAP: - current->thread.fpu.UDF_IEX_trap &= ~act; - break; - case ENABLE_UDF_IEX_TRAP: - current->thread.fpu.UDF_IEX_trap |= act; - break; - case GET_UDF_IEX_TRAP: - break; - default: - return -EINVAL; - } - return old_udf_iex; -#else - return -ENOTSUPP; -#endif -} diff --git a/arch/nds32/kernel/syscall_table.c b/arch/nds32/kernel/syscall_table.c deleted file mode 100644 index 7879c061b87f..000000000000 --- a/arch/nds32/kernel/syscall_table.c +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include - -#undef __SYSCALL -#define __SYSCALL(nr, call) [nr] = (call), - -#define sys_rt_sigreturn sys_rt_sigreturn_wrapper -#define sys_fadvise64_64 sys_fadvise64_64_wrapper -void *sys_call_table[__NR_syscalls] __aligned(8192) = { - [0 ... __NR_syscalls - 1] = sys_ni_syscall, -#include -}; diff --git a/arch/nds32/kernel/time.c b/arch/nds32/kernel/time.c deleted file mode 100644 index 574a3d0a8539..000000000000 --- a/arch/nds32/kernel/time.c +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include - -void __init time_init(void) -{ - of_clk_init(NULL); - timer_probe(); -} diff --git a/arch/nds32/kernel/traps.c b/arch/nds32/kernel/traps.c deleted file mode 100644 index c0a8f3344fb9..000000000000 --- a/arch/nds32/kernel/traps.c +++ /dev/null @@ -1,354 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -extern void show_pte(struct mm_struct *mm, unsigned long addr); - -/* - * Dump out the contents of some memory nicely... - */ -void dump_mem(const char *lvl, unsigned long bottom, unsigned long top) -{ - unsigned long first; - int i; - - pr_emerg("%s(0x%08lx to 0x%08lx)\n", lvl, bottom, top); - - for (first = bottom & ~31; first < top; first += 32) { - unsigned long p; - char str[sizeof(" 12345678") * 8 + 1]; - - memset(str, ' ', sizeof(str)); - str[sizeof(str) - 1] = '\0'; - - for (p = first, i = 0; i < 8 && p < top; i++, p += 4) { - if (p >= bottom && p < top) { - unsigned long val; - - if (get_kernel_nofault(val, - (unsigned long *)p) == 0) - sprintf(str + i * 9, " %08lx", val); - else - sprintf(str + i * 9, " ????????"); - } - } - pr_emerg("%s%04lx:%s\n", lvl, first & 0xffff, str); - } -} - -EXPORT_SYMBOL(dump_mem); - -#define LOOP_TIMES (100) -static void __dump(struct task_struct *tsk, unsigned long *base_reg, - const char *loglvl) -{ - unsigned long ret_addr; - int cnt = LOOP_TIMES, graph = 0; - printk("%sCall Trace:\n", loglvl); - if (!IS_ENABLED(CONFIG_FRAME_POINTER)) { - while (!kstack_end(base_reg)) { - ret_addr = *base_reg++; - if (__kernel_text_address(ret_addr)) { - ret_addr = ftrace_graph_ret_addr( - tsk, &graph, ret_addr, NULL); - print_ip_sym(loglvl, ret_addr); - } - if (--cnt < 0) - break; - } - } else { - while (!kstack_end((void *)base_reg) && - !((unsigned long)base_reg & 0x3) && - ((unsigned long)base_reg >= TASK_SIZE)) { - unsigned long next_fp; - ret_addr = base_reg[LP_OFFSET]; - next_fp = base_reg[FP_OFFSET]; - if (__kernel_text_address(ret_addr)) { - - ret_addr = ftrace_graph_ret_addr( - tsk, &graph, ret_addr, NULL); - print_ip_sym(loglvl, ret_addr); - } - if (--cnt < 0) - break; - base_reg = (unsigned long *)next_fp; - } - } - printk("%s\n", loglvl); -} - -void show_stack(struct task_struct *tsk, unsigned long *sp, const char *loglvl) -{ - unsigned long *base_reg; - - if (!tsk) - tsk = current; - if (!IS_ENABLED(CONFIG_FRAME_POINTER)) { - if (tsk != current) - base_reg = (unsigned long *)(tsk->thread.cpu_context.sp); - else - __asm__ __volatile__("\tori\t%0, $sp, #0\n":"=r"(base_reg)); - } else { - if (tsk != current) - base_reg = (unsigned long *)(tsk->thread.cpu_context.fp); - else - __asm__ __volatile__("\tori\t%0, $fp, #0\n":"=r"(base_reg)); - } - __dump(tsk, base_reg, loglvl); - barrier(); -} - -DEFINE_SPINLOCK(die_lock); - -/* - * This function is protected against re-entrancy. - */ -void __noreturn die(const char *str, struct pt_regs *regs, int err) -{ - struct task_struct *tsk = current; - static int die_counter; - - console_verbose(); - spin_lock_irq(&die_lock); - bust_spinlocks(1); - - pr_emerg("Internal error: %s: %x [#%d]\n", str, err, ++die_counter); - print_modules(); - pr_emerg("CPU: %i\n", smp_processor_id()); - show_regs(regs); - pr_emerg("Process %s (pid: %d, stack limit = 0x%p)\n", - tsk->comm, tsk->pid, end_of_stack(tsk)); - - if (!user_mode(regs) || in_interrupt()) { - dump_mem("Stack: ", regs->sp, (regs->sp + PAGE_SIZE) & PAGE_MASK); - dump_stack(); - } - - bust_spinlocks(0); - spin_unlock_irq(&die_lock); - make_task_dead(SIGSEGV); -} - -EXPORT_SYMBOL(die); - -void die_if_kernel(const char *str, struct pt_regs *regs, int err) -{ - if (user_mode(regs)) - return; - - die(str, regs, err); -} - -int bad_syscall(int n, struct pt_regs *regs) -{ - if (current->personality != PER_LINUX) { - send_sig(SIGSEGV, current, 1); - return regs->uregs[0]; - } - - force_sig_fault(SIGILL, ILL_ILLTRP, - (void __user *)instruction_pointer(regs) - 4); - die_if_kernel("Oops - bad syscall", regs, n); - return regs->uregs[0]; -} - -void __pte_error(const char *file, int line, unsigned long val) -{ - pr_emerg("%s:%d: bad pte %08lx.\n", file, line, val); -} - -void __pmd_error(const char *file, int line, unsigned long val) -{ - pr_emerg("%s:%d: bad pmd %08lx.\n", file, line, val); -} - -void __pgd_error(const char *file, int line, unsigned long val) -{ - pr_emerg("%s:%d: bad pgd %08lx.\n", file, line, val); -} - -extern char *exception_vector, *exception_vector_end; -void __init early_trap_init(void) -{ - unsigned long ivb = 0; - unsigned long base = PAGE_OFFSET; - - memcpy((unsigned long *)base, (unsigned long *)&exception_vector, - ((unsigned long)&exception_vector_end - - (unsigned long)&exception_vector)); - ivb = __nds32__mfsr(NDS32_SR_IVB); - /* Check platform support. */ - if (((ivb & IVB_mskNIVIC) >> IVB_offNIVIC) < 2) - panic - ("IVIC mode is not allowed on the platform with interrupt controller\n"); - __nds32__mtsr((ivb & ~IVB_mskESZ) | (IVB_valESZ16 << IVB_offESZ) | - IVB_BASE, NDS32_SR_IVB); - __nds32__mtsr(INT_MASK_INITAIAL_VAL, NDS32_SR_INT_MASK); - - /* - * 0x800 = 128 vectors * 16byte. - * It should be enough to flush a page. - */ - cpu_cache_wbinval_page(base, true); -} - -static void send_sigtrap(struct pt_regs *regs, int error_code, int si_code) -{ - struct task_struct *tsk = current; - - tsk->thread.trap_no = ENTRY_DEBUG_RELATED; - tsk->thread.error_code = error_code; - - force_sig_fault(SIGTRAP, si_code, - (void __user *)instruction_pointer(regs)); -} - -void do_debug_trap(unsigned long entry, unsigned long addr, - unsigned long type, struct pt_regs *regs) -{ - if (notify_die(DIE_OOPS, "Oops", regs, addr, type, SIGTRAP) - == NOTIFY_STOP) - return; - - if (user_mode(regs)) { - /* trap_signal */ - send_sigtrap(regs, 0, TRAP_BRKPT); - } else { - /* kernel_trap */ - if (!fixup_exception(regs)) - die("unexpected kernel_trap", regs, 0); - } -} - -void unhandled_interruption(struct pt_regs *regs) -{ - pr_emerg("unhandled_interruption\n"); - show_regs(regs); - if (!user_mode(regs)) - make_task_dead(SIGKILL); - force_sig(SIGKILL); -} - -void unhandled_exceptions(unsigned long entry, unsigned long addr, - unsigned long type, struct pt_regs *regs) -{ - pr_emerg("Unhandled Exception: entry: %lx addr:%lx itype:%lx\n", entry, - addr, type); - show_regs(regs); - if (!user_mode(regs)) - make_task_dead(SIGKILL); - force_sig(SIGKILL); -} - -extern int do_page_fault(unsigned long entry, unsigned long addr, - unsigned int error_code, struct pt_regs *regs); - -/* - * 2:DEF dispatch for TLB MISC exception handler -*/ - -void do_dispatch_tlb_misc(unsigned long entry, unsigned long addr, - unsigned long type, struct pt_regs *regs) -{ - type = type & (ITYPE_mskINST | ITYPE_mskETYPE); - if ((type & ITYPE_mskETYPE) < 5) { - /* Permission exceptions */ - do_page_fault(entry, addr, type, regs); - } else - unhandled_exceptions(entry, addr, type, regs); -} - -void do_revinsn(struct pt_regs *regs) -{ - pr_emerg("Reserved Instruction\n"); - show_regs(regs); - if (!user_mode(regs)) - make_task_dead(SIGILL); - force_sig(SIGILL); -} - -#ifdef CONFIG_ALIGNMENT_TRAP -extern int unalign_access_mode; -extern int do_unaligned_access(unsigned long addr, struct pt_regs *regs); -#endif -void do_dispatch_general(unsigned long entry, unsigned long addr, - unsigned long itype, struct pt_regs *regs, - unsigned long oipc) -{ - unsigned int swid = itype >> ITYPE_offSWID; - unsigned long type = itype & (ITYPE_mskINST | ITYPE_mskETYPE); - if (type == ETYPE_ALIGNMENT_CHECK) { -#ifdef CONFIG_ALIGNMENT_TRAP - /* Alignment check */ - if (user_mode(regs) && unalign_access_mode) { - int ret; - ret = do_unaligned_access(addr, regs); - - if (ret == 0) - return; - - if (ret == -EFAULT) - pr_emerg - ("Unhandled unaligned access exception\n"); - } -#endif - do_page_fault(entry, addr, type, regs); - } else if (type == ETYPE_RESERVED_INSTRUCTION) { - /* Reserved instruction */ - do_revinsn(regs); - } else if (type == ETYPE_COPROCESSOR) { - /* Coprocessor */ -#if IS_ENABLED(CONFIG_FPU) - unsigned int fucop_exist = __nds32__mfsr(NDS32_SR_FUCOP_EXIST); - unsigned int cpid = ((itype & ITYPE_mskCPID) >> ITYPE_offCPID); - - if ((cpid == FPU_CPID) && - (fucop_exist & FUCOP_EXIST_mskCP0ISFPU)) { - unsigned int subtype = (itype & ITYPE_mskSTYPE); - - if (true == do_fpu_exception(subtype, regs)) - return; - } -#endif - unhandled_exceptions(entry, addr, type, regs); - } else if (type == ETYPE_TRAP && swid == SWID_RAISE_INTERRUPT_LEVEL) { - /* trap, used on v3 EDM target debugging workaround */ - /* - * DIPC(OIPC) is passed as parameter before - * interrupt is enabled, so the DIPC will not be corrupted - * even though interrupts are coming in - */ - /* - * 1. update ipc - * 2. update pt_regs ipc with oipc - * 3. update pt_regs ipsw (clear DEX) - */ - __asm__ volatile ("mtsr %0, $IPC\n\t"::"r" (oipc)); - regs->ipc = oipc; - if (regs->pipsw & PSW_mskDEX) { - pr_emerg - ("Nested Debug exception is possibly happened\n"); - pr_emerg("ipc:%08x pipc:%08x\n", - (unsigned int)regs->ipc, - (unsigned int)regs->pipc); - } - do_debug_trap(entry, addr, itype, regs); - regs->ipsw &= ~PSW_mskDEX; - } else - unhandled_exceptions(entry, addr, type, regs); -} diff --git a/arch/nds32/kernel/vdso.c b/arch/nds32/kernel/vdso.c deleted file mode 100644 index e16009a07971..000000000000 --- a/arch/nds32/kernel/vdso.c +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2012 ARM Limited -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -extern struct cache_info L1_cache_info[2]; -extern char vdso_start[], vdso_end[]; -static unsigned long vdso_pages __ro_after_init; -static unsigned long timer_mapping_base; - -struct timer_info_t timer_info = { - .cycle_count_down = true, - .mapping_base = EMPTY_TIMER_MAPPING, - .cycle_count_reg_offset = EMPTY_REG_OFFSET -}; -/* - * The vDSO data page. - */ -static struct page *no_pages[] = { NULL }; - -static union { - struct vdso_data data; - u8 page[PAGE_SIZE]; -} vdso_data_store __page_aligned_data; -struct vdso_data *vdso_data = &vdso_data_store.data; -static struct vm_special_mapping vdso_spec[2] __ro_after_init = { - { - .name = "[vvar]", - .pages = no_pages, - }, - { - .name = "[vdso]", - }, -}; - -static void get_timer_node_info(void) -{ - timer_mapping_base = timer_info.mapping_base; - vdso_data->cycle_count_offset = - timer_info.cycle_count_reg_offset; - vdso_data->cycle_count_down = - timer_info.cycle_count_down; -} - -static int __init vdso_init(void) -{ - int i; - struct page **vdso_pagelist; - - if (memcmp(vdso_start, "\177ELF", 4)) { - pr_err("vDSO is not a valid ELF object!\n"); - return -EINVAL; - } - /* Creat a timer io mapping to get clock cycles counter */ - get_timer_node_info(); - - vdso_pages = (vdso_end - vdso_start) >> PAGE_SHIFT; - pr_info("vdso: %ld pages (%ld code @ %p, %ld data @ %p)\n", - vdso_pages + 1, vdso_pages, vdso_start, 1L, vdso_data); - - /* Allocate the vDSO pagelist */ - vdso_pagelist = kcalloc(vdso_pages, sizeof(struct page *), GFP_KERNEL); - if (vdso_pagelist == NULL) - return -ENOMEM; - - for (i = 0; i < vdso_pages; i++) - vdso_pagelist[i] = virt_to_page(vdso_start + i * PAGE_SIZE); - vdso_spec[1].pages = &vdso_pagelist[0]; - - return 0; -} - -arch_initcall(vdso_init); - -unsigned long inline vdso_random_addr(unsigned long vdso_mapping_len) -{ - unsigned long start = current->mm->mmap_base, end, offset, addr; - start = PAGE_ALIGN(start); - - /* Round the lowest possible end address up to a PMD boundary. */ - end = (start + vdso_mapping_len + PMD_SIZE - 1) & PMD_MASK; - if (end >= TASK_SIZE) - end = TASK_SIZE; - end -= vdso_mapping_len; - - if (end > start) { - offset = get_random_int() % (((end - start) >> PAGE_SHIFT) + 1); - addr = start + (offset << PAGE_SHIFT); - } else { - addr = start; - } - return addr; -} - -int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) -{ - struct mm_struct *mm = current->mm; - unsigned long vdso_base, vdso_text_len, vdso_mapping_len; - struct vm_area_struct *vma; - unsigned long addr = 0; - pgprot_t prot; - int ret, vvar_page_num = 2; - - vdso_text_len = vdso_pages << PAGE_SHIFT; - - if(timer_mapping_base == EMPTY_VALUE) - vvar_page_num = 1; - /* Be sure to map the data page */ - vdso_mapping_len = vdso_text_len + vvar_page_num * PAGE_SIZE; -#ifdef CONFIG_CPU_CACHE_ALIASING - vdso_mapping_len += L1_cache_info[DCACHE].aliasing_num - 1; -#endif - - if (mmap_write_lock_killable(mm)) - return -EINTR; - - addr = vdso_random_addr(vdso_mapping_len); - vdso_base = get_unmapped_area(NULL, addr, vdso_mapping_len, 0, 0); - if (IS_ERR_VALUE(vdso_base)) { - ret = vdso_base; - goto up_fail; - } - -#ifdef CONFIG_CPU_CACHE_ALIASING - { - unsigned int aliasing_mask = - L1_cache_info[DCACHE].aliasing_mask; - unsigned int page_colour_ofs; - page_colour_ofs = ((unsigned int)vdso_data & aliasing_mask) - - (vdso_base & aliasing_mask); - vdso_base += page_colour_ofs & aliasing_mask; - } -#endif - - vma = _install_special_mapping(mm, vdso_base, vvar_page_num * PAGE_SIZE, - VM_READ | VM_MAYREAD, &vdso_spec[0]); - if (IS_ERR(vma)) { - ret = PTR_ERR(vma); - goto up_fail; - } - - /*Map vdata to user space */ - ret = io_remap_pfn_range(vma, vdso_base, - virt_to_phys(vdso_data) >> PAGE_SHIFT, - PAGE_SIZE, vma->vm_page_prot); - if (ret) - goto up_fail; - - /*Map timer to user space */ - vdso_base += PAGE_SIZE; - prot = __pgprot(_PAGE_V | _PAGE_M_UR_KR | _PAGE_D | _PAGE_C_DEV); - ret = io_remap_pfn_range(vma, vdso_base, timer_mapping_base >> PAGE_SHIFT, - PAGE_SIZE, prot); - if (ret) - goto up_fail; - - /*Map vdso to user space */ - vdso_base += PAGE_SIZE; - mm->context.vdso = (void *)vdso_base; - vma = _install_special_mapping(mm, vdso_base, vdso_text_len, - VM_READ | VM_EXEC | - VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC, - &vdso_spec[1]); - if (IS_ERR(vma)) { - ret = PTR_ERR(vma); - goto up_fail; - } - - mmap_write_unlock(mm); - return 0; - -up_fail: - mm->context.vdso = NULL; - mmap_write_unlock(mm); - return ret; -} - -static void vdso_write_begin(struct vdso_data *vdata) -{ - ++vdso_data->seq_count; - smp_wmb(); /* Pairs with smp_rmb in vdso_read_retry */ -} - -static void vdso_write_end(struct vdso_data *vdata) -{ - smp_wmb(); /* Pairs with smp_rmb in vdso_read_begin */ - ++vdso_data->seq_count; -} - -void update_vsyscall(struct timekeeper *tk) -{ - vdso_write_begin(vdso_data); - vdso_data->cs_mask = tk->tkr_mono.mask; - vdso_data->cs_mult = tk->tkr_mono.mult; - vdso_data->cs_shift = tk->tkr_mono.shift; - vdso_data->cs_cycle_last = tk->tkr_mono.cycle_last; - vdso_data->wtm_clock_sec = tk->wall_to_monotonic.tv_sec; - vdso_data->wtm_clock_nsec = tk->wall_to_monotonic.tv_nsec; - vdso_data->xtime_clock_sec = tk->xtime_sec; - vdso_data->xtime_clock_nsec = tk->tkr_mono.xtime_nsec; - vdso_data->xtime_coarse_sec = tk->xtime_sec; - vdso_data->xtime_coarse_nsec = tk->tkr_mono.xtime_nsec >> - tk->tkr_mono.shift; - vdso_data->hrtimer_res = hrtimer_resolution; - vdso_write_end(vdso_data); -} - -void update_vsyscall_tz(void) -{ - vdso_data->tz_minuteswest = sys_tz.tz_minuteswest; - vdso_data->tz_dsttime = sys_tz.tz_dsttime; -} diff --git a/arch/nds32/kernel/vdso/Makefile b/arch/nds32/kernel/vdso/Makefile deleted file mode 100644 index 55df25ef0057..000000000000 --- a/arch/nds32/kernel/vdso/Makefile +++ /dev/null @@ -1,79 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Building a vDSO image for AArch64. -# -# Author: Will Deacon -# Heavily based on the vDSO Makefiles for other archs. -# - -obj-vdso := note.o datapage.o sigreturn.o gettimeofday.o - -# Build rules -targets := $(obj-vdso) vdso.so vdso.so.dbg -obj-vdso := $(addprefix $(obj)/, $(obj-vdso)) - -ccflags-y := -shared -fno-common -fno-builtin -nostdlib -fPIC -Wl,-shared -g \ - -Wl,-soname=linux-vdso.so.1 -Wl,--hash-style=sysv - -# Disable gcov profiling for VDSO code -GCOV_PROFILE := n - - -obj-y += vdso.o -targets += vdso.lds -CPPFLAGS_vdso.lds += -P -C -U$(ARCH) - -# Force dependency -$(obj)/vdso.o : $(obj)/vdso.so - -# Link rule for the .so file, .lds has to be first -$(obj)/vdso.so.dbg: $(obj)/vdso.lds $(obj-vdso) FORCE - $(call if_changed,vdsold) - - -# Strip rule for the .so file -$(obj)/%.so: OBJCOPYFLAGS := -S -$(obj)/%.so: $(obj)/%.so.dbg FORCE - $(call if_changed,objcopy) - -# Generate VDSO offsets using helper script -gen-vdsosym := $(srctree)/$(src)/gen_vdso_offsets.sh -quiet_cmd_vdsosym = VDSOSYM $@ - cmd_vdsosym = $(NM) $< | $(gen-vdsosym) | LC_ALL=C sort > $@ - -include/generated/vdso-offsets.h: $(obj)/vdso.so.dbg FORCE - $(call if_changed,vdsosym) - - - -# Assembly rules for the .S files - -sigreturn.o : sigreturn.S - $(call if_changed_dep,vdsoas) - -note.o : note.S - $(call if_changed_dep,vdsoas) - -datapage.o : datapage.S - $(call if_changed_dep,vdsoas) - -gettimeofday.o : gettimeofday.c FORCE - $(call if_changed_dep,vdsocc) - -# Actual build commands -quiet_cmd_vdsold = VDSOL $@ - cmd_vdsold = $(CC) $(c_flags) -Wl,-n -Wl,-T $(real-prereqs) -o $@ -quiet_cmd_vdsoas = VDSOA $@ - cmd_vdsoas = $(CC) $(a_flags) -c -o $@ $< -quiet_cmd_vdsocc = VDSOA $@ - cmd_vdsocc = $(CC) $(c_flags) -c -o $@ $< - -# Install commands for the unstripped file -quiet_cmd_vdso_install = INSTALL $@ - cmd_vdso_install = cp $(obj)/$@.dbg $(MODLIB)/vdso/$@ - -vdso.so: $(obj)/vdso.so.dbg - @mkdir -p $(MODLIB)/vdso - $(call cmd,vdso_install) - -vdso_install: vdso.so diff --git a/arch/nds32/kernel/vdso/datapage.S b/arch/nds32/kernel/vdso/datapage.S deleted file mode 100644 index 4a62c3cab1c8..000000000000 --- a/arch/nds32/kernel/vdso/datapage.S +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include - -ENTRY(__get_timerpage) - sethi $r0, hi20(. + PAGE_SIZE + 8) - ori $r0, $r0, lo12(. + PAGE_SIZE + 4) - mfusr $r1, $pc - sub $r0, $r1, $r0 - ret -ENDPROC(__get_timerpage) - -ENTRY(__get_datapage) - sethi $r0, hi20(. + 2*PAGE_SIZE + 8) - ori $r0, $r0, lo12(. + 2*PAGE_SIZE + 4) - mfusr $r1, $pc - sub $r0, $r1, $r0 - ret -ENDPROC(__get_datapage) diff --git a/arch/nds32/kernel/vdso/gen_vdso_offsets.sh b/arch/nds32/kernel/vdso/gen_vdso_offsets.sh deleted file mode 100755 index 01924ff071ad..000000000000 --- a/arch/nds32/kernel/vdso/gen_vdso_offsets.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/sh - -# -# Match symbols in the DSO that look like VDSO_*; produce a header file -# of constant offsets into the shared object. -# -# Doing this inside the Makefile will break the $(filter-out) function, -# causing Kbuild to rebuild the vdso-offsets header file every time. -# -# Author: Will Deacon -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define X(x) #x -#define Y(x) X(x) - -extern struct vdso_data *__get_datapage(void); -extern struct vdso_data *__get_timerpage(void); - -static notrace unsigned int __vdso_read_begin(const struct vdso_data *vdata) -{ - u32 seq; -repeat: - seq = READ_ONCE(vdata->seq_count); - if (seq & 1) { - cpu_relax(); - goto repeat; - } - return seq; -} - -static notrace unsigned int vdso_read_begin(const struct vdso_data *vdata) -{ - unsigned int seq; - - seq = __vdso_read_begin(vdata); - - smp_rmb(); /* Pairs with smp_wmb in vdso_write_end */ - return seq; -} - -static notrace int vdso_read_retry(const struct vdso_data *vdata, u32 start) -{ - smp_rmb(); /* Pairs with smp_wmb in vdso_write_begin */ - return vdata->seq_count != start; -} - -static notrace long clock_gettime_fallback(clockid_t _clkid, - struct __kernel_old_timespec *_ts) -{ - register struct __kernel_old_timespec *ts asm("$r1") = _ts; - register clockid_t clkid asm("$r0") = _clkid; - register long ret asm("$r0"); - - asm volatile ("movi $r15, %3\n" - "syscall 0x0\n" - :"=r" (ret) - :"r"(clkid), "r"(ts), "i"(__NR_clock_gettime) - :"$r15", "memory"); - - return ret; -} - -static notrace int do_realtime_coarse(struct __kernel_old_timespec *ts, - struct vdso_data *vdata) -{ - u32 seq; - - do { - seq = vdso_read_begin(vdata); - - ts->tv_sec = vdata->xtime_coarse_sec; - ts->tv_nsec = vdata->xtime_coarse_nsec; - - } while (vdso_read_retry(vdata, seq)); - return 0; -} - -static notrace int do_monotonic_coarse(struct __kernel_old_timespec *ts, - struct vdso_data *vdata) -{ - u32 seq; - u64 ns; - - do { - seq = vdso_read_begin(vdata); - - ts->tv_sec = vdata->xtime_coarse_sec + vdata->wtm_clock_sec; - ns = vdata->xtime_coarse_nsec + vdata->wtm_clock_nsec; - - } while (vdso_read_retry(vdata, seq)); - - ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); - ts->tv_nsec = ns; - - return 0; -} - -static notrace inline u64 vgetsns(struct vdso_data *vdso) -{ - u32 cycle_now; - u32 cycle_delta; - u32 *timer_cycle_base; - - timer_cycle_base = - (u32 *) ((char *)__get_timerpage() + vdso->cycle_count_offset); - cycle_now = readl_relaxed(timer_cycle_base); - if (true == vdso->cycle_count_down) - cycle_now = ~(*timer_cycle_base); - cycle_delta = cycle_now - (u32) vdso->cs_cycle_last; - return ((u64) cycle_delta & vdso->cs_mask) * vdso->cs_mult; -} - -static notrace int do_realtime(struct __kernel_old_timespec *ts, struct vdso_data *vdata) -{ - unsigned count; - u64 ns; - do { - count = vdso_read_begin(vdata); - ts->tv_sec = vdata->xtime_clock_sec; - ns = vdata->xtime_clock_nsec; - ns += vgetsns(vdata); - ns >>= vdata->cs_shift; - } while (vdso_read_retry(vdata, count)); - - ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); - ts->tv_nsec = ns; - - return 0; -} - -static notrace int do_monotonic(struct __kernel_old_timespec *ts, struct vdso_data *vdata) -{ - u64 ns; - u32 seq; - - do { - seq = vdso_read_begin(vdata); - - ts->tv_sec = vdata->xtime_clock_sec; - ns = vdata->xtime_clock_nsec; - ns += vgetsns(vdata); - ns >>= vdata->cs_shift; - - ts->tv_sec += vdata->wtm_clock_sec; - ns += vdata->wtm_clock_nsec; - - } while (vdso_read_retry(vdata, seq)); - - ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns); - ts->tv_nsec = ns; - - return 0; -} - -notrace int __vdso_clock_gettime(clockid_t clkid, struct __kernel_old_timespec *ts) -{ - struct vdso_data *vdata; - int ret = -1; - - vdata = __get_datapage(); - if (vdata->cycle_count_offset == EMPTY_REG_OFFSET) - return clock_gettime_fallback(clkid, ts); - - switch (clkid) { - case CLOCK_REALTIME_COARSE: - ret = do_realtime_coarse(ts, vdata); - break; - case CLOCK_MONOTONIC_COARSE: - ret = do_monotonic_coarse(ts, vdata); - break; - case CLOCK_REALTIME: - ret = do_realtime(ts, vdata); - break; - case CLOCK_MONOTONIC: - ret = do_monotonic(ts, vdata); - break; - default: - break; - } - - if (ret) - ret = clock_gettime_fallback(clkid, ts); - - return ret; -} - -static notrace int clock_getres_fallback(clockid_t _clk_id, - struct __kernel_old_timespec *_res) -{ - register clockid_t clk_id asm("$r0") = _clk_id; - register struct __kernel_old_timespec *res asm("$r1") = _res; - register int ret asm("$r0"); - - asm volatile ("movi $r15, %3\n" - "syscall 0x0\n" - :"=r" (ret) - :"r"(clk_id), "r"(res), "i"(__NR_clock_getres) - :"$r15", "memory"); - - return ret; -} - -notrace int __vdso_clock_getres(clockid_t clk_id, struct __kernel_old_timespec *res) -{ - struct vdso_data *vdata = __get_datapage(); - - if (res == NULL) - return 0; - switch (clk_id) { - case CLOCK_REALTIME: - case CLOCK_MONOTONIC: - case CLOCK_MONOTONIC_RAW: - res->tv_sec = 0; - res->tv_nsec = vdata->hrtimer_res; - break; - case CLOCK_REALTIME_COARSE: - case CLOCK_MONOTONIC_COARSE: - res->tv_sec = 0; - res->tv_nsec = CLOCK_COARSE_RES; - break; - default: - return clock_getres_fallback(clk_id, res); - } - return 0; -} - -static notrace inline int gettimeofday_fallback(struct __kernel_old_timeval *_tv, - struct timezone *_tz) -{ - register struct __kernel_old_timeval *tv asm("$r0") = _tv; - register struct timezone *tz asm("$r1") = _tz; - register int ret asm("$r0"); - - asm volatile ("movi $r15, %3\n" - "syscall 0x0\n" - :"=r" (ret) - :"r"(tv), "r"(tz), "i"(__NR_gettimeofday) - :"$r15", "memory"); - - return ret; -} - -notrace int __vdso_gettimeofday(struct __kernel_old_timeval *tv, struct timezone *tz) -{ - struct __kernel_old_timespec ts; - struct vdso_data *vdata; - int ret; - - vdata = __get_datapage(); - - if (vdata->cycle_count_offset == EMPTY_REG_OFFSET) - return gettimeofday_fallback(tv, tz); - - ret = do_realtime(&ts, vdata); - - if (tv) { - tv->tv_sec = ts.tv_sec; - tv->tv_usec = ts.tv_nsec / 1000; - } - if (tz) { - tz->tz_minuteswest = vdata->tz_minuteswest; - tz->tz_dsttime = vdata->tz_dsttime; - } - - return ret; -} diff --git a/arch/nds32/kernel/vdso/note.S b/arch/nds32/kernel/vdso/note.S deleted file mode 100644 index 0aeaa19b05f0..000000000000 --- a/arch/nds32/kernel/vdso/note.S +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2012 ARM Limited -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include - -ELFNOTE_START(Linux, 0, "a") - .long LINUX_VERSION_CODE -ELFNOTE_END diff --git a/arch/nds32/kernel/vdso/sigreturn.S b/arch/nds32/kernel/vdso/sigreturn.S deleted file mode 100644 index 67e4d1d1612a..000000000000 --- a/arch/nds32/kernel/vdso/sigreturn.S +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2012 ARM Limited -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include - - .text - -ENTRY(__kernel_rt_sigreturn) - .cfi_startproc - movi $r15, __NR_rt_sigreturn - /* - * The SWID of syscall should be __NR_rt_sigreturn to synchronize - * the unwinding scheme in gcc - */ - syscall __NR_rt_sigreturn - .cfi_endproc -ENDPROC(__kernel_rt_sigreturn) diff --git a/arch/nds32/kernel/vdso/vdso.S b/arch/nds32/kernel/vdso/vdso.S deleted file mode 100644 index 16737c11e55b..000000000000 --- a/arch/nds32/kernel/vdso/vdso.S +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2012 ARM Limited -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include - - .globl vdso_start, vdso_end - .section .rodata - .balign PAGE_SIZE -vdso_start: - .incbin "arch/nds32/kernel/vdso/vdso.so" - .balign PAGE_SIZE -vdso_end: - - .previous diff --git a/arch/nds32/kernel/vdso/vdso.lds.S b/arch/nds32/kernel/vdso/vdso.lds.S deleted file mode 100644 index 1f2b16004594..000000000000 --- a/arch/nds32/kernel/vdso/vdso.lds.S +++ /dev/null @@ -1,75 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 - * Copyright (C) 2005-2017 Andes Technology Corporation - */ - - -#include -#include -#include - -OUTPUT_ARCH(nds32) - -SECTIONS -{ - . = SIZEOF_HEADERS; - - .hash : { *(.hash) } :text - .gnu.hash : { *(.gnu.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .gnu.version : { *(.gnu.version) } - .gnu.version_d : { *(.gnu.version_d) } - .gnu.version_r : { *(.gnu.version_r) } - - .note : { *(.note.*) } :text :note - - - .text : { *(.text*) } :text - - .eh_frame_hdr : { *(.eh_frame_hdr) } :text :eh_frame_hdr - .eh_frame : { KEEP (*(.eh_frame)) } :text - - .dynamic : { *(.dynamic) } :text :dynamic - - .rodata : { *(.rodata*) } :text - - - /DISCARD/ : { - *(.note.GNU-stack) - *(.data .data.* .gnu.linkonce.d.* .sdata*) - *(.bss .sbss .dynbss .dynsbss) - } -} - -/* - * We must supply the ELF program headers explicitly to get just one - * PT_LOAD segment, and set the flags explicitly to make segments read-only. - */ -PHDRS -{ - text PT_LOAD FLAGS(5) FILEHDR PHDRS; /* PF_R|PF_X */ - dynamic PT_DYNAMIC FLAGS(4); /* PF_R */ - note PT_NOTE FLAGS(4); /* PF_R */ - eh_frame_hdr PT_GNU_EH_FRAME; -} - -/* - * This controls what symbols we export from the DSO. - */ -VERSION -{ - LINUX_4 { - global: - __kernel_rt_sigreturn; - __vdso_gettimeofday; - __vdso_clock_getres; - __vdso_clock_gettime; - local: *; - }; -} - -/* - * Make the rt_sigreturn code visible to the kernel. - */ -VDSO_rt_sigtramp = __kernel_rt_sigreturn; diff --git a/arch/nds32/kernel/vmlinux.lds.S b/arch/nds32/kernel/vmlinux.lds.S deleted file mode 100644 index 6a91b965fb1e..000000000000 --- a/arch/nds32/kernel/vmlinux.lds.S +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include - -#define LOAD_OFFSET (PAGE_OFFSET - PHYS_OFFSET) -#include - -OUTPUT_ARCH(nds32) -ENTRY(_stext_lma) -jiffies = jiffies_64; - -#if defined(CONFIG_GCOV_KERNEL) -#define NDS32_EXIT_KEEP(x) x -#else -#define NDS32_EXIT_KEEP(x) -#endif - -SECTIONS -{ - _stext_lma = TEXTADDR - LOAD_OFFSET; - . = TEXTADDR; - __init_begin = .; - HEAD_TEXT_SECTION - .exit.text : { - NDS32_EXIT_KEEP(EXIT_TEXT) - } - INIT_TEXT_SECTION(PAGE_SIZE) - INIT_DATA_SECTION(16) - .exit.data : { - NDS32_EXIT_KEEP(EXIT_DATA) - } - PERCPU_SECTION(L1_CACHE_BYTES) - __init_end = .; - - . = ALIGN(PAGE_SIZE); - _stext = .; - /* Real text segment */ - .text : AT(ADDR(.text) - LOAD_OFFSET) { - _text = .; /* Text and read-only data */ - TEXT_TEXT - SCHED_TEXT - CPUIDLE_TEXT - LOCK_TEXT - KPROBES_TEXT - IRQENTRY_TEXT - SOFTIRQENTRY_TEXT - *(.fixup) - } - - _etext = .; /* End of text and rodata section */ - - _sdata = .; - RO_DATA(PAGE_SIZE) - RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE) - _edata = .; - - EXCEPTION_TABLE(16) - BSS_SECTION(4, 4, 4) - _end = .; - - STABS_DEBUG - DWARF_DEBUG - ELF_DETAILS - - DISCARDS -} diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile deleted file mode 100644 index dddbc15d6b37..000000000000 --- a/arch/nds32/lib/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -lib-y := copy_page.o memcpy.o memmove.o \ - memset.o memzero.o \ - copy_from_user.o copy_to_user.o clear_user.o diff --git a/arch/nds32/lib/clear_user.S b/arch/nds32/lib/clear_user.S deleted file mode 100644 index 805dfcd25bf8..000000000000 --- a/arch/nds32/lib/clear_user.S +++ /dev/null @@ -1,42 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include - -/* Prototype: int __arch_clear_user(void *addr, size_t sz) - * Purpose : clear some user memory - * Params : addr - user memory address to clear - * : sz - number of bytes to clear - * Returns : number of bytes NOT cleared - */ - .text - .align 5 -ENTRY(__arch_clear_user) - add $r5, $r0, $r1 - beqz $r1, clear_exit - xor $p1, $p1, $p1 ! Use $p1=0 to clear mem - srli $p0, $r1, #2 ! $p0 = number of word to clear - andi $r1, $r1, #3 ! Bytes less than a word to copy - beqz $p0, byte_clear ! Only less than a word to clear -word_clear: -USER( smw.bim,$p1, [$r0], $p1) ! Clear the word - addi $p0, $p0, #-1 ! Decrease word count - bnez $p0, word_clear ! Continue looping to clear all words - beqz $r1, clear_exit ! No left bytes to copy -byte_clear: -USER( sbi.bi, $p1, [$r0], #1) ! Clear the byte - addi $r1, $r1, #-1 ! Decrease byte count - bnez $r1, byte_clear ! Continue looping to clear all left bytes -clear_exit: - move $r0, $r1 ! Set return value - ret - - .section .fixup,"ax" - .align 0 -9001: - sub $r0, $r5, $r0 ! Bytes left to copy - ret - .previous -ENDPROC(__arch_clear_user) diff --git a/arch/nds32/lib/copy_from_user.S b/arch/nds32/lib/copy_from_user.S deleted file mode 100644 index ad1857b20067..000000000000 --- a/arch/nds32/lib/copy_from_user.S +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include - -.macro lbi1 dst, addr, adj -USER( lbi.bi, \dst, [\addr], \adj) -.endm - -.macro sbi1 src, addr, adj -sbi.bi \src, [\addr], \adj -.endm - -.macro lmw1 start_reg, addr, end_reg -USER( lmw.bim, \start_reg, [\addr], \end_reg) -.endm - -.macro smw1 start_reg, addr, end_reg -smw.bim \start_reg, [\addr], \end_reg -.endm - - -/* Prototype: int __arch_copy_from_user(void *to, const char *from, size_t n) - * Purpose : copy a block from user memory to kernel memory - * Params : to - kernel memory - * : from - user memory - * : n - number of bytes to copy - * Returns : Number of bytes NOT copied. - */ - -.text -ENTRY(__arch_copy_from_user) - add $r5, $r0, $r2 -#include "copy_template.S" - move $r0, $r2 - ret -.section .fixup,"ax" -.align 2 -9001: - sub $r0, $r5, $r0 - ret -.previous -ENDPROC(__arch_copy_from_user) diff --git a/arch/nds32/lib/copy_page.S b/arch/nds32/lib/copy_page.S deleted file mode 100644 index f8701ed161a8..000000000000 --- a/arch/nds32/lib/copy_page.S +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include - - .text -ENTRY(copy_page) - pushm $r2, $r10 - movi $r2, PAGE_SIZE >> 5 -.Lcopy_loop: - lmw.bim $r3, [$r1], $r10 - smw.bim $r3, [$r0], $r10 - subi45 $r2, #1 - bnez38 $r2, .Lcopy_loop - popm $r2, $r10 - ret -ENDPROC(copy_page) -EXPORT_SYMBOL(copy_page) - -ENTRY(clear_page) - pushm $r1, $r9 - movi $r1, PAGE_SIZE >> 5 - movi55 $r2, #0 - movi55 $r3, #0 - movi55 $r4, #0 - movi55 $r5, #0 - movi55 $r6, #0 - movi55 $r7, #0 - movi55 $r8, #0 - movi55 $r9, #0 -.Lclear_loop: - smw.bim $r2, [$r0], $r9 - subi45 $r1, #1 - bnez38 $r1, .Lclear_loop - popm $r1, $r9 - ret -ENDPROC(clear_page) -EXPORT_SYMBOL(clear_page) diff --git a/arch/nds32/lib/copy_template.S b/arch/nds32/lib/copy_template.S deleted file mode 100644 index 3a9a2de468c2..000000000000 --- a/arch/nds32/lib/copy_template.S +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - - - beq $r1, $r0, quit_memcpy - beqz $r2, quit_memcpy - srli $r3, $r2, #5 ! check if len < cache-line size 32 - beqz $r3, word_copy_entry - andi $r4, $r0, #0x3 ! check byte-align - beqz $r4, unalign_word_copy_entry - - addi $r4, $r4,#-4 - abs $r4, $r4 ! check how many un-align byte to copy - sub $r2, $r2, $r4 ! update $R2 - -unalign_byte_copy: - lbi1 $r3, $r1, #1 - addi $r4, $r4, #-1 - sbi1 $r3, $r0, #1 - bnez $r4, unalign_byte_copy - beqz $r2, quit_memcpy - -unalign_word_copy_entry: - andi $r3, $r0, 0x1f ! check cache-line unaligncount - beqz $r3, cache_copy - - addi $r3, $r3, #-32 - abs $r3, $r3 - sub $r2, $r2, $r3 ! update $R2 - -unalign_word_copy: - lmw1 $r4, $r1, $r4 - addi $r3, $r3, #-4 - smw1 $r4, $r0, $r4 - bnez $r3, unalign_word_copy - beqz $r2, quit_memcpy - - addi $r3, $r2, #-32 ! to check $r2< cache_line , than go to word_copy - bltz $r3, word_copy_entry -cache_copy: - srli $r3, $r2, #5 - beqz $r3, word_copy_entry -3: - lmw1 $r17, $r1, $r24 - addi $r3, $r3, #-1 - smw1 $r17, $r0, $r24 - bnez $r3, 3b - -word_copy_entry: - andi $r2, $r2, #31 - - beqz $r2, quit_memcpy -5: - srli $r3, $r2, #2 - beqz $r3, byte_copy -word_copy: - lmw1 $r4, $r1, $r4 - addi $r3, $r3, #-1 - smw1 $r4, $r0, $r4 - bnez $r3, word_copy - andi $r2, $r2, #3 - beqz $r2, quit_memcpy -byte_copy: - lbi1 $r3, $r1, #1 - addi $r2, $r2, #-1 - - sbi1 $r3, $r0, #1 - bnez $r2, byte_copy -quit_memcpy: diff --git a/arch/nds32/lib/copy_to_user.S b/arch/nds32/lib/copy_to_user.S deleted file mode 100644 index 3230044dcfb8..000000000000 --- a/arch/nds32/lib/copy_to_user.S +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include - -.macro lbi1 dst, addr, adj -lbi.bi \dst, [\addr], \adj -.endm - -.macro sbi1 src, addr, adj -USER( sbi.bi, \src, [\addr], \adj) -.endm - -.macro lmw1 start_reg, addr, end_reg -lmw.bim \start_reg, [\addr], \end_reg -.endm - -.macro smw1 start_reg, addr, end_reg -USER( smw.bim, \start_reg, [\addr], \end_reg) -.endm - - -/* Prototype: int __arch_copy_to_user(void *to, const char *from, size_t n) - * Purpose : copy a block to user memory from kernel memory - * Params : to - user memory - * : from - kernel memory - * : n - number of bytes to copy - * Returns : Number of bytes NOT copied. - */ - -.text -ENTRY(__arch_copy_to_user) - add $r5, $r0, $r2 -#include "copy_template.S" - move $r0, $r2 - ret -.section .fixup,"ax" -.align 2 -9001: - sub $r0, $r5, $r0 - ret -.previous -ENDPROC(__arch_copy_to_user) diff --git a/arch/nds32/lib/memcpy.S b/arch/nds32/lib/memcpy.S deleted file mode 100644 index a2345ea721e4..000000000000 --- a/arch/nds32/lib/memcpy.S +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include - - -.macro lbi1 dst, addr, adj -lbi.bi \dst, [\addr], \adj -.endm - -.macro sbi1 src, addr, adj -sbi.bi \src, [\addr], \adj -.endm - -.macro lmw1 start_reg, addr, end_reg -lmw.bim \start_reg, [\addr], \end_reg -.endm - -.macro smw1 start_reg, addr, end_reg -smw.bim \start_reg, [\addr], \end_reg -.endm - -.text -ENTRY(memcpy) - move $r5, $r0 -#include "copy_template.S" - move $r0, $r5 - ret - -ENDPROC(memcpy) diff --git a/arch/nds32/lib/memmove.S b/arch/nds32/lib/memmove.S deleted file mode 100644 index c823aada2271..000000000000 --- a/arch/nds32/lib/memmove.S +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include - -/* - void *memmove(void *dst, const void *src, int n); - - dst: $r0 - src: $r1 - n : $r2 - ret: $r0 - pointer to the memory area dst. -*/ - .text - -ENTRY(memmove) - move $r5, $r0 ! Set return value = det - beq $r0, $r1, exit_memcpy ! Exit when det = src - beqz $r2, exit_memcpy ! Exit when n = 0 - pushm $t0, $t1 ! Save reg - srli $p1, $r2, #2 ! $p1 is how many words to copy - - ! Avoid data lost when memory overlap - ! Copy data reversely when src < dst - slt $p0, $r0, $r1 ! check if $r0 < $r1 - beqz $p0, do_reverse ! branch if dst > src - - ! No reverse, dst < src - andi $r2, $r2, #3 ! How many bytes are less than a word - li $t0, #1 ! Determining copy direction in byte_cpy - beqz $p1, byte_cpy ! When n is less than a word - -word_cpy: - lmw.bim $p0, [$r1], $p0 ! Read a word from src - addi $p1, $p1, #-1 ! How many words left to copy - smw.bim $p0, [$r0], $p0 ! Copy the word to det - bnez $p1, word_cpy ! If remained words > 0 - beqz $r2, end_memcpy ! No left bytes to copy - b byte_cpy - -do_reverse: - add $r0, $r0, $r2 ! Start with the end of $r0 - add $r1, $r1, $r2 ! Start with the end of $r1 - andi $r2, $r2, #3 ! How many bytes are less than a word - li $t0, #-1 ! Determining copy direction in byte_cpy - beqz $p1, reverse_byte_cpy ! When n is less than a word - -reverse_word_cpy: - lmw.adm $p0, [$r1], $p0 ! Read a word from src - addi $p1, $p1, #-1 ! How many words left to copy - smw.adm $p0, [$r0], $p0 ! Copy the word to det - bnez $p1, reverse_word_cpy ! If remained words > 0 - beqz $r2, end_memcpy ! No left bytes to copy - -reverse_byte_cpy: - addi $r0, $r0, #-1 - addi $r1, $r1, #-1 -byte_cpy: ! Less than 4 bytes to copy now - lb.bi $p0, [$r1], $t0 ! Read a byte from src - addi $r2, $r2, #-1 ! How many bytes left to copy - sb.bi $p0, [$r0], $t0 ! copy the byte to det - bnez $r2, byte_cpy ! If remained bytes > 0 - -end_memcpy: - popm $t0, $t1 -exit_memcpy: - move $r0, $r5 - ret - -ENDPROC(memmove) diff --git a/arch/nds32/lib/memset.S b/arch/nds32/lib/memset.S deleted file mode 100644 index 193cb6ce21a9..000000000000 --- a/arch/nds32/lib/memset.S +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include - - .text -ENTRY(memset) - move $r5, $r0 ! Return value - beqz $r2, end_memset ! Exit when len = 0 - srli $p1, $r2, 2 ! $p1 is how many words to copy - andi $r2, $r2, 3 ! How many bytes are less than a word - beqz $p1, byte_set ! When n is less than a word - - ! set $r1 from ??????ab to abababab - andi $r1, $r1, #0x00ff ! $r1 = 000000ab - slli $p0, $r1, #8 ! $p0 = 0000ab00 - or $r1, $r1, $p0 ! $r1 = 0000abab - slli $p0, $r1, #16 ! $p0 = abab0000 - or $r1, $r1, $p0 ! $r1 = abababab -word_set: - addi $p1, $p1, #-1 ! How many words left to copy - smw.bim $r1, [$r0], $r1 ! Copy the word to det - bnez $p1, word_set ! Still words to set, continue looping - beqz $r2, end_memset ! No left byte to set -byte_set: ! Less than 4 bytes left to set - addi $r2, $r2, #-1 ! Decrease len by 1 - sbi.bi $r1, [$r0], #1 ! Set data of the next byte to $r1 - bnez $r2, byte_set ! Still bytes left to set -end_memset: - move $r0, $r5 - ret - -ENDPROC(memset) diff --git a/arch/nds32/lib/memzero.S b/arch/nds32/lib/memzero.S deleted file mode 100644 index f055972c9343..000000000000 --- a/arch/nds32/lib/memzero.S +++ /dev/null @@ -1,18 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include - - .text -ENTRY(memzero) - beqz $r1, 1f - push $lp - move $r2, $r1 - move $r1, #0 - push $r0 - bal memset - pop $r0 - pop $lp -1: - ret -ENDPROC(memzero) diff --git a/arch/nds32/math-emu/Makefile b/arch/nds32/math-emu/Makefile deleted file mode 100644 index 3bed7e5d5d05..000000000000 --- a/arch/nds32/math-emu/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Makefile for the Linux/nds32 kernel FPU emulation. -# - -obj-y := fpuemu.o \ - fdivd.o fmuld.o fsubd.o faddd.o fs2d.o fsqrtd.o fcmpd.o fnegs.o \ - fd2si.o fd2ui.o fd2siz.o fd2uiz.o fsi2d.o fui2d.o \ - fdivs.o fmuls.o fsubs.o fadds.o fd2s.o fsqrts.o fcmps.o fnegd.o \ - fs2si.o fs2ui.o fs2siz.o fs2uiz.o fsi2s.o fui2s.o diff --git a/arch/nds32/math-emu/faddd.c b/arch/nds32/math-emu/faddd.c deleted file mode 100644 index f7fd4e3c3904..000000000000 --- a/arch/nds32/math-emu/faddd.c +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include - -#include -#include -#include -void faddd(void *ft, void *fa, void *fb) -{ - FP_DECL_D(A); - FP_DECL_D(B); - FP_DECL_D(R); - FP_DECL_EX; - - FP_UNPACK_DP(A, fa); - FP_UNPACK_DP(B, fb); - - FP_ADD_D(R, A, B); - - FP_PACK_DP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - -} diff --git a/arch/nds32/math-emu/fadds.c b/arch/nds32/math-emu/fadds.c deleted file mode 100644 index f5af6ca8cca5..000000000000 --- a/arch/nds32/math-emu/fadds.c +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include - -#include -#include -#include -void fadds(void *ft, void *fa, void *fb) -{ - FP_DECL_S(A); - FP_DECL_S(B); - FP_DECL_S(R); - FP_DECL_EX; - - FP_UNPACK_SP(A, fa); - FP_UNPACK_SP(B, fb); - - FP_ADD_S(R, A, B); - - FP_PACK_SP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - -} diff --git a/arch/nds32/math-emu/fcmpd.c b/arch/nds32/math-emu/fcmpd.c deleted file mode 100644 index 0ea225abe880..000000000000 --- a/arch/nds32/math-emu/fcmpd.c +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include -#include -#include -int fcmpd(void *ft, void *fa, void *fb, int cmpop) -{ - FP_DECL_D(A); - FP_DECL_D(B); - FP_DECL_EX; - long cmp; - - FP_UNPACK_DP(A, fa); - FP_UNPACK_DP(B, fb); - - FP_CMP_D(cmp, A, B, SF_CUN); - cmp += 2; - if (cmp == SF_CGT) - *(long *)ft = 0; - else - *(long *)ft = (cmp & cmpop) ? 1 : 0; - - return 0; -} diff --git a/arch/nds32/math-emu/fcmps.c b/arch/nds32/math-emu/fcmps.c deleted file mode 100644 index 681480758213..000000000000 --- a/arch/nds32/math-emu/fcmps.c +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include -#include -#include -int fcmps(void *ft, void *fa, void *fb, int cmpop) -{ - FP_DECL_S(A); - FP_DECL_S(B); - FP_DECL_EX; - long cmp; - - FP_UNPACK_SP(A, fa); - FP_UNPACK_SP(B, fb); - - FP_CMP_S(cmp, A, B, SF_CUN); - cmp += 2; - if (cmp == SF_CGT) - *(int *)ft = 0x0; - else - *(int *)ft = (cmp & cmpop) ? 0x1 : 0x0; - - return 0; -} diff --git a/arch/nds32/math-emu/fd2s.c b/arch/nds32/math-emu/fd2s.c deleted file mode 100644 index 1328371e8170..000000000000 --- a/arch/nds32/math-emu/fd2s.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include - -#include -#include -#include -#include -void fd2s(void *ft, void *fa) -{ - FP_DECL_D(A); - FP_DECL_S(R); - FP_DECL_EX; - - FP_UNPACK_DP(A, fa); - - FP_CONV(S, D, 1, 2, R, A); - - FP_PACK_SP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fd2si.c b/arch/nds32/math-emu/fd2si.c deleted file mode 100644 index fae3e16a0a10..000000000000 --- a/arch/nds32/math-emu/fd2si.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fd2si(void *ft, void *fa) -{ - int r; - - FP_DECL_D(A); - FP_DECL_EX; - - FP_UNPACK_DP(A, fa); - - if (A_c == FP_CLS_INF) { - *(int *)ft = (A_s == 0) ? 0x7fffffff : 0x80000000; - __FPU_FPCSR |= FP_EX_INVALID; - } else if (A_c == FP_CLS_NAN) { - *(int *)ft = 0xffffffff; - __FPU_FPCSR |= FP_EX_INVALID; - } else { - FP_TO_INT_ROUND_D(r, A, 32, 1); - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - *(int *)ft = r; - } - -} diff --git a/arch/nds32/math-emu/fd2siz.c b/arch/nds32/math-emu/fd2siz.c deleted file mode 100644 index 92fe6774f112..000000000000 --- a/arch/nds32/math-emu/fd2siz.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fd2si_z(void *ft, void *fa) -{ - int r; - - FP_DECL_D(A); - FP_DECL_EX; - - FP_UNPACK_DP(A, fa); - - if (A_c == FP_CLS_INF) { - *(int *)ft = (A_s == 0) ? 0x7fffffff : 0x80000000; - __FPU_FPCSR |= FP_EX_INVALID; - } else if (A_c == FP_CLS_NAN) { - *(int *)ft = 0xffffffff; - __FPU_FPCSR |= FP_EX_INVALID; - } else { - FP_TO_INT_D(r, A, 32, 1); - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - *(int *)ft = r; - } - -} diff --git a/arch/nds32/math-emu/fd2ui.c b/arch/nds32/math-emu/fd2ui.c deleted file mode 100644 index a0423b699aa4..000000000000 --- a/arch/nds32/math-emu/fd2ui.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fd2ui(void *ft, void *fa) -{ - unsigned int r; - - FP_DECL_D(A); - FP_DECL_EX; - - FP_UNPACK_DP(A, fa); - - if (A_c == FP_CLS_INF) { - *(unsigned int *)ft = (A_s == 0) ? 0xffffffff : 0x00000000; - __FPU_FPCSR |= FP_EX_INVALID; - } else if (A_c == FP_CLS_NAN) { - *(unsigned int *)ft = 0xffffffff; - __FPU_FPCSR |= FP_EX_INVALID; - } else { - FP_TO_INT_ROUND_D(r, A, 32, 0); - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - *(unsigned int *)ft = r; - } - -} diff --git a/arch/nds32/math-emu/fd2uiz.c b/arch/nds32/math-emu/fd2uiz.c deleted file mode 100644 index 8ae17cfce90d..000000000000 --- a/arch/nds32/math-emu/fd2uiz.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fd2ui_z(void *ft, void *fa) -{ - unsigned int r; - - FP_DECL_D(A); - FP_DECL_EX; - - FP_UNPACK_DP(A, fa); - - if (A_c == FP_CLS_INF) { - *(unsigned int *)ft = (A_s == 0) ? 0xffffffff : 0x00000000; - __FPU_FPCSR |= FP_EX_INVALID; - } else if (A_c == FP_CLS_NAN) { - *(unsigned int *)ft = 0xffffffff; - __FPU_FPCSR |= FP_EX_INVALID; - } else { - FP_TO_INT_D(r, A, 32, 0); - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - *(unsigned int *)ft = r; - } - -} diff --git a/arch/nds32/math-emu/fdivd.c b/arch/nds32/math-emu/fdivd.c deleted file mode 100644 index 458e7e98b08e..000000000000 --- a/arch/nds32/math-emu/fdivd.c +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation - -#include -#include -#include -#include - -void fdivd(void *ft, void *fa, void *fb) -{ - FP_DECL_D(A); - FP_DECL_D(B); - FP_DECL_D(R); - FP_DECL_EX; - - FP_UNPACK_DP(A, fa); - FP_UNPACK_DP(B, fb); - - if (B_c == FP_CLS_ZERO && A_c != FP_CLS_ZERO) - FP_SET_EXCEPTION(FP_EX_DIVZERO); - - FP_DIV_D(R, A, B); - - FP_PACK_DP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fdivs.c b/arch/nds32/math-emu/fdivs.c deleted file mode 100644 index c7d202159ce2..000000000000 --- a/arch/nds32/math-emu/fdivs.c +++ /dev/null @@ -1,26 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include - -#include -#include -#include -void fdivs(void *ft, void *fa, void *fb) -{ - FP_DECL_S(A); - FP_DECL_S(B); - FP_DECL_S(R); - FP_DECL_EX; - - FP_UNPACK_SP(A, fa); - FP_UNPACK_SP(B, fb); - - if (B_c == FP_CLS_ZERO && A_c != FP_CLS_ZERO) - FP_SET_EXCEPTION(FP_EX_DIVZERO); - - FP_DIV_S(R, A, B); - - FP_PACK_SP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fmuld.c b/arch/nds32/math-emu/fmuld.c deleted file mode 100644 index f3c77a45ddc2..000000000000 --- a/arch/nds32/math-emu/fmuld.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include - -#include -#include -#include -void fmuld(void *ft, void *fa, void *fb) -{ - FP_DECL_D(A); - FP_DECL_D(B); - FP_DECL_D(R); - FP_DECL_EX; - - FP_UNPACK_DP(A, fa); - FP_UNPACK_DP(B, fb); - - FP_MUL_D(R, A, B); - - FP_PACK_DP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fmuls.c b/arch/nds32/math-emu/fmuls.c deleted file mode 100644 index cf150df938f9..000000000000 --- a/arch/nds32/math-emu/fmuls.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include - -#include -#include -#include -void fmuls(void *ft, void *fa, void *fb) -{ - FP_DECL_S(A); - FP_DECL_S(B); - FP_DECL_S(R); - FP_DECL_EX; - - FP_UNPACK_SP(A, fa); - FP_UNPACK_SP(B, fb); - - FP_MUL_S(R, A, B); - - FP_PACK_SP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fnegd.c b/arch/nds32/math-emu/fnegd.c deleted file mode 100644 index de7ea6a0873e..000000000000 --- a/arch/nds32/math-emu/fnegd.c +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include - -#include -#include -#include -void fnegd(void *ft, void *fa) -{ - FP_DECL_D(A); - FP_DECL_D(R); - FP_DECL_EX; - - FP_UNPACK_DP(A, fa); - - FP_NEG_D(R, A); - - FP_PACK_DP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fnegs.c b/arch/nds32/math-emu/fnegs.c deleted file mode 100644 index 07270b326a77..000000000000 --- a/arch/nds32/math-emu/fnegs.c +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include - -#include -#include -#include -void fnegs(void *ft, void *fa) -{ - FP_DECL_S(A); - FP_DECL_S(R); - FP_DECL_EX; - - FP_UNPACK_SP(A, fa); - - FP_NEG_S(R, A); - - FP_PACK_SP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fpuemu.c b/arch/nds32/math-emu/fpuemu.c deleted file mode 100644 index 46558a15c0dc..000000000000 --- a/arch/nds32/math-emu/fpuemu.c +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation - -#include -#include -#include -#include -#include - -#define DPFROMREG(dp, x) (dp = (void *)((unsigned long *)fpu_reg + 2*x)) -#ifdef __NDS32_EL__ -#define SPFROMREG(sp, x)\ - ((sp) = (void *)((unsigned long *)fpu_reg + (x^1))) -#else -#define SPFROMREG(sp, x) ((sp) = (void *)((unsigned long *)fpu_reg + x)) -#endif - -#define DEF3OP(name, p, f1, f2) \ -void fpemu_##name##p(void *ft, void *fa, void *fb) \ -{ \ - f1(fa, fa, fb); \ - f2(ft, ft, fa); \ -} - -#define DEF3OPNEG(name, p, f1, f2, f3) \ -void fpemu_##name##p(void *ft, void *fa, void *fb) \ -{ \ - f1(fa, fa, fb); \ - f2(ft, ft, fa); \ - f3(ft, ft); \ -} -DEF3OP(fmadd, s, fmuls, fadds); -DEF3OP(fmsub, s, fmuls, fsubs); -DEF3OP(fmadd, d, fmuld, faddd); -DEF3OP(fmsub, d, fmuld, fsubd); -DEF3OPNEG(fnmadd, s, fmuls, fadds, fnegs); -DEF3OPNEG(fnmsub, s, fmuls, fsubs, fnegs); -DEF3OPNEG(fnmadd, d, fmuld, faddd, fnegd); -DEF3OPNEG(fnmsub, d, fmuld, fsubd, fnegd); - -static const unsigned char cmptab[8] = { - SF_CEQ, - SF_CEQ, - SF_CLT, - SF_CLT, - SF_CLT | SF_CEQ, - SF_CLT | SF_CEQ, - SF_CUN, - SF_CUN -}; - -enum ARGTYPE { - S1S = 1, - S2S, - S1D, - CS, - D1D, - D2D, - D1S, - CD -}; -union func_t { - void (*t)(void *ft, void *fa, void *fb); - void (*b)(void *ft, void *fa); -}; -/* - * Emulate a single FPU arithmetic instruction. - */ -static int fpu_emu(struct fpu_struct *fpu_reg, unsigned long insn) -{ - int rfmt; /* resulting format */ - union func_t func; - int ftype = 0; - - switch (rfmt = NDS32Insn_OPCODE_COP0(insn)) { - case fs1_op:{ - switch (NDS32Insn_OPCODE_BIT69(insn)) { - case fadds_op: - func.t = fadds; - ftype = S2S; - break; - case fsubs_op: - func.t = fsubs; - ftype = S2S; - break; - case fmadds_op: - func.t = fpemu_fmadds; - ftype = S2S; - break; - case fmsubs_op: - func.t = fpemu_fmsubs; - ftype = S2S; - break; - case fnmadds_op: - func.t = fpemu_fnmadds; - ftype = S2S; - break; - case fnmsubs_op: - func.t = fpemu_fnmsubs; - ftype = S2S; - break; - case fmuls_op: - func.t = fmuls; - ftype = S2S; - break; - case fdivs_op: - func.t = fdivs; - ftype = S2S; - break; - case fs1_f2op_op: - switch (NDS32Insn_OPCODE_BIT1014(insn)) { - case fs2d_op: - func.b = fs2d; - ftype = S1D; - break; - case fs2si_op: - func.b = fs2si; - ftype = S1S; - break; - case fs2si_z_op: - func.b = fs2si_z; - ftype = S1S; - break; - case fs2ui_op: - func.b = fs2ui; - ftype = S1S; - break; - case fs2ui_z_op: - func.b = fs2ui_z; - ftype = S1S; - break; - case fsi2s_op: - func.b = fsi2s; - ftype = S1S; - break; - case fui2s_op: - func.b = fui2s; - ftype = S1S; - break; - case fsqrts_op: - func.b = fsqrts; - ftype = S1S; - break; - default: - return SIGILL; - } - break; - default: - return SIGILL; - } - break; - } - case fs2_op: - switch (NDS32Insn_OPCODE_BIT69(insn)) { - case fcmpeqs_op: - case fcmpeqs_e_op: - case fcmplts_op: - case fcmplts_e_op: - case fcmples_op: - case fcmples_e_op: - case fcmpuns_op: - case fcmpuns_e_op: - ftype = CS; - break; - default: - return SIGILL; - } - break; - case fd1_op:{ - switch (NDS32Insn_OPCODE_BIT69(insn)) { - case faddd_op: - func.t = faddd; - ftype = D2D; - break; - case fsubd_op: - func.t = fsubd; - ftype = D2D; - break; - case fmaddd_op: - func.t = fpemu_fmaddd; - ftype = D2D; - break; - case fmsubd_op: - func.t = fpemu_fmsubd; - ftype = D2D; - break; - case fnmaddd_op: - func.t = fpemu_fnmaddd; - ftype = D2D; - break; - case fnmsubd_op: - func.t = fpemu_fnmsubd; - ftype = D2D; - break; - case fmuld_op: - func.t = fmuld; - ftype = D2D; - break; - case fdivd_op: - func.t = fdivd; - ftype = D2D; - break; - case fd1_f2op_op: - switch (NDS32Insn_OPCODE_BIT1014(insn)) { - case fd2s_op: - func.b = fd2s; - ftype = D1S; - break; - case fd2si_op: - func.b = fd2si; - ftype = D1S; - break; - case fd2si_z_op: - func.b = fd2si_z; - ftype = D1S; - break; - case fd2ui_op: - func.b = fd2ui; - ftype = D1S; - break; - case fd2ui_z_op: - func.b = fd2ui_z; - ftype = D1S; - break; - case fsi2d_op: - func.b = fsi2d; - ftype = D1S; - break; - case fui2d_op: - func.b = fui2d; - ftype = D1S; - break; - case fsqrtd_op: - func.b = fsqrtd; - ftype = D1D; - break; - default: - return SIGILL; - } - break; - default: - return SIGILL; - - } - break; - } - - case fd2_op: - switch (NDS32Insn_OPCODE_BIT69(insn)) { - case fcmpeqd_op: - case fcmpeqd_e_op: - case fcmpltd_op: - case fcmpltd_e_op: - case fcmpled_op: - case fcmpled_e_op: - case fcmpund_op: - case fcmpund_e_op: - ftype = CD; - break; - default: - return SIGILL; - } - break; - - default: - return SIGILL; - } - - switch (ftype) { - case S1S:{ - void *ft, *fa; - - SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn)); - SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn)); - func.b(ft, fa); - break; - } - case S2S:{ - void *ft, *fa, *fb; - - SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn)); - SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn)); - SPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn)); - func.t(ft, fa, fb); - break; - } - case S1D:{ - void *ft, *fa; - - DPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn)); - SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn)); - func.b(ft, fa); - break; - } - case CS:{ - unsigned int cmpop = NDS32Insn_OPCODE_BIT69(insn); - void *ft, *fa, *fb; - - SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn)); - SPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn)); - SPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn)); - if (cmpop < 0x8) { - cmpop = cmptab[cmpop]; - fcmps(ft, fa, fb, cmpop); - } else - return SIGILL; - break; - } - case D1D:{ - void *ft, *fa; - - DPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn)); - DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn)); - func.b(ft, fa); - break; - } - case D2D:{ - void *ft, *fa, *fb; - - DPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn)); - DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn)); - DPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn)); - func.t(ft, fa, fb); - break; - } - case D1S:{ - void *ft, *fa; - - SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn)); - DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn)); - func.b(ft, fa); - break; - } - case CD:{ - unsigned int cmpop = NDS32Insn_OPCODE_BIT69(insn); - void *ft, *fa, *fb; - - SPFROMREG(ft, NDS32Insn_OPCODE_Rt(insn)); - DPFROMREG(fa, NDS32Insn_OPCODE_Ra(insn)); - DPFROMREG(fb, NDS32Insn_OPCODE_Rb(insn)); - if (cmpop < 0x8) { - cmpop = cmptab[cmpop]; - fcmpd(ft, fa, fb, cmpop); - } else - return SIGILL; - break; - } - default: - return SIGILL; - } - - /* - * If an exception is required, generate a tidy SIGFPE exception. - */ -#if IS_ENABLED(CONFIG_SUPPORT_DENORMAL_ARITHMETIC) - if (((fpu_reg->fpcsr << 5) & fpu_reg->fpcsr & FPCSR_mskALLE_NO_UDF_IEXE) - || ((fpu_reg->fpcsr << 5) & (fpu_reg->UDF_IEX_trap))) { -#else - if ((fpu_reg->fpcsr << 5) & fpu_reg->fpcsr & FPCSR_mskALLE) { -#endif - return SIGFPE; - } - return 0; -} - -int do_fpuemu(struct pt_regs *regs, struct fpu_struct *fpu) -{ - unsigned long insn = 0, addr = regs->ipc; - unsigned long emulpc, contpc; - unsigned char *pc = (void *)&insn; - char c; - int i = 0, ret; - - for (i = 0; i < 4; i++) { - if (__get_user(c, (unsigned char *)addr++)) - return SIGBUS; - *pc++ = c; - } - - insn = be32_to_cpu(insn); - - emulpc = regs->ipc; - contpc = regs->ipc + 4; - - if (NDS32Insn_OPCODE(insn) != cop0_op) - return SIGILL; - - switch (NDS32Insn_OPCODE_COP0(insn)) { - case fs1_op: - case fs2_op: - case fd1_op: - case fd2_op: - { - /* a real fpu computation instruction */ - ret = fpu_emu(fpu, insn); - if (!ret) - regs->ipc = contpc; - } - break; - - default: - return SIGILL; - } - - return ret; -} diff --git a/arch/nds32/math-emu/fs2d.c b/arch/nds32/math-emu/fs2d.c deleted file mode 100644 index 0e8db9035631..000000000000 --- a/arch/nds32/math-emu/fs2d.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation - -#include -#include -#include -#include -#include - -void fs2d(void *ft, void *fa) -{ - FP_DECL_S(A); - FP_DECL_D(R); - FP_DECL_EX; - - FP_UNPACK_SP(A, fa); - - FP_CONV(D, S, 2, 1, R, A); - - FP_PACK_DP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fs2si.c b/arch/nds32/math-emu/fs2si.c deleted file mode 100644 index b4931d60980e..000000000000 --- a/arch/nds32/math-emu/fs2si.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fs2si(void *ft, void *fa) -{ - int r; - - FP_DECL_S(A); - FP_DECL_EX; - - FP_UNPACK_SP(A, fa); - - if (A_c == FP_CLS_INF) { - *(int *)ft = (A_s == 0) ? 0x7fffffff : 0x80000000; - __FPU_FPCSR |= FP_EX_INVALID; - } else if (A_c == FP_CLS_NAN) { - *(int *)ft = 0xffffffff; - __FPU_FPCSR |= FP_EX_INVALID; - } else { - FP_TO_INT_ROUND_S(r, A, 32, 1); - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - *(int *)ft = r; - } -} diff --git a/arch/nds32/math-emu/fs2siz.c b/arch/nds32/math-emu/fs2siz.c deleted file mode 100644 index 1c2b99ce3e38..000000000000 --- a/arch/nds32/math-emu/fs2siz.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fs2si_z(void *ft, void *fa) -{ - int r; - - FP_DECL_S(A); - FP_DECL_EX; - - FP_UNPACK_SP(A, fa); - - if (A_c == FP_CLS_INF) { - *(int *)ft = (A_s == 0) ? 0x7fffffff : 0x80000000; - __FPU_FPCSR |= FP_EX_INVALID; - } else if (A_c == FP_CLS_NAN) { - *(int *)ft = 0xffffffff; - __FPU_FPCSR |= FP_EX_INVALID; - } else { - FP_TO_INT_S(r, A, 32, 1); - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - *(int *)ft = r; - } -} diff --git a/arch/nds32/math-emu/fs2ui.c b/arch/nds32/math-emu/fs2ui.c deleted file mode 100644 index c337f0384d06..000000000000 --- a/arch/nds32/math-emu/fs2ui.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fs2ui(void *ft, void *fa) -{ - unsigned int r; - - FP_DECL_S(A); - FP_DECL_EX; - - FP_UNPACK_SP(A, fa); - - if (A_c == FP_CLS_INF) { - *(unsigned int *)ft = (A_s == 0) ? 0xffffffff : 0x00000000; - __FPU_FPCSR |= FP_EX_INVALID; - } else if (A_c == FP_CLS_NAN) { - *(unsigned int *)ft = 0xffffffff; - __FPU_FPCSR |= FP_EX_INVALID; - } else { - FP_TO_INT_ROUND_S(r, A, 32, 0); - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - *(unsigned int *)ft = r; - } -} diff --git a/arch/nds32/math-emu/fs2uiz.c b/arch/nds32/math-emu/fs2uiz.c deleted file mode 100644 index 22c5e4768044..000000000000 --- a/arch/nds32/math-emu/fs2uiz.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fs2ui_z(void *ft, void *fa) -{ - unsigned int r; - - FP_DECL_S(A); - FP_DECL_EX; - - FP_UNPACK_SP(A, fa); - - if (A_c == FP_CLS_INF) { - *(unsigned int *)ft = (A_s == 0) ? 0xffffffff : 0x00000000; - __FPU_FPCSR |= FP_EX_INVALID; - } else if (A_c == FP_CLS_NAN) { - *(unsigned int *)ft = 0xffffffff; - __FPU_FPCSR |= FP_EX_INVALID; - } else { - FP_TO_INT_S(r, A, 32, 0); - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - *(unsigned int *)ft = r; - } - -} diff --git a/arch/nds32/math-emu/fsi2d.c b/arch/nds32/math-emu/fsi2d.c deleted file mode 100644 index 6b04cec0c5c5..000000000000 --- a/arch/nds32/math-emu/fsi2d.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fsi2d(void *ft, void *fa) -{ - int a = *(int *)fa; - - FP_DECL_D(R); - FP_DECL_EX; - - FP_FROM_INT_D(R, a, 32, int); - - FP_PACK_DP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - -} diff --git a/arch/nds32/math-emu/fsi2s.c b/arch/nds32/math-emu/fsi2s.c deleted file mode 100644 index 689864a5df90..000000000000 --- a/arch/nds32/math-emu/fsi2s.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fsi2s(void *ft, void *fa) -{ - int a = *(int *)fa; - - FP_DECL_S(R); - FP_DECL_EX; - - FP_FROM_INT_S(R, a, 32, int); - - FP_PACK_SP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - -} diff --git a/arch/nds32/math-emu/fsqrtd.c b/arch/nds32/math-emu/fsqrtd.c deleted file mode 100644 index c3a8dbd81d4e..000000000000 --- a/arch/nds32/math-emu/fsqrtd.c +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation - -#include -#include -#include -#include -void fsqrtd(void *ft, void *fa) -{ - FP_DECL_D(A); - FP_DECL_D(R); - FP_DECL_EX; - - FP_UNPACK_DP(A, fa); - - FP_SQRT_D(R, A); - - FP_PACK_DP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fsqrts.c b/arch/nds32/math-emu/fsqrts.c deleted file mode 100644 index 4c6f94b27328..000000000000 --- a/arch/nds32/math-emu/fsqrts.c +++ /dev/null @@ -1,21 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation - -#include -#include -#include -#include -void fsqrts(void *ft, void *fa) -{ - FP_DECL_S(A); - FP_DECL_S(R); - FP_DECL_EX; - - FP_UNPACK_SP(A, fa); - - FP_SQRT_S(R, A); - - FP_PACK_SP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fsubd.c b/arch/nds32/math-emu/fsubd.c deleted file mode 100644 index 81b6a0d02a1f..000000000000 --- a/arch/nds32/math-emu/fsubd.c +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include - -#include -#include -#include -void fsubd(void *ft, void *fa, void *fb) -{ - - FP_DECL_D(A); - FP_DECL_D(B); - FP_DECL_D(R); - FP_DECL_EX; - - FP_UNPACK_DP(A, fa); - FP_UNPACK_DP(B, fb); - - if (B_c != FP_CLS_NAN) - B_s ^= 1; - - FP_ADD_D(R, A, B); - - FP_PACK_DP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fsubs.c b/arch/nds32/math-emu/fsubs.c deleted file mode 100644 index 61ddd9708465..000000000000 --- a/arch/nds32/math-emu/fsubs.c +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2018 Andes Technology Corporation -#include - -#include -#include -#include -void fsubs(void *ft, void *fa, void *fb) -{ - - FP_DECL_S(A); - FP_DECL_S(B); - FP_DECL_S(R); - FP_DECL_EX; - - FP_UNPACK_SP(A, fa); - FP_UNPACK_SP(B, fb); - - if (B_c != FP_CLS_NAN) - B_s ^= 1; - - FP_ADD_S(R, A, B); - - FP_PACK_SP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; -} diff --git a/arch/nds32/math-emu/fui2d.c b/arch/nds32/math-emu/fui2d.c deleted file mode 100644 index 9689d33a8d50..000000000000 --- a/arch/nds32/math-emu/fui2d.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fui2d(void *ft, void *fa) -{ - unsigned int a = *(unsigned int *)fa; - - FP_DECL_D(R); - FP_DECL_EX; - - FP_FROM_INT_D(R, a, 32, int); - - FP_PACK_DP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - -} diff --git a/arch/nds32/math-emu/fui2s.c b/arch/nds32/math-emu/fui2s.c deleted file mode 100644 index f70f0762547d..000000000000 --- a/arch/nds32/math-emu/fui2s.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2019 Andes Technology Corporation -#include - -#include -#include -#include - -void fui2s(void *ft, void *fa) -{ - unsigned int a = *(unsigned int *)fa; - - FP_DECL_S(R); - FP_DECL_EX; - - FP_FROM_INT_S(R, a, 32, int); - - FP_PACK_SP(ft, R); - - __FPU_FPCSR |= FP_CUR_EXCEPTIONS; - -} diff --git a/arch/nds32/mm/Makefile b/arch/nds32/mm/Makefile deleted file mode 100644 index 14fb2e8eb036..000000000000 --- a/arch/nds32/mm/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -obj-y := extable.o tlb.o fault.o init.o mmap.o \ - mm-nds32.o cacheflush.o proc.o - -obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o - -ifdef CONFIG_FUNCTION_TRACER -CFLAGS_REMOVE_proc.o = $(CC_FLAGS_FTRACE) -endif -CFLAGS_proc.o += -fomit-frame-pointer diff --git a/arch/nds32/mm/alignment.c b/arch/nds32/mm/alignment.c deleted file mode 100644 index 1eb7ded6992b..000000000000 --- a/arch/nds32/mm/alignment.c +++ /dev/null @@ -1,578 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include - -#define DEBUG(enable, tagged, ...) \ - do{ \ - if (enable) { \ - if (tagged) \ - pr_warn("[ %30s() ] ", __func__); \ - pr_warn(__VA_ARGS__); \ - } \ - } while (0) - -#define RT(inst) (((inst) >> 20) & 0x1FUL) -#define RA(inst) (((inst) >> 15) & 0x1FUL) -#define RB(inst) (((inst) >> 10) & 0x1FUL) -#define SV(inst) (((inst) >> 8) & 0x3UL) -#define IMM(inst) (((inst) >> 0) & 0x7FFFUL) - -#define RA3(inst) (((inst) >> 3) & 0x7UL) -#define RT3(inst) (((inst) >> 6) & 0x7UL) -#define IMM3U(inst) (((inst) >> 0) & 0x7UL) - -#define RA5(inst) (((inst) >> 0) & 0x1FUL) -#define RT4(inst) (((inst) >> 5) & 0xFUL) - -#define GET_IMMSVAL(imm_value) \ - (((imm_value >> 14) & 0x1) ? (imm_value - 0x8000) : imm_value) - -#define __get8_data(val,addr,err) \ - __asm__( \ - "1: lbi.bi %1, [%2], #1\n" \ - "2:\n" \ - " .pushsection .text.fixup,\"ax\"\n" \ - " .align 2\n" \ - "3: movi %0, #1\n" \ - " j 2b\n" \ - " .popsection\n" \ - " .pushsection __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 3b\n" \ - " .popsection\n" \ - : "=r" (err), "=&r" (val), "=r" (addr) \ - : "0" (err), "2" (addr)) - -#define get16_data(addr, val_ptr) \ - do { \ - unsigned int err = 0, v, a = addr; \ - __get8_data(v,a,err); \ - *val_ptr = v << 0; \ - __get8_data(v,a,err); \ - *val_ptr |= v << 8; \ - if (err) \ - goto fault; \ - *val_ptr = le16_to_cpu(*val_ptr); \ - } while(0) - -#define get32_data(addr, val_ptr) \ - do { \ - unsigned int err = 0, v, a = addr; \ - __get8_data(v,a,err); \ - *val_ptr = v << 0; \ - __get8_data(v,a,err); \ - *val_ptr |= v << 8; \ - __get8_data(v,a,err); \ - *val_ptr |= v << 16; \ - __get8_data(v,a,err); \ - *val_ptr |= v << 24; \ - if (err) \ - goto fault; \ - *val_ptr = le32_to_cpu(*val_ptr); \ - } while(0) - -#define get_data(addr, val_ptr, len) \ - if (len == 2) \ - get16_data(addr, val_ptr); \ - else \ - get32_data(addr, val_ptr); - -#define set16_data(addr, val) \ - do { \ - unsigned int err = 0, *ptr = addr ; \ - val = le32_to_cpu(val); \ - __asm__( \ - "1: sbi.bi %2, [%1], #1\n" \ - " srli %2, %2, #8\n" \ - "2: sbi %2, [%1]\n" \ - "3:\n" \ - " .pushsection .text.fixup,\"ax\"\n" \ - " .align 2\n" \ - "4: movi %0, #1\n" \ - " j 3b\n" \ - " .popsection\n" \ - " .pushsection __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 4b\n" \ - " .long 2b, 4b\n" \ - " .popsection\n" \ - : "=r" (err), "+r" (ptr), "+r" (val) \ - : "0" (err) \ - ); \ - if (err) \ - goto fault; \ - } while(0) - -#define set32_data(addr, val) \ - do { \ - unsigned int err = 0, *ptr = addr ; \ - val = le32_to_cpu(val); \ - __asm__( \ - "1: sbi.bi %2, [%1], #1\n" \ - " srli %2, %2, #8\n" \ - "2: sbi.bi %2, [%1], #1\n" \ - " srli %2, %2, #8\n" \ - "3: sbi.bi %2, [%1], #1\n" \ - " srli %2, %2, #8\n" \ - "4: sbi %2, [%1]\n" \ - "5:\n" \ - " .pushsection .text.fixup,\"ax\"\n" \ - " .align 2\n" \ - "6: movi %0, #1\n" \ - " j 5b\n" \ - " .popsection\n" \ - " .pushsection __ex_table,\"a\"\n" \ - " .align 3\n" \ - " .long 1b, 6b\n" \ - " .long 2b, 6b\n" \ - " .long 3b, 6b\n" \ - " .long 4b, 6b\n" \ - " .popsection\n" \ - : "=r" (err), "+r" (ptr), "+r" (val) \ - : "0" (err) \ - ); \ - if (err) \ - goto fault; \ - } while(0) -#define set_data(addr, val, len) \ - if (len == 2) \ - set16_data(addr, val); \ - else \ - set32_data(addr, val); -#define NDS32_16BIT_INSTRUCTION 0x80000000 - -extern pte_t va_present(struct mm_struct *mm, unsigned long addr); -extern pte_t va_kernel_present(unsigned long addr); -extern int va_readable(struct pt_regs *regs, unsigned long addr); -extern int va_writable(struct pt_regs *regs, unsigned long addr); - -int unalign_access_mode = 0, unalign_access_debug = 0; - -static inline unsigned long *idx_to_addr(struct pt_regs *regs, int idx) -{ - /* this should be consistent with ptrace.h */ - if (idx >= 0 && idx <= 25) /* R0-R25 */ - return ®s->uregs[0] + idx; - else if (idx >= 28 && idx <= 30) /* FP, GP, LP */ - return ®s->fp + (idx - 28); - else if (idx == 31) /* SP */ - return ®s->sp; - else - return NULL; /* cause a segfault */ -} - -static inline unsigned long get_inst(unsigned long addr) -{ - return be32_to_cpu(get_unaligned((u32 *) addr)); -} - -static inline unsigned long sign_extend(unsigned long val, int len) -{ - unsigned long ret = 0; - unsigned char *s, *t; - int i = 0; - - val = cpu_to_le32(val); - - s = (void *)&val; - t = (void *)&ret; - - while (i++ < len) - *t++ = *s++; - - if (((*(t - 1)) & 0x80) && (i < 4)) { - - while (i++ <= 4) - *t++ = 0xff; - } - - return le32_to_cpu(ret); -} - -static inline int do_16(unsigned long inst, struct pt_regs *regs) -{ - int imm, regular, load, len, addr_mode, idx_mode; - unsigned long unaligned_addr, target_val, source_idx, target_idx, - shift = 0; - switch ((inst >> 9) & 0x3F) { - - case 0x12: /* LHI333 */ - imm = 1; - regular = 1; - load = 1; - len = 2; - addr_mode = 3; - idx_mode = 3; - break; - case 0x10: /* LWI333 */ - imm = 1; - regular = 1; - load = 1; - len = 4; - addr_mode = 3; - idx_mode = 3; - break; - case 0x11: /* LWI333.bi */ - imm = 1; - regular = 0; - load = 1; - len = 4; - addr_mode = 3; - idx_mode = 3; - break; - case 0x1A: /* LWI450 */ - imm = 0; - regular = 1; - load = 1; - len = 4; - addr_mode = 5; - idx_mode = 4; - break; - case 0x16: /* SHI333 */ - imm = 1; - regular = 1; - load = 0; - len = 2; - addr_mode = 3; - idx_mode = 3; - break; - case 0x14: /* SWI333 */ - imm = 1; - regular = 1; - load = 0; - len = 4; - addr_mode = 3; - idx_mode = 3; - break; - case 0x15: /* SWI333.bi */ - imm = 1; - regular = 0; - load = 0; - len = 4; - addr_mode = 3; - idx_mode = 3; - break; - case 0x1B: /* SWI450 */ - imm = 0; - regular = 1; - load = 0; - len = 4; - addr_mode = 5; - idx_mode = 4; - break; - - default: - return -EFAULT; - } - - if (addr_mode == 3) { - unaligned_addr = *idx_to_addr(regs, RA3(inst)); - source_idx = RA3(inst); - } else { - unaligned_addr = *idx_to_addr(regs, RA5(inst)); - source_idx = RA5(inst); - } - - if (idx_mode == 3) - target_idx = RT3(inst); - else - target_idx = RT4(inst); - - if (imm) - shift = IMM3U(inst) * len; - - if (regular) - unaligned_addr += shift; - - if (load) { - if (!access_ok((void *)unaligned_addr, len)) - return -EACCES; - - get_data(unaligned_addr, &target_val, len); - *idx_to_addr(regs, target_idx) = target_val; - } else { - if (!access_ok((void *)unaligned_addr, len)) - return -EACCES; - target_val = *idx_to_addr(regs, target_idx); - set_data((void *)unaligned_addr, target_val, len); - } - - if (!regular) - *idx_to_addr(regs, source_idx) = unaligned_addr + shift; - regs->ipc += 2; - - return 0; -fault: - return -EACCES; -} - -static inline int do_32(unsigned long inst, struct pt_regs *regs) -{ - int imm, regular, load, len, sign_ext; - unsigned long unaligned_addr, target_val, shift; - - unaligned_addr = *idx_to_addr(regs, RA(inst)); - - switch ((inst >> 25) << 1) { - - case 0x02: /* LHI */ - imm = 1; - regular = 1; - load = 1; - len = 2; - sign_ext = 0; - break; - case 0x0A: /* LHI.bi */ - imm = 1; - regular = 0; - load = 1; - len = 2; - sign_ext = 0; - break; - case 0x22: /* LHSI */ - imm = 1; - regular = 1; - load = 1; - len = 2; - sign_ext = 1; - break; - case 0x2A: /* LHSI.bi */ - imm = 1; - regular = 0; - load = 1; - len = 2; - sign_ext = 1; - break; - case 0x04: /* LWI */ - imm = 1; - regular = 1; - load = 1; - len = 4; - sign_ext = 0; - break; - case 0x0C: /* LWI.bi */ - imm = 1; - regular = 0; - load = 1; - len = 4; - sign_ext = 0; - break; - case 0x12: /* SHI */ - imm = 1; - regular = 1; - load = 0; - len = 2; - sign_ext = 0; - break; - case 0x1A: /* SHI.bi */ - imm = 1; - regular = 0; - load = 0; - len = 2; - sign_ext = 0; - break; - case 0x14: /* SWI */ - imm = 1; - regular = 1; - load = 0; - len = 4; - sign_ext = 0; - break; - case 0x1C: /* SWI.bi */ - imm = 1; - regular = 0; - load = 0; - len = 4; - sign_ext = 0; - break; - - default: - switch (inst & 0xff) { - - case 0x01: /* LH */ - imm = 0; - regular = 1; - load = 1; - len = 2; - sign_ext = 0; - break; - case 0x05: /* LH.bi */ - imm = 0; - regular = 0; - load = 1; - len = 2; - sign_ext = 0; - break; - case 0x11: /* LHS */ - imm = 0; - regular = 1; - load = 1; - len = 2; - sign_ext = 1; - break; - case 0x15: /* LHS.bi */ - imm = 0; - regular = 0; - load = 1; - len = 2; - sign_ext = 1; - break; - case 0x02: /* LW */ - imm = 0; - regular = 1; - load = 1; - len = 4; - sign_ext = 0; - break; - case 0x06: /* LW.bi */ - imm = 0; - regular = 0; - load = 1; - len = 4; - sign_ext = 0; - break; - case 0x09: /* SH */ - imm = 0; - regular = 1; - load = 0; - len = 2; - sign_ext = 0; - break; - case 0x0D: /* SH.bi */ - imm = 0; - regular = 0; - load = 0; - len = 2; - sign_ext = 0; - break; - case 0x0A: /* SW */ - imm = 0; - regular = 1; - load = 0; - len = 4; - sign_ext = 0; - break; - case 0x0E: /* SW.bi */ - imm = 0; - regular = 0; - load = 0; - len = 4; - sign_ext = 0; - break; - - default: - return -EFAULT; - } - } - - if (imm) - shift = GET_IMMSVAL(IMM(inst)) * len; - else - shift = *idx_to_addr(regs, RB(inst)) << SV(inst); - - if (regular) - unaligned_addr += shift; - - if (load) { - - if (!access_ok((void *)unaligned_addr, len)) - return -EACCES; - - get_data(unaligned_addr, &target_val, len); - - if (sign_ext) - *idx_to_addr(regs, RT(inst)) = - sign_extend(target_val, len); - else - *idx_to_addr(regs, RT(inst)) = target_val; - } else { - - if (!access_ok((void *)unaligned_addr, len)) - return -EACCES; - - target_val = *idx_to_addr(regs, RT(inst)); - set_data((void *)unaligned_addr, target_val, len); - } - - if (!regular) - *idx_to_addr(regs, RA(inst)) = unaligned_addr + shift; - - regs->ipc += 4; - - return 0; -fault: - return -EACCES; -} - -int do_unaligned_access(unsigned long addr, struct pt_regs *regs) -{ - unsigned long inst; - int ret = -EFAULT; - mm_segment_t seg; - - inst = get_inst(regs->ipc); - - DEBUG((unalign_access_debug > 0), 1, - "Faulting addr: 0x%08lx, pc: 0x%08lx [inst: 0x%08lx ]\n", addr, - regs->ipc, inst); - - seg = force_uaccess_begin(); - if (inst & NDS32_16BIT_INSTRUCTION) - ret = do_16((inst >> 16) & 0xffff, regs); - else - ret = do_32(inst, regs); - force_uaccess_end(seg); - - return ret; -} - -#ifdef CONFIG_PROC_FS - -static struct ctl_table alignment_tbl[3] = { - { - .procname = "enable", - .data = &unalign_access_mode, - .maxlen = sizeof(unalign_access_mode), - .mode = 0666, - .proc_handler = &proc_dointvec - } - , - { - .procname = "debug_info", - .data = &unalign_access_debug, - .maxlen = sizeof(unalign_access_debug), - .mode = 0644, - .proc_handler = &proc_dointvec - } - , - {} -}; - -static struct ctl_table nds32_sysctl_table[2] = { - { - .procname = "unaligned_access", - .mode = 0555, - .child = alignment_tbl}, - {} -}; - -static struct ctl_path nds32_path[2] = { - {.procname = "nds32"}, - {} -}; - -/* - * Initialize nds32 alignment-correction interface - */ -static int __init nds32_sysctl_init(void) -{ - register_sysctl_paths(nds32_path, nds32_sysctl_table); - return 0; -} - -__initcall(nds32_sysctl_init); -#endif /* CONFIG_PROC_FS */ diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c deleted file mode 100644 index 07aac65d1cab..000000000000 --- a/arch/nds32/mm/cacheflush.c +++ /dev/null @@ -1,338 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern struct cache_info L1_cache_info[2]; - -void flush_icache_range(unsigned long start, unsigned long end) -{ - unsigned long line_size, flags; - line_size = L1_cache_info[DCACHE].line_size; - start = start & ~(line_size - 1); - end = (end + line_size - 1) & ~(line_size - 1); - local_irq_save(flags); - cpu_cache_wbinval_range(start, end, 1); - local_irq_restore(flags); -} -EXPORT_SYMBOL(flush_icache_range); - -void flush_icache_page(struct vm_area_struct *vma, struct page *page) -{ - unsigned long flags; - unsigned long kaddr; - local_irq_save(flags); - kaddr = (unsigned long)kmap_atomic(page); - cpu_cache_wbinval_page(kaddr, vma->vm_flags & VM_EXEC); - kunmap_atomic((void *)kaddr); - local_irq_restore(flags); -} - -void flush_icache_user_page(struct vm_area_struct *vma, struct page *page, - unsigned long addr, int len) -{ - unsigned long kaddr; - kaddr = (unsigned long)kmap_atomic(page) + (addr & ~PAGE_MASK); - flush_icache_range(kaddr, kaddr + len); - kunmap_atomic((void *)kaddr); -} - -void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, - pte_t * pte) -{ - struct page *page; - unsigned long pfn = pte_pfn(*pte); - unsigned long flags; - - if (!pfn_valid(pfn)) - return; - - if (vma->vm_mm == current->active_mm) { - local_irq_save(flags); - __nds32__mtsr_dsb(addr, NDS32_SR_TLB_VPN); - __nds32__tlbop_rwr(*pte); - __nds32__isb(); - local_irq_restore(flags); - } - page = pfn_to_page(pfn); - - if ((test_and_clear_bit(PG_dcache_dirty, &page->flags)) || - (vma->vm_flags & VM_EXEC)) { - unsigned long kaddr; - local_irq_save(flags); - kaddr = (unsigned long)kmap_atomic(page); - cpu_cache_wbinval_page(kaddr, vma->vm_flags & VM_EXEC); - kunmap_atomic((void *)kaddr); - local_irq_restore(flags); - } -} -#ifdef CONFIG_CPU_CACHE_ALIASING -extern pte_t va_present(struct mm_struct *mm, unsigned long addr); - -static inline unsigned long aliasing(unsigned long addr, unsigned long page) -{ - return ((addr & PAGE_MASK) ^ page) & (SHMLBA - 1); -} - -static inline unsigned long kremap0(unsigned long uaddr, unsigned long pa) -{ - unsigned long kaddr, pte; - -#define BASE_ADDR0 0xffffc000 - kaddr = BASE_ADDR0 | (uaddr & L1_cache_info[DCACHE].aliasing_mask); - pte = (pa | PAGE_KERNEL); - __nds32__mtsr_dsb(kaddr, NDS32_SR_TLB_VPN); - __nds32__tlbop_rwlk(pte); - __nds32__isb(); - return kaddr; -} - -static inline void kunmap01(unsigned long kaddr) -{ - __nds32__tlbop_unlk(kaddr); - __nds32__tlbop_inv(kaddr); - __nds32__isb(); -} - -static inline unsigned long kremap1(unsigned long uaddr, unsigned long pa) -{ - unsigned long kaddr, pte; - -#define BASE_ADDR1 0xffff8000 - kaddr = BASE_ADDR1 | (uaddr & L1_cache_info[DCACHE].aliasing_mask); - pte = (pa | PAGE_KERNEL); - __nds32__mtsr_dsb(kaddr, NDS32_SR_TLB_VPN); - __nds32__tlbop_rwlk(pte); - __nds32__isb(); - return kaddr; -} - -void flush_cache_mm(struct mm_struct *mm) -{ - unsigned long flags; - - local_irq_save(flags); - cpu_dcache_wbinval_all(); - cpu_icache_inval_all(); - local_irq_restore(flags); -} - -void flush_cache_dup_mm(struct mm_struct *mm) -{ -} - -void flush_cache_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end) -{ - unsigned long flags; - - if ((end - start) > 8 * PAGE_SIZE) { - cpu_dcache_wbinval_all(); - if (vma->vm_flags & VM_EXEC) - cpu_icache_inval_all(); - return; - } - local_irq_save(flags); - while (start < end) { - if (va_present(vma->vm_mm, start)) - cpu_cache_wbinval_page(start, vma->vm_flags & VM_EXEC); - start += PAGE_SIZE; - } - local_irq_restore(flags); - return; -} - -void flush_cache_page(struct vm_area_struct *vma, - unsigned long addr, unsigned long pfn) -{ - unsigned long vto, flags; - - local_irq_save(flags); - vto = kremap0(addr, pfn << PAGE_SHIFT); - cpu_cache_wbinval_page(vto, vma->vm_flags & VM_EXEC); - kunmap01(vto); - local_irq_restore(flags); -} - -void flush_cache_vmap(unsigned long start, unsigned long end) -{ - cpu_dcache_wbinval_all(); - cpu_icache_inval_all(); -} - -void flush_cache_vunmap(unsigned long start, unsigned long end) -{ - cpu_dcache_wbinval_all(); - cpu_icache_inval_all(); -} - -void copy_user_page(void *vto, void *vfrom, unsigned long vaddr, - struct page *to) -{ - cpu_dcache_wbinval_page((unsigned long)vaddr); - cpu_icache_inval_page((unsigned long)vaddr); - copy_page(vto, vfrom); - cpu_dcache_wbinval_page((unsigned long)vto); - cpu_icache_inval_page((unsigned long)vto); -} - -void clear_user_page(void *addr, unsigned long vaddr, struct page *page) -{ - cpu_dcache_wbinval_page((unsigned long)vaddr); - cpu_icache_inval_page((unsigned long)vaddr); - clear_page(addr); - cpu_dcache_wbinval_page((unsigned long)addr); - cpu_icache_inval_page((unsigned long)addr); -} - -void copy_user_highpage(struct page *to, struct page *from, - unsigned long vaddr, struct vm_area_struct *vma) -{ - unsigned long vto, vfrom, flags, kto, kfrom, pfrom, pto; - kto = ((unsigned long)page_address(to) & PAGE_MASK); - kfrom = ((unsigned long)page_address(from) & PAGE_MASK); - pto = page_to_phys(to); - pfrom = page_to_phys(from); - - local_irq_save(flags); - if (aliasing(vaddr, (unsigned long)kfrom)) - cpu_dcache_wb_page((unsigned long)kfrom); - vto = kremap0(vaddr, pto); - vfrom = kremap1(vaddr, pfrom); - copy_page((void *)vto, (void *)vfrom); - kunmap01(vfrom); - kunmap01(vto); - local_irq_restore(flags); -} - -EXPORT_SYMBOL(copy_user_highpage); - -void clear_user_highpage(struct page *page, unsigned long vaddr) -{ - unsigned long vto, flags, kto; - - kto = ((unsigned long)page_address(page) & PAGE_MASK); - - local_irq_save(flags); - if (aliasing(kto, vaddr) && kto != 0) { - cpu_dcache_inval_page(kto); - cpu_icache_inval_page(kto); - } - vto = kremap0(vaddr, page_to_phys(page)); - clear_page((void *)vto); - kunmap01(vto); - local_irq_restore(flags); -} - -EXPORT_SYMBOL(clear_user_highpage); - -void flush_dcache_page(struct page *page) -{ - struct address_space *mapping; - - mapping = page_mapping_file(page); - if (mapping && !mapping_mapped(mapping)) - set_bit(PG_dcache_dirty, &page->flags); - else { - unsigned long kaddr, flags; - - kaddr = (unsigned long)page_address(page); - local_irq_save(flags); - cpu_dcache_wbinval_page(kaddr); - if (mapping) { - unsigned long vaddr, kto; - - vaddr = page->index << PAGE_SHIFT; - if (aliasing(vaddr, kaddr)) { - kto = kremap0(vaddr, page_to_phys(page)); - cpu_dcache_wbinval_page(kto); - kunmap01(kto); - } - } - local_irq_restore(flags); - } -} -EXPORT_SYMBOL(flush_dcache_page); - -void copy_to_user_page(struct vm_area_struct *vma, struct page *page, - unsigned long vaddr, void *dst, void *src, int len) -{ - unsigned long line_size, start, end, vto, flags; - - local_irq_save(flags); - vto = kremap0(vaddr, page_to_phys(page)); - dst = (void *)(vto | (vaddr & (PAGE_SIZE - 1))); - memcpy(dst, src, len); - if (vma->vm_flags & VM_EXEC) { - line_size = L1_cache_info[DCACHE].line_size; - start = (unsigned long)dst & ~(line_size - 1); - end = - ((unsigned long)dst + len + line_size - 1) & ~(line_size - - 1); - cpu_cache_wbinval_range(start, end, 1); - } - kunmap01(vto); - local_irq_restore(flags); -} - -void copy_from_user_page(struct vm_area_struct *vma, struct page *page, - unsigned long vaddr, void *dst, void *src, int len) -{ - unsigned long vto, flags; - - local_irq_save(flags); - vto = kremap0(vaddr, page_to_phys(page)); - src = (void *)(vto | (vaddr & (PAGE_SIZE - 1))); - memcpy(dst, src, len); - kunmap01(vto); - local_irq_restore(flags); -} - -void flush_anon_page(struct vm_area_struct *vma, - struct page *page, unsigned long vaddr) -{ - unsigned long kaddr, flags, ktmp; - if (!PageAnon(page)) - return; - - if (vma->vm_mm != current->active_mm) - return; - - local_irq_save(flags); - if (vma->vm_flags & VM_EXEC) - cpu_icache_inval_page(vaddr & PAGE_MASK); - kaddr = (unsigned long)page_address(page); - if (aliasing(vaddr, kaddr)) { - ktmp = kremap0(vaddr, page_to_phys(page)); - cpu_dcache_wbinval_page(ktmp); - kunmap01(ktmp); - } - local_irq_restore(flags); -} - -void flush_kernel_vmap_range(void *addr, int size) -{ - unsigned long flags; - local_irq_save(flags); - cpu_dcache_wb_range((unsigned long)addr, (unsigned long)addr + size); - local_irq_restore(flags); -} -EXPORT_SYMBOL(flush_kernel_vmap_range); - -void invalidate_kernel_vmap_range(void *addr, int size) -{ - unsigned long flags; - local_irq_save(flags); - cpu_dcache_inval_range((unsigned long)addr, (unsigned long)addr + size); - local_irq_restore(flags); -} -EXPORT_SYMBOL(invalidate_kernel_vmap_range); -#endif diff --git a/arch/nds32/mm/extable.c b/arch/nds32/mm/extable.c deleted file mode 100644 index db7f0a7c8966..000000000000 --- a/arch/nds32/mm/extable.c +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include - -int fixup_exception(struct pt_regs *regs) -{ - const struct exception_table_entry *fixup; - - fixup = search_exception_tables(instruction_pointer(regs)); - if (fixup) - regs->ipc = fixup->fixup; - - return fixup != NULL; -} diff --git a/arch/nds32/mm/fault.c b/arch/nds32/mm/fault.c deleted file mode 100644 index 636977a1c8b9..000000000000 --- a/arch/nds32/mm/fault.c +++ /dev/null @@ -1,396 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -extern void __noreturn die(const char *str, struct pt_regs *regs, long err); - -/* - * This is useful to dump out the page tables associated with - * 'addr' in mm 'mm'. - */ -void show_pte(struct mm_struct *mm, unsigned long addr) -{ - pgd_t *pgd; - if (!mm) - mm = &init_mm; - - pr_alert("pgd = %p\n", mm->pgd); - pgd = pgd_offset(mm, addr); - pr_alert("[%08lx] *pgd=%08lx", addr, pgd_val(*pgd)); - - do { - p4d_t *p4d; - pud_t *pud; - pmd_t *pmd; - - if (pgd_none(*pgd)) - break; - - if (pgd_bad(*pgd)) { - pr_alert("(bad)"); - break; - } - - p4d = p4d_offset(pgd, addr); - pud = pud_offset(p4d, addr); - pmd = pmd_offset(pud, addr); -#if PTRS_PER_PMD != 1 - pr_alert(", *pmd=%08lx", pmd_val(*pmd)); -#endif - - if (pmd_none(*pmd)) - break; - - if (pmd_bad(*pmd)) { - pr_alert("(bad)"); - break; - } - - if (IS_ENABLED(CONFIG_HIGHMEM)) - { - pte_t *pte; - /* We must not map this if we have highmem enabled */ - pte = pte_offset_map(pmd, addr); - pr_alert(", *pte=%08lx", pte_val(*pte)); - pte_unmap(pte); - } - } while (0); - - pr_alert("\n"); -} - -void do_page_fault(unsigned long entry, unsigned long addr, - unsigned int error_code, struct pt_regs *regs) -{ - struct task_struct *tsk; - struct mm_struct *mm; - struct vm_area_struct *vma; - int si_code; - vm_fault_t fault; - unsigned int mask = VM_ACCESS_FLAGS; - unsigned int flags = FAULT_FLAG_DEFAULT; - - error_code = error_code & (ITYPE_mskINST | ITYPE_mskETYPE); - tsk = current; - mm = tsk->mm; - si_code = SEGV_MAPERR; - /* - * We fault-in kernel-space virtual memory on-demand. The - * 'reference' page table is init_mm.pgd. - * - * NOTE! We MUST NOT take any locks for this case. We may - * be in an interrupt or a critical region, and should - * only copy the information from the master page table, - * nothing more. - */ - if (addr >= TASK_SIZE) { - if (user_mode(regs)) - goto bad_area_nosemaphore; - - if (addr >= TASK_SIZE && addr < VMALLOC_END - && (entry == ENTRY_PTE_NOT_PRESENT)) - goto vmalloc_fault; - else - goto no_context; - } - - /* Send a signal to the task for handling the unalignment access. */ - if (entry == ENTRY_GENERAL_EXCPETION - && error_code == ETYPE_ALIGNMENT_CHECK) { - if (user_mode(regs)) - goto bad_area_nosemaphore; - else - goto no_context; - } - - /* - * If we're in an interrupt or have no user - * context, we must not take the fault.. - */ - if (unlikely(faulthandler_disabled() || !mm)) - goto no_context; - - perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, addr); - - /* - * As per x86, we may deadlock here. However, since the kernel only - * validly references user space from well defined areas of the code, - * we can bug out early if this is from code which shouldn't. - */ - if (unlikely(!mmap_read_trylock(mm))) { - if (!user_mode(regs) && - !search_exception_tables(instruction_pointer(regs))) - goto no_context; -retry: - mmap_read_lock(mm); - } else { - /* - * The above down_read_trylock() might have succeeded in which - * case, we'll have missed the might_sleep() from down_read(). - */ - might_sleep(); - if (IS_ENABLED(CONFIG_DEBUG_VM)) { - if (!user_mode(regs) && - !search_exception_tables(instruction_pointer(regs))) - goto no_context; - } - } - - vma = find_vma(mm, addr); - - if (unlikely(!vma)) - goto bad_area; - - if (vma->vm_start <= addr) - goto good_area; - - if (unlikely(!(vma->vm_flags & VM_GROWSDOWN))) - goto bad_area; - - if (unlikely(expand_stack(vma, addr))) - goto bad_area; - - /* - * Ok, we have a good vm_area for this memory access, so - * we can handle it.. - */ - -good_area: - si_code = SEGV_ACCERR; - - /* first do some preliminary protection checks */ - if (entry == ENTRY_PTE_NOT_PRESENT) { - if (error_code & ITYPE_mskINST) - mask = VM_EXEC; - else { - mask = VM_READ | VM_WRITE; - } - } else if (entry == ENTRY_TLB_MISC) { - switch (error_code & ITYPE_mskETYPE) { - case RD_PROT: - mask = VM_READ; - break; - case WRT_PROT: - mask = VM_WRITE; - flags |= FAULT_FLAG_WRITE; - break; - case NOEXEC: - mask = VM_EXEC; - break; - case PAGE_MODIFY: - mask = VM_WRITE; - flags |= FAULT_FLAG_WRITE; - break; - case ACC_BIT: - BUG(); - default: - break; - } - - } - if (!(vma->vm_flags & mask)) - goto bad_area; - - /* - * If for any reason at all we couldn't handle the fault, - * make sure we exit gracefully rather than endlessly redo - * the fault. - */ - - fault = handle_mm_fault(vma, addr, flags, regs); - - /* - * If we need to retry but a fatal signal is pending, handle the - * signal first. We do not need to release the mmap_lock because it - * would already be released in __lock_page_or_retry in mm/filemap.c. - */ - if (fault_signal_pending(fault, regs)) { - if (!user_mode(regs)) - goto no_context; - return; - } - - if (unlikely(fault & VM_FAULT_ERROR)) { - if (fault & VM_FAULT_OOM) - goto out_of_memory; - else if (fault & VM_FAULT_SIGBUS) - goto do_sigbus; - else - goto bad_area; - } - - if (fault & VM_FAULT_RETRY) { - flags |= FAULT_FLAG_TRIED; - - /* No need to mmap_read_unlock(mm) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ - goto retry; - } - - mmap_read_unlock(mm); - return; - - /* - * Something tried to access memory that isn't in our memory map.. - * Fix it, but check if it's kernel or user first.. - */ -bad_area: - mmap_read_unlock(mm); - -bad_area_nosemaphore: - - /* User mode accesses just cause a SIGSEGV */ - - if (user_mode(regs)) { - tsk->thread.address = addr; - tsk->thread.error_code = error_code; - tsk->thread.trap_no = entry; - force_sig_fault(SIGSEGV, si_code, (void __user *)addr); - return; - } - -no_context: - - /* Are we prepared to handle this kernel fault? - * - * (The kernel has valid exception-points in the source - * when it acesses user-memory. When it fails in one - * of those points, we find it in a table and do a jump - * to some fixup code that loads an appropriate error - * code) - */ - - { - const struct exception_table_entry *entry; - - if ((entry = - search_exception_tables(instruction_pointer(regs))) != - NULL) { - /* Adjust the instruction pointer in the stackframe */ - instruction_pointer(regs) = entry->fixup; - return; - } - } - - /* - * Oops. The kernel tried to access some bad page. We'll have to - * terminate things with extreme prejudice. - */ - - bust_spinlocks(1); - pr_alert("Unable to handle kernel %s at virtual address %08lx\n", - (addr < PAGE_SIZE) ? "NULL pointer dereference" : - "paging request", addr); - - show_pte(mm, addr); - die("Oops", regs, error_code); - - /* - * We ran out of memory, or some other thing happened to us that made - * us unable to handle the page fault gracefully. - */ - -out_of_memory: - mmap_read_unlock(mm); - if (!user_mode(regs)) - goto no_context; - pagefault_out_of_memory(); - return; - -do_sigbus: - mmap_read_unlock(mm); - - /* Kernel mode? Handle exceptions or die */ - if (!user_mode(regs)) - goto no_context; - - /* - * Send a sigbus - */ - tsk->thread.address = addr; - tsk->thread.error_code = error_code; - tsk->thread.trap_no = entry; - force_sig_fault(SIGBUS, BUS_ADRERR, (void __user *)addr); - - return; - -vmalloc_fault: - { - /* - * Synchronize this task's top level page-table - * with the 'reference' page table. - * - * Use current_pgd instead of tsk->active_mm->pgd - * since the latter might be unavailable if this - * code is executed in a misfortunately run irq - * (like inside schedule() between switch_mm and - * switch_to...). - */ - - unsigned int index = pgd_index(addr); - pgd_t *pgd, *pgd_k; - p4d_t *p4d, *p4d_k; - pud_t *pud, *pud_k; - pmd_t *pmd, *pmd_k; - pte_t *pte_k; - - pgd = (pgd_t *) __va(__nds32__mfsr(NDS32_SR_L1_PPTB)) + index; - pgd_k = init_mm.pgd + index; - - if (!pgd_present(*pgd_k)) - goto no_context; - - p4d = p4d_offset(pgd, addr); - p4d_k = p4d_offset(pgd_k, addr); - if (!p4d_present(*p4d_k)) - goto no_context; - - pud = pud_offset(p4d, addr); - pud_k = pud_offset(p4d_k, addr); - if (!pud_present(*pud_k)) - goto no_context; - - pmd = pmd_offset(pud, addr); - pmd_k = pmd_offset(pud_k, addr); - if (!pmd_present(*pmd_k)) - goto no_context; - - if (!pmd_present(*pmd)) - set_pmd(pmd, *pmd_k); - else - BUG_ON(pmd_page(*pmd) != pmd_page(*pmd_k)); - - /* - * Since the vmalloc area is global, we don't - * need to copy individual PTE's, it is enough to - * copy the pgd pointer into the pte page of the - * root task. If that is there, we'll find our pte if - * it exists. - */ - - /* Make sure the actual PTE exists as well to - * catch kernel vmalloc-area accesses to non-mapped - * addres. If we don't do this, this will just - * silently loop forever. - */ - - pte_k = pte_offset_kernel(pmd_k, addr); - if (!pte_present(*pte_k)) - goto no_context; - - return; - } -} diff --git a/arch/nds32/mm/init.c b/arch/nds32/mm/init.c deleted file mode 100644 index 825c85cab1a1..000000000000 --- a/arch/nds32/mm/init.c +++ /dev/null @@ -1,262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 1995-2005 Russell King -// Copyright (C) 2012 ARM Ltd. -// Copyright (C) 2013-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -DEFINE_SPINLOCK(anon_alias_lock); -extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; - -/* - * empty_zero_page is a special page that is used for - * zero-initialized data and COW. - */ -struct page *empty_zero_page; -EXPORT_SYMBOL(empty_zero_page); - -static void __init zone_sizes_init(void) -{ - unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 }; - - max_zone_pfn[ZONE_NORMAL] = max_low_pfn; -#ifdef CONFIG_HIGHMEM - max_zone_pfn[ZONE_HIGHMEM] = max_pfn; -#endif - free_area_init(max_zone_pfn); - -} - -/* - * Map all physical memory under high_memory into kernel's address space. - * - * This is explicitly coded for two-level page tables, so if you need - * something else then this needs to change. - */ -static void __init map_ram(void) -{ - unsigned long v, p, e; - pgd_t *pge; - p4d_t *p4e; - pud_t *pue; - pmd_t *pme; - pte_t *pte; - /* These mark extents of read-only kernel pages... - * ...from vmlinux.lds.S - */ - - p = (u32) memblock_start_of_DRAM() & PAGE_MASK; - e = min((u32) memblock_end_of_DRAM(), (u32) __pa(high_memory)); - - v = (u32) __va(p); - pge = pgd_offset_k(v); - - while (p < e) { - int j; - p4e = p4d_offset(pge, v); - pue = pud_offset(p4e, v); - pme = pmd_offset(pue, v); - - if ((u32) pue != (u32) pge || (u32) pme != (u32) pge) { - panic("%s: Kernel hardcoded for " - "two-level page tables", __func__); - } - - /* Alloc one page for holding PTE's... */ - pte = memblock_alloc(PAGE_SIZE, PAGE_SIZE); - if (!pte) - panic("%s: Failed to allocate %lu bytes align=0x%lx\n", - __func__, PAGE_SIZE, PAGE_SIZE); - set_pmd(pme, __pmd(__pa(pte) + _PAGE_KERNEL_TABLE)); - - /* Fill the newly allocated page with PTE'S */ - for (j = 0; p < e && j < PTRS_PER_PTE; - v += PAGE_SIZE, p += PAGE_SIZE, j++, pte++) { - /* Create mapping between p and v. */ - /* TODO: more fine grant for page access permission */ - set_pte(pte, __pte(p + pgprot_val(PAGE_KERNEL))); - } - - pge++; - } -} -static pmd_t *fixmap_pmd_p; -static void __init fixedrange_init(void) -{ - unsigned long vaddr; - pmd_t *pmd; -#ifdef CONFIG_HIGHMEM - pte_t *pte; -#endif /* CONFIG_HIGHMEM */ - - /* - * Fixed mappings: - */ - vaddr = __fix_to_virt(__end_of_fixed_addresses - 1); - pmd = pmd_off_k(vaddr); - fixmap_pmd_p = memblock_alloc(PAGE_SIZE, PAGE_SIZE); - if (!fixmap_pmd_p) - panic("%s: Failed to allocate %lu bytes align=0x%lx\n", - __func__, PAGE_SIZE, PAGE_SIZE); - set_pmd(pmd, __pmd(__pa(fixmap_pmd_p) + _PAGE_KERNEL_TABLE)); - -#ifdef CONFIG_HIGHMEM - /* - * Permanent kmaps: - */ - vaddr = PKMAP_BASE; - - pmd = pmd_off_k(vaddr); - pte = memblock_alloc(PAGE_SIZE, PAGE_SIZE); - if (!pte) - panic("%s: Failed to allocate %lu bytes align=0x%lx\n", - __func__, PAGE_SIZE, PAGE_SIZE); - set_pmd(pmd, __pmd(__pa(pte) + _PAGE_KERNEL_TABLE)); - pkmap_page_table = pte; -#endif /* CONFIG_HIGHMEM */ -} - -/* - * paging_init() sets up the page tables, initialises the zone memory - * maps, and sets up the zero page, bad page and bad page tables. - */ -void __init paging_init(void) -{ - int i; - void *zero_page; - - pr_info("Setting up paging and PTEs.\n"); - /* clear out the init_mm.pgd that will contain the kernel's mappings */ - for (i = 0; i < PTRS_PER_PGD; i++) - swapper_pg_dir[i] = __pgd(1); - - map_ram(); - - fixedrange_init(); - - /* allocate space for empty_zero_page */ - zero_page = memblock_alloc(PAGE_SIZE, PAGE_SIZE); - if (!zero_page) - panic("%s: Failed to allocate %lu bytes align=0x%lx\n", - __func__, PAGE_SIZE, PAGE_SIZE); - zone_sizes_init(); - - empty_zero_page = virt_to_page(zero_page); - flush_dcache_page(empty_zero_page); -} - -static inline void __init free_highmem(void) -{ -#ifdef CONFIG_HIGHMEM - unsigned long pfn; - for (pfn = PFN_UP(__pa(high_memory)); pfn < max_pfn; pfn++) { - phys_addr_t paddr = (phys_addr_t) pfn << PAGE_SHIFT; - if (!memblock_is_reserved(paddr)) - free_highmem_page(pfn_to_page(pfn)); - } -#endif -} - -static void __init set_max_mapnr_init(void) -{ - max_mapnr = max_pfn; -} - -/* - * mem_init() marks the free areas in the mem_map and tells us how much - * memory is free. This is done after various parts of the system have - * claimed their memory after the kernel image. - */ -void __init mem_init(void) -{ - phys_addr_t memory_start = memblock_start_of_DRAM(); - BUG_ON(!mem_map); - set_max_mapnr_init(); - - free_highmem(); - - /* this will put all low memory onto the freelists */ - memblock_free_all(); - - pr_info("virtual kernel memory layout:\n" - " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n" -#ifdef CONFIG_HIGHMEM - " pkmap : 0x%08lx - 0x%08lx (%4ld kB)\n" -#endif - " consist : 0x%08lx - 0x%08lx (%4ld MB)\n" - " vmalloc : 0x%08lx - 0x%08lx (%4ld MB)\n" - " lowmem : 0x%08lx - 0x%08lx (%4ld MB)\n" - " .init : 0x%08lx - 0x%08lx (%4ld kB)\n" - " .data : 0x%08lx - 0x%08lx (%4ld kB)\n" - " .text : 0x%08lx - 0x%08lx (%4ld kB)\n", - FIXADDR_START, FIXADDR_TOP, (FIXADDR_TOP - FIXADDR_START) >> 10, -#ifdef CONFIG_HIGHMEM - PKMAP_BASE, PKMAP_BASE + LAST_PKMAP * PAGE_SIZE, - (LAST_PKMAP * PAGE_SIZE) >> 10, -#endif - CONSISTENT_BASE, CONSISTENT_END, - ((CONSISTENT_END) - (CONSISTENT_BASE)) >> 20, VMALLOC_START, - (unsigned long)VMALLOC_END, (VMALLOC_END - VMALLOC_START) >> 20, - (unsigned long)__va(memory_start), (unsigned long)high_memory, - ((unsigned long)high_memory - - (unsigned long)__va(memory_start)) >> 20, - (unsigned long)&__init_begin, (unsigned long)&__init_end, - ((unsigned long)&__init_end - - (unsigned long)&__init_begin) >> 10, (unsigned long)&_etext, - (unsigned long)&_edata, - ((unsigned long)&_edata - (unsigned long)&_etext) >> 10, - (unsigned long)&_text, (unsigned long)&_etext, - ((unsigned long)&_etext - (unsigned long)&_text) >> 10); - - /* - * Check boundaries twice: Some fundamental inconsistencies can - * be detected at build time already. - */ -#ifdef CONFIG_HIGHMEM - BUILD_BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE > FIXADDR_START); - BUILD_BUG_ON((CONSISTENT_END) > PKMAP_BASE); -#endif - BUILD_BUG_ON(VMALLOC_END > CONSISTENT_BASE); - BUILD_BUG_ON(VMALLOC_START >= VMALLOC_END); - -#ifdef CONFIG_HIGHMEM - BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE > FIXADDR_START); - BUG_ON(CONSISTENT_END > PKMAP_BASE); -#endif - BUG_ON(VMALLOC_END > CONSISTENT_BASE); - BUG_ON(VMALLOC_START >= VMALLOC_END); - BUG_ON((unsigned long)high_memory > VMALLOC_START); - - return; -} - -void __set_fixmap(enum fixed_addresses idx, - phys_addr_t phys, pgprot_t flags) -{ - unsigned long addr = __fix_to_virt(idx); - pte_t *pte; - - BUG_ON(idx <= FIX_HOLE || idx >= __end_of_fixed_addresses); - - pte = (pte_t *)&fixmap_pmd_p[pte_index(addr)]; - - if (pgprot_val(flags)) { - set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, flags)); - } else { - pte_clear(&init_mm, addr, pte); - flush_tlb_kernel_range(addr, addr + PAGE_SIZE); - } -} diff --git a/arch/nds32/mm/mm-nds32.c b/arch/nds32/mm/mm-nds32.c deleted file mode 100644 index f2778f2b39f6..000000000000 --- a/arch/nds32/mm/mm-nds32.c +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include - -#define __HAVE_ARCH_PGD_FREE -#include - -#define FIRST_KERNEL_PGD_NR (USER_PTRS_PER_PGD) - -/* - * need to get a page for level 1 - */ - -pgd_t *pgd_alloc(struct mm_struct *mm) -{ - pgd_t *new_pgd, *init_pgd; - int i; - - new_pgd = (pgd_t *) __get_free_pages(GFP_KERNEL, 0); - if (!new_pgd) - return NULL; - for (i = 0; i < PTRS_PER_PGD; i++) { - (*new_pgd) = 1; - new_pgd++; - } - new_pgd -= PTRS_PER_PGD; - - init_pgd = pgd_offset_k(0); - - memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR, - (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t)); - - cpu_dcache_wb_range((unsigned long)new_pgd, - (unsigned long)new_pgd + - PTRS_PER_PGD * sizeof(pgd_t)); - inc_lruvec_page_state(virt_to_page((unsigned long *)new_pgd), - NR_PAGETABLE); - - return new_pgd; -} - -void pgd_free(struct mm_struct *mm, pgd_t * pgd) -{ - pmd_t *pmd; - struct page *pte; - - if (!pgd) - return; - - pmd = (pmd_t *) pgd; - if (pmd_none(*pmd)) - goto free; - if (pmd_bad(*pmd)) { - pmd_ERROR(*pmd); - pmd_clear(pmd); - goto free; - } - - pte = pmd_page(*pmd); - pmd_clear(pmd); - dec_lruvec_page_state(virt_to_page((unsigned long *)pgd), NR_PAGETABLE); - pte_free(mm, pte); - mm_dec_nr_ptes(mm); - pmd_free(mm, pmd); -free: - free_pages((unsigned long)pgd, 0); -} - -/* - * In order to soft-boot, we need to insert a 1:1 mapping in place of - * the user-mode pages. This will then ensure that we have predictable - * results when turning the mmu off - */ -void setup_mm_for_reboot(char mode) -{ - unsigned long pmdval; - pgd_t *pgd; - p4d_t *p4d; - pud_t *pud; - pmd_t *pmd; - int i; - - if (current->mm && current->mm->pgd) - pgd = current->mm->pgd; - else - pgd = init_mm.pgd; - - for (i = 0; i < USER_PTRS_PER_PGD; i++) { - pmdval = (i << PGDIR_SHIFT); - p4d = p4d_offset(pgd, i << PGDIR_SHIFT); - pud = pud_offset(p4d, i << PGDIR_SHIFT); - pmd = pmd_offset(pud + i, i << PGDIR_SHIFT); - set_pmd(pmd, __pmd(pmdval)); - } -} diff --git a/arch/nds32/mm/mmap.c b/arch/nds32/mm/mmap.c deleted file mode 100644 index 1bdf5e7d1b43..000000000000 --- a/arch/nds32/mm/mmap.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include - -#define COLOUR_ALIGN(addr,pgoff) \ - ((((addr)+SHMLBA-1)&~(SHMLBA-1)) + \ - (((pgoff)<mm; - struct vm_area_struct *vma; - int do_align = 0; - struct vm_unmapped_area_info info; - int aliasing = 0; - if(IS_ENABLED(CONFIG_CPU_CACHE_ALIASING)) - aliasing = 1; - - /* - * We only need to do colour alignment if either the I or D - * caches alias. - */ - if (aliasing) - do_align = filp || (flags & MAP_SHARED); - - /* - * We enforce the MAP_FIXED case. - */ - if (flags & MAP_FIXED) { - if (aliasing && flags & MAP_SHARED && - (addr - (pgoff << PAGE_SHIFT)) & (SHMLBA - 1)) - return -EINVAL; - return addr; - } - - if (len > TASK_SIZE) - return -ENOMEM; - - if (addr) { - if (do_align) - addr = COLOUR_ALIGN(addr, pgoff); - else - addr = PAGE_ALIGN(addr); - - vma = find_vma(mm, addr); - if (TASK_SIZE - len >= addr && - (!vma || addr + len <= vm_start_gap(vma))) - return addr; - } - - info.flags = 0; - info.length = len; - info.low_limit = mm->mmap_base; - info.high_limit = TASK_SIZE; - info.align_mask = do_align ? (PAGE_MASK & (SHMLBA - 1)) : 0; - info.align_offset = pgoff << PAGE_SHIFT; - return vm_unmapped_area(&info); -} diff --git a/arch/nds32/mm/proc.c b/arch/nds32/mm/proc.c deleted file mode 100644 index 848c845f5f33..000000000000 --- a/arch/nds32/mm/proc.c +++ /dev/null @@ -1,536 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -extern struct cache_info L1_cache_info[2]; - -int va_kernel_present(unsigned long addr) -{ - pmd_t *pmd; - pte_t *ptep, pte; - - pmd = pmd_off_k(addr); - if (!pmd_none(*pmd)) { - ptep = pte_offset_map(pmd, addr); - pte = *ptep; - if (pte_present(pte)) - return pte; - } - return 0; -} - -pte_t va_present(struct mm_struct * mm, unsigned long addr) -{ - pgd_t *pgd; - p4d_t *p4d; - pud_t *pud; - pmd_t *pmd; - pte_t *ptep, pte; - - pgd = pgd_offset(mm, addr); - if (!pgd_none(*pgd)) { - p4d = p4d_offset(pgd, addr); - if (!p4d_none(*p4d)) { - pud = pud_offset(p4d, addr); - if (!pud_none(*pud)) { - pmd = pmd_offset(pud, addr); - if (!pmd_none(*pmd)) { - ptep = pte_offset_map(pmd, addr); - pte = *ptep; - if (pte_present(pte)) - return pte; - } - } - } - } - return 0; - -} - -int va_readable(struct pt_regs *regs, unsigned long addr) -{ - struct mm_struct *mm = current->mm; - pte_t pte; - int ret = 0; - - if (user_mode(regs)) { - /* user mode */ - pte = va_present(mm, addr); - if (!pte && pte_read(pte)) - ret = 1; - } else { - /* superuser mode is always readable, so we can only - * check it is present or not*/ - return (! !va_kernel_present(addr)); - } - return ret; -} - -int va_writable(struct pt_regs *regs, unsigned long addr) -{ - struct mm_struct *mm = current->mm; - pte_t pte; - int ret = 0; - - if (user_mode(regs)) { - /* user mode */ - pte = va_present(mm, addr); - if (!pte && pte_write(pte)) - ret = 1; - } else { - /* superuser mode */ - pte = va_kernel_present(addr); - if (!pte && pte_kernel_write(pte)) - ret = 1; - } - return ret; -} - -/* - * All - */ -void cpu_icache_inval_all(void) -{ - unsigned long end, line_size; - - line_size = L1_cache_info[ICACHE].line_size; - end = - line_size * L1_cache_info[ICACHE].ways * L1_cache_info[ICACHE].sets; - - do { - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); - } while (end > 0); - __nds32__isb(); -} - -void cpu_dcache_inval_all(void) -{ - __nds32__cctl_l1d_invalall(); -} - -#ifdef CONFIG_CACHE_L2 -void dcache_wb_all_level(void) -{ - unsigned long flags, cmd; - local_irq_save(flags); - __nds32__cctl_l1d_wball_alvl(); - /* Section 1: Ensure the section 2 & 3 program code execution after */ - __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0); - - /* Section 2: Confirm the writeback all level is done in CPU and L2C */ - cmd = CCTL_CMD_L2_SYNC; - L2_CMD_RDY(); - L2C_W_REG(L2_CCTL_CMD_OFF, cmd); - L2_CMD_RDY(); - - /* Section 3: Writeback whole L2 cache */ - cmd = CCTL_ALL_CMD | CCTL_CMD_L2_IX_WB; - L2_CMD_RDY(); - L2C_W_REG(L2_CCTL_CMD_OFF, cmd); - L2_CMD_RDY(); - __nds32__msync_all(); - local_irq_restore(flags); -} -EXPORT_SYMBOL(dcache_wb_all_level); -#endif - -void cpu_dcache_wb_all(void) -{ - __nds32__cctl_l1d_wball_one_lvl(); - __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0); -} - -void cpu_dcache_wbinval_all(void) -{ -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - unsigned long flags; - local_irq_save(flags); -#endif - cpu_dcache_wb_all(); - cpu_dcache_inval_all(); -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - local_irq_restore(flags); -#endif -} - -/* - * Page - */ -void cpu_icache_inval_page(unsigned long start) -{ - unsigned long line_size, end; - - line_size = L1_cache_info[ICACHE].line_size; - end = start + PAGE_SIZE; - - do { - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end)); - } while (end != start); - __nds32__isb(); -} - -void cpu_dcache_inval_page(unsigned long start) -{ - unsigned long line_size, end; - - line_size = L1_cache_info[DCACHE].line_size; - end = start + PAGE_SIZE; - - do { - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); - } while (end != start); -} - -void cpu_dcache_wb_page(unsigned long start) -{ -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - unsigned long line_size, end; - - line_size = L1_cache_info[DCACHE].line_size; - end = start + PAGE_SIZE; - - do { - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); - end -= line_size; - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); - } while (end != start); - __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0); -#endif -} - -void cpu_dcache_wbinval_page(unsigned long start) -{ - unsigned long line_size, end; - - line_size = L1_cache_info[DCACHE].line_size; - end = start + PAGE_SIZE; - - do { - end -= line_size; -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); -#endif - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); - end -= line_size; -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); -#endif - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); - end -= line_size; -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); -#endif - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); - end -= line_size; -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); -#endif - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); - } while (end != start); - __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0); -} - -void cpu_cache_wbinval_page(unsigned long page, int flushi) -{ - cpu_dcache_wbinval_page(page); - if (flushi) - cpu_icache_inval_page(page); -} - -/* - * Range - */ -void cpu_icache_inval_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = L1_cache_info[ICACHE].line_size; - - while (end > start) { - __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (start)); - start += line_size; - } - __nds32__isb(); -} - -void cpu_dcache_inval_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = L1_cache_info[DCACHE].line_size; - - while (end > start) { - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start)); - start += line_size; - } -} - -void cpu_dcache_wb_range(unsigned long start, unsigned long end) -{ -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - unsigned long line_size; - - line_size = L1_cache_info[DCACHE].line_size; - - while (end > start) { - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start)); - start += line_size; - } - __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0); -#endif -} - -void cpu_dcache_wbinval_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = L1_cache_info[DCACHE].line_size; - - while (end > start) { -#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH - __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start)); -#endif - __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start)); - start += line_size; - } - __nds32__cctlidx_read(NDS32_CCTL_L1D_IX_RWD,0); -} - -void cpu_cache_wbinval_range(unsigned long start, unsigned long end, int flushi) -{ - unsigned long line_size, align_start, align_end; - - line_size = L1_cache_info[DCACHE].line_size; - align_start = start & ~(line_size - 1); - align_end = (end + line_size - 1) & ~(line_size - 1); - cpu_dcache_wbinval_range(align_start, align_end); - - if (flushi) { - line_size = L1_cache_info[ICACHE].line_size; - align_start = start & ~(line_size - 1); - align_end = (end + line_size - 1) & ~(line_size - 1); - cpu_icache_inval_range(align_start, align_end); - } -} - -void cpu_cache_wbinval_range_check(struct vm_area_struct *vma, - unsigned long start, unsigned long end, - bool flushi, bool wbd) -{ - unsigned long line_size, t_start, t_end; - - if (!flushi && !wbd) - return; - line_size = L1_cache_info[DCACHE].line_size; - start = start & ~(line_size - 1); - end = (end + line_size - 1) & ~(line_size - 1); - - if ((end - start) > (8 * PAGE_SIZE)) { - if (wbd) - cpu_dcache_wbinval_all(); - if (flushi) - cpu_icache_inval_all(); - return; - } - - t_start = (start + PAGE_SIZE) & PAGE_MASK; - t_end = ((end - 1) & PAGE_MASK); - - if ((start & PAGE_MASK) == t_end) { - if (va_present(vma->vm_mm, start)) { - if (wbd) - cpu_dcache_wbinval_range(start, end); - if (flushi) - cpu_icache_inval_range(start, end); - } - return; - } - - if (va_present(vma->vm_mm, start)) { - if (wbd) - cpu_dcache_wbinval_range(start, t_start); - if (flushi) - cpu_icache_inval_range(start, t_start); - } - - if (va_present(vma->vm_mm, end - 1)) { - if (wbd) - cpu_dcache_wbinval_range(t_end, end); - if (flushi) - cpu_icache_inval_range(t_end, end); - } - - while (t_start < t_end) { - if (va_present(vma->vm_mm, t_start)) { - if (wbd) - cpu_dcache_wbinval_page(t_start); - if (flushi) - cpu_icache_inval_page(t_start); - } - t_start += PAGE_SIZE; - } -} - -#ifdef CONFIG_CACHE_L2 -static inline void cpu_l2cache_op(unsigned long start, unsigned long end, unsigned long op) -{ - if (atl2c_base) { - unsigned long p_start = __pa(start); - unsigned long p_end = __pa(end); - unsigned long cmd; - unsigned long line_size; - /* TODO Can Use PAGE Mode to optimize if range large than PAGE_SIZE */ - line_size = L2_CACHE_LINE_SIZE(); - p_start = p_start & (~(line_size - 1)); - p_end = (p_end + line_size - 1) & (~(line_size - 1)); - cmd = - (p_start & ~(line_size - 1)) | op | - CCTL_SINGLE_CMD; - do { - L2_CMD_RDY(); - L2C_W_REG(L2_CCTL_CMD_OFF, cmd); - cmd += line_size; - p_start += line_size; - } while (p_end > p_start); - cmd = CCTL_CMD_L2_SYNC; - L2_CMD_RDY(); - L2C_W_REG(L2_CCTL_CMD_OFF, cmd); - L2_CMD_RDY(); - } -} -#else -#define cpu_l2cache_op(start,end,op) do { } while (0) -#endif -/* - * DMA - */ -void cpu_dma_wb_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - unsigned long flags; - line_size = L1_cache_info[DCACHE].line_size; - start = start & (~(line_size - 1)); - end = (end + line_size - 1) & (~(line_size - 1)); - if (unlikely(start == end)) - return; - - local_irq_save(flags); - cpu_dcache_wb_range(start, end); - cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WB); - __nds32__msync_all(); - local_irq_restore(flags); -} - -void cpu_dma_inval_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - unsigned long old_start = start; - unsigned long old_end = end; - unsigned long flags; - line_size = L1_cache_info[DCACHE].line_size; - start = start & (~(line_size - 1)); - end = (end + line_size - 1) & (~(line_size - 1)); - if (unlikely(start == end)) - return; - local_irq_save(flags); - if (start != old_start) { - cpu_dcache_wbinval_range(start, start + line_size); - cpu_l2cache_op(start, start + line_size, CCTL_CMD_L2_PA_WBINVAL); - } - if (end != old_end) { - cpu_dcache_wbinval_range(end - line_size, end); - cpu_l2cache_op(end - line_size, end, CCTL_CMD_L2_PA_WBINVAL); - } - cpu_dcache_inval_range(start, end); - cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_INVAL); - __nds32__msync_all(); - local_irq_restore(flags); - -} - -void cpu_dma_wbinval_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - unsigned long flags; - line_size = L1_cache_info[DCACHE].line_size; - start = start & (~(line_size - 1)); - end = (end + line_size - 1) & (~(line_size - 1)); - if (unlikely(start == end)) - return; - - local_irq_save(flags); - cpu_dcache_wbinval_range(start, end); - cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WBINVAL); - __nds32__msync_all(); - local_irq_restore(flags); -} - -void cpu_proc_init(void) -{ -} - -void cpu_proc_fin(void) -{ -} - -void cpu_do_idle(void) -{ - __nds32__standby_no_wake_grant(); -} - -void cpu_reset(unsigned long reset) -{ - u32 tmp; - GIE_DISABLE(); - tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL); - tmp &= ~(CACHE_CTL_mskIC_EN | CACHE_CTL_mskDC_EN); - __nds32__mtsr_isb(tmp, NDS32_SR_CACHE_CTL); - cpu_dcache_wbinval_all(); - cpu_icache_inval_all(); - - __asm__ __volatile__("jr.toff %0\n\t"::"r"(reset)); -} - -void cpu_switch_mm(struct mm_struct *mm) -{ - unsigned long cid; - cid = __nds32__mfsr(NDS32_SR_TLB_MISC); - cid = (cid & ~TLB_MISC_mskCID) | mm->context.id; - __nds32__mtsr_dsb(cid, NDS32_SR_TLB_MISC); - __nds32__mtsr_isb(__pa(mm->pgd), NDS32_SR_L1_PPTB); -} diff --git a/arch/nds32/mm/tlb.c b/arch/nds32/mm/tlb.c deleted file mode 100644 index dd41f5e0712f..000000000000 --- a/arch/nds32/mm/tlb.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include - -unsigned int cpu_last_cid = { TLB_MISC_mskCID + (2 << TLB_MISC_offCID) }; - -DEFINE_SPINLOCK(cid_lock); - -void local_flush_tlb_range(struct vm_area_struct *vma, - unsigned long start, unsigned long end) -{ - unsigned long flags, ocid, ncid; - - if ((end - start) > 0x400000) { - __nds32__tlbop_flua(); - __nds32__isb(); - return; - } - - spin_lock_irqsave(&cid_lock, flags); - ocid = __nds32__mfsr(NDS32_SR_TLB_MISC); - ncid = (ocid & ~TLB_MISC_mskCID) | vma->vm_mm->context.id; - __nds32__mtsr_dsb(ncid, NDS32_SR_TLB_MISC); - while (start < end) { - __nds32__tlbop_inv(start); - __nds32__isb(); - start += PAGE_SIZE; - } - __nds32__mtsr_dsb(ocid, NDS32_SR_TLB_MISC); - spin_unlock_irqrestore(&cid_lock, flags); -} - -void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) -{ - unsigned long flags, ocid, ncid; - - spin_lock_irqsave(&cid_lock, flags); - ocid = __nds32__mfsr(NDS32_SR_TLB_MISC); - ncid = (ocid & ~TLB_MISC_mskCID) | vma->vm_mm->context.id; - __nds32__mtsr_dsb(ncid, NDS32_SR_TLB_MISC); - __nds32__tlbop_inv(addr); - __nds32__isb(); - __nds32__mtsr_dsb(ocid, NDS32_SR_TLB_MISC); - spin_unlock_irqrestore(&cid_lock, flags); -} diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig index 33fd06f5fa41..4167f1eb4cd8 100644 --- a/arch/nios2/Kconfig +++ b/arch/nios2/Kconfig @@ -24,7 +24,6 @@ config NIOS2 select USB_ARCH_HAS_HCD if USB_SUPPORT select CPU_NO_EFFICIENT_FFS select MMU_GATHER_NO_RANGE if MMU - select SET_FS config GENERIC_CSUM def_bool y diff --git a/arch/nios2/include/asm/thread_info.h b/arch/nios2/include/asm/thread_info.h index 272d2c72a727..bcc0e9915ebd 100644 --- a/arch/nios2/include/asm/thread_info.h +++ b/arch/nios2/include/asm/thread_info.h @@ -26,10 +26,6 @@ #ifndef __ASSEMBLY__ -typedef struct { - unsigned long seg; -} mm_segment_t; - /* * low level task data that entry.S needs immediate access to * - this struct should fit entirely inside of one cache line @@ -42,10 +38,6 @@ struct thread_info { unsigned long flags; /* low level flags */ __u32 cpu; /* current CPU */ int preempt_count; /* 0 => preemptable,<0 => BUG */ - mm_segment_t addr_limit; /* thread address space: - 0-0x7FFFFFFF for user-thead - 0-0xFFFFFFFF for kernel-thread - */ struct pt_regs *regs; }; @@ -60,7 +52,6 @@ struct thread_info { .flags = 0, \ .cpu = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ } /* how to get the thread information struct from C */ diff --git a/arch/nios2/include/asm/uaccess.h b/arch/nios2/include/asm/uaccess.h index ba9340e96fd4..b8299082adbe 100644 --- a/arch/nios2/include/asm/uaccess.h +++ b/arch/nios2/include/asm/uaccess.h @@ -18,31 +18,10 @@ #include #include - -/* - * Segment stuff - */ -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) -#define USER_DS MAKE_MM_SEG(0x80000000UL) -#define KERNEL_DS MAKE_MM_SEG(0) - - -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(seg) (current_thread_info()->addr_limit = (seg)) - -#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) - -#define __access_ok(addr, len) \ - (((signed long)(((long)get_fs().seg) & \ - ((long)(addr) | (((long)(addr)) + (len)) | (len)))) == 0) - -#define access_ok(addr, len) \ - likely(__access_ok((unsigned long)(addr), (unsigned long)(len))) +#include # define __EX_TABLE_SECTION ".section __ex_table,\"a\"\n" -#define user_addr_max() (uaccess_kernel() ? ~0UL : TASK_SIZE) - /* * Zero Userspace */ @@ -88,6 +67,7 @@ extern __must_check long strnlen_user(const char __user *s, long n); /* Optimized macros */ #define __get_user_asm(val, insn, addr, err) \ { \ + unsigned long __gu_val; \ __asm__ __volatile__( \ " movi %0, %3\n" \ "1: " insn " %1, 0(%2)\n" \ @@ -96,14 +76,20 @@ extern __must_check long strnlen_user(const char __user *s, long n); " .section __ex_table,\"a\"\n" \ " .word 1b, 2b\n" \ " .previous" \ - : "=&r" (err), "=r" (val) \ + : "=&r" (err), "=r" (__gu_val) \ : "r" (addr), "i" (-EFAULT)); \ + val = (__force __typeof__(*(addr)))__gu_val; \ } -#define __get_user_unknown(val, size, ptr, err) do { \ +extern void __get_user_unknown(void); + +#define __get_user_8(val, ptr, err) do { \ + u64 __val = 0; \ err = 0; \ - if (__copy_from_user(&(val), ptr, size)) { \ + if (raw_copy_from_user(&(__val), ptr, sizeof(val))) { \ err = -EFAULT; \ + } else { \ + val = (typeof(val))(typeof((val) - (val)))__val; \ } \ } while (0) @@ -119,8 +105,11 @@ do { \ case 4: \ __get_user_asm(val, "ldw", ptr, err); \ break; \ + case 8: \ + __get_user_8(val, ptr, err); \ + break; \ default: \ - __get_user_unknown(val, size, ptr, err); \ + __get_user_unknown(); \ break; \ } \ } while (0) @@ -129,9 +118,7 @@ do { \ ({ \ long __gu_err = -EFAULT; \ const __typeof__(*(ptr)) __user *__gu_ptr = (ptr); \ - unsigned long __gu_val = 0; \ - __get_user_common(__gu_val, sizeof(*(ptr)), __gu_ptr, __gu_err);\ - (x) = (__force __typeof__(x))__gu_val; \ + __get_user_common(x, sizeof(*(ptr)), __gu_ptr, __gu_err); \ __gu_err; \ }) @@ -139,11 +126,9 @@ do { \ ({ \ long __gu_err = -EFAULT; \ const __typeof__(*(ptr)) __user *__gu_ptr = (ptr); \ - unsigned long __gu_val = 0; \ if (access_ok( __gu_ptr, sizeof(*__gu_ptr))) \ - __get_user_common(__gu_val, sizeof(*__gu_ptr), \ + __get_user_common(x, sizeof(*__gu_ptr), \ __gu_ptr, __gu_err); \ - (x) = (__force __typeof__(x))__gu_val; \ __gu_err; \ }) @@ -161,34 +146,44 @@ do { \ : "r" (val), "r" (ptr), "i" (-EFAULT)); \ } -#define put_user(x, ptr) \ +#define __put_user_common(__pu_val, __pu_ptr) \ ({ \ long __pu_err = -EFAULT; \ - __typeof__(*(ptr)) __user *__pu_ptr = (ptr); \ - __typeof__(*(ptr)) __pu_val = (__typeof(*ptr))(x); \ - if (access_ok(__pu_ptr, sizeof(*__pu_ptr))) { \ - switch (sizeof(*__pu_ptr)) { \ - case 1: \ - __put_user_asm(__pu_val, "stb", __pu_ptr, __pu_err); \ - break; \ - case 2: \ - __put_user_asm(__pu_val, "sth", __pu_ptr, __pu_err); \ - break; \ - case 4: \ - __put_user_asm(__pu_val, "stw", __pu_ptr, __pu_err); \ - break; \ - default: \ - /* XXX: This looks wrong... */ \ - __pu_err = 0; \ - if (copy_to_user(__pu_ptr, &(__pu_val), \ - sizeof(*__pu_ptr))) \ - __pu_err = -EFAULT; \ - break; \ - } \ + switch (sizeof(*__pu_ptr)) { \ + case 1: \ + __put_user_asm(__pu_val, "stb", __pu_ptr, __pu_err); \ + break; \ + case 2: \ + __put_user_asm(__pu_val, "sth", __pu_ptr, __pu_err); \ + break; \ + case 4: \ + __put_user_asm(__pu_val, "stw", __pu_ptr, __pu_err); \ + break; \ + default: \ + /* XXX: This looks wrong... */ \ + __pu_err = 0; \ + if (__copy_to_user(__pu_ptr, &(__pu_val), \ + sizeof(*__pu_ptr))) \ + __pu_err = -EFAULT; \ + break; \ } \ __pu_err; \ }) -#define __put_user(x, ptr) put_user(x, ptr) +#define __put_user(x, ptr) \ +({ \ + __auto_type __pu_ptr = (ptr); \ + typeof(*__pu_ptr) __pu_val = (typeof(*__pu_ptr))(x); \ + __put_user_common(__pu_val, __pu_ptr); \ +}) + +#define put_user(x, ptr) \ +({ \ + __auto_type __pu_ptr = (ptr); \ + typeof(*__pu_ptr) __pu_val = (typeof(*__pu_ptr))(x); \ + access_ok(__pu_ptr, sizeof(*__pu_ptr)) ? \ + __put_user_common(__pu_val, __pu_ptr) : \ + -EFAULT; \ +}) #endif /* _ASM_NIOS2_UACCESS_H */ diff --git a/arch/nios2/kernel/signal.c b/arch/nios2/kernel/signal.c index 2009ae2d3c3b..386e46443b60 100644 --- a/arch/nios2/kernel/signal.c +++ b/arch/nios2/kernel/signal.c @@ -36,10 +36,10 @@ struct rt_sigframe { static inline int rt_restore_ucontext(struct pt_regs *regs, struct switch_stack *sw, - struct ucontext *uc, int *pr2) + struct ucontext __user *uc, int *pr2) { int temp; - unsigned long *gregs = uc->uc_mcontext.gregs; + unsigned long __user *gregs = uc->uc_mcontext.gregs; int err; /* Always make any pending restarted system calls return -EINTR */ @@ -102,10 +102,11 @@ asmlinkage int do_rt_sigreturn(struct switch_stack *sw) { struct pt_regs *regs = (struct pt_regs *)(sw + 1); /* Verify, can we follow the stack back */ - struct rt_sigframe *frame = (struct rt_sigframe *) regs->sp; + struct rt_sigframe __user *frame; sigset_t set; int rval; + frame = (struct rt_sigframe __user *) regs->sp; if (!access_ok(frame, sizeof(*frame))) goto badframe; @@ -124,10 +125,10 @@ badframe: return 0; } -static inline int rt_setup_ucontext(struct ucontext *uc, struct pt_regs *regs) +static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs *regs) { struct switch_stack *sw = (struct switch_stack *)regs - 1; - unsigned long *gregs = uc->uc_mcontext.gregs; + unsigned long __user *gregs = uc->uc_mcontext.gregs; int err = 0; err |= __put_user(MCONTEXT_VERSION, &uc->uc_mcontext.version); @@ -162,8 +163,9 @@ static inline int rt_setup_ucontext(struct ucontext *uc, struct pt_regs *regs) return err; } -static inline void *get_sigframe(struct ksignal *ksig, struct pt_regs *regs, - size_t frame_size) +static inline void __user *get_sigframe(struct ksignal *ksig, + struct pt_regs *regs, + size_t frame_size) { unsigned long usp; @@ -174,13 +176,13 @@ static inline void *get_sigframe(struct ksignal *ksig, struct pt_regs *regs, usp = sigsp(usp, ksig); /* Verify, is it 32 or 64 bit aligned */ - return (void *)((usp - frame_size) & -8UL); + return (void __user *)((usp - frame_size) & -8UL); } static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs) { - struct rt_sigframe *frame; + struct rt_sigframe __user *frame; int err = 0; frame = get_sigframe(ksig, regs, sizeof(*frame)); diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig index f724b3f1aeed..0d68adf6e02b 100644 --- a/arch/openrisc/Kconfig +++ b/arch/openrisc/Kconfig @@ -36,7 +36,6 @@ config OPENRISC select ARCH_WANT_FRAME_POINTERS select GENERIC_IRQ_MULTI_HANDLER select MMU_GATHER_NO_RANGE if MMU - select SET_FS select TRACE_IRQFLAGS_SUPPORT config CPU_BIG_ENDIAN diff --git a/arch/openrisc/include/asm/thread_info.h b/arch/openrisc/include/asm/thread_info.h index 659834ab87fa..4af3049c34c2 100644 --- a/arch/openrisc/include/asm/thread_info.h +++ b/arch/openrisc/include/asm/thread_info.h @@ -40,18 +40,12 @@ */ #ifndef __ASSEMBLY__ -typedef unsigned long mm_segment_t; - struct thread_info { struct task_struct *task; /* main task structure */ unsigned long flags; /* low level flags */ __u32 cpu; /* current CPU */ __s32 preempt_count; /* 0 => preemptable, <0 => BUG */ - mm_segment_t addr_limit; /* thread address space: - 0-0x7FFFFFFF for user-thead - 0-0xFFFFFFFF for kernel-thread - */ __u8 supervisor_stack[0]; /* saved context data */ @@ -71,7 +65,6 @@ struct thread_info { .flags = 0, \ .cpu = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ .ksp = 0, \ } diff --git a/arch/openrisc/include/asm/uaccess.h b/arch/openrisc/include/asm/uaccess.h index 120f5005461b..d6500a374e18 100644 --- a/arch/openrisc/include/asm/uaccess.h +++ b/arch/openrisc/include/asm/uaccess.h @@ -22,44 +22,7 @@ #include #include #include - -/* - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - * - * For historical reasons, these macros are grossly misnamed. - */ - -/* addr_limit is the maximum accessible address for the task. we misuse - * the KERNEL_DS and USER_DS values to both assign and compare the - * addr_limit values through the equally misnamed get/set_fs macros. - * (see above) - */ - -#define KERNEL_DS (~0UL) - -#define USER_DS (TASK_SIZE) -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(x) (current_thread_info()->addr_limit = (x)) - -#define uaccess_kernel() (get_fs() == KERNEL_DS) - -/* Ensure that the range from addr to addr+size is all within the process' - * address space - */ -static inline int __range_ok(unsigned long addr, unsigned long size) -{ - const mm_segment_t fs = get_fs(); - - return size <= fs && addr <= (fs - size); -} - -#define access_ok(addr, size) \ -({ \ - __chk_user_ptr(addr); \ - __range_ok((unsigned long)(addr), (size)); \ -}) +#include /* * These are the main single-value transfer routines. They automatically @@ -268,9 +231,6 @@ clear_user(void __user *addr, unsigned long size) return size; } -#define user_addr_max() \ - (uaccess_kernel() ? ~0UL : TASK_SIZE) - extern long strncpy_from_user(char *dest, const char __user *src, long count); extern __must_check long strnlen_user(const char __user *str, long n); diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig index 864b4756dcdf..00cb889bd9a6 100644 --- a/arch/parisc/Kconfig +++ b/arch/parisc/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 config PARISC def_bool y + select ALTERNATE_USER_ADDRESS_SPACE select ARCH_32BIT_OFF_T if !64BIT select ARCH_MIGHT_HAVE_PC_PARPORT select HAVE_FUNCTION_TRACER diff --git a/arch/parisc/include/asm/futex.h b/arch/parisc/include/asm/futex.h index b5835325d44b..3222206cb3ea 100644 --- a/arch/parisc/include/asm/futex.h +++ b/arch/parisc/include/asm/futex.h @@ -96,12 +96,6 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, u32 val; unsigned long flags; - /* futex.c wants to do a cmpxchg_inatomic on kernel NULL, which is - * our gateway page, and causes no end of trouble... - */ - if (uaccess_kernel() && !uaddr) - return -EFAULT; - if (!access_ok(uaddr, sizeof(u32))) return -EFAULT; diff --git a/arch/parisc/include/asm/uaccess.h b/arch/parisc/include/asm/uaccess.h index b3eb4541e441..2bf660eabe42 100644 --- a/arch/parisc/include/asm/uaccess.h +++ b/arch/parisc/include/asm/uaccess.h @@ -11,15 +11,9 @@ #include #include -/* - * Note that since kernel addresses are in a separate address space on - * parisc, we don't need to do anything for access_ok(). - * We just let the page fault handler do the right thing. This also means - * that put_user is the same as __put_user, etc. - */ - -#define access_ok(uaddr, size) \ - ( (uaddr) == (uaddr) ) +#define TASK_SIZE_MAX DEFAULT_TASK_SIZE +#include +#include #define put_user __put_user #define get_user __get_user @@ -95,7 +89,6 @@ struct exception_table_entry { (val) = (__force __typeof__(*(ptr))) __gu_val; \ } -#define HAVE_GET_KERNEL_NOFAULT #define __get_kernel_nofault(dst, src, type, err_label) \ { \ type __z; \ diff --git a/arch/parisc/include/uapi/asm/shmbuf.h b/arch/parisc/include/uapi/asm/shmbuf.h index 5da3089be65e..532da742fb56 100644 --- a/arch/parisc/include/uapi/asm/shmbuf.h +++ b/arch/parisc/include/uapi/asm/shmbuf.h @@ -3,6 +3,8 @@ #define _PARISC_SHMBUF_H #include +#include +#include /* * The shmid64_ds structure for parisc architecture. diff --git a/arch/parisc/include/uapi/asm/signal.h b/arch/parisc/include/uapi/asm/signal.h index e5a2657477ac..8e4895c5ea5d 100644 --- a/arch/parisc/include/uapi/asm/signal.h +++ b/arch/parisc/include/uapi/asm/signal.h @@ -67,7 +67,7 @@ struct siginfo; typedef struct sigaltstack { void __user *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; #endif /* !__ASSEMBLY */ diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c index 24443908f905..3dd672e2e301 100644 --- a/arch/parisc/kernel/signal.c +++ b/arch/parisc/kernel/signal.c @@ -236,7 +236,7 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs, DBG(1, "%s: frame %p info %p\n", __func__, frame, &ksig->info); start = (unsigned long) frame; - if (start >= user_addr_max() - sigframe_size) + if (start >= TASK_SIZE_MAX - sigframe_size) return -EFAULT; #ifdef CONFIG_64BIT @@ -497,7 +497,7 @@ insert_restart_trampoline(struct pt_regs *regs) long err = 0; /* check that we don't exceed the stack */ - if (A(&usp[0]) >= user_addr_max() - 5 * sizeof(int)) + if (A(&usp[0]) >= TASK_SIZE_MAX - 5 * sizeof(int)) return; /* Call trampoline in vdso to restart the syscall diff --git a/arch/powerpc/include/asm/uaccess.h b/arch/powerpc/include/asm/uaccess.h index 63316100080c..2e83217f52de 100644 --- a/arch/powerpc/include/asm/uaccess.h +++ b/arch/powerpc/include/asm/uaccess.h @@ -11,18 +11,9 @@ #ifdef __powerpc64__ /* We use TASK_SIZE_USER64 as TASK_SIZE is not constant */ #define TASK_SIZE_MAX TASK_SIZE_USER64 -#else -#define TASK_SIZE_MAX TASK_SIZE #endif -static inline bool __access_ok(unsigned long addr, unsigned long size) -{ - return addr < TASK_SIZE_MAX && size <= TASK_SIZE_MAX - addr; -} - -#define access_ok(addr, size) \ - (__chk_user_ptr(addr), \ - __access_ok((unsigned long)(addr), (size))) +#include /* * These are the main single-value transfer routines. They automatically @@ -467,8 +458,6 @@ do { \ unsafe_put_user(*(u8*)(_src + _i), (u8 __user *)(_dst + _i), e); \ } while (0) -#define HAVE_GET_KERNEL_NOFAULT - #define __get_kernel_nofault(dst, src, type, err_label) \ __get_user_size_goto(*((type *)(dst)), \ (__force type __user *)(src), sizeof(type), err_label) diff --git a/arch/powerpc/include/uapi/asm/shmbuf.h b/arch/powerpc/include/uapi/asm/shmbuf.h index 00422b2f3c63..439a3a02ba64 100644 --- a/arch/powerpc/include/uapi/asm/shmbuf.h +++ b/arch/powerpc/include/uapi/asm/shmbuf.h @@ -2,6 +2,9 @@ #ifndef _ASM_POWERPC_SHMBUF_H #define _ASM_POWERPC_SHMBUF_H +#include +#include + /* * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -34,7 +37,7 @@ struct shmid64_ds { unsigned long shm_ctime; /* last change time */ unsigned long __unused4; #endif - size_t shm_segsz; /* size of segment (bytes) */ + __kernel_size_t shm_segsz; /* size of segment (bytes) */ __kernel_pid_t shm_cpid; /* pid of creator */ __kernel_pid_t shm_lpid; /* pid of last operator */ unsigned long shm_nattch; /* no. of current attaches */ diff --git a/arch/powerpc/include/uapi/asm/signal.h b/arch/powerpc/include/uapi/asm/signal.h index 04873dd311c2..37d41d87c45b 100644 --- a/arch/powerpc/include/uapi/asm/signal.h +++ b/arch/powerpc/include/uapi/asm/signal.h @@ -86,7 +86,7 @@ struct sigaction { typedef struct sigaltstack { void __user *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c index bd3734d5be89..5ed88fbee0db 100644 --- a/arch/powerpc/lib/sstep.c +++ b/arch/powerpc/lib/sstep.c @@ -112,9 +112,9 @@ static nokprobe_inline long address_ok(struct pt_regs *regs, { if (!user_mode(regs)) return 1; - if (__access_ok(ea, nb)) + if (access_ok((void __user *)ea, nb)) return 1; - if (__access_ok(ea, 1)) + if (access_ok((void __user *)ea, 1)) /* Access overlaps the end of the user region */ regs->dar = TASK_SIZE_MAX - 1; else diff --git a/arch/riscv/include/asm/uaccess.h b/arch/riscv/include/asm/uaccess.h index c701a5e57a2b..855450bed9f5 100644 --- a/arch/riscv/include/asm/uaccess.h +++ b/arch/riscv/include/asm/uaccess.h @@ -21,42 +21,13 @@ #include #include #include +#include #define __enable_user_access() \ __asm__ __volatile__ ("csrs sstatus, %0" : : "r" (SR_SUM) : "memory") #define __disable_user_access() \ __asm__ __volatile__ ("csrc sstatus, %0" : : "r" (SR_SUM) : "memory") -/** - * access_ok: - Checks if a user space pointer is valid - * @addr: User space pointer to start of block to check - * @size: Size of block to check - * - * Context: User context only. This function may sleep. - * - * Checks if a pointer to a block of memory in user space is valid. - * - * Returns true (nonzero) if the memory block may be valid, false (zero) - * if it is definitely invalid. - * - * Note that, depending on architecture, this function probably just - * checks that the pointer is in the user space range - after calling - * this function, memory access functions may still return -EFAULT. - */ -#define access_ok(addr, size) ({ \ - __chk_user_ptr(addr); \ - likely(__access_ok((unsigned long __force)(addr), (size))); \ -}) - -/* - * Ensure that the range [addr, addr+size) is within the process's - * address space - */ -static inline int __access_ok(unsigned long addr, unsigned long size) -{ - return size <= TASK_SIZE && addr <= TASK_SIZE - size; -} - /* * The exception table consists of pairs of addresses: the first is the * address of an instruction that is allowed to fault, and the second is @@ -346,8 +317,6 @@ unsigned long __must_check clear_user(void __user *to, unsigned long n) __clear_user(to, n) : n; } -#define HAVE_GET_KERNEL_NOFAULT - #define __get_kernel_nofault(dst, src, type, err_label) \ do { \ long __kr_err; \ diff --git a/arch/riscv/kernel/perf_callchain.c b/arch/riscv/kernel/perf_callchain.c index 1fc075b8f764..55faa4991b87 100644 --- a/arch/riscv/kernel/perf_callchain.c +++ b/arch/riscv/kernel/perf_callchain.c @@ -15,8 +15,8 @@ static unsigned long user_backtrace(struct perf_callchain_entry_ctx *entry, { struct stackframe buftail; unsigned long ra = 0; - unsigned long *user_frame_tail = - (unsigned long *)(fp - sizeof(struct stackframe)); + unsigned long __user *user_frame_tail = + (unsigned long __user *)(fp - sizeof(struct stackframe)); /* Check accessibility of one struct frame_tail beyond */ if (!access_ok(user_frame_tail, sizeof(buftail))) diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 4845ab549dd1..2e11ef97c8b9 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig @@ -55,6 +55,7 @@ config S390 # Note: keep this list sorted alphabetically # imply IMA_SECURE_AND_OR_TRUSTED_BOOT + select ALTERNATE_USER_ADDRESS_SPACE select ARCH_32BIT_USTAT_F_TINODE select ARCH_BINFMT_ELF_STATE select ARCH_ENABLE_MEMORY_HOTPLUG if SPARSEMEM diff --git a/arch/s390/include/asm/uaccess.h b/arch/s390/include/asm/uaccess.h index d74e26b48604..5cb258cd9d29 100644 --- a/arch/s390/include/asm/uaccess.h +++ b/arch/s390/include/asm/uaccess.h @@ -17,22 +17,10 @@ #include #include #include +#include void debug_user_asce(int exit); -static inline int __range_ok(unsigned long addr, unsigned long size) -{ - return 1; -} - -#define __access_ok(addr, size) \ -({ \ - __chk_user_ptr(addr); \ - __range_ok((unsigned long)(addr), (size)); \ -}) - -#define access_ok(addr, size) __access_ok(addr, size) - unsigned long __must_check raw_copy_from_user(void *to, const void __user *from, unsigned long n); @@ -282,8 +270,6 @@ static inline unsigned long __must_check clear_user(void __user *to, unsigned lo int copy_to_user_real(void __user *dest, void *src, unsigned long count); void *s390_kernel_write(void *dst, const void *src, size_t size); -#define HAVE_GET_KERNEL_NOFAULT - int __noreturn __put_kernel_bad(void); #define __put_kernel_asm(val, to, insn) \ diff --git a/arch/s390/include/uapi/asm/signal.h b/arch/s390/include/uapi/asm/signal.h index 0189f326aac5..e74d6ba1bd3b 100644 --- a/arch/s390/include/uapi/asm/signal.h +++ b/arch/s390/include/uapi/asm/signal.h @@ -108,7 +108,7 @@ struct sigaction { typedef struct sigaltstack { void __user *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 1c2b53bf3093..5f220e903e5a 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -66,7 +66,6 @@ config SUPERH select PERF_EVENTS select PERF_USE_VMALLOC select RTC_LIB - select SET_FS select SPARSE_IRQ select TRACE_IRQFLAGS_SUPPORT help diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index 3820d698846e..85a6c1c3c16e 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -3,7 +3,6 @@ #define __ASM_SH_PROCESSOR_H #include -#include #include #ifndef __ASSEMBLY__ diff --git a/arch/sh/include/asm/segment.h b/arch/sh/include/asm/segment.h deleted file mode 100644 index 02e54a3335d6..000000000000 --- a/arch/sh/include/asm/segment.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_SH_SEGMENT_H -#define __ASM_SH_SEGMENT_H - -#ifndef __ASSEMBLY__ - -typedef struct { - unsigned long seg; -} mm_segment_t; - -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) - -/* - * The fs value determines whether argument validity checking should be - * performed or not. If get_fs() == USER_DS, checking is performed, with - * get_fs() == KERNEL_DS, checking is bypassed. - * - * For historical reasons, these macros are grossly misnamed. - */ -#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFFUL) -#ifdef CONFIG_MMU -#define USER_DS MAKE_MM_SEG(PAGE_OFFSET) -#else -#define USER_DS KERNEL_DS -#endif - -#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) - -#define get_fs() (current_thread_info()->addr_limit) -#define set_fs(x) (current_thread_info()->addr_limit = (x)) - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_SH_SEGMENT_H */ diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h index 598d0184ffea..b119b859a0a3 100644 --- a/arch/sh/include/asm/thread_info.h +++ b/arch/sh/include/asm/thread_info.h @@ -30,7 +30,6 @@ struct thread_info { __u32 status; /* thread synchronous flags */ __u32 cpu; int preempt_count; /* 0 => preemptable, <0 => BUG */ - mm_segment_t addr_limit; /* thread address space */ unsigned long previous_sp; /* sp of previous stack in case of nested IRQ stacks */ __u8 supervisor_stack[0]; @@ -58,7 +57,6 @@ struct thread_info { .status = 0, \ .cpu = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ } /* how to get the current stack pointer from C */ diff --git a/arch/sh/include/asm/uaccess.h b/arch/sh/include/asm/uaccess.h index 8867bb04b00e..a79609eb14be 100644 --- a/arch/sh/include/asm/uaccess.h +++ b/arch/sh/include/asm/uaccess.h @@ -2,30 +2,8 @@ #ifndef __ASM_SH_UACCESS_H #define __ASM_SH_UACCESS_H -#include #include - -#define __addr_ok(addr) \ - ((unsigned long __force)(addr) < current_thread_info()->addr_limit.seg) - -/* - * __access_ok: Check if address with size is OK or not. - * - * Uhhuh, this needs 33-bit arithmetic. We have a carry.. - * - * sum := addr + size; carry? --> flag = true; - * if (sum >= addr_limit) flag = true; - */ -#define __access_ok(addr, size) ({ \ - unsigned long __ao_a = (addr), __ao_b = (size); \ - unsigned long __ao_end = __ao_a + __ao_b - !!__ao_b; \ - __ao_end >= __ao_a && __addr_ok(__ao_end); }) - -#define access_ok(addr, size) \ - (__chk_user_ptr(addr), \ - __access_ok((unsigned long __force)(addr), (size))) - -#define user_addr_max() (current_thread_info()->addr_limit.seg) +#include /* * Uh, these should become the main single-value transfer routines ... diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c index 004ad0130b10..e803b14ef12e 100644 --- a/arch/sh/kernel/io_trapped.c +++ b/arch/sh/kernel/io_trapped.c @@ -270,7 +270,6 @@ static struct mem_access trapped_io_access = { int handle_trapped_io(struct pt_regs *regs, unsigned long address) { - mm_segment_t oldfs; insn_size_t instruction; int tmp; @@ -281,16 +280,12 @@ int handle_trapped_io(struct pt_regs *regs, unsigned long address) WARN_ON(user_mode(regs)); - oldfs = get_fs(); - set_fs(KERNEL_DS); - if (copy_from_user(&instruction, (void *)(regs->pc), - sizeof(instruction))) { - set_fs(oldfs); + if (copy_from_kernel_nofault(&instruction, (void *)(regs->pc), + sizeof(instruction))) { return 0; } tmp = handle_unaligned_access(instruction, regs, &trapped_io_access, 1, address); - set_fs(oldfs); return tmp == 0; } diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c index 1c28e3cddb60..ca01286a0610 100644 --- a/arch/sh/kernel/process_32.c +++ b/arch/sh/kernel/process_32.c @@ -123,7 +123,6 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, unsigned long arg, #if defined(CONFIG_SH_FPU) childregs->sr |= SR_FD; #endif - ti->addr_limit = KERNEL_DS; ti->status &= ~TS_USEDFPU; p->thread.fpu_counter = 0; return 0; @@ -132,7 +131,6 @@ int copy_thread(unsigned long clone_flags, unsigned long usp, unsigned long arg, if (usp) childregs->regs[15] = usp; - ti->addr_limit = USER_DS; if (clone_flags & CLONE_SETTLS) childregs->gbr = tls; diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c index b3c715bc254b..6cdda3a621a1 100644 --- a/arch/sh/kernel/traps_32.c +++ b/arch/sh/kernel/traps_32.c @@ -75,6 +75,23 @@ static struct mem_access user_mem_access = { copy_to_user, }; +static unsigned long copy_from_kernel_wrapper(void *dst, const void __user *src, + unsigned long cnt) +{ + return copy_from_kernel_nofault(dst, (const void __force *)src, cnt); +} + +static unsigned long copy_to_kernel_wrapper(void __user *dst, const void *src, + unsigned long cnt) +{ + return copy_to_kernel_nofault((void __force *)dst, src, cnt); +} + +static struct mem_access kernel_mem_access = { + copy_from_kernel_wrapper, + copy_to_kernel_wrapper, +}; + /* * handle an instruction that does an unaligned memory access by emulating the * desired behaviour @@ -473,7 +490,6 @@ asmlinkage void do_address_error(struct pt_regs *regs, unsigned long address) { unsigned long error_code = 0; - mm_segment_t oldfs; insn_size_t instruction; int tmp; @@ -489,13 +505,10 @@ asmlinkage void do_address_error(struct pt_regs *regs, local_irq_enable(); inc_unaligned_user_access(); - oldfs = force_uaccess_begin(); if (copy_from_user(&instruction, (insn_size_t __user *)(regs->pc & ~1), sizeof(instruction))) { - force_uaccess_end(oldfs); goto uspace_segv; } - force_uaccess_end(oldfs); /* shout about userspace fixups */ unaligned_fixups_notify(current, instruction, regs); @@ -518,11 +531,9 @@ fixup: goto uspace_segv; } - oldfs = force_uaccess_begin(); tmp = handle_unaligned_access(instruction, regs, &user_mem_access, 0, address); - force_uaccess_end(oldfs); if (tmp == 0) return; /* sorted */ @@ -538,21 +549,18 @@ uspace_segv: if (regs->pc & 1) die("unaligned program counter", regs, error_code); - set_fs(KERNEL_DS); - if (copy_from_user(&instruction, (void __user *)(regs->pc), + if (copy_from_kernel_nofault(&instruction, (void *)(regs->pc), sizeof(instruction))) { /* Argh. Fault on the instruction itself. This should never happen non-SMP */ - set_fs(oldfs); die("insn faulting in do_address_error", regs, 0); } unaligned_fixups_notify(current, instruction, regs); - handle_unaligned_access(instruction, regs, &user_mem_access, + handle_unaligned_access(instruction, regs, &kernel_mem_access, 0, address); - set_fs(oldfs); } } diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 1cab1b284f1a..9200bc04701c 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -46,7 +46,6 @@ config SPARC select LOCKDEP_SMALL if LOCKDEP select NEED_DMA_MAP_STATE select NEED_SG_DMA_LENGTH - select SET_FS select TRACE_IRQFLAGS_SUPPORT config SPARC32 @@ -62,6 +61,7 @@ config SPARC32 config SPARC64 def_bool 64BIT + select ALTERNATE_USER_ADDRESS_SPACE select HAVE_FUNCTION_TRACER select HAVE_FUNCTION_GRAPH_TRACER select HAVE_KRETPROBES diff --git a/arch/sparc/include/asm/processor_32.h b/arch/sparc/include/asm/processor_32.h index 647bf0ac7beb..b26c35336b51 100644 --- a/arch/sparc/include/asm/processor_32.h +++ b/arch/sparc/include/asm/processor_32.h @@ -32,10 +32,6 @@ struct fpq { }; #endif -typedef struct { - int seg; -} mm_segment_t; - /* The Sparc processor specific thread struct. */ struct thread_struct { struct pt_regs *kregs; @@ -50,11 +46,9 @@ struct thread_struct { unsigned long fsr; unsigned long fpqdepth; struct fpq fpqueue[16]; - mm_segment_t current_ds; }; #define INIT_THREAD { \ - .current_ds = KERNEL_DS, \ .kregs = (struct pt_regs *)(init_stack+THREAD_SIZE)-1 \ } diff --git a/arch/sparc/include/asm/processor_64.h b/arch/sparc/include/asm/processor_64.h index ae851e8fce4c..89850dff6b03 100644 --- a/arch/sparc/include/asm/processor_64.h +++ b/arch/sparc/include/asm/processor_64.h @@ -47,10 +47,6 @@ #ifndef __ASSEMBLY__ -typedef struct { - unsigned char seg; -} mm_segment_t; - /* The Sparc processor specific thread struct. */ /* XXX This should die, everything can go into thread_info now. */ struct thread_struct { diff --git a/arch/sparc/include/asm/switch_to_64.h b/arch/sparc/include/asm/switch_to_64.h index b1d4e2e3210f..14f3c49bfdbc 100644 --- a/arch/sparc/include/asm/switch_to_64.h +++ b/arch/sparc/include/asm/switch_to_64.h @@ -20,10 +20,8 @@ do { \ */ #define switch_to(prev, next, last) \ do { save_and_clear_fpu(); \ - /* If you are tempted to conditionalize the following */ \ - /* so that ASI is only written if it changes, think again. */ \ __asm__ __volatile__("wr %%g0, %0, %%asi" \ - : : "r" (task_thread_info(next)->current_ds));\ + : : "r" (ASI_AIUS)); \ trap_block[current_thread_info()->cpu].thread = \ task_thread_info(next); \ __asm__ __volatile__( \ diff --git a/arch/sparc/include/asm/thread_info_64.h b/arch/sparc/include/asm/thread_info_64.h index 8047a9caab2f..1a44372e2bc0 100644 --- a/arch/sparc/include/asm/thread_info_64.h +++ b/arch/sparc/include/asm/thread_info_64.h @@ -46,7 +46,7 @@ struct thread_info { struct pt_regs *kregs; int preempt_count; /* 0 => preemptable, <0 => BUG */ __u8 new_child; - __u8 current_ds; + __u8 __pad; __u16 cpu; unsigned long *utraps; @@ -81,7 +81,6 @@ struct thread_info { #define TI_KREGS 0x00000028 #define TI_PRE_COUNT 0x00000030 #define TI_NEW_CHILD 0x00000034 -#define TI_CURRENT_DS 0x00000035 #define TI_CPU 0x00000036 #define TI_UTRAPS 0x00000038 #define TI_REG_WINDOW 0x00000040 @@ -116,7 +115,6 @@ struct thread_info { #define INIT_THREAD_INFO(tsk) \ { \ .task = &tsk, \ - .current_ds = ASI_P, \ .preempt_count = INIT_PREEMPT_COUNT, \ .kregs = (struct pt_regs *)(init_stack+THREAD_SIZE)-1 \ } diff --git a/arch/sparc/include/asm/uaccess.h b/arch/sparc/include/asm/uaccess.h index 390094200fc4..ee75f69e3fcd 100644 --- a/arch/sparc/include/asm/uaccess.h +++ b/arch/sparc/include/asm/uaccess.h @@ -10,9 +10,6 @@ #include #endif -#define user_addr_max() \ - (uaccess_kernel() ? ~0UL : TASK_SIZE) - long strncpy_from_user(char *dest, const char __user *src, long count); #endif diff --git a/arch/sparc/include/asm/uaccess_32.h b/arch/sparc/include/asm/uaccess_32.h index 4a12346bb69c..9fd6c53644b6 100644 --- a/arch/sparc/include/asm/uaccess_32.h +++ b/arch/sparc/include/asm/uaccess_32.h @@ -12,30 +12,7 @@ #include #include - -/* Sparc is not segmented, however we need to be able to fool access_ok() - * when doing system calls from kernel mode legitimately. - * - * "For historical reasons, these macros are grossly misnamed." -Linus - */ - -#define KERNEL_DS ((mm_segment_t) { 0 }) -#define USER_DS ((mm_segment_t) { -1 }) - -#define get_fs() (current->thread.current_ds) -#define set_fs(val) ((current->thread.current_ds) = (val)) - -#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) - -/* We have there a nice not-mapped page at PAGE_OFFSET - PAGE_SIZE, so that this test - * can be fairly lightweight. - * No one can read/write anything from userland in the kernel space by setting - * large size and address near to PAGE_OFFSET - a fault will break his intentions. - */ -#define __user_ok(addr, size) ({ (void)(size); (addr) < STACK_TOP; }) -#define __kernel_ok (uaccess_kernel()) -#define __access_ok(addr, size) (__user_ok((addr) & get_fs().seg, (size))) -#define access_ok(addr, size) __access_ok((unsigned long)(addr), size) +#include /* Uh, these should become the main single-value transfer routines.. * They automatically use the right size if we just have the right @@ -47,13 +24,13 @@ * and hide all the ugliness from the user. */ #define put_user(x, ptr) ({ \ - unsigned long __pu_addr = (unsigned long)(ptr); \ + void __user *__pu_addr = (ptr); \ __chk_user_ptr(ptr); \ __put_user_check((__typeof__(*(ptr)))(x), __pu_addr, sizeof(*(ptr))); \ }) #define get_user(x, ptr) ({ \ - unsigned long __gu_addr = (unsigned long)(ptr); \ + const void __user *__gu_addr = (ptr); \ __chk_user_ptr(ptr); \ __get_user_check((x), __gu_addr, sizeof(*(ptr)), __typeof__(*(ptr))); \ }) @@ -232,7 +209,7 @@ static inline unsigned long __clear_user(void __user *addr, unsigned long size) static inline unsigned long clear_user(void __user *addr, unsigned long n) { - if (n && __access_ok((unsigned long) addr, n)) + if (n && __access_ok(addr, n)) return __clear_user(addr, n); else return n; diff --git a/arch/sparc/include/asm/uaccess_64.h b/arch/sparc/include/asm/uaccess_64.h index 30eb4c6414d1..94266a5c5b04 100644 --- a/arch/sparc/include/asm/uaccess_64.h +++ b/arch/sparc/include/asm/uaccess_64.h @@ -12,33 +12,15 @@ #include #include +#include /* * Sparc64 is segmented, though more like the M68K than the I386. * We use the secondary ASI to address user memory, which references a * completely different VM map, thus there is zero chance of the user * doing something queer and tricking us into poking kernel memory. - * - * What is left here is basically what is needed for the other parts of - * the kernel that expect to be able to manipulate, erum, "segments". - * Or perhaps more properly, permissions. - * - * "For historical reasons, these macros are grossly misnamed." -Linus */ -#define KERNEL_DS ((mm_segment_t) { ASI_P }) -#define USER_DS ((mm_segment_t) { ASI_AIUS }) /* har har har */ - -#define get_fs() ((mm_segment_t){(current_thread_info()->current_ds)}) - -#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) - -#define set_fs(val) \ -do { \ - current_thread_info()->current_ds = (val).seg; \ - __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "r" ((val).seg)); \ -} while(0) - /* * Test whether a block of memory is a valid user space address. * Returns 0 if the range is valid, nonzero otherwise. @@ -61,16 +43,6 @@ static inline bool __chk_range_not_ok(unsigned long addr, unsigned long size, un __chk_range_not_ok((unsigned long __force)(addr), size, limit); \ }) -static inline int __access_ok(const void __user * addr, unsigned long size) -{ - return 1; -} - -static inline int access_ok(const void __user * addr, unsigned long size) -{ - return 1; -} - void __retl_efault(void); /* Uh, these should become the main single-value transfer routines.. @@ -100,6 +72,42 @@ void __retl_efault(void); struct __large_struct { unsigned long buf[100]; }; #define __m(x) ((struct __large_struct *)(x)) +#define __put_kernel_nofault(dst, src, type, label) \ +do { \ + type *addr = (type __force *)(dst); \ + type data = *(type *)src; \ + register int __pu_ret; \ + switch (sizeof(type)) { \ + case 1: __put_kernel_asm(data, b, addr, __pu_ret); break; \ + case 2: __put_kernel_asm(data, h, addr, __pu_ret); break; \ + case 4: __put_kernel_asm(data, w, addr, __pu_ret); break; \ + case 8: __put_kernel_asm(data, x, addr, __pu_ret); break; \ + default: __pu_ret = __put_user_bad(); break; \ + } \ + if (__pu_ret) \ + goto label; \ +} while (0) + +#define __put_kernel_asm(x, size, addr, ret) \ +__asm__ __volatile__( \ + "/* Put kernel asm, inline. */\n" \ + "1:\t" "st"#size " %1, [%2]\n\t" \ + "clr %0\n" \ + "2:\n\n\t" \ + ".section .fixup,#alloc,#execinstr\n\t" \ + ".align 4\n" \ + "3:\n\t" \ + "sethi %%hi(2b), %0\n\t" \ + "jmpl %0 + %%lo(2b), %%g0\n\t" \ + " mov %3, %0\n\n\t" \ + ".previous\n\t" \ + ".section __ex_table,\"a\"\n\t" \ + ".align 4\n\t" \ + ".word 1b, 3b\n\t" \ + ".previous\n\n\t" \ + : "=r" (ret) : "r" (x), "r" (__m(addr)), \ + "i" (-EFAULT)) + #define __put_user_nocheck(data, addr, size) ({ \ register int __pu_ret; \ switch (size) { \ @@ -134,6 +142,46 @@ __asm__ __volatile__( \ int __put_user_bad(void); +#define __get_kernel_nofault(dst, src, type, label) \ +do { \ + type *addr = (type __force *)(src); \ + register int __gu_ret; \ + register unsigned long __gu_val; \ + switch (sizeof(type)) { \ + case 1: __get_kernel_asm(__gu_val, ub, addr, __gu_ret); break; \ + case 2: __get_kernel_asm(__gu_val, uh, addr, __gu_ret); break; \ + case 4: __get_kernel_asm(__gu_val, uw, addr, __gu_ret); break; \ + case 8: __get_kernel_asm(__gu_val, x, addr, __gu_ret); break; \ + default: \ + __gu_val = 0; \ + __gu_ret = __get_user_bad(); \ + break; \ + } \ + if (__gu_ret) \ + goto label; \ + *(type *)dst = (__force type) __gu_val; \ +} while (0) +#define __get_kernel_asm(x, size, addr, ret) \ +__asm__ __volatile__( \ + "/* Get kernel asm, inline. */\n" \ + "1:\t" "ld"#size " [%2], %1\n\t" \ + "clr %0\n" \ + "2:\n\n\t" \ + ".section .fixup,#alloc,#execinstr\n\t" \ + ".align 4\n" \ + "3:\n\t" \ + "sethi %%hi(2b), %0\n\t" \ + "clr %1\n\t" \ + "jmpl %0 + %%lo(2b), %%g0\n\t" \ + " mov %3, %0\n\n\t" \ + ".previous\n\t" \ + ".section __ex_table,\"a\"\n\t" \ + ".align 4\n\t" \ + ".word 1b, 3b\n\n\t" \ + ".previous\n\t" \ + : "=r" (ret), "=r" (x) : "r" (__m(addr)), \ + "i" (-EFAULT)) + #define __get_user_nocheck(data, addr, size, type) ({ \ register int __gu_ret; \ register unsigned long __gu_val; \ diff --git a/arch/sparc/include/uapi/asm/shmbuf.h b/arch/sparc/include/uapi/asm/shmbuf.h index a5d7d8d681c4..ed4f061c7a15 100644 --- a/arch/sparc/include/uapi/asm/shmbuf.h +++ b/arch/sparc/include/uapi/asm/shmbuf.h @@ -2,6 +2,9 @@ #ifndef _SPARC_SHMBUF_H #define _SPARC_SHMBUF_H +#include +#include + /* * The shmid64_ds structure for sparc architecture. * Note extra padding because this structure is passed back and forth @@ -25,7 +28,7 @@ struct shmid64_ds { unsigned long shm_ctime_high; unsigned long shm_ctime; /* last change time */ #endif - size_t shm_segsz; /* size of segment (bytes) */ + __kernel_size_t shm_segsz; /* size of segment (bytes) */ __kernel_pid_t shm_cpid; /* pid of creator */ __kernel_pid_t shm_lpid; /* pid of last operator */ unsigned long shm_nattch; /* no. of current attaches */ diff --git a/arch/sparc/include/uapi/asm/signal.h b/arch/sparc/include/uapi/asm/signal.h index 53758d53ac0e..b61382924725 100644 --- a/arch/sparc/include/uapi/asm/signal.h +++ b/arch/sparc/include/uapi/asm/signal.h @@ -151,6 +151,7 @@ struct sigstack { #include +#include #ifndef __KERNEL__ struct __new_sigaction { @@ -171,7 +172,7 @@ struct __old_sigaction { typedef struct sigaltstack { void __user *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c index 2dc0bf9fe62e..88c0c14aaff0 100644 --- a/arch/sparc/kernel/process_32.c +++ b/arch/sparc/kernel/process_32.c @@ -300,7 +300,6 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg, extern int nwindows; unsigned long psr; memset(new_stack, 0, STACKFRAME_SZ + TRACEREG_SZ); - p->thread.current_ds = KERNEL_DS; ti->kpc = (((unsigned long) ret_from_kernel_thread) - 0x8); childregs->u_regs[UREG_G1] = sp; /* function */ childregs->u_regs[UREG_G2] = arg; @@ -311,7 +310,6 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg, } memcpy(new_stack, (char *)regs - STACKFRAME_SZ, STACKFRAME_SZ + TRACEREG_SZ); childregs->u_regs[UREG_FP] = sp; - p->thread.current_ds = USER_DS; ti->kpc = (((unsigned long) ret_from_fork) - 0x8); ti->kpsr = current->thread.fork_kpsr | PSR_PIL; ti->kwim = current->thread.fork_kwim; diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c index f5b2cac8669f..9a2ceb080ac9 100644 --- a/arch/sparc/kernel/process_64.c +++ b/arch/sparc/kernel/process_64.c @@ -106,18 +106,13 @@ static void show_regwindow32(struct pt_regs *regs) { struct reg_window32 __user *rw; struct reg_window32 r_w; - mm_segment_t old_fs; __asm__ __volatile__ ("flushw"); rw = compat_ptr((unsigned int)regs->u_regs[14]); - old_fs = get_fs(); - set_fs (USER_DS); if (copy_from_user (&r_w, rw, sizeof(r_w))) { - set_fs (old_fs); return; } - set_fs (old_fs); printk("l0: %08x l1: %08x l2: %08x l3: %08x " "l4: %08x l5: %08x l6: %08x l7: %08x\n", r_w.locals[0], r_w.locals[1], r_w.locals[2], r_w.locals[3], @@ -136,7 +131,6 @@ static void show_regwindow(struct pt_regs *regs) struct reg_window __user *rw; struct reg_window *rwk; struct reg_window r_w; - mm_segment_t old_fs; if ((regs->tstate & TSTATE_PRIV) || !(test_thread_flag(TIF_32BIT))) { __asm__ __volatile__ ("flushw"); @@ -145,14 +139,10 @@ static void show_regwindow(struct pt_regs *regs) rwk = (struct reg_window *) (regs->u_regs[14] + STACK_BIAS); if (!(regs->tstate & TSTATE_PRIV)) { - old_fs = get_fs(); - set_fs (USER_DS); if (copy_from_user (&r_w, rw, sizeof(r_w))) { - set_fs (old_fs); return; } rwk = &r_w; - set_fs (old_fs); } } else { show_regwindow32(regs); @@ -598,7 +588,6 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg, memset(child_trap_frame, 0, child_stack_sz); __thread_flag_byte_ptr(t)[TI_FLAG_BYTE_CWP] = (current_pt_regs()->tstate + 1) & TSTATE_CWP; - t->current_ds = ASI_P; t->kregs->u_regs[UREG_G1] = sp; /* function */ t->kregs->u_regs[UREG_G2] = arg; return 0; @@ -613,7 +602,6 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg, t->kregs->u_regs[UREG_FP] = sp; __thread_flag_byte_ptr(t)[TI_FLAG_BYTE_CWP] = (regs->tstate + 1) & TSTATE_CWP; - t->current_ds = ASI_AIUS; if (sp != regs->u_regs[UREG_FP]) { unsigned long csp; diff --git a/arch/sparc/kernel/signal_32.c b/arch/sparc/kernel/signal_32.c index ffab16369bea..74f80443b195 100644 --- a/arch/sparc/kernel/signal_32.c +++ b/arch/sparc/kernel/signal_32.c @@ -65,7 +65,7 @@ struct rt_signal_frame { */ static inline bool invalid_frame_pointer(void __user *fp, int fplen) { - if ((((unsigned long) fp) & 15) || !__access_ok((unsigned long)fp, fplen)) + if ((((unsigned long) fp) & 15) || !access_ok(fp, fplen)) return true; return false; diff --git a/arch/sparc/kernel/traps_64.c b/arch/sparc/kernel/traps_64.c index 21077821f427..5b4de4a89dec 100644 --- a/arch/sparc/kernel/traps_64.c +++ b/arch/sparc/kernel/traps_64.c @@ -2857,8 +2857,6 @@ void __init trap_init(void) TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) || TI_NEW_CHILD != offsetof(struct thread_info, new_child) || - TI_CURRENT_DS != offsetof(struct thread_info, - current_ds) || TI_KUNA_REGS != offsetof(struct thread_info, kern_una_regs) || TI_KUNA_INSN != offsetof(struct thread_info, diff --git a/arch/sparc/lib/NGmemcpy.S b/arch/sparc/lib/NGmemcpy.S index 8e4d22a6ba0b..ee51c1230689 100644 --- a/arch/sparc/lib/NGmemcpy.S +++ b/arch/sparc/lib/NGmemcpy.S @@ -10,8 +10,7 @@ #include #define GLOBAL_SPARE %g7 #define RESTORE_ASI(TMP) \ - ldub [%g6 + TI_CURRENT_DS], TMP; \ - wr TMP, 0x0, %asi; + wr %g0, ASI_AIUS, %asi #else #define GLOBAL_SPARE %g5 #define RESTORE_ASI(TMP) \ diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c index 1b23639e2fcd..8b1911591581 100644 --- a/arch/sparc/mm/init_64.c +++ b/arch/sparc/mm/init_64.c @@ -709,9 +709,10 @@ static void __init inherit_prom_mappings(void) void prom_world(int enter) { - if (!enter) - set_fs(get_fs()); - + /* + * No need to change the address space any more, just flush + * the register windows + */ __asm__ __volatile__("flushw"); } diff --git a/arch/um/include/asm/uaccess.h b/arch/um/include/asm/uaccess.h index 17d18cfd82a5..7d9d60e41e4e 100644 --- a/arch/um/include/asm/uaccess.h +++ b/arch/um/include/asm/uaccess.h @@ -25,7 +25,7 @@ extern unsigned long raw_copy_from_user(void *to, const void __user *from, unsigned long n); extern unsigned long raw_copy_to_user(void __user *to, const void *from, unsigned long n); extern unsigned long __clear_user(void __user *mem, unsigned long len); -static inline int __access_ok(unsigned long addr, unsigned long size); +static inline int __access_ok(const void __user *ptr, unsigned long size); /* Teach asm-generic/uaccess.h that we have C functions for these. */ #define __access_ok __access_ok @@ -36,16 +36,15 @@ static inline int __access_ok(unsigned long addr, unsigned long size); #include -static inline int __access_ok(unsigned long addr, unsigned long size) +static inline int __access_ok(const void __user *ptr, unsigned long size) { + unsigned long addr = (unsigned long)ptr; return __addr_range_nowrap(addr, size) && (__under_task_size(addr, size) || __access_ok_vsyscall(addr, size)); } /* no pagefaults for kernel addresses in um */ -#define HAVE_GET_KERNEL_NOFAULT 1 - #define __get_kernel_nofault(dst, src, type, err_label) \ do { \ *((type *)dst) = get_unaligned((type *)(src)); \ diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index e686c5e0537b..eef816fc216d 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2794,7 +2794,7 @@ perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *re static inline int valid_user_frame(const void __user *fp, unsigned long size) { - return (__range_not_ok(fp, size, TASK_SIZE) == 0); + return __access_ok(fp, size); } static unsigned long get_segment_base(unsigned int segment) diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index ac96f9b2d64b..f78e2b3501a1 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -12,35 +12,6 @@ #include #include -/* - * Test whether a block of memory is a valid user space address. - * Returns 0 if the range is valid, nonzero otherwise. - */ -static inline bool __chk_range_not_ok(unsigned long addr, unsigned long size, unsigned long limit) -{ - /* - * If we have used "sizeof()" for the size, - * we know it won't overflow the limit (but - * it might overflow the 'addr', so it's - * important to subtract the size from the - * limit, not add it to the address). - */ - if (__builtin_constant_p(size)) - return unlikely(addr > limit - size); - - /* Arbitrary sizes? Be careful about overflow */ - addr += size; - if (unlikely(addr < size)) - return true; - return unlikely(addr > limit); -} - -#define __range_not_ok(addr, size, limit) \ -({ \ - __chk_user_ptr(addr); \ - __chk_range_not_ok((unsigned long __force)(addr), size, limit); \ -}) - #ifdef CONFIG_DEBUG_ATOMIC_SLEEP static inline bool pagefault_disabled(void); # define WARN_ON_IN_IRQ() \ @@ -69,9 +40,11 @@ static inline bool pagefault_disabled(void); #define access_ok(addr, size) \ ({ \ WARN_ON_IN_IRQ(); \ - likely(!__range_not_ok(addr, size, TASK_SIZE_MAX)); \ + likely(__access_ok(addr, size)); \ }) +#include + extern int __get_user_1(void); extern int __get_user_2(void); extern int __get_user_4(void); @@ -524,8 +497,6 @@ do { \ unsafe_copy_loop(__ucu_dst, __ucu_src, __ucu_len, u8, label); \ } while (0) -#define HAVE_GET_KERNEL_NOFAULT - #ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT #define __get_kernel_nofault(dst, src, type, err_label) \ __get_user_size(*((type *)(dst)), (__force type __user *)(src), \ diff --git a/arch/x86/include/uapi/asm/shmbuf.h b/arch/x86/include/uapi/asm/shmbuf.h index fce18eaa070c..13775bfdfee2 100644 --- a/arch/x86/include/uapi/asm/shmbuf.h +++ b/arch/x86/include/uapi/asm/shmbuf.h @@ -5,6 +5,10 @@ #if !defined(__x86_64__) || !defined(__ILP32__) #include #else + +#include +#include + /* * The shmid64_ds structure for x86 architecture with x32 ABI. * @@ -15,7 +19,7 @@ struct shmid64_ds { struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ + __kernel_size_t shm_segsz; /* size of segment (bytes) */ __kernel_long_t shm_atime; /* last attach time */ __kernel_long_t shm_dtime; /* last detach time */ __kernel_long_t shm_ctime; /* last change time */ diff --git a/arch/x86/include/uapi/asm/signal.h b/arch/x86/include/uapi/asm/signal.h index 164a22a72984..777c3a0f4e23 100644 --- a/arch/x86/include/uapi/asm/signal.h +++ b/arch/x86/include/uapi/asm/signal.h @@ -104,7 +104,7 @@ struct sigaction { typedef struct sigaltstack { void __user *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 53de044e5654..afae4dd77495 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -81,12 +81,6 @@ static int copy_code(struct pt_regs *regs, u8 *buf, unsigned long src, /* The user space code from other tasks cannot be accessed. */ if (regs != task_pt_regs(current)) return -EPERM; - /* - * Make sure userspace isn't trying to trick us into dumping kernel - * memory by pointing the userspace instruction pointer at it. - */ - if (__chk_range_not_ok(src, nbytes, TASK_SIZE_MAX)) - return -EINVAL; /* * Even if named copy_from_user_nmi() this can be invoked from diff --git a/arch/x86/kernel/stacktrace.c b/arch/x86/kernel/stacktrace.c index 15b058eefc4e..ee117fcf46ed 100644 --- a/arch/x86/kernel/stacktrace.c +++ b/arch/x86/kernel/stacktrace.c @@ -90,7 +90,7 @@ copy_stack_frame(const struct stack_frame_user __user *fp, { int ret; - if (__range_not_ok(fp, sizeof(*frame), TASK_SIZE)) + if (!__access_ok(fp, sizeof(*frame))) return 0; ret = 1; diff --git a/arch/x86/lib/usercopy.c b/arch/x86/lib/usercopy.c index c3e8a62ca561..ad0139d25401 100644 --- a/arch/x86/lib/usercopy.c +++ b/arch/x86/lib/usercopy.c @@ -32,7 +32,7 @@ copy_from_user_nmi(void *to, const void __user *from, unsigned long n) { unsigned long ret; - if (__range_not_ok(from, n, TASK_SIZE)) + if (!__access_ok(from, n)) return n; if (!nmi_uaccess_okay()) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 887432327613..95bdbaaa5ae6 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -41,7 +41,6 @@ config XTENSA select IRQ_DOMAIN select MODULES_USE_ELF_RELA select PERF_USE_VMALLOC - select SET_FS select TRACE_IRQFLAGS_SUPPORT select VIRT_TO_BUS help diff --git a/arch/xtensa/include/asm/asm-uaccess.h b/arch/xtensa/include/asm/asm-uaccess.h index 7f6cf4151843..7cec869136e3 100644 --- a/arch/xtensa/include/asm/asm-uaccess.h +++ b/arch/xtensa/include/asm/asm-uaccess.h @@ -23,76 +23,6 @@ #include #include -/* - * These assembly macros mirror the C macros in asm/uaccess.h. They - * should always have identical functionality. See - * arch/xtensa/kernel/sys.S for usage. - */ - -#define KERNEL_DS 0 -#define USER_DS 1 - -/* - * get_fs reads current->thread.current_ds into a register. - * On Entry: - * anything - * stack - * On Exit: - * contains current->thread.current_ds - */ - .macro get_fs ad, sp - GET_CURRENT(\ad,\sp) -#if THREAD_CURRENT_DS > 1020 - addi \ad, \ad, TASK_THREAD - l32i \ad, \ad, THREAD_CURRENT_DS - TASK_THREAD -#else - l32i \ad, \ad, THREAD_CURRENT_DS -#endif - .endm - -/* - * set_fs sets current->thread.current_ds to some value. - * On Entry: - * anything (temp register) - * value to write - * stack - * On Exit: - * destroyed (actually, current) - * preserved, value to write - */ - .macro set_fs at, av, sp - GET_CURRENT(\at,\sp) - s32i \av, \at, THREAD_CURRENT_DS - .endm - -/* - * kernel_ok determines whether we should bypass addr/size checking. - * See the equivalent C-macro version below for clarity. - * On success, kernel_ok branches to a label indicated by parameter - * . This implies that the macro falls through to the next - * insruction on an error. - * - * Note that while this macro can be used independently, we designed - * in for optimal use in the access_ok macro below (i.e., we fall - * through on error). - * - * On Entry: - * anything (temp register) - * label to branch to on success; implies - * fall-through macro on error - * stack pointer - * On Exit: - * destroyed (actually, current->thread.current_ds) - */ - -#if ((KERNEL_DS != 0) || (USER_DS == 0)) -# error Assembly macro kernel_ok fails -#endif - .macro kernel_ok at, sp, success - get_fs \at, \sp - beqz \at, \success - .endm - /* * user_ok determines whether the access to user-space memory is allowed. * See the equivalent C-macro version below for clarity. @@ -147,7 +77,6 @@ * destroyed */ .macro access_ok aa, as, at, sp, error - kernel_ok \at, \sp, .Laccess_ok_\@ user_ok \aa, \as, \at, \error .Laccess_ok_\@: .endm diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h index 37d3e9887fe7..abad7c3df46f 100644 --- a/arch/xtensa/include/asm/processor.h +++ b/arch/xtensa/include/asm/processor.h @@ -152,18 +152,12 @@ */ #define SPILL_SLOT_CALL12(sp, reg) (*(((unsigned long *)(sp)) - 16 + (reg))) -typedef struct { - unsigned long seg; -} mm_segment_t; - struct thread_struct { /* kernel's return address and stack pointer for context switching */ unsigned long ra; /* kernel's a0: return address and window call size */ unsigned long sp; /* kernel's a1: stack pointer */ - mm_segment_t current_ds; /* see uaccess.h for example uses */ - /* struct xtensa_cpuinfo info; */ unsigned long bad_vaddr; /* last user fault */ @@ -186,7 +180,6 @@ struct thread_struct { { \ ra: 0, \ sp: sizeof(init_stack) + (long) &init_stack, \ - current_ds: {0}, \ /*info: {0}, */ \ bad_vaddr: 0, \ bad_uaddr: 0, \ diff --git a/arch/xtensa/include/asm/thread_info.h b/arch/xtensa/include/asm/thread_info.h index a312333a9add..f6fcbba1d02f 100644 --- a/arch/xtensa/include/asm/thread_info.h +++ b/arch/xtensa/include/asm/thread_info.h @@ -52,8 +52,6 @@ struct thread_info { __u32 cpu; /* current CPU */ __s32 preempt_count; /* 0 => preemptable,< 0 => BUG*/ - mm_segment_t addr_limit; /* thread address space */ - unsigned long cpenable; #if XCHAL_HAVE_EXCLUSIVE /* result of the most recent exclusive store */ @@ -81,7 +79,6 @@ struct thread_info { .flags = 0, \ .cpu = 0, \ .preempt_count = INIT_PREEMPT_COUNT, \ - .addr_limit = KERNEL_DS, \ } /* how to get the thread information struct from C */ diff --git a/arch/xtensa/include/asm/uaccess.h b/arch/xtensa/include/asm/uaccess.h index 75bd8fbf52ba..56aec6d504fe 100644 --- a/arch/xtensa/include/asm/uaccess.h +++ b/arch/xtensa/include/asm/uaccess.h @@ -19,31 +19,7 @@ #include #include #include - -/* - * The fs value determines whether argument validity checking should - * be performed or not. If get_fs() == USER_DS, checking is - * performed, with get_fs() == KERNEL_DS, checking is bypassed. - * - * For historical reasons (Data Segment Register?), these macros are - * grossly misnamed. - */ - -#define KERNEL_DS ((mm_segment_t) { 0 }) -#define USER_DS ((mm_segment_t) { 1 }) - -#define get_fs() (current->thread.current_ds) -#define set_fs(val) (current->thread.current_ds = (val)) - -#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) - -#define __kernel_ok (uaccess_kernel()) -#define __user_ok(addr, size) \ - (((size) <= TASK_SIZE)&&((addr) <= TASK_SIZE-(size))) -#define __access_ok(addr, size) (__kernel_ok || __user_ok((addr), (size))) -#define access_ok(addr, size) __access_ok((unsigned long)(addr), (size)) - -#define user_addr_max() (uaccess_kernel() ? ~0UL : TASK_SIZE) +#include /* * These are the main single-value transfer routines. They diff --git a/arch/xtensa/include/uapi/asm/shmbuf.h b/arch/xtensa/include/uapi/asm/shmbuf.h index 554a57a6a90f..bb8bdddae9b5 100644 --- a/arch/xtensa/include/uapi/asm/shmbuf.h +++ b/arch/xtensa/include/uapi/asm/shmbuf.h @@ -20,9 +20,12 @@ #ifndef _XTENSA_SHMBUF_H #define _XTENSA_SHMBUF_H +#include +#include + struct shmid64_ds { struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ + __kernel_size_t shm_segsz; /* size of segment (bytes) */ unsigned long shm_atime; /* last attach time */ unsigned long shm_atime_high; unsigned long shm_dtime; /* last detach time */ diff --git a/arch/xtensa/include/uapi/asm/signal.h b/arch/xtensa/include/uapi/asm/signal.h index 79ddabaa4e5d..b8c824dd4b74 100644 --- a/arch/xtensa/include/uapi/asm/signal.h +++ b/arch/xtensa/include/uapi/asm/signal.h @@ -103,7 +103,7 @@ struct sigaction { typedef struct sigaltstack { void *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; #endif /* __ASSEMBLY__ */ diff --git a/arch/xtensa/kernel/asm-offsets.c b/arch/xtensa/kernel/asm-offsets.c index dc5c83cad9be..f1fd1390d069 100644 --- a/arch/xtensa/kernel/asm-offsets.c +++ b/arch/xtensa/kernel/asm-offsets.c @@ -87,7 +87,6 @@ int main(void) OFFSET(TI_STSTUS, thread_info, status); OFFSET(TI_CPU, thread_info, cpu); OFFSET(TI_PRE_COUNT, thread_info, preempt_count); - OFFSET(TI_ADDR_LIMIT, thread_info, addr_limit); /* struct thread_info (offset from start_struct) */ DEFINE(THREAD_RA, offsetof (struct task_struct, thread.ra)); @@ -108,8 +107,6 @@ int main(void) #endif DEFINE(THREAD_XTREGS_USER, offsetof (struct thread_info, xtregs_user)); DEFINE(XTREGS_USER_SIZE, sizeof(xtregs_user_t)); - DEFINE(THREAD_CURRENT_DS, offsetof (struct task_struct, \ - thread.current_ds)); /* struct mm_struct */ DEFINE(MM_USERS, offsetof(struct mm_struct, mm_users)); diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index bccb275b65ba..60fbd42041dd 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c @@ -64,6 +64,11 @@ struct cs_timing_state { struct cs_timing cs[MAX_CS_COUNT]; }; +struct weim_priv { + void __iomem *base; + struct cs_timing_state timing_state; +}; + static const struct of_device_id weim_id_table[] = { /* i.MX1/21 */ { .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, }, @@ -128,21 +133,26 @@ err: } /* Parse and set the timing for this device. */ -static int weim_timing_setup(struct device *dev, - struct device_node *np, void __iomem *base, - const struct imx_weim_devtype *devtype, - struct cs_timing_state *ts) +static int weim_timing_setup(struct device *dev, struct device_node *np, + const struct imx_weim_devtype *devtype) { u32 cs_idx, value[MAX_CS_REGS_COUNT]; int i, ret; int reg_idx, num_regs; struct cs_timing *cst; + struct weim_priv *priv; + struct cs_timing_state *ts; + void __iomem *base; if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT)) return -EINVAL; if (WARN_ON(devtype->cs_count > MAX_CS_COUNT)) return -EINVAL; + priv = dev_get_drvdata(dev); + base = priv->base; + ts = &priv->timing_state; + ret = of_property_read_u32_array(np, "fsl,weim-cs-timing", value, devtype->cs_regs_count); if (ret) @@ -189,14 +199,15 @@ static int weim_timing_setup(struct device *dev, return 0; } -static int weim_parse_dt(struct platform_device *pdev, void __iomem *base) +static int weim_parse_dt(struct platform_device *pdev) { const struct of_device_id *of_id = of_match_device(weim_id_table, &pdev->dev); const struct imx_weim_devtype *devtype = of_id->data; struct device_node *child; int ret, have_child = 0; - struct cs_timing_state ts = {}; + struct weim_priv *priv; + void __iomem *base; u32 reg; if (devtype == &imx50_weim_devtype) { @@ -205,6 +216,9 @@ static int weim_parse_dt(struct platform_device *pdev, void __iomem *base) return ret; } + priv = dev_get_drvdata(&pdev->dev); + base = priv->base; + if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) { if (devtype->wcr_bcm) { reg = readl(base + devtype->wcr_offset); @@ -229,7 +243,7 @@ static int weim_parse_dt(struct platform_device *pdev, void __iomem *base) } for_each_available_child_of_node(pdev->dev.of_node, child) { - ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts); + ret = weim_timing_setup(&pdev->dev, child, devtype); if (ret) dev_warn(&pdev->dev, "%pOF set timing failed.\n", child); @@ -248,17 +262,25 @@ static int weim_parse_dt(struct platform_device *pdev, void __iomem *base) static int weim_probe(struct platform_device *pdev) { + struct weim_priv *priv; struct resource *res; struct clk *clk; void __iomem *base; int ret; + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + /* get the resource */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(base)) return PTR_ERR(base); + priv->base = base; + dev_set_drvdata(&pdev->dev, priv); + /* get the clock */ clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(clk)) @@ -269,7 +291,7 @@ static int weim_probe(struct platform_device *pdev) return ret; /* parse the device node */ - ret = weim_parse_dt(pdev, base); + ret = weim_parse_dt(pdev); if (ret) clk_disable_unprepare(clk); else @@ -278,6 +300,81 @@ static int weim_probe(struct platform_device *pdev) return ret; } +#if IS_ENABLED(CONFIG_OF_DYNAMIC) +static int of_weim_notify(struct notifier_block *nb, unsigned long action, + void *arg) +{ + const struct imx_weim_devtype *devtype; + struct of_reconfig_data *rd = arg; + const struct of_device_id *of_id; + struct platform_device *pdev; + int ret = NOTIFY_OK; + + switch (of_reconfig_get_state_change(action, rd)) { + case OF_RECONFIG_CHANGE_ADD: + of_id = of_match_node(weim_id_table, rd->dn->parent); + if (!of_id) + return NOTIFY_OK; /* not for us */ + + devtype = of_id->data; + + pdev = of_find_device_by_node(rd->dn->parent); + if (!pdev) { + pr_err("%s: could not find platform device for '%pOF'\n", + __func__, rd->dn->parent); + + return notifier_from_errno(-EINVAL); + } + + if (weim_timing_setup(&pdev->dev, rd->dn, devtype)) + dev_warn(&pdev->dev, + "Failed to setup timing for '%pOF'\n", rd->dn); + + if (!of_node_check_flag(rd->dn, OF_POPULATED)) { + if (!of_platform_device_create(rd->dn, NULL, &pdev->dev)) { + dev_err(&pdev->dev, + "Failed to create child device '%pOF'\n", + rd->dn); + ret = notifier_from_errno(-EINVAL); + } + } + + platform_device_put(pdev); + + break; + case OF_RECONFIG_CHANGE_REMOVE: + if (!of_node_check_flag(rd->dn, OF_POPULATED)) + return NOTIFY_OK; /* device already destroyed */ + + of_id = of_match_node(weim_id_table, rd->dn->parent); + if (!of_id) + return NOTIFY_OK; /* not for us */ + + pdev = of_find_device_by_node(rd->dn); + if (!pdev) { + dev_err(&pdev->dev, + "Could not find platform device for '%pOF'\n", + rd->dn); + + ret = notifier_from_errno(-EINVAL); + } else { + of_platform_device_destroy(&pdev->dev, NULL); + platform_device_put(pdev); + } + + break; + default: + break; + } + + return ret; +} + +struct notifier_block weim_of_notifier = { + .notifier_call = of_weim_notify, +}; +#endif /* IS_ENABLED(CONFIG_OF_DYNAMIC) */ + static struct platform_driver weim_driver = { .driver = { .name = "imx-weim", @@ -285,7 +382,27 @@ static struct platform_driver weim_driver = { }, .probe = weim_probe, }; -module_platform_driver(weim_driver); + +static int __init weim_init(void) +{ +#if IS_ENABLED(CONFIG_OF_DYNAMIC) + WARN_ON(of_reconfig_notifier_register(&weim_of_notifier)); +#endif /* IS_ENABLED(CONFIG_OF_DYNAMIC) */ + + return platform_driver_register(&weim_driver); +} +module_init(weim_init); + +static void __exit weim_exit(void) +{ +#if IS_ENABLED(CONFIG_OF_DYNAMIC) + of_reconfig_notifier_unregister(&weim_of_notifier); +#endif /* IS_ENABLED(CONFIG_OF_DYNAMIC) */ + + return platform_driver_unregister(&weim_driver); + +} +module_exit(weim_exit); MODULE_AUTHOR("Freescale Semiconductor Inc."); MODULE_DESCRIPTION("i.MX EIM Controller Driver"); diff --git a/drivers/char/hw_random/optee-rng.c b/drivers/char/hw_random/optee-rng.c index 135a82590923..a948c0727b2b 100644 --- a/drivers/char/hw_random/optee-rng.c +++ b/drivers/char/hw_random/optee-rng.c @@ -145,10 +145,10 @@ static int optee_rng_init(struct hwrng *rng) struct optee_rng_private *pvt_data = to_optee_rng_private(rng); struct tee_shm *entropy_shm_pool = NULL; - entropy_shm_pool = tee_shm_alloc(pvt_data->ctx, MAX_ENTROPY_REQ_SZ, - TEE_SHM_MAPPED | TEE_SHM_DMA_BUF); + entropy_shm_pool = tee_shm_alloc_kernel_buf(pvt_data->ctx, + MAX_ENTROPY_REQ_SZ); if (IS_ERR(entropy_shm_pool)) { - dev_err(pvt_data->dev, "tee_shm_alloc failed\n"); + dev_err(pvt_data->dev, "tee_shm_alloc_kernel_buf failed\n"); return PTR_ERR(entropy_shm_pool); } diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c index 1e357d364ca2..2c7a830ce308 100644 --- a/drivers/clk/clk-scmi.c +++ b/drivers/clk/clk-scmi.c @@ -2,7 +2,7 @@ /* * System Control and Power Interface (SCMI) Protocol based clock driver * - * Copyright (C) 2018-2021 ARM Ltd. + * Copyright (C) 2018-2022 ARM Ltd. */ #include @@ -88,21 +88,51 @@ static void scmi_clk_disable(struct clk_hw *hw) scmi_proto_clk_ops->disable(clk->ph, clk->id); } +static int scmi_clk_atomic_enable(struct clk_hw *hw) +{ + struct scmi_clk *clk = to_scmi_clk(hw); + + return scmi_proto_clk_ops->enable_atomic(clk->ph, clk->id); +} + +static void scmi_clk_atomic_disable(struct clk_hw *hw) +{ + struct scmi_clk *clk = to_scmi_clk(hw); + + scmi_proto_clk_ops->disable_atomic(clk->ph, clk->id); +} + +/* + * We can provide enable/disable atomic callbacks only if the underlying SCMI + * transport for an SCMI instance is configured to handle SCMI commands in an + * atomic manner. + * + * When no SCMI atomic transport support is available we instead provide only + * the prepare/unprepare API, as allowed by the clock framework when atomic + * calls are not available. + * + * Two distinct sets of clk_ops are provided since we could have multiple SCMI + * instances with different underlying transport quality, so they cannot be + * shared. + */ static const struct clk_ops scmi_clk_ops = { .recalc_rate = scmi_clk_recalc_rate, .round_rate = scmi_clk_round_rate, .set_rate = scmi_clk_set_rate, - /* - * We can't provide enable/disable callback as we can't perform the same - * in atomic context. Since the clock framework provides standard API - * clk_prepare_enable that helps cases using clk_enable in non-atomic - * context, it should be fine providing prepare/unprepare. - */ .prepare = scmi_clk_enable, .unprepare = scmi_clk_disable, }; -static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk) +static const struct clk_ops scmi_atomic_clk_ops = { + .recalc_rate = scmi_clk_recalc_rate, + .round_rate = scmi_clk_round_rate, + .set_rate = scmi_clk_set_rate, + .enable = scmi_clk_atomic_enable, + .disable = scmi_clk_atomic_disable, +}; + +static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk, + const struct clk_ops *scmi_ops) { int ret; unsigned long min_rate, max_rate; @@ -110,7 +140,7 @@ static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk) struct clk_init_data init = { .flags = CLK_GET_RATE_NOCACHE, .num_parents = 0, - .ops = &scmi_clk_ops, + .ops = scmi_ops, .name = sclk->info->name, }; @@ -139,6 +169,8 @@ static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk) static int scmi_clocks_probe(struct scmi_device *sdev) { int idx, count, err; + unsigned int atomic_threshold; + bool is_atomic; struct clk_hw **hws; struct clk_hw_onecell_data *clk_data; struct device *dev = &sdev->dev; @@ -168,8 +200,11 @@ static int scmi_clocks_probe(struct scmi_device *sdev) clk_data->num = count; hws = clk_data->hws; + is_atomic = handle->is_transport_atomic(handle, &atomic_threshold); + for (idx = 0; idx < count; idx++) { struct scmi_clk *sclk; + const struct clk_ops *scmi_ops; sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL); if (!sclk) @@ -184,13 +219,27 @@ static int scmi_clocks_probe(struct scmi_device *sdev) sclk->id = idx; sclk->ph = ph; - err = scmi_clk_ops_init(dev, sclk); + /* + * Note that when transport is atomic but SCMI protocol did not + * specify (or support) an enable_latency associated with a + * clock, we default to use atomic operations mode. + */ + if (is_atomic && + sclk->info->enable_latency <= atomic_threshold) + scmi_ops = &scmi_atomic_clk_ops; + else + scmi_ops = &scmi_clk_ops; + + err = scmi_clk_ops_init(dev, sclk, scmi_ops); if (err) { dev_err(dev, "failed to register clock %d\n", idx); devm_kfree(dev, sclk); hws[idx] = NULL; } else { - dev_dbg(dev, "Registered clock:%s\n", sclk->info->name); + dev_dbg(dev, "Registered clock:%s%s\n", + sclk->info->name, + scmi_ops == &scmi_atomic_clk_ops ? + " (atomic ops)" : ""); hws[idx] = &sclk->hw; } } diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index 0e18d6ff2916..8e8245ab3fd1 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -11,6 +11,7 @@ config COMMON_CLK_SAMSUNG select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410 select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS + select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD config S3C64XX_COMMON_CLK bool "Samsung S3C64xx clock controller support" if COMPILE_TEST @@ -124,3 +125,11 @@ config S3C2443_COMMON_CLK help Support for the clock controller present on the Samsung S3C2416/S3C2443 SoCs. Choose Y here only if you build for this SoC. + +config TESLA_FSD_COMMON_CLK + bool "Tesla FSD clock controller support" if COMPILE_TEST + depends on COMMON_CLK_SAMSUNG + depends on EXYNOS_ARM64_COMMON_CLK + help + Support for the clock controller present on the Tesla FSD SoC. + Choose Y here only if you build for this SoC. diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 0df74916a895..17e5d1cb9da2 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o +obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c new file mode 100644 index 000000000000..5d009c70e97d --- /dev/null +++ b/drivers/clk/samsung/clk-fsd.c @@ -0,0 +1,1803 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2022 Tesla, Inc. + * https://www.tesla.com + * + * Common Clock Framework support for FSD SoC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-exynos-arm64.h" + +/* Register Offset definitions for CMU_CMU (0x11c10000) */ +#define PLL_LOCKTIME_PLL_SHARED0 0x0 +#define PLL_LOCKTIME_PLL_SHARED1 0x4 +#define PLL_LOCKTIME_PLL_SHARED2 0x8 +#define PLL_LOCKTIME_PLL_SHARED3 0xc +#define PLL_CON0_PLL_SHARED0 0x100 +#define PLL_CON0_PLL_SHARED1 0x120 +#define PLL_CON0_PLL_SHARED2 0x140 +#define PLL_CON0_PLL_SHARED3 0x160 +#define MUX_CMU_CIS0_CLKMUX 0x1000 +#define MUX_CMU_CIS1_CLKMUX 0x1004 +#define MUX_CMU_CIS2_CLKMUX 0x1008 +#define MUX_CMU_CPUCL_SWITCHMUX 0x100c +#define MUX_CMU_FSYS1_ACLK_MUX 0x1014 +#define MUX_PLL_SHARED0_MUX 0x1020 +#define MUX_PLL_SHARED1_MUX 0x1024 +#define DIV_CMU_CIS0_CLK 0x1800 +#define DIV_CMU_CIS1_CLK 0x1804 +#define DIV_CMU_CIS2_CLK 0x1808 +#define DIV_CMU_CMU_ACLK 0x180c +#define DIV_CMU_CPUCL_SWITCH 0x1810 +#define DIV_CMU_FSYS0_SHARED0DIV4 0x181c +#define DIV_CMU_FSYS0_SHARED1DIV3 0x1820 +#define DIV_CMU_FSYS0_SHARED1DIV4 0x1824 +#define DIV_CMU_FSYS1_SHARED0DIV4 0x1828 +#define DIV_CMU_FSYS1_SHARED0DIV8 0x182c +#define DIV_CMU_IMEM_ACLK 0x1834 +#define DIV_CMU_IMEM_DMACLK 0x1838 +#define DIV_CMU_IMEM_TCUCLK 0x183c +#define DIV_CMU_PERIC_SHARED0DIV20 0x1844 +#define DIV_CMU_PERIC_SHARED0DIV3_TBUCLK 0x1848 +#define DIV_CMU_PERIC_SHARED1DIV36 0x184c +#define DIV_CMU_PERIC_SHARED1DIV4_DMACLK 0x1850 +#define DIV_PLL_SHARED0_DIV2 0x1858 +#define DIV_PLL_SHARED0_DIV3 0x185c +#define DIV_PLL_SHARED0_DIV4 0x1860 +#define DIV_PLL_SHARED0_DIV6 0x1864 +#define DIV_PLL_SHARED1_DIV3 0x1868 +#define DIV_PLL_SHARED1_DIV36 0x186c +#define DIV_PLL_SHARED1_DIV4 0x1870 +#define DIV_PLL_SHARED1_DIV9 0x1874 +#define GAT_CMU_CIS0_CLKGATE 0x2000 +#define GAT_CMU_CIS1_CLKGATE 0x2004 +#define GAT_CMU_CIS2_CLKGATE 0x2008 +#define GAT_CMU_CPUCL_SWITCH_GATE 0x200c +#define GAT_CMU_FSYS0_SHARED0DIV4_GATE 0x2018 +#define GAT_CMU_FSYS0_SHARED1DIV4_CLK 0x201c +#define GAT_CMU_FSYS0_SHARED1DIV4_GATE 0x2020 +#define GAT_CMU_FSYS1_SHARED0DIV4_GATE 0x2024 +#define GAT_CMU_FSYS1_SHARED1DIV4_GATE 0x2028 +#define GAT_CMU_IMEM_ACLK_GATE 0x2030 +#define GAT_CMU_IMEM_DMACLK_GATE 0x2034 +#define GAT_CMU_IMEM_TCUCLK_GATE 0x2038 +#define GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE 0x2040 +#define GAT_CMU_PERIC_SHARED0DIVE4_GATE 0x2044 +#define GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE 0x2048 +#define GAT_CMU_PERIC_SHARED1DIVE4_GATE 0x204c +#define GAT_CMU_CMU_CMU_IPCLKPORT_PCLK 0x2054 +#define GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK 0x2058 +#define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU 0x205c +#define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK 0x2060 + +static const unsigned long cmu_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_SHARED0, + PLL_LOCKTIME_PLL_SHARED1, + PLL_LOCKTIME_PLL_SHARED2, + PLL_LOCKTIME_PLL_SHARED3, + PLL_CON0_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, + PLL_CON0_PLL_SHARED2, + PLL_CON0_PLL_SHARED3, + MUX_CMU_CIS0_CLKMUX, + MUX_CMU_CIS1_CLKMUX, + MUX_CMU_CIS2_CLKMUX, + MUX_CMU_CPUCL_SWITCHMUX, + MUX_CMU_FSYS1_ACLK_MUX, + MUX_PLL_SHARED0_MUX, + MUX_PLL_SHARED1_MUX, + DIV_CMU_CIS0_CLK, + DIV_CMU_CIS1_CLK, + DIV_CMU_CIS2_CLK, + DIV_CMU_CMU_ACLK, + DIV_CMU_CPUCL_SWITCH, + DIV_CMU_FSYS0_SHARED0DIV4, + DIV_CMU_FSYS0_SHARED1DIV3, + DIV_CMU_FSYS0_SHARED1DIV4, + DIV_CMU_FSYS1_SHARED0DIV4, + DIV_CMU_FSYS1_SHARED0DIV8, + DIV_CMU_IMEM_ACLK, + DIV_CMU_IMEM_DMACLK, + DIV_CMU_IMEM_TCUCLK, + DIV_CMU_PERIC_SHARED0DIV20, + DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, + DIV_CMU_PERIC_SHARED1DIV36, + DIV_CMU_PERIC_SHARED1DIV4_DMACLK, + DIV_PLL_SHARED0_DIV2, + DIV_PLL_SHARED0_DIV3, + DIV_PLL_SHARED0_DIV4, + DIV_PLL_SHARED0_DIV6, + DIV_PLL_SHARED1_DIV3, + DIV_PLL_SHARED1_DIV36, + DIV_PLL_SHARED1_DIV4, + DIV_PLL_SHARED1_DIV9, + GAT_CMU_CIS0_CLKGATE, + GAT_CMU_CIS1_CLKGATE, + GAT_CMU_CIS2_CLKGATE, + GAT_CMU_CPUCL_SWITCH_GATE, + GAT_CMU_FSYS0_SHARED0DIV4_GATE, + GAT_CMU_FSYS0_SHARED1DIV4_CLK, + GAT_CMU_FSYS0_SHARED1DIV4_GATE, + GAT_CMU_FSYS1_SHARED0DIV4_GATE, + GAT_CMU_FSYS1_SHARED1DIV4_GATE, + GAT_CMU_IMEM_ACLK_GATE, + GAT_CMU_IMEM_DMACLK_GATE, + GAT_CMU_IMEM_TCUCLK_GATE, + GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, + GAT_CMU_PERIC_SHARED0DIVE4_GATE, + GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, + GAT_CMU_PERIC_SHARED1DIVE4_GATE, + GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, + GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, + GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, + GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, +}; + +static const struct samsung_pll_rate_table pll_shared0_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 2000000000U, 250, 3, 0), +}; + +static const struct samsung_pll_rate_table pll_shared1_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0), +}; + +static const struct samsung_pll_rate_table pll_shared2_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0), +}; + +static const struct samsung_pll_rate_table pll_shared3_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 1800000000U, 150, 2, 0), +}; + +static const struct samsung_pll_clock cmu_pll_clks[] __initconst = { + PLL(pll_142xx, 0, "fout_pll_shared0", "fin_pll", PLL_LOCKTIME_PLL_SHARED0, + PLL_CON0_PLL_SHARED0, pll_shared0_rate_table), + PLL(pll_142xx, 0, "fout_pll_shared1", "fin_pll", PLL_LOCKTIME_PLL_SHARED1, + PLL_CON0_PLL_SHARED1, pll_shared1_rate_table), + PLL(pll_142xx, 0, "fout_pll_shared2", "fin_pll", PLL_LOCKTIME_PLL_SHARED2, + PLL_CON0_PLL_SHARED2, pll_shared2_rate_table), + PLL(pll_142xx, 0, "fout_pll_shared3", "fin_pll", PLL_LOCKTIME_PLL_SHARED3, + PLL_CON0_PLL_SHARED3, pll_shared3_rate_table), +}; + +/* List of parent clocks for Muxes in CMU_CMU */ +PNAME(mout_cmu_shared0_pll_p) = { "fin_pll", "fout_pll_shared0" }; +PNAME(mout_cmu_shared1_pll_p) = { "fin_pll", "fout_pll_shared1" }; +PNAME(mout_cmu_shared2_pll_p) = { "fin_pll", "fout_pll_shared2" }; +PNAME(mout_cmu_shared3_pll_p) = { "fin_pll", "fout_pll_shared3" }; +PNAME(mout_cmu_cis0_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; +PNAME(mout_cmu_cis1_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; +PNAME(mout_cmu_cis2_clkmux_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; +PNAME(mout_cmu_cpucl_switchmux_p) = { "mout_cmu_pll_shared2", "mout_cmu_pll_shared0_mux" }; +PNAME(mout_cmu_fsys1_aclk_mux_p) = { "dout_cmu_pll_shared0_div4", "fin_pll" }; +PNAME(mout_cmu_pll_shared0_mux_p) = { "fin_pll", "mout_cmu_pll_shared0" }; +PNAME(mout_cmu_pll_shared1_mux_p) = { "fin_pll", "mout_cmu_pll_shared1" }; + +static const struct samsung_mux_clock cmu_mux_clks[] __initconst = { + MUX(0, "mout_cmu_pll_shared0", mout_cmu_shared0_pll_p, PLL_CON0_PLL_SHARED0, 4, 1), + MUX(0, "mout_cmu_pll_shared1", mout_cmu_shared1_pll_p, PLL_CON0_PLL_SHARED1, 4, 1), + MUX(0, "mout_cmu_pll_shared2", mout_cmu_shared2_pll_p, PLL_CON0_PLL_SHARED2, 4, 1), + MUX(0, "mout_cmu_pll_shared3", mout_cmu_shared3_pll_p, PLL_CON0_PLL_SHARED3, 4, 1), + MUX(0, "mout_cmu_cis0_clkmux", mout_cmu_cis0_clkmux_p, MUX_CMU_CIS0_CLKMUX, 0, 1), + MUX(0, "mout_cmu_cis1_clkmux", mout_cmu_cis1_clkmux_p, MUX_CMU_CIS1_CLKMUX, 0, 1), + MUX(0, "mout_cmu_cis2_clkmux", mout_cmu_cis2_clkmux_p, MUX_CMU_CIS2_CLKMUX, 0, 1), + MUX(0, "mout_cmu_cpucl_switchmux", mout_cmu_cpucl_switchmux_p, + MUX_CMU_CPUCL_SWITCHMUX, 0, 1), + MUX(0, "mout_cmu_fsys1_aclk_mux", mout_cmu_fsys1_aclk_mux_p, MUX_CMU_FSYS1_ACLK_MUX, 0, 1), + MUX(0, "mout_cmu_pll_shared0_mux", mout_cmu_pll_shared0_mux_p, MUX_PLL_SHARED0_MUX, 0, 1), + MUX(0, "mout_cmu_pll_shared1_mux", mout_cmu_pll_shared1_mux_p, MUX_PLL_SHARED1_MUX, 0, 1), +}; + +static const struct samsung_div_clock cmu_div_clks[] __initconst = { + DIV(0, "dout_cmu_cis0_clk", "cmu_cis0_clkgate", DIV_CMU_CIS0_CLK, 0, 4), + DIV(0, "dout_cmu_cis1_clk", "cmu_cis1_clkgate", DIV_CMU_CIS1_CLK, 0, 4), + DIV(0, "dout_cmu_cis2_clk", "cmu_cis2_clkgate", DIV_CMU_CIS2_CLK, 0, 4), + DIV(0, "dout_cmu_cmu_aclk", "dout_cmu_pll_shared1_div9", DIV_CMU_CMU_ACLK, 0, 4), + DIV(0, "dout_cmu_cpucl_switch", "cmu_cpucl_switch_gate", DIV_CMU_CPUCL_SWITCH, 0, 4), + DIV(DOUT_CMU_FSYS0_SHARED0DIV4, "dout_cmu_fsys0_shared0div4", "cmu_fsys0_shared0div4_gate", + DIV_CMU_FSYS0_SHARED0DIV4, 0, 4), + DIV(0, "dout_cmu_fsys0_shared1div3", "cmu_fsys0_shared1div4_clk", + DIV_CMU_FSYS0_SHARED1DIV3, 0, 4), + DIV(DOUT_CMU_FSYS0_SHARED1DIV4, "dout_cmu_fsys0_shared1div4", "cmu_fsys0_shared1div4_gate", + DIV_CMU_FSYS0_SHARED1DIV4, 0, 4), + DIV(DOUT_CMU_FSYS1_SHARED0DIV4, "dout_cmu_fsys1_shared0div4", "cmu_fsys1_shared0div4_gate", + DIV_CMU_FSYS1_SHARED0DIV4, 0, 4), + DIV(DOUT_CMU_FSYS1_SHARED0DIV8, "dout_cmu_fsys1_shared0div8", "cmu_fsys1_shared1div4_gate", + DIV_CMU_FSYS1_SHARED0DIV8, 0, 4), + DIV(DOUT_CMU_IMEM_ACLK, "dout_cmu_imem_aclk", "cmu_imem_aclk_gate", + DIV_CMU_IMEM_ACLK, 0, 4), + DIV(DOUT_CMU_IMEM_DMACLK, "dout_cmu_imem_dmaclk", "cmu_imem_dmaclk_gate", + DIV_CMU_IMEM_DMACLK, 0, 4), + DIV(DOUT_CMU_IMEM_TCUCLK, "dout_cmu_imem_tcuclk", "cmu_imem_tcuclk_gate", + DIV_CMU_IMEM_TCUCLK, 0, 4), + DIV(DOUT_CMU_PERIC_SHARED0DIV20, "dout_cmu_peric_shared0div20", + "cmu_peric_shared0dive4_gate", DIV_CMU_PERIC_SHARED0DIV20, 0, 4), + DIV(DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK, "dout_cmu_peric_shared0div3_tbuclk", + "cmu_peric_shared0dive3_tbuclk_gate", DIV_CMU_PERIC_SHARED0DIV3_TBUCLK, 0, 4), + DIV(DOUT_CMU_PERIC_SHARED1DIV36, "dout_cmu_peric_shared1div36", + "cmu_peric_shared1dive4_gate", DIV_CMU_PERIC_SHARED1DIV36, 0, 4), + DIV(DOUT_CMU_PERIC_SHARED1DIV4_DMACLK, "dout_cmu_peric_shared1div4_dmaclk", + "cmu_peric_shared1div4_dmaclk_gate", DIV_CMU_PERIC_SHARED1DIV4_DMACLK, 0, 4), + DIV(0, "dout_cmu_pll_shared0_div2", "mout_cmu_pll_shared0_mux", + DIV_PLL_SHARED0_DIV2, 0, 4), + DIV(0, "dout_cmu_pll_shared0_div3", "mout_cmu_pll_shared0_mux", + DIV_PLL_SHARED0_DIV3, 0, 4), + DIV(DOUT_CMU_PLL_SHARED0_DIV4, "dout_cmu_pll_shared0_div4", "dout_cmu_pll_shared0_div2", + DIV_PLL_SHARED0_DIV4, 0, 4), + DIV(DOUT_CMU_PLL_SHARED0_DIV6, "dout_cmu_pll_shared0_div6", "dout_cmu_pll_shared0_div3", + DIV_PLL_SHARED0_DIV6, 0, 4), + DIV(0, "dout_cmu_pll_shared1_div3", "mout_cmu_pll_shared1_mux", + DIV_PLL_SHARED1_DIV3, 0, 4), + DIV(0, "dout_cmu_pll_shared1_div36", "dout_cmu_pll_shared1_div9", + DIV_PLL_SHARED1_DIV36, 0, 4), + DIV(0, "dout_cmu_pll_shared1_div4", "mout_cmu_pll_shared1_mux", + DIV_PLL_SHARED1_DIV4, 0, 4), + DIV(0, "dout_cmu_pll_shared1_div9", "dout_cmu_pll_shared1_div3", + DIV_PLL_SHARED1_DIV9, 0, 4), +}; + +static const struct samsung_gate_clock cmu_gate_clks[] __initconst = { + GATE(0, "cmu_cis0_clkgate", "mout_cmu_cis0_clkmux", GAT_CMU_CIS0_CLKGATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_cis1_clkgate", "mout_cmu_cis1_clkmux", GAT_CMU_CIS1_CLKGATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_cis2_clkgate", "mout_cmu_cis2_clkmux", GAT_CMU_CIS2_CLKGATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(CMU_CPUCL_SWITCH_GATE, "cmu_cpucl_switch_gate", "mout_cmu_cpucl_switchmux", + GAT_CMU_CPUCL_SWITCH_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(GAT_CMU_FSYS0_SHARED0DIV4, "cmu_fsys0_shared0div4_gate", "dout_cmu_pll_shared0_div4", + GAT_CMU_FSYS0_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_fsys0_shared1div4_clk", "dout_cmu_pll_shared1_div3", + GAT_CMU_FSYS0_SHARED1DIV4_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_fsys0_shared1div4_gate", "dout_cmu_pll_shared1_div4", + GAT_CMU_FSYS0_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_fsys1_shared0div4_gate", "mout_cmu_fsys1_aclk_mux", + GAT_CMU_FSYS1_SHARED0DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_fsys1_shared1div4_gate", "dout_cmu_fsys1_shared0div4", + GAT_CMU_FSYS1_SHARED1DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_imem_aclk_gate", "dout_cmu_pll_shared1_div9", GAT_CMU_IMEM_ACLK_GATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_imem_dmaclk_gate", "mout_cmu_pll_shared1_mux", GAT_CMU_IMEM_DMACLK_GATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_imem_tcuclk_gate", "dout_cmu_pll_shared0_div3", GAT_CMU_IMEM_TCUCLK_GATE, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_peric_shared0dive3_tbuclk_gate", "dout_cmu_pll_shared0_div3", + GAT_CMU_PERIC_SHARED0DIVE3_TBUCLK_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_peric_shared0dive4_gate", "dout_cmu_pll_shared0_div4", + GAT_CMU_PERIC_SHARED0DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_peric_shared1div4_dmaclk_gate", "dout_cmu_pll_shared1_div4", + GAT_CMU_PERIC_SHARED1DIV4_DMACLK_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_peric_shared1dive4_gate", "dout_cmu_pll_shared1_div36", + GAT_CMU_PERIC_SHARED1DIVE4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_uid_cmu_cmu_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk", + GAT_CMU_CMU_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_uid_axi2apb_cmu_ipclkport_aclk", "dout_cmu_cmu_aclk", + GAT_CMU_AXI2APB_CMU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_uid_ns_brdg_cmu_ipclkport_clk__psoc_cmu__clk_cmu", "dout_cmu_cmu_aclk", + GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cmu_uid_sysreg_cmu_ipclkport_pclk", "dout_cmu_cmu_aclk", + GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info cmu_cmu_info __initconst = { + .pll_clks = cmu_pll_clks, + .nr_pll_clks = ARRAY_SIZE(cmu_pll_clks), + .mux_clks = cmu_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cmu_mux_clks), + .div_clks = cmu_div_clks, + .nr_div_clks = ARRAY_SIZE(cmu_div_clks), + .gate_clks = cmu_gate_clks, + .nr_gate_clks = ARRAY_SIZE(cmu_gate_clks), + .nr_clk_ids = CMU_NR_CLK, + .clk_regs = cmu_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cmu_clk_regs), +}; + +static void __init fsd_clk_cmu_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_cmu_info); +} + +CLK_OF_DECLARE(fsd_clk_cmu, "tesla,fsd-clock-cmu", fsd_clk_cmu_init); + +/* Register Offset definitions for CMU_PERIC (0x14010000) */ +#define PLL_CON0_PERIC_DMACLK_MUX 0x100 +#define PLL_CON0_PERIC_EQOS_BUSCLK_MUX 0x120 +#define PLL_CON0_PERIC_PCLK_MUX 0x140 +#define PLL_CON0_PERIC_TBUCLK_MUX 0x160 +#define PLL_CON0_SPI_CLK 0x180 +#define PLL_CON0_SPI_PCLK 0x1a0 +#define PLL_CON0_UART_CLK 0x1c0 +#define PLL_CON0_UART_PCLK 0x1e0 +#define MUX_PERIC_EQOS_PHYRXCLK 0x1000 +#define DIV_EQOS_BUSCLK 0x1800 +#define DIV_PERIC_MCAN_CLK 0x1804 +#define DIV_RGMII_CLK 0x1808 +#define DIV_RII_CLK 0x180c +#define DIV_RMII_CLK 0x1810 +#define DIV_SPI_CLK 0x1814 +#define DIV_UART_CLK 0x1818 +#define GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 0x2000 +#define GAT_GPIO_PERIC_IPCLKPORT_OSCCLK 0x2004 +#define GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK 0x2008 +#define GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK 0x200c +#define GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK 0x2010 +#define GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK 0x2014 +#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM 0x2018 +#define GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS 0x201c +#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM 0x2020 +#define GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS 0x2024 +#define GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK 0x2028 +#define GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK 0x202c +#define GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK 0x2030 +#define GAT_BUS_D_PERIC_IPCLKPORT_DMACLK 0x2034 +#define GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK 0x2038 +#define GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK 0x203c +#define GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK 0x2040 +#define GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK 0x2044 +#define GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK 0x2048 +#define GAT_EQOS_TOP_IPCLKPORT_ACLK_I 0x204c +#define GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I 0x2050 +#define GAT_EQOS_TOP_IPCLKPORT_HCLK_I 0x2054 +#define GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 0x2058 +#define GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I 0x205c +#define GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I 0x2060 +#define GAT_GPIO_PERIC_IPCLKPORT_PCLK 0x2064 +#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D 0x2068 +#define GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P 0x206c +#define GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0 0x2070 +#define GAT_PERIC_DMA0_IPCLKPORT_ACLK 0x2074 +#define GAT_PERIC_DMA1_IPCLKPORT_ACLK 0x2078 +#define GAT_PERIC_I2C0_IPCLKPORT_I_PCLK 0x207c +#define GAT_PERIC_I2C1_IPCLKPORT_I_PCLK 0x2080 +#define GAT_PERIC_I2C2_IPCLKPORT_I_PCLK 0x2084 +#define GAT_PERIC_I2C3_IPCLKPORT_I_PCLK 0x2088 +#define GAT_PERIC_I2C4_IPCLKPORT_I_PCLK 0x208c +#define GAT_PERIC_I2C5_IPCLKPORT_I_PCLK 0x2090 +#define GAT_PERIC_I2C6_IPCLKPORT_I_PCLK 0x2094 +#define GAT_PERIC_I2C7_IPCLKPORT_I_PCLK 0x2098 +#define GAT_PERIC_MCAN0_IPCLKPORT_CCLK 0x209c +#define GAT_PERIC_MCAN0_IPCLKPORT_PCLK 0x20a0 +#define GAT_PERIC_MCAN1_IPCLKPORT_CCLK 0x20a4 +#define GAT_PERIC_MCAN1_IPCLKPORT_PCLK 0x20a8 +#define GAT_PERIC_MCAN2_IPCLKPORT_CCLK 0x20ac +#define GAT_PERIC_MCAN2_IPCLKPORT_PCLK 0x20b0 +#define GAT_PERIC_MCAN3_IPCLKPORT_CCLK 0x20b4 +#define GAT_PERIC_MCAN3_IPCLKPORT_PCLK 0x20b8 +#define GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0 0x20bc +#define GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0 0x20c0 +#define GAT_PERIC_SMMU_IPCLKPORT_CCLK 0x20c4 +#define GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK 0x20c8 +#define GAT_PERIC_SPI0_IPCLKPORT_I_PCLK 0x20cc +#define GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI 0x20d0 +#define GAT_PERIC_SPI1_IPCLKPORT_I_PCLK 0x20d4 +#define GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI 0x20d8 +#define GAT_PERIC_SPI2_IPCLKPORT_I_PCLK 0x20dc +#define GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI 0x20e0 +#define GAT_PERIC_TDM0_IPCLKPORT_HCLK_M 0x20e4 +#define GAT_PERIC_TDM0_IPCLKPORT_PCLK 0x20e8 +#define GAT_PERIC_TDM1_IPCLKPORT_HCLK_M 0x20ec +#define GAT_PERIC_TDM1_IPCLKPORT_PCLK 0x20f0 +#define GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART 0x20f4 +#define GAT_PERIC_UART0_IPCLKPORT_PCLK 0x20f8 +#define GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART 0x20fc +#define GAT_PERIC_UART1_IPCLKPORT_PCLK 0x2100 +#define GAT_SYSREG_PERI_IPCLKPORT_PCLK 0x2104 + +static const unsigned long peric_clk_regs[] __initconst = { + PLL_CON0_PERIC_DMACLK_MUX, + PLL_CON0_PERIC_EQOS_BUSCLK_MUX, + PLL_CON0_PERIC_PCLK_MUX, + PLL_CON0_PERIC_TBUCLK_MUX, + PLL_CON0_SPI_CLK, + PLL_CON0_SPI_PCLK, + PLL_CON0_UART_CLK, + PLL_CON0_UART_PCLK, + MUX_PERIC_EQOS_PHYRXCLK, + DIV_EQOS_BUSCLK, + DIV_PERIC_MCAN_CLK, + DIV_RGMII_CLK, + DIV_RII_CLK, + DIV_RMII_CLK, + DIV_SPI_CLK, + DIV_UART_CLK, + GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, + GAT_GPIO_PERIC_IPCLKPORT_OSCCLK, + GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, + GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, + GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, + GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, + GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, + GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, + GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, + GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, + GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, + GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, + GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, + GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, + GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, + GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, + GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, + GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, + GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, + GAT_EQOS_TOP_IPCLKPORT_ACLK_I, + GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, + GAT_EQOS_TOP_IPCLKPORT_HCLK_I, + GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, + GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, + GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, + GAT_GPIO_PERIC_IPCLKPORT_PCLK, + GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, + GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, + GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, + GAT_PERIC_DMA0_IPCLKPORT_ACLK, + GAT_PERIC_DMA1_IPCLKPORT_ACLK, + GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, + GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, + GAT_PERIC_MCAN0_IPCLKPORT_CCLK, + GAT_PERIC_MCAN0_IPCLKPORT_PCLK, + GAT_PERIC_MCAN1_IPCLKPORT_CCLK, + GAT_PERIC_MCAN1_IPCLKPORT_PCLK, + GAT_PERIC_MCAN2_IPCLKPORT_CCLK, + GAT_PERIC_MCAN2_IPCLKPORT_PCLK, + GAT_PERIC_MCAN3_IPCLKPORT_CCLK, + GAT_PERIC_MCAN3_IPCLKPORT_PCLK, + GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, + GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, + GAT_PERIC_SMMU_IPCLKPORT_CCLK, + GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, + GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, + GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, + GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, + GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, + GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, + GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, + GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, + GAT_PERIC_TDM0_IPCLKPORT_PCLK, + GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, + GAT_PERIC_TDM1_IPCLKPORT_PCLK, + GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, + GAT_PERIC_UART0_IPCLKPORT_PCLK, + GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, + GAT_PERIC_UART1_IPCLKPORT_PCLK, + GAT_SYSREG_PERI_IPCLKPORT_PCLK, +}; + +static const struct samsung_fixed_rate_clock peric_fixed_clks[] __initconst = { + FRATE(PERIC_EQOS_PHYRXCLK, "eqos_phyrxclk", NULL, 0, 125000000), +}; + +/* List of parent clocks for Muxes in CMU_PERIC */ +PNAME(mout_peric_dmaclk_p) = { "fin_pll", "cmu_peric_shared1div4_dmaclk_gate" }; +PNAME(mout_peric_eqos_busclk_p) = { "fin_pll", "dout_cmu_pll_shared0_div4" }; +PNAME(mout_peric_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; +PNAME(mout_peric_tbuclk_p) = { "fin_pll", "dout_cmu_peric_shared0div3_tbuclk" }; +PNAME(mout_peric_spi_clk_p) = { "fin_pll", "dout_cmu_peric_shared0div20" }; +PNAME(mout_peric_spi_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; +PNAME(mout_peric_uart_clk_p) = { "fin_pll", "dout_cmu_peric_shared1div4_dmaclk" }; +PNAME(mout_peric_uart_pclk_p) = { "fin_pll", "dout_cmu_peric_shared1div36" }; +PNAME(mout_peric_eqos_phyrxclk_p) = { "dout_peric_rgmii_clk", "eqos_phyrxclk" }; + +static const struct samsung_mux_clock peric_mux_clks[] __initconst = { + MUX(0, "mout_peric_dmaclk", mout_peric_dmaclk_p, PLL_CON0_PERIC_DMACLK_MUX, 4, 1), + MUX(0, "mout_peric_eqos_busclk", mout_peric_eqos_busclk_p, + PLL_CON0_PERIC_EQOS_BUSCLK_MUX, 4, 1), + MUX(0, "mout_peric_pclk", mout_peric_pclk_p, PLL_CON0_PERIC_PCLK_MUX, 4, 1), + MUX(0, "mout_peric_tbuclk", mout_peric_tbuclk_p, PLL_CON0_PERIC_TBUCLK_MUX, 4, 1), + MUX(0, "mout_peric_spi_clk", mout_peric_spi_clk_p, PLL_CON0_SPI_CLK, 4, 1), + MUX(0, "mout_peric_spi_pclk", mout_peric_spi_pclk_p, PLL_CON0_SPI_PCLK, 4, 1), + MUX(0, "mout_peric_uart_clk", mout_peric_uart_clk_p, PLL_CON0_UART_CLK, 4, 1), + MUX(0, "mout_peric_uart_pclk", mout_peric_uart_pclk_p, PLL_CON0_UART_PCLK, 4, 1), + MUX(PERIC_EQOS_PHYRXCLK_MUX, "mout_peric_eqos_phyrxclk", mout_peric_eqos_phyrxclk_p, + MUX_PERIC_EQOS_PHYRXCLK, 0, 1), +}; + +static const struct samsung_div_clock peric_div_clks[] __initconst = { + DIV(0, "dout_peric_eqos_busclk", "mout_peric_eqos_busclk", DIV_EQOS_BUSCLK, 0, 4), + DIV(0, "dout_peric_mcan_clk", "mout_peric_dmaclk", DIV_PERIC_MCAN_CLK, 0, 4), + DIV(PERIC_DOUT_RGMII_CLK, "dout_peric_rgmii_clk", "mout_peric_eqos_busclk", + DIV_RGMII_CLK, 0, 4), + DIV(0, "dout_peric_rii_clk", "dout_peric_rmii_clk", DIV_RII_CLK, 0, 4), + DIV(0, "dout_peric_rmii_clk", "dout_peric_rgmii_clk", DIV_RMII_CLK, 0, 4), + DIV(0, "dout_peric_spi_clk", "mout_peric_spi_clk", DIV_SPI_CLK, 0, 6), + DIV(0, "dout_peric_uart_clk", "mout_peric_uart_clk", DIV_UART_CLK, 0, 6), +}; + +static const struct samsung_gate_clock peric_gate_clks[] __initconst = { + GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, "peric_eqos_top_ipclkport_clk_ptp_ref_i", + "fin_pll", GAT_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_gpio_peric_ipclkport_oscclk", "fin_pll", GAT_GPIO_PERIC_IPCLKPORT_OSCCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_ADCIF, "peric_adc0_ipclkport_i_oscclk", "fin_pll", + GAT_PERIC_ADC0_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_cmu_peric_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_CMU_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_pwm0_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM0_IPCLKPORT_I_OSCCLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_pwm1_ipclkport_i_oscclk", "fin_pll", GAT_PERIC_PWM1_IPCLKPORT_I_OSCCLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_async_apb_dma0_ipclkport_pclkm", "mout_peric_dmaclk", + GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_async_apb_dma0_ipclkport_pclks", "mout_peric_pclk", + GAT_ASYNC_APB_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_async_apb_dma1_ipclkport_pclkm", "mout_peric_dmaclk", + GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_async_apb_dma1_ipclkport_pclks", "mout_peric_pclk", + GAT_ASYNC_APB_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_axi2apb_peric0_ipclkport_aclk", "mout_peric_pclk", + GAT_AXI2APB_PERIC0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_axi2apb_peric1_ipclkport_aclk", "mout_peric_pclk", + GAT_AXI2APB_PERIC1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_axi2apb_peric2_ipclkport_aclk", "mout_peric_pclk", + GAT_AXI2APB_PERIC2_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_bus_d_peric_ipclkport_dmaclk", "mout_peric_dmaclk", + GAT_BUS_D_PERIC_IPCLKPORT_DMACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_d_peric_ipclkport_eqosclk", + "dout_peric_eqos_busclk", GAT_BUS_D_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_bus_d_peric_ipclkport_mainclk", "mout_peric_tbuclk", + GAT_BUS_D_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK, "peric_bus_p_peric_ipclkport_eqosclk", + "dout_peric_eqos_busclk", GAT_BUS_P_PERIC_IPCLKPORT_EQOSCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_bus_p_peric_ipclkport_mainclk", "mout_peric_pclk", + GAT_BUS_P_PERIC_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_bus_p_peric_ipclkport_smmuclk", "mout_peric_tbuclk", + GAT_BUS_P_PERIC_IPCLKPORT_SMMUCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_EQOS_TOP_IPCLKPORT_ACLK_I, "peric_eqos_top_ipclkport_aclk_i", + "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_ACLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I, "peric_eqos_top_ipclkport_clk_rx_i", + "mout_peric_eqos_phyrxclk", GAT_EQOS_TOP_IPCLKPORT_CLK_RX_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_EQOS_TOP_IPCLKPORT_HCLK_I, "peric_eqos_top_ipclkport_hclk_i", + "dout_peric_eqos_busclk", GAT_EQOS_TOP_IPCLKPORT_HCLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, "peric_eqos_top_ipclkport_rgmii_clk_i", + "dout_peric_rgmii_clk", GAT_EQOS_TOP_IPCLKPORT_RGMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_eqos_top_ipclkport_rii_clk_i", "dout_peric_rii_clk", + GAT_EQOS_TOP_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_eqos_top_ipclkport_rmii_clk_i", "dout_peric_rmii_clk", + GAT_EQOS_TOP_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_gpio_peric_ipclkport_pclk", "mout_peric_pclk", + GAT_GPIO_PERIC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_d", "mout_peric_tbuclk", + GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_D, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_ns_brdg_peric_ipclkport_clk__psoc_peric__clk_peric_p", "mout_peric_pclk", + GAT_NS_BRDG_PERIC_IPCLKPORT_CLK__PSOC_PERIC__CLK_PERIC_P, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_adc0_ipclkport_pclk_s0", "mout_peric_pclk", + GAT_PERIC_ADC0_IPCLKPORT_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_DMA0_IPCLKPORT_ACLK, "peric_dma0_ipclkport_aclk", "mout_peric_dmaclk", + GAT_PERIC_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_DMA1_IPCLKPORT_ACLK, "peric_dma1_ipclkport_aclk", "mout_peric_dmaclk", + GAT_PERIC_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C0, "peric_i2c0_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C1, "peric_i2c1_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C2, "peric_i2c2_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C3, "peric_i2c3_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C4, "peric_i2c4_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C4_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C5, "peric_i2c5_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C5_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C6, "peric_i2c6_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C6_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_HSI2C7, "peric_i2c7_ipclkport_i_pclk", "mout_peric_pclk", + GAT_PERIC_I2C7_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN0_IPCLKPORT_CCLK, "peric_mcan0_ipclkport_cclk", "dout_peric_mcan_clk", + GAT_PERIC_MCAN0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN0_IPCLKPORT_PCLK, "peric_mcan0_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_MCAN0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN1_IPCLKPORT_CCLK, "peric_mcan1_ipclkport_cclk", "dout_peric_mcan_clk", + GAT_PERIC_MCAN1_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN1_IPCLKPORT_PCLK, "peric_mcan1_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_MCAN1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN2_IPCLKPORT_CCLK, "peric_mcan2_ipclkport_cclk", "dout_peric_mcan_clk", + GAT_PERIC_MCAN2_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN2_IPCLKPORT_PCLK, "peric_mcan2_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_MCAN2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN3_IPCLKPORT_CCLK, "peric_mcan3_ipclkport_cclk", "dout_peric_mcan_clk", + GAT_PERIC_MCAN3_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_MCAN3_IPCLKPORT_PCLK, "peric_mcan3_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_MCAN3_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PWM0_IPCLKPORT_I_PCLK_S0, "peric_pwm0_ipclkport_i_pclk_s0", "mout_peric_pclk", + GAT_PERIC_PWM0_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PWM1_IPCLKPORT_I_PCLK_S0, "peric_pwm1_ipclkport_i_pclk_s0", "mout_peric_pclk", + GAT_PERIC_PWM1_IPCLKPORT_I_PCLK_S0, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_smmu_ipclkport_cclk", "mout_peric_tbuclk", + GAT_PERIC_SMMU_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_smmu_ipclkport_peric_bclk", "mout_peric_tbuclk", + GAT_PERIC_SMMU_IPCLKPORT_PERIC_BCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_SPI0, "peric_spi0_ipclkport_i_pclk", "mout_peric_spi_pclk", + GAT_PERIC_SPI0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_SCLK_SPI0, "peric_spi0_ipclkport_i_sclk_spi", "dout_peric_spi_clk", + GAT_PERIC_SPI0_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_SPI1, "peric_spi1_ipclkport_i_pclk", "mout_peric_spi_pclk", + GAT_PERIC_SPI1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_SCLK_SPI1, "peric_spi1_ipclkport_i_sclk_spi", "dout_peric_spi_clk", + GAT_PERIC_SPI1_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_SPI2, "peric_spi2_ipclkport_i_pclk", "mout_peric_spi_pclk", + GAT_PERIC_SPI2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_SCLK_SPI2, "peric_spi2_ipclkport_i_sclk_spi", "dout_peric_spi_clk", + GAT_PERIC_SPI2_IPCLKPORT_I_SCLK_SPI, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_HCLK_TDM0, "peric_tdm0_ipclkport_hclk_m", "mout_peric_pclk", + GAT_PERIC_TDM0_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_TDM0, "peric_tdm0_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_TDM0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_HCLK_TDM1, "peric_tdm1_ipclkport_hclk_m", "mout_peric_pclk", + GAT_PERIC_TDM1_IPCLKPORT_HCLK_M, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_TDM1, "peric_tdm1_ipclkport_pclk", "mout_peric_pclk", + GAT_PERIC_TDM1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_SCLK_UART0, "peric_uart0_ipclkport_i_sclk_uart", "dout_peric_uart_clk", + GAT_PERIC_UART0_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_UART0, "peric_uart0_ipclkport_pclk", "mout_peric_uart_pclk", + GAT_PERIC_UART0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_SCLK_UART1, "peric_uart1_ipclkport_i_sclk_uart", "dout_peric_uart_clk", + GAT_PERIC_UART1_IPCLKPORT_I_SCLK_UART, 21, CLK_IGNORE_UNUSED, 0), + GATE(PERIC_PCLK_UART1, "peric_uart1_ipclkport_pclk", "mout_peric_uart_pclk", + GAT_PERIC_UART1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "peric_sysreg_peri_ipclkport_pclk", "mout_peric_pclk", + GAT_SYSREG_PERI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info peric_cmu_info __initconst = { + .mux_clks = peric_mux_clks, + .nr_mux_clks = ARRAY_SIZE(peric_mux_clks), + .div_clks = peric_div_clks, + .nr_div_clks = ARRAY_SIZE(peric_div_clks), + .gate_clks = peric_gate_clks, + .nr_gate_clks = ARRAY_SIZE(peric_gate_clks), + .fixed_clks = peric_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(peric_fixed_clks), + .nr_clk_ids = PERIC_NR_CLK, + .clk_regs = peric_clk_regs, + .nr_clk_regs = ARRAY_SIZE(peric_clk_regs), + .clk_name = "dout_cmu_pll_shared0_div4", +}; + +/* Register Offset definitions for CMU_FSYS0 (0x15010000) */ +#define PLL_CON0_CLKCMU_FSYS0_UNIPRO 0x100 +#define PLL_CON0_CLK_FSYS0_SLAVEBUSCLK 0x140 +#define PLL_CON0_EQOS_RGMII_125_MUX1 0x160 +#define DIV_CLK_UNIPRO 0x1800 +#define DIV_EQS_RGMII_CLK_125 0x1804 +#define DIV_PERIBUS_GRP 0x1808 +#define DIV_EQOS_RII_CLK2O5 0x180c +#define DIV_EQOS_RMIICLK_25 0x1810 +#define DIV_PCIE_PHY_OSCCLK 0x1814 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 0x2004 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 0x2008 +#define GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x200c +#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK 0x2010 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO 0x2014 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK 0x2018 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC 0x201c +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2020 +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x2024 +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24 0x2028 +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26 0x202c +#define GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK 0x2038 +#define GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK 0x203c +#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK 0x2040 +#define GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK 0x2044 +#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK 0x2048 +#define GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK 0x204c +#define GAT_FSYS0_CPE425_IPCLKPORT_ACLK 0x2050 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 0x2054 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 0x2058 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 0x205c +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I 0x2060 +#define GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I 0x2064 +#define GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK 0x2068 +#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D 0x206c +#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1 0x2070 +#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P 0x2074 +#define GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S 0x2078 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK 0x207c +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL 0x2080 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0 0x2084 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC 0x2088 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x208c +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC 0x2090 +#define GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC 0x2094 +#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK 0x2098 +#define GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK 0x209c +#define GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK 0x20a0 +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS 0x20a4 +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK 0x20a8 +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO 0x20ac +#define GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK 0x20b0 +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS 0x20b4 +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK 0x20b8 +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO 0x20bc +#define GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK 0x20c0 +#define GAT_FSYS0_RII_CLK_DIVGATE 0x20d4 + +static const unsigned long fsys0_clk_regs[] __initconst = { + PLL_CON0_CLKCMU_FSYS0_UNIPRO, + PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, + PLL_CON0_EQOS_RGMII_125_MUX1, + DIV_CLK_UNIPRO, + DIV_EQS_RGMII_CLK_125, + DIV_PERIBUS_GRP, + DIV_EQOS_RII_CLK2O5, + DIV_EQOS_RMIICLK_25, + DIV_PCIE_PHY_OSCCLK, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, + GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, + GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, + GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, + GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, + GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, + GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, + GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, + GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, + GAT_FSYS0_CPE425_IPCLKPORT_ACLK, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, + GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, + GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, + GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, + GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, + GAT_FSYS0_RII_CLK_DIVGATE, +}; + +static const struct samsung_fixed_rate_clock fsys0_fixed_clks[] __initconst = { + FRATE(0, "pad_eqos0_phyrxclk", NULL, 0, 125000000), + FRATE(0, "i_mphy_refclk_ixtal26", NULL, 0, 26000000), + FRATE(0, "xtal_clk_pcie_phy", NULL, 0, 100000000), +}; + +/* List of parent clocks for Muxes in CMU_FSYS0 */ +PNAME(mout_fsys0_clkcmu_fsys0_unipro_p) = { "fin_pll", "dout_cmu_pll_shared0_div6" }; +PNAME(mout_fsys0_clk_fsys0_slavebusclk_p) = { "fin_pll", "dout_cmu_fsys0_shared1div4" }; +PNAME(mout_fsys0_eqos_rgmii_125_mux1_p) = { "fin_pll", "dout_cmu_fsys0_shared0div4" }; + +static const struct samsung_mux_clock fsys0_mux_clks[] __initconst = { + MUX(0, "mout_fsys0_clkcmu_fsys0_unipro", mout_fsys0_clkcmu_fsys0_unipro_p, + PLL_CON0_CLKCMU_FSYS0_UNIPRO, 4, 1), + MUX(0, "mout_fsys0_clk_fsys0_slavebusclk", mout_fsys0_clk_fsys0_slavebusclk_p, + PLL_CON0_CLK_FSYS0_SLAVEBUSCLK, 4, 1), + MUX(0, "mout_fsys0_eqos_rgmii_125_mux1", mout_fsys0_eqos_rgmii_125_mux1_p, + PLL_CON0_EQOS_RGMII_125_MUX1, 4, 1), +}; + +static const struct samsung_div_clock fsys0_div_clks[] __initconst = { + DIV(0, "dout_fsys0_clk_unipro", "mout_fsys0_clkcmu_fsys0_unipro", DIV_CLK_UNIPRO, 0, 4), + DIV(0, "dout_fsys0_eqs_rgmii_clk_125", "mout_fsys0_eqos_rgmii_125_mux1", + DIV_EQS_RGMII_CLK_125, 0, 4), + DIV(FSYS0_DOUT_FSYS0_PERIBUS_GRP, "dout_fsys0_peribus_grp", + "mout_fsys0_clk_fsys0_slavebusclk", DIV_PERIBUS_GRP, 0, 4), + DIV(0, "dout_fsys0_eqos_rii_clk2o5", "fsys0_rii_clk_divgate", DIV_EQOS_RII_CLK2O5, 0, 4), + DIV(0, "dout_fsys0_eqos_rmiiclk_25", "mout_fsys0_eqos_rgmii_125_mux1", + DIV_EQOS_RMIICLK_25, 0, 5), + DIV(0, "dout_fsys0_pcie_phy_oscclk", "mout_fsys0_eqos_rgmii_125_mux1", + DIV_PCIE_PHY_OSCCLK, 0, 4), +}; + +static const struct samsung_gate_clock fsys0_gate_clks[] __initconst = { + GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, "fsys0_eqos_top0_ipclkport_clk_rx_i", + "pad_eqos0_phyrxclk", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_SUBCTRL_INST0_AUX_CLK_SOC, + "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_aux_clk_soc", "fin_pll", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_AUX_CLK_SOC, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_fsys0_cmu_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, + "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_xo", + "xtal_clk_pcie_phy", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_XO, 21, + CLK_IGNORE_UNUSED, 0), + GATE(UFS0_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal24", + "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21, + CLK_IGNORE_UNUSED, 0), + GATE(UFS0_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top0_ipclkport_i_mphy_refclk_ixtal26", + "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21, + CLK_IGNORE_UNUSED, 0), + GATE(UFS1_MPHY_REFCLK_IXTAL24, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal24", + "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL24, 21, + CLK_IGNORE_UNUSED, 0), + GATE(UFS1_MPHY_REFCLK_IXTAL26, "fsys0_ufs_top1_ipclkport_i_mphy_refclk_ixtal26", + "i_mphy_refclk_ixtal26", GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_MPHY_REFCLK_IXTAL26, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_ahbbr_fsys0_ipclkport_hclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_AHBBR_FSYS0_IPCLKPORT_HCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_axi2apb_fsys0_ipclkport_aclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_AXI2APB_FSYS0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_bus_d_fsys0_ipclkport_mainclk", "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_bus_d_fsys0_ipclkport_periclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_BUS_D_FSYS0_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_bus_p_fsys0_ipclkport_mainclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_bus_p_fsys0_ipclkport_tcuclk", "mout_fsys0_eqos_rgmii_125_mux1", + GAT_FSYS0_BUS_P_FSYS0_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_cpe425_ipclkport_aclk", "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_CPE425_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, "fsys0_eqos_top0_ipclkport_aclk_i", + "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I, 21, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, "fsys0_eqos_top0_ipclkport_hclk_i", + "dout_fsys0_peribus_grp", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I, 21, + CLK_IGNORE_UNUSED, 0), + GATE(FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, "fsys0_eqos_top0_ipclkport_rgmii_clk_i", + "dout_fsys0_eqs_rgmii_clk_125", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_eqos_top0_ipclkport_rii_clk_i", "dout_fsys0_eqos_rii_clk2o5", + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_eqos_top0_ipclkport_rmii_clk_i", "dout_fsys0_eqos_rmiiclk_25", + GAT_FSYS0_EQOS_TOP0_IPCLKPORT_RMII_CLK_I, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_gpio_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_gpio_fsys0_ipclkport_oscclk", "fin_pll", + GAT_FSYS0_GPIO_FSYS0_IPCLKPORT_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d", + "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_d1", + "mout_fsys0_eqos_rgmii_125_mux1", + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_D1, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_p", + "dout_fsys0_peribus_grp", + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_P, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_ns_brdg_fsys0_ipclkport_clk__psoc_fsys0__clk_fsys0_s", + "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_NS_BRDG_FSYS0_IPCLKPORT_CLK__PSOC_FSYS0__CLK_FSYS0_S, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_i_apb_pclk", + "dout_fsys0_peribus_grp", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_I_APB_PCLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, + "fsys0_pcie_top_ipclkport_pcieg3_phy_x4_inst_0_pll_refclk_from_syspll", + "dout_fsys0_pcie_phy_oscclk", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PCIEG3_PHY_X4_INST_0_PLL_REFCLK_FROM_SYSPLL, + 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_apb_pclk_0", "dout_fsys0_peribus_grp", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_APB_PCLK_0, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_pcie_top_ipclkport_pipe_pal_inst_0_i_immortal_clk", "fin_pll", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_PIPE_PAL_INST_0_I_IMMORTAL_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PCIE_SUBCTRL_INST0_DBI_ACLK_SOC, + "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_dbi_aclk_soc", + "dout_fsys0_peribus_grp", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_DBI_ACLK_SOC, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_i_driver_apb_clk", + "dout_fsys0_peribus_grp", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC, + "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_mstr_aclk_soc", + "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_MSTR_ACLK_SOC, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_SUBCTRL_INST0_SLV_ACLK_SOC, + "fsys0_pcie_top_ipclkport_fsd_pcie_sub_ctrl_inst_0_slv_aclk_soc", + "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_PCIE_TOP_IPCLKPORT_FSD_PCIE_SUB_CTRL_INST_0_SLV_ACLK_SOC, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_smmu_fsys0_ipclkport_cclk", "mout_fsys0_eqos_rgmii_125_mux1", + GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_smmu_fsys0_ipclkport_fsys0_bclk", "mout_fsys0_clk_fsys0_slavebusclk", + GAT_FSYS0_SMMU_FSYS0_IPCLKPORT_FSYS0_BCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_sysreg_fsys0_ipclkport_pclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_SYSREG_FSYS0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS0_TOP0_HCLK_BUS, "fsys0_ufs_top0_ipclkport_hclk_bus", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP0_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS0_TOP0_ACLK, "fsys0_ufs_top0_ipclkport_i_aclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS0_TOP0_CLK_UNIPRO, "fsys0_ufs_top0_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro", + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS0_TOP0_FMP_CLK, "fsys0_ufs_top0_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP0_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS1_TOP1_HCLK_BUS, "fsys0_ufs_top1_ipclkport_hclk_bus", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP1_IPCLKPORT_HCLK_BUS, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS1_TOP1_ACLK, "fsys0_ufs_top1_ipclkport_i_aclk", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS1_TOP1_CLK_UNIPRO, "fsys0_ufs_top1_ipclkport_i_clk_unipro", "dout_fsys0_clk_unipro", + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_CLK_UNIPRO, 21, CLK_IGNORE_UNUSED, 0), + GATE(UFS1_TOP1_FMP_CLK, "fsys0_ufs_top1_ipclkport_i_fmp_clk", "dout_fsys0_peribus_grp", + GAT_FSYS0_UFS_TOP1_IPCLKPORT_I_FMP_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys0_rii_clk_divgate", "dout_fsys0_eqos_rmiiclk_25", GAT_FSYS0_RII_CLK_DIVGATE, + 21, CLK_IGNORE_UNUSED, 0), + GATE(FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, "fsys0_eqos_top0_ipclkport_clk_ptp_ref_i", + "fin_pll", GAT_FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info fsys0_cmu_info __initconst = { + .mux_clks = fsys0_mux_clks, + .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks), + .div_clks = fsys0_div_clks, + .nr_div_clks = ARRAY_SIZE(fsys0_div_clks), + .gate_clks = fsys0_gate_clks, + .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks), + .fixed_clks = fsys0_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(fsys0_fixed_clks), + .nr_clk_ids = FSYS0_NR_CLK, + .clk_regs = fsys0_clk_regs, + .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs), + .clk_name = "dout_cmu_fsys0_shared1div4", +}; + +/* Register Offset definitions for CMU_FSYS1 (0x16810000) */ +#define PLL_CON0_ACLK_FSYS1_BUSP_MUX 0x100 +#define PLL_CON0_PCLKL_FSYS1_BUSP_MUX 0x180 +#define DIV_CLK_FSYS1_PHY0_OSCCLK 0x1800 +#define DIV_CLK_FSYS1_PHY1_OSCCLK 0x1804 +#define GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2000 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK 0x2004 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK 0x2008 +#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK 0x200c +#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL 0x202c +#define GAT_FSYS1_PHY0_OSCCLLK 0x2034 +#define GAT_FSYS1_PHY1_OSCCLK 0x2038 +#define GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK 0x203c +#define GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK 0x2040 +#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK 0x2048 +#define GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK 0x204c +#define GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK 0x2054 +#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0 0x205c +#define GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0 0x2064 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK 0x206c +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK 0x2070 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK 0x2074 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK 0x2078 +#define GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK 0x207c +#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK 0x2080 +#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK 0x2084 +#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK 0x2088 +#define GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK 0x208c +#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK 0x20a4 +#define GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL 0x20a8 +#define GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK 0x20b4 +#define GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK 0x20b8 + +static const unsigned long fsys1_clk_regs[] __initconst = { + PLL_CON0_ACLK_FSYS1_BUSP_MUX, + PLL_CON0_PCLKL_FSYS1_BUSP_MUX, + DIV_CLK_FSYS1_PHY0_OSCCLK, + DIV_CLK_FSYS1_PHY1_OSCCLK, + GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, + GAT_FSYS1_PHY0_OSCCLLK, + GAT_FSYS1_PHY1_OSCCLK, + GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, + GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, + GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, + GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, + GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, + GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, + GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, + GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, + GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, +}; + +static const struct samsung_fixed_rate_clock fsys1_fixed_clks[] __initconst = { + FRATE(0, "clk_fsys1_phy0_ref", NULL, 0, 100000000), + FRATE(0, "clk_fsys1_phy1_ref", NULL, 0, 100000000), +}; + +/* List of parent clocks for Muxes in CMU_FSYS1 */ +PNAME(mout_fsys1_pclkl_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div8" }; +PNAME(mout_fsys1_aclk_fsys1_busp_mux_p) = { "fin_pll", "dout_cmu_fsys1_shared0div4" }; + +static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = { + MUX(0, "mout_fsys1_pclkl_fsys1_busp_mux", mout_fsys1_pclkl_fsys1_busp_mux_p, + PLL_CON0_PCLKL_FSYS1_BUSP_MUX, 4, 1), + MUX(0, "mout_fsys1_aclk_fsys1_busp_mux", mout_fsys1_aclk_fsys1_busp_mux_p, + PLL_CON0_ACLK_FSYS1_BUSP_MUX, 4, 1), +}; + +static const struct samsung_div_clock fsys1_div_clks[] __initconst = { + DIV(0, "dout_fsys1_clk_fsys1_phy0_oscclk", "fsys1_phy0_osccllk", + DIV_CLK_FSYS1_PHY0_OSCCLK, 0, 4), + DIV(0, "dout_fsys1_clk_fsys1_phy1_oscclk", "fsys1_phy1_oscclk", + DIV_CLK_FSYS1_PHY1_OSCCLK, 0, 4), +}; + +static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = { + GATE(0, "fsys1_cmu_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_xtal", "clk_fsys1_phy0_ref", + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_XTAL, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_phy0_osccllk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_PHY0_OSCCLLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_phy1_oscclk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_PHY1_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_axi2apb_fsys1_ipclkport_aclk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_AXI2APB_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_bus_d0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_BUS_D0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_bus_s0_fsys1_ipclkport_m250clk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_M250CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_bus_s0_fsys1_ipclkport_mainclk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_BUS_S0_FSYS1_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_cpe425_0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_CPE425_0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_d0", + "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_D0, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_ns_brdg_fsys1_ipclkport_clk__psoc_fsys1__clk_fsys1_s0", + "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_NS_BRDG_FSYS1_IPCLKPORT_CLK__PSOC_FSYS1__CLK_FSYS1_S0, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK0_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link0_ipclkport_dbi_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_DBI_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_link0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_link0_ipclkport_i_soc_ref_clk", "fin_pll", + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_SOC_REF_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_link0_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK0_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link0_ipclkport_mstr_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_MSTR_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK0_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link0_ipclkport_slv_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK0_IPCLKPORT_SLV_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK1_IPCLKPORT_DBI_ACLK, "fsys1_pcie_link1_ipclkport_dbi_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_DBI_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_link1_ipclkport_i_driver_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_I_DRIVER_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK1_IPCLKPORT_MSTR_ACLK, "fsys1_pcie_link1_ipclkport_mstr_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_MSTR_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK1_IPCLKPORT_SLV_ACLK, "fsys1_pcie_link1_ipclkport_slv_aclk", + "mout_fsys1_aclk_fsys1_busp_mux", GAT_FSYS1_PCIE_LINK1_IPCLKPORT_SLV_ACLK, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_phy0_ipclkport_i_apb_clk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_APB_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK0_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link0_ipclkport_auxclk", "fin_pll", + GAT_FSYS1_PCIE_LINK0_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(PCIE_LINK1_IPCLKPORT_AUX_ACLK, "fsys1_pcie_link1_ipclkport_auxclk", "fin_pll", + GAT_FSYS1_PCIE_LINK1_IPCLKPORT_AUXCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_pcie_phy0_ipclkport_i_ref_soc_pll", "dout_fsys1_clk_fsys1_phy0_oscclk", + GAT_FSYS1_PCIE_PHY0_IPCLKPORT_I_REF_SOC_PLL, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_sysreg_fsys1_ipclkport_pclk", "mout_fsys1_pclkl_fsys1_busp_mux", + GAT_FSYS1_SYSREG_FSYS1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "fsys1_tbu0_fsys1_ipclkport_aclk", "mout_fsys1_aclk_fsys1_busp_mux", + GAT_FSYS1_TBU0_FSYS1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info fsys1_cmu_info __initconst = { + .mux_clks = fsys1_mux_clks, + .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks), + .div_clks = fsys1_div_clks, + .nr_div_clks = ARRAY_SIZE(fsys1_div_clks), + .gate_clks = fsys1_gate_clks, + .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks), + .fixed_clks = fsys1_fixed_clks, + .nr_fixed_clks = ARRAY_SIZE(fsys1_fixed_clks), + .nr_clk_ids = FSYS1_NR_CLK, + .clk_regs = fsys1_clk_regs, + .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs), + .clk_name = "dout_cmu_fsys1_shared0div4", +}; + +/* Register Offset definitions for CMU_IMEM (0x10010000) */ +#define PLL_CON0_CLK_IMEM_ACLK 0x100 +#define PLL_CON0_CLK_IMEM_INTMEMCLK 0x120 +#define PLL_CON0_CLK_IMEM_TCUCLK 0x140 +#define DIV_OSCCLK_IMEM_TMUTSCLK 0x1800 +#define GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK 0x2000 +#define GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO 0x2004 +#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x2008 +#define GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK 0x200c +#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK 0x2010 +#define GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 0x2014 +#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK 0x2018 +#define GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 0x201c +#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK 0x2020 +#define GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 0x2024 +#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK 0x2028 +#define GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 0x202c +#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK 0x2030 +#define GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 0x2034 +#define GAT_IMEM_WDT0_IPCLKPORT_CLK 0x2038 +#define GAT_IMEM_WDT1_IPCLKPORT_CLK 0x203c +#define GAT_IMEM_WDT2_IPCLKPORT_CLK 0x2040 +#define GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM 0x2044 +#define GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM 0x2048 +#define GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM 0x204c +#define GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS 0x2050 +#define GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS 0x2054 +#define GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS 0x2058 +#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM 0x205c +#define GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS 0x2060 +#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM 0x2064 +#define GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS 0x2068 +#define GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK 0x206c +#define GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK 0x2070 +#define GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK 0x2074 +#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK 0x2078 +#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK 0x207c +#define GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK 0x2080 +#define GAT_IMEM_DMA0_IPCLKPORT_ACLK 0x2084 +#define GAT_IMEM_DMA1_IPCLKPORT_ACLK 0x2088 +#define GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK 0x208c +#define GAT_IMEM_GIC_IPCLKPORT_CLK 0x2090 +#define GAT_IMEM_INTMEM_IPCLKPORT_ACLK 0x2094 +#define GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK 0x2098 +#define GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK 0x209c +#define GAT_IMEM_MCT_IPCLKPORT_PCLK 0x20a0 +#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D 0x20a4 +#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU 0x20a8 +#define GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P 0x20ac +#define GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK 0x20b0 +#define GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK 0x20b4 +#define GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK 0x20b8 +#define GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK 0x20bc +#define GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK 0x20c0 +#define GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK 0x20c4 +#define GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK 0x20c8 +#define GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK 0x20cc +#define GAT_IMEM_TCU_IPCLKPORT_ACLK 0x20d0 +#define GAT_IMEM_WDT0_IPCLKPORT_PCLK 0x20d4 +#define GAT_IMEM_WDT1_IPCLKPORT_PCLK 0x20d8 +#define GAT_IMEM_WDT2_IPCLKPORT_PCLK 0x20dc + +static const unsigned long imem_clk_regs[] __initconst = { + PLL_CON0_CLK_IMEM_ACLK, + PLL_CON0_CLK_IMEM_INTMEMCLK, + PLL_CON0_CLK_IMEM_TCUCLK, + DIV_OSCCLK_IMEM_TMUTSCLK, + GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, + GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, + GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, + GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, + GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, + GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, + GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, + GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, + GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, + GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, + GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, + GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, + GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, + GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, + GAT_IMEM_WDT0_IPCLKPORT_CLK, + GAT_IMEM_WDT1_IPCLKPORT_CLK, + GAT_IMEM_WDT2_IPCLKPORT_CLK, + GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, + GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, + GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, + GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, + GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, + GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, + GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, + GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, + GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, + GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, + GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, + GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, + GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, + GAT_IMEM_DMA0_IPCLKPORT_ACLK, + GAT_IMEM_DMA1_IPCLKPORT_ACLK, + GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, + GAT_IMEM_GIC_IPCLKPORT_CLK, + GAT_IMEM_INTMEM_IPCLKPORT_ACLK, + GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, + GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, + GAT_IMEM_MCT_IPCLKPORT_PCLK, + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, + GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, + GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, + GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, + GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, + GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, + GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, + GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, + GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, + GAT_IMEM_TCU_IPCLKPORT_ACLK, + GAT_IMEM_WDT0_IPCLKPORT_PCLK, + GAT_IMEM_WDT1_IPCLKPORT_PCLK, + GAT_IMEM_WDT2_IPCLKPORT_PCLK, +}; + +PNAME(mout_imem_clk_imem_tcuclk_p) = { "fin_pll", "dout_cmu_imem_tcuclk" }; +PNAME(mout_imem_clk_imem_aclk_p) = { "fin_pll", "dout_cmu_imem_aclk" }; +PNAME(mout_imem_clk_imem_intmemclk_p) = { "fin_pll", "dout_cmu_imem_dmaclk" }; + +static const struct samsung_mux_clock imem_mux_clks[] __initconst = { + MUX(0, "mout_imem_clk_imem_tcuclk", mout_imem_clk_imem_tcuclk_p, + PLL_CON0_CLK_IMEM_TCUCLK, 4, 1), + MUX(0, "mout_imem_clk_imem_aclk", mout_imem_clk_imem_aclk_p, PLL_CON0_CLK_IMEM_ACLK, 4, 1), + MUX(0, "mout_imem_clk_imem_intmemclk", mout_imem_clk_imem_intmemclk_p, + PLL_CON0_CLK_IMEM_INTMEMCLK, 4, 1), +}; + +static const struct samsung_div_clock imem_div_clks[] __initconst = { + DIV(0, "dout_imem_oscclk_imem_tmutsclk", "fin_pll", DIV_OSCCLK_IMEM_TMUTSCLK, 0, 4), +}; + +static const struct samsung_gate_clock imem_gate_clks[] __initconst = { + GATE(0, "imem_imem_cmu_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_otp_con_top_ipclkport_i_oscclk", "fin_pll", + GAT_IMEM_OTP_CON_TOP_IPCLKPORT_I_OSCCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tmu_top_ipclkport_i_clk", "fin_pll", + GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tmu_gt_ipclkport_i_clk", "fin_pll", + GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tmu_cpu0_ipclkport_i_clk", "fin_pll", + GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tmu_gpu_ipclkport_i_clk", "fin_pll", + GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_mct_ipclkport_oscclk__alo", "fin_pll", + GAT_IMEM_MCT_IPCLKPORT_OSCCLK__ALO, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_wdt0_ipclkport_clk", "fin_pll", + GAT_IMEM_WDT0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_wdt1_ipclkport_clk", "fin_pll", + GAT_IMEM_WDT1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_wdt2_ipclkport_clk", "fin_pll", + GAT_IMEM_WDT2_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu0_ipclkport_i_clk_ts", + "dout_imem_oscclk_imem_tmutsclk", + GAT_IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, "imem_tmu_cpu2_ipclkport_i_clk_ts", + "dout_imem_oscclk_imem_tmutsclk", + GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, "imem_tmu_gpu_ipclkport_i_clk_ts", + "dout_imem_oscclk_imem_tmutsclk", + GAT_IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, "imem_tmu_gt_ipclkport_i_clk_ts", + "dout_imem_oscclk_imem_tmutsclk", + GAT_IMEM_TMU_GT_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, "imem_tmu_top_ipclkport_i_clk_ts", + "dout_imem_oscclk_imem_tmutsclk", + GAT_IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_adm_axi4st_i0_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADM_AXI4ST_I0_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_adm_axi4st_i1_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADM_AXI4ST_I1_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_adm_axi4st_i2_imem_ipclkport_aclkm", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADM_AXI4ST_I2_IMEM_IPCLKPORT_ACLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ads_axi4st_i0_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADS_AXI4ST_I0_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ads_axi4st_i1_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADS_AXI4ST_I1_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ads_axi4st_i2_imem_ipclkport_aclks", "mout_imem_clk_imem_aclk", + GAT_IMEM_ADS_AXI4ST_I2_IMEM_IPCLKPORT_ACLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_async_dma0_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_async_dma0_ipclkport_pclks", "mout_imem_clk_imem_aclk", + GAT_IMEM_ASYNC_DMA0_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_async_dma1_ipclkport_pclkm", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_async_dma1_ipclkport_pclks", "mout_imem_clk_imem_aclk", + GAT_IMEM_ASYNC_DMA1_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_axi2apb_imemp0_ipclkport_aclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_AXI2APB_IMEMP0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_axi2apb_imemp1_ipclkport_aclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_AXI2APB_IMEMP1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_bus_d_imem_ipclkport_mainclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_BUS_D_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_bus_p_imem_ipclkport_mainclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_MAINCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_bus_p_imem_ipclkport_pericclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_PERICLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_bus_p_imem_ipclkport_tcuclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_BUS_P_IMEM_IPCLKPORT_TCUCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_DMA0_IPCLKPORT_ACLK, "imem_dma0_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_DMA0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0), + GATE(IMEM_DMA1_IPCLKPORT_ACLK, "imem_dma1_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_DMA1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, 0), + GATE(0, "imem_gic500_input_sync_ipclkport_clk", "mout_imem_clk_imem_aclk", + GAT_IMEM_GIC500_INPUT_SYNC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_gic_ipclkport_clk", "mout_imem_clk_imem_aclk", + GAT_IMEM_GIC_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_intmem_ipclkport_aclk", "mout_imem_clk_imem_intmemclk", + GAT_IMEM_INTMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_mailbox_scs_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_MAILBOX_SCS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_mailbox_sms_ca72_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_MAILBOX_SMS_CA72_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_MCT_PCLK, "imem_mct_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_MCT_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_d", + "mout_imem_clk_imem_tcuclk", + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_D, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psco_imem__clk_imem_tcu", + "mout_imem_clk_imem_tcuclk", + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSCO_IMEM__CLK_IMEM_TCU, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_ns_brdg_imem_ipclkport_clk__psoc_imem__clk_imem_p", "mout_imem_clk_imem_aclk", + GAT_IMEM_NS_BRDG_IMEM_IPCLKPORT_CLK__PSOC_IMEM__CLK_IMEM_P, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_otp_con_top_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_OTP_CON_TOP_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_rstnsync_aclk_ipclkport_clk", "mout_imem_clk_imem_aclk", + GAT_IMEM_RSTNSYNC_ACLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_rstnsync_oscclk_ipclkport_clk", "fin_pll", + GAT_IMEM_RSTNSYNC_OSCCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_rstnsync_intmemclk_ipclkport_clk", "mout_imem_clk_imem_intmemclk", + GAT_IMEM_RSTNSYNC_INTMEMCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_rstnsync_tcuclk_ipclkport_clk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_RSTNSYNC_TCUCLK_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_sfrif_tmu0_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_SFRIF_TMU0_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_sfrif_tmu1_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_SFRIF_TMU1_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tmu_cpu2_ipclkport_i_clk", "fin_pll", + GAT_IMEM_TMU_CPU2_IPCLKPORT_I_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_sysreg_imem_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_SYSREG_IMEM_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tbu_imem_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_TBU_IMEM_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "imem_tcu_ipclkport_aclk", "mout_imem_clk_imem_tcuclk", + GAT_IMEM_TCU_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_WDT0_IPCLKPORT_PCLK, "imem_wdt0_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_WDT0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_WDT1_IPCLKPORT_PCLK, "imem_wdt1_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_WDT1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(IMEM_WDT2_IPCLKPORT_PCLK, "imem_wdt2_ipclkport_pclk", "mout_imem_clk_imem_aclk", + GAT_IMEM_WDT2_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info imem_cmu_info __initconst = { + .mux_clks = imem_mux_clks, + .nr_mux_clks = ARRAY_SIZE(imem_mux_clks), + .div_clks = imem_div_clks, + .nr_div_clks = ARRAY_SIZE(imem_div_clks), + .gate_clks = imem_gate_clks, + .nr_gate_clks = ARRAY_SIZE(imem_gate_clks), + .nr_clk_ids = IMEM_NR_CLK, + .clk_regs = imem_clk_regs, + .nr_clk_regs = ARRAY_SIZE(imem_clk_regs), +}; + +static void __init fsd_clk_imem_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &imem_cmu_info); +} + +CLK_OF_DECLARE(fsd_clk_imem, "tesla,fsd-clock-imem", fsd_clk_imem_init); + +/* Register Offset definitions for CMU_MFC (0x12810000) */ +#define PLL_LOCKTIME_PLL_MFC 0x0 +#define PLL_CON0_PLL_MFC 0x100 +#define MUX_MFC_BUSD 0x1000 +#define MUX_MFC_BUSP 0x1008 +#define DIV_MFC_BUSD_DIV4 0x1800 +#define GAT_MFC_CMU_MFC_IPCLKPORT_PCLK 0x2000 +#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM 0x2004 +#define GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS 0x2008 +#define GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK 0x200c +#define GAT_MFC_MFC_IPCLKPORT_ACLK 0x2010 +#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D 0x2018 +#define GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P 0x201c +#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK 0x2028 +#define GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK 0x202c +#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK 0x2030 +#define GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK 0x2034 +#define GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK 0x2038 +#define GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK 0x203c +#define GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK 0x2040 +#define GAT_MFC_BUSD_DIV4_GATE 0x2044 +#define GAT_MFC_BUSD_GATE 0x2048 + +static const unsigned long mfc_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_MFC, + PLL_CON0_PLL_MFC, + MUX_MFC_BUSD, + MUX_MFC_BUSP, + DIV_MFC_BUSD_DIV4, + GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, + GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, + GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, + GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, + GAT_MFC_MFC_IPCLKPORT_ACLK, + GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, + GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, + GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, + GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, + GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, + GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, + GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, + GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, + GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, + GAT_MFC_BUSD_DIV4_GATE, + GAT_MFC_BUSD_GATE, +}; + +static const struct samsung_pll_rate_table pll_mfc_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 666000000U, 111, 4, 0), +}; + +static const struct samsung_pll_clock mfc_pll_clks[] __initconst = { + PLL(pll_142xx, 0, "fout_pll_mfc", "fin_pll", + PLL_LOCKTIME_PLL_MFC, PLL_CON0_PLL_MFC, pll_mfc_rate_table), +}; + +PNAME(mout_mfc_pll_p) = { "fin_pll", "fout_pll_mfc" }; +PNAME(mout_mfc_busp_p) = { "fin_pll", "dout_mfc_busd_div4" }; +PNAME(mout_mfc_busd_p) = { "fin_pll", "mfc_busd_gate" }; + +static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { + MUX(0, "mout_mfc_pll", mout_mfc_pll_p, PLL_CON0_PLL_MFC, 4, 1), + MUX(0, "mout_mfc_busp", mout_mfc_busp_p, MUX_MFC_BUSP, 0, 1), + MUX(0, "mout_mfc_busd", mout_mfc_busd_p, MUX_MFC_BUSD, 0, 1), +}; + +static const struct samsung_div_clock mfc_div_clks[] __initconst = { + DIV(0, "dout_mfc_busd_div4", "mfc_busd_div4_gate", DIV_MFC_BUSD_DIV4, 0, 4), +}; + +static const struct samsung_gate_clock mfc_gate_clks[] __initconst = { + GATE(0, "mfc_cmu_mfc_ipclkport_pclk", "mout_mfc_busp", + GAT_MFC_CMU_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_as_p_mfc_ipclkport_pclkm", "mout_mfc_busd", + GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKM, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_as_p_mfc_ipclkport_pclks", "mout_mfc_busp", + GAT_MFC_AS_P_MFC_IPCLKPORT_PCLKS, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_axi2apb_mfc_ipclkport_aclk", "mout_mfc_busp", + GAT_MFC_AXI2APB_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(MFC_MFC_IPCLKPORT_ACLK, "mfc_mfc_ipclkport_aclk", "mout_mfc_busd", + GAT_MFC_MFC_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_d", "mout_mfc_busd", + GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_D, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ns_brdg_mfc_ipclkport_clk__pmfc__clk_mfc_p", "mout_mfc_busp", + GAT_MFC_NS_BRDG_MFC_IPCLKPORT_CLK__PMFC__CLK_MFC_P, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ppmu_mfcd0_ipclkport_aclk", "mout_mfc_busd", + GAT_MFC_PPMU_MFCD0_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ppmu_mfcd0_ipclkport_pclk", "mout_mfc_busp", + GAT_MFC_PPMU_MFCD0_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ppmu_mfcd1_ipclkport_aclk", "mout_mfc_busd", + GAT_MFC_PPMU_MFCD1_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_ppmu_mfcd1_ipclkport_pclk", "mout_mfc_busp", + GAT_MFC_PPMU_MFCD1_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_sysreg_mfc_ipclkport_pclk", "mout_mfc_busp", + GAT_MFC_SYSREG_MFC_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_tbu_mfcd0_ipclkport_clk", "mout_mfc_busd", + GAT_MFC_TBU_MFCD0_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_tbu_mfcd1_ipclkport_clk", "mout_mfc_busd", + GAT_MFC_TBU_MFCD1_IPCLKPORT_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_busd_div4_gate", "mout_mfc_pll", + GAT_MFC_BUSD_DIV4_GATE, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "mfc_busd_gate", "mout_mfc_pll", GAT_MFC_BUSD_GATE, 21, CLK_IS_CRITICAL, 0), +}; + +static const struct samsung_cmu_info mfc_cmu_info __initconst = { + .pll_clks = mfc_pll_clks, + .nr_pll_clks = ARRAY_SIZE(mfc_pll_clks), + .mux_clks = mfc_mux_clks, + .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks), + .div_clks = mfc_div_clks, + .nr_div_clks = ARRAY_SIZE(mfc_div_clks), + .gate_clks = mfc_gate_clks, + .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks), + .nr_clk_ids = MFC_NR_CLK, + .clk_regs = mfc_clk_regs, + .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), +}; + +/* Register Offset definitions for CMU_CAM_CSI (0x12610000) */ +#define PLL_LOCKTIME_PLL_CAM_CSI 0x0 +#define PLL_CON0_PLL_CAM_CSI 0x100 +#define DIV_CAM_CSI0_ACLK 0x1800 +#define DIV_CAM_CSI1_ACLK 0x1804 +#define DIV_CAM_CSI2_ACLK 0x1808 +#define DIV_CAM_CSI_BUSD 0x180c +#define DIV_CAM_CSI_BUSP 0x1810 +#define GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK 0x2000 +#define GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK 0x2004 +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0 0x2008 +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1 0x200c +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2 0x2010 +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC 0x2014 +#define GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC 0x2018 +#define GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK 0x201c +#define GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK 0x2020 +#define GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK 0x2024 +#define GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK 0x2028 +#define GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK 0x202c +#define GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK 0x2030 +#define GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK 0x2034 +#define GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK 0x2038 +#define GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK 0x203c +#define GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK 0x2040 +#define GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK 0x2044 +#define GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK 0x2048 +#define GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK 0x204c +#define GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK 0x2050 +#define GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK 0x2054 +#define GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK 0x2058 +#define GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK 0x205c +#define GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK 0x2060 +#define GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK 0x2064 +#define GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK 0x2068 +#define GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK 0x206c +#define GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK 0x2070 +#define GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK 0x2074 +#define GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK 0x2078 +#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D 0x207c +#define GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P 0x2080 +#define GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK 0x2084 +#define GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK 0x2088 + +static const unsigned long cam_csi_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_CAM_CSI, + PLL_CON0_PLL_CAM_CSI, + DIV_CAM_CSI0_ACLK, + DIV_CAM_CSI1_ACLK, + DIV_CAM_CSI2_ACLK, + DIV_CAM_CSI_BUSD, + DIV_CAM_CSI_BUSP, + GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, + GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, + GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, + GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, + GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, + GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, + GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, + GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, + GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, + GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, + GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, + GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, + GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, + GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, + GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, + GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, + GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, + GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, + GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, + GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, + GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, + GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, + GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, + GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, + GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, + GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, + GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, + GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, +}; + +static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst = { + PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 12, 0), +}; + +static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = { + PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll", + PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table), +}; + +PNAME(mout_cam_csi_pll_p) = { "fin_pll", "fout_pll_cam_csi" }; + +static const struct samsung_mux_clock cam_csi_mux_clks[] __initconst = { + MUX(0, "mout_cam_csi_pll", mout_cam_csi_pll_p, PLL_CON0_PLL_CAM_CSI, 4, 1), +}; + +static const struct samsung_div_clock cam_csi_div_clks[] __initconst = { + DIV(0, "dout_cam_csi0_aclk", "mout_cam_csi_pll", DIV_CAM_CSI0_ACLK, 0, 4), + DIV(0, "dout_cam_csi1_aclk", "mout_cam_csi_pll", DIV_CAM_CSI1_ACLK, 0, 4), + DIV(0, "dout_cam_csi2_aclk", "mout_cam_csi_pll", DIV_CAM_CSI2_ACLK, 0, 4), + DIV(0, "dout_cam_csi_busd", "mout_cam_csi_pll", DIV_CAM_CSI_BUSD, 0, 4), + DIV(0, "dout_cam_csi_busp", "mout_cam_csi_pll", DIV_CAM_CSI_BUSP, 0, 4), +}; + +static const struct samsung_gate_clock cam_csi_gate_clks[] __initconst = { + GATE(0, "cam_csi_cmu_cam_csi_ipclkport_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI_CMU_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_axi2apb_cam_csi_ipclkport_aclk", "dout_cam_csi_busp", + GAT_CAM_AXI2APB_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi0", "dout_cam_csi0_aclk", + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI0, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi1", "dout_cam_csi1_aclk", + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI1, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_csi2", "dout_cam_csi2_aclk", + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_CSI2, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__clk_soc_noc", "dout_cam_csi_busd", + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__CLK_SOC_NOC, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi_bus_d_cam_csi_ipclkport_clk__system__noc", "dout_cam_csi_busd", + GAT_CAM_CSI_BUS_D_CAM_CSI_IPCLKPORT_CLK__SYSTEM__NOC, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI0_0_IPCLKPORT_I_ACLK, "cam_csi0_0_ipclkport_i_aclk", "dout_cam_csi0_aclk", + GAT_CAM_CSI0_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi0_0_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI0_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI0_1_IPCLKPORT_I_ACLK, "cam_csi0_1_ipclkport_i_aclk", "dout_cam_csi0_aclk", + GAT_CAM_CSI0_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi0_1_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI0_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI0_2_IPCLKPORT_I_ACLK, "cam_csi0_2_ipclkport_i_aclk", "dout_cam_csi0_aclk", + GAT_CAM_CSI0_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi0_2_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI0_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI0_3_IPCLKPORT_I_ACLK, "cam_csi0_3_ipclkport_i_aclk", "dout_cam_csi0_aclk", + GAT_CAM_CSI0_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi0_3_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI0_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI1_0_IPCLKPORT_I_ACLK, "cam_csi1_0_ipclkport_i_aclk", "dout_cam_csi1_aclk", + GAT_CAM_CSI1_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi1_0_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI1_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI1_1_IPCLKPORT_I_ACLK, "cam_csi1_1_ipclkport_i_aclk", "dout_cam_csi1_aclk", + GAT_CAM_CSI1_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi1_1_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI1_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI1_2_IPCLKPORT_I_ACLK, "cam_csi1_2_ipclkport_i_aclk", "dout_cam_csi1_aclk", + GAT_CAM_CSI1_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi1_2_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI1_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI1_3_IPCLKPORT_I_ACLK, "cam_csi1_3_ipclkport_i_aclk", "dout_cam_csi1_aclk", + GAT_CAM_CSI1_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi1_3_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI1_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI2_0_IPCLKPORT_I_ACLK, "cam_csi2_0_ipclkport_i_aclk", "dout_cam_csi2_aclk", + GAT_CAM_CSI2_0_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi2_0_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI2_0_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI2_1_IPCLKPORT_I_ACLK, "cam_csi2_1_ipclkport_i_aclk", "dout_cam_csi2_aclk", + GAT_CAM_CSI2_1_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi2_1_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI2_1_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI2_2_IPCLKPORT_I_ACLK, "cam_csi2_2_ipclkport_i_aclk", "dout_cam_csi2_aclk", + GAT_CAM_CSI2_2_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi2_2_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI2_2_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CAM_CSI2_3_IPCLKPORT_I_ACLK, "cam_csi2_3_ipclkport_i_aclk", "dout_cam_csi2_aclk", + GAT_CAM_CSI2_3_IPCLKPORT_I_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_csi2_3_ipclkport_i_pclk", "dout_cam_csi_busp", + GAT_CAM_CSI2_3_IPCLKPORT_I_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_d", + "dout_cam_csi_busd", + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_D, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_ns_brdg_cam_csi_ipclkport_clk__psoc_cam_csi__clk_cam_csi_p", + "dout_cam_csi_busp", + GAT_CAM_NS_BRDG_CAM_CSI_IPCLKPORT_CLK__PSOC_CAM_CSI__CLK_CAM_CSI_P, 21, + CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_sysreg_cam_csi_ipclkport_pclk", "dout_cam_csi_busp", + GAT_CAM_SYSREG_CAM_CSI_IPCLKPORT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(0, "cam_tbu_cam_csi_ipclkport_aclk", "dout_cam_csi_busd", + GAT_CAM_TBU_CAM_CSI_IPCLKPORT_ACLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info cam_csi_cmu_info __initconst = { + .pll_clks = cam_csi_pll_clks, + .nr_pll_clks = ARRAY_SIZE(cam_csi_pll_clks), + .mux_clks = cam_csi_mux_clks, + .nr_mux_clks = ARRAY_SIZE(cam_csi_mux_clks), + .div_clks = cam_csi_div_clks, + .nr_div_clks = ARRAY_SIZE(cam_csi_div_clks), + .gate_clks = cam_csi_gate_clks, + .nr_gate_clks = ARRAY_SIZE(cam_csi_gate_clks), + .nr_clk_ids = CAM_CSI_NR_CLK, + .clk_regs = cam_csi_clk_regs, + .nr_clk_regs = ARRAY_SIZE(cam_csi_clk_regs), +}; + +/** + * fsd_cmu_probe - Probe function for FSD platform clocks + * @pdev: Pointer to platform device + * + * Configure clock hierarchy for clock domains of FSD platform + */ +static int __init fsd_cmu_probe(struct platform_device *pdev) +{ + const struct samsung_cmu_info *info; + struct device *dev = &pdev->dev; + + info = of_device_get_match_data(dev); + exynos_arm64_register_cmu(dev, dev->of_node, info); + + return 0; +} + +/* CMUs which belong to Power Domains and need runtime PM to be implemented */ +static const struct of_device_id fsd_cmu_of_match[] = { + { + .compatible = "tesla,fsd-clock-peric", + .data = &peric_cmu_info, + }, { + .compatible = "tesla,fsd-clock-fsys0", + .data = &fsys0_cmu_info, + }, { + .compatible = "tesla,fsd-clock-fsys1", + .data = &fsys1_cmu_info, + }, { + .compatible = "tesla,fsd-clock-mfc", + .data = &mfc_cmu_info, + }, { + .compatible = "tesla,fsd-clock-cam_csi", + .data = &cam_csi_cmu_info, + }, { + }, +}; + +static struct platform_driver fsd_cmu_driver __refdata = { + .driver = { + .name = "fsd-cmu", + .of_match_table = fsd_cmu_of_match, + .suppress_bind_attrs = true, + }, + .probe = fsd_cmu_probe, +}; + +static int __init fsd_cmu_init(void) +{ + return platform_driver_register(&fsd_cmu_driver); +} +core_initcall(fsd_cmu_init); diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 70cdc87f714e..fe383471c5f0 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1469,6 +1469,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_1450x: case pll_1451x: case pll_1452x: + case pll_142xx: pll->enable_offs = PLL35XX_ENABLE_SHIFT; pll->lock_offs = PLL35XX_LOCK_STAT_SHIFT; if (!pll->rate_table) diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index c83a20195f6d..a9892c2d1f57 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -39,6 +39,7 @@ enum samsung_pll_type { pll_1460x, pll_0822x, pll_0831x, + pll_142xx, }; #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 2a3b7e582e45..240ecfb1938e 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -617,15 +617,6 @@ config CLKSRC_ST_LPC Enable this option to use the Low Power controller timer as clocksource. -config ATCPIT100_TIMER - bool "ATCPIT100 timer driver" - depends on NDS32 || COMPILE_TEST - depends on HAS_IOMEM - select TIMER_OF - default NDS32 - help - This option enables support for the Andestech ATCPIT100 timers. - config RISCV_TIMER bool "Timer for the RISC-V platform" if COMPILE_TEST depends on GENERIC_SCHED_CLOCK && RISCV && RISCV_SBI diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index fa5f624eadb6..9c85ee2bb373 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -81,7 +81,6 @@ obj-$(CONFIG_INGENIC_SYSOST) += ingenic-sysost.o obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o -obj-$(CONFIG_ATCPIT100_TIMER) += timer-atcpit100.o obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o obj-$(CONFIG_CLINT_TIMER) += timer-clint.o obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o diff --git a/drivers/clocksource/timer-atcpit100.c b/drivers/clocksource/timer-atcpit100.c deleted file mode 100644 index b4bd2f5b801d..000000000000 --- a/drivers/clocksource/timer-atcpit100.c +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation -/* - * Andestech ATCPIT100 Timer Device Driver Implementation - * Rick Chen, Andes Technology Corporation - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "timer-of.h" -#ifdef CONFIG_NDS32 -#include -#endif - -/* - * Definition of register offsets - */ - -/* ID and Revision Register */ -#define ID_REV 0x0 - -/* Configuration Register */ -#define CFG 0x10 - -/* Interrupt Enable Register */ -#define INT_EN 0x14 -#define CH_INT_EN(c, i) ((1<event_handler(evt); - - return IRQ_HANDLED; -} - -static struct timer_of to = { - .flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE, - - .clkevt = { - .name = "atcpit100_tick", - .rating = 300, - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, - .set_state_shutdown = atcpit100_clkevt_shutdown, - .set_state_periodic = atcpit100_clkevt_set_periodic, - .set_state_oneshot = atcpit100_clkevt_set_oneshot, - .tick_resume = atcpit100_clkevt_shutdown, - .set_next_event = atcpit100_clkevt_next_event, - .cpumask = cpu_possible_mask, - }, - - .of_irq = { - .handler = atcpit100_timer_interrupt, - .flags = IRQF_TIMER | IRQF_IRQPOLL, - }, - - /* - * FIXME: we currently only support clocking using PCLK - * and using EXTCLK is not supported in the driver. - */ - .of_clk = { - .name = "PCLK", - } -}; - -static u64 notrace atcpit100_timer_sched_read(void) -{ - return ~readl(timer_of_base(&to) + CH1_CNT); -} - -#ifdef CONFIG_NDS32 -static void fill_vdso_need_info(struct device_node *node) -{ - struct resource timer_res; - of_address_to_resource(node, 0, &timer_res); - timer_info.mapping_base = (unsigned long)timer_res.start; - timer_info.cycle_count_down = true; - timer_info.cycle_count_reg_offset = CH1_CNT; -} -#endif - -static int __init atcpit100_timer_init(struct device_node *node) -{ - int ret; - u32 val; - void __iomem *base; - - ret = timer_of_init(node, &to); - if (ret) - return ret; - - base = timer_of_base(&to); - - sched_clock_register(atcpit100_timer_sched_read, 32, - timer_of_rate(&to)); - - ret = clocksource_mmio_init(base + CH1_CNT, - node->name, timer_of_rate(&to), 300, 32, - clocksource_mmio_readl_down); - - if (ret) { - pr_err("Failed to register clocksource\n"); - return ret; - } - - /* clear channel 0 timer0 interrupt */ - atcpit100_timer_clear_interrupt(base); - - clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), - TIMER_SYNC_TICKS, 0xffffffff); - atcpit100_ch0_tmr0_en(base); - atcpit100_ch1_tmr0_en(base); - atcpit100_clocksource_start(base); - atcpit100_clkevt_time_start(base); - - /* Enable channel 0 timer0 interrupt */ - val = readl(base + INT_EN); - writel(val | CH0INT0EN, base + INT_EN); - -#ifdef CONFIG_NDS32 - fill_vdso_need_info(node); -#endif - - return ret; -} - -TIMER_OF_DECLARE(atcpit100, "andestech,atcpit100", atcpit100_timer_init); diff --git a/drivers/cpuidle/cpuidle-qcom-spm.c b/drivers/cpuidle/cpuidle-qcom-spm.c index 01e77913a414..beedf22cbe78 100644 --- a/drivers/cpuidle/cpuidle-qcom-spm.c +++ b/drivers/cpuidle/cpuidle-qcom-spm.c @@ -122,10 +122,6 @@ static int spm_cpuidle_register(struct device *cpuidle_dev, int cpu) if (ret <= 0) return ret ? : -ENODEV; - ret = qcom_scm_set_warm_boot_addr(cpu_resume_arm, cpumask_of(cpu)); - if (ret) - return ret; - return cpuidle_register(&data->cpuidle_driver, NULL); } @@ -136,6 +132,10 @@ static int spm_cpuidle_drv_probe(struct platform_device *pdev) if (!qcom_scm_is_available()) return -EPROBE_DEFER; + ret = qcom_scm_set_warm_boot_addr(cpu_resume_arm); + if (ret) + return dev_err_probe(&pdev->dev, ret, "set warm boot addr failed"); + for_each_possible_cpu(cpu) { ret = spm_cpuidle_register(&pdev->dev, cpu); if (ret && ret != -ENODEV) { @@ -155,6 +155,22 @@ static struct platform_driver spm_cpuidle_driver = { }, }; +static bool __init qcom_spm_find_any_cpu(void) +{ + struct device_node *cpu_node, *saw_node; + + for_each_of_cpu_node(cpu_node) { + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + if (of_device_is_available(saw_node)) { + of_node_put(saw_node); + of_node_put(cpu_node); + return true; + } + of_node_put(saw_node); + } + return false; +} + static int __init qcom_spm_cpuidle_init(void) { struct platform_device *pdev; @@ -164,6 +180,10 @@ static int __init qcom_spm_cpuidle_init(void) if (ret) return ret; + /* Make sure there is actually any CPU managed by the SPM */ + if (!qcom_spm_find_any_cpu()) + return 0; + pdev = platform_device_register_simple("qcom-spm-cpuidle", -1, NULL, 0); if (IS_ERR(pdev)) { diff --git a/drivers/crypto/ixp4xx_crypto.c b/drivers/crypto/ixp4xx_crypto.c index 98730aab287c..d39a386b31ac 100644 --- a/drivers/crypto/ixp4xx_crypto.c +++ b/drivers/crypto/ixp4xx_crypto.c @@ -33,7 +33,6 @@ /* Intermittent includes, delete this after v5.14-rc1 */ #include -#include #define MAX_KEYLEN 32 diff --git a/drivers/firmware/arm_scmi/Kconfig b/drivers/firmware/arm_scmi/Kconfig index 3d7081e84853..7794bd41eaa0 100644 --- a/drivers/firmware/arm_scmi/Kconfig +++ b/drivers/firmware/arm_scmi/Kconfig @@ -54,6 +54,18 @@ config ARM_SCMI_TRANSPORT_MAILBOX If you want the ARM SCMI PROTOCOL stack to include support for a transport based on mailboxes, answer Y. +config ARM_SCMI_TRANSPORT_OPTEE + bool "SCMI transport based on OP-TEE service" + depends on OPTEE=y || OPTEE=ARM_SCMI_PROTOCOL + select ARM_SCMI_HAVE_TRANSPORT + select ARM_SCMI_HAVE_SHMEM + default y + help + This enables the OP-TEE service based transport for SCMI. + + If you want the ARM SCMI PROTOCOL stack to include support for a + transport based on OP-TEE SCMI service, answer Y. + config ARM_SCMI_TRANSPORT_SMC bool "SCMI transport based on SMC" depends on HAVE_ARM_SMCCC_DISCOVERY @@ -66,6 +78,20 @@ config ARM_SCMI_TRANSPORT_SMC If you want the ARM SCMI PROTOCOL stack to include support for a transport based on SMC, answer Y. +config ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE + bool "Enable atomic mode support for SCMI SMC transport" + depends on ARM_SCMI_TRANSPORT_SMC + help + Enable support of atomic operation for SCMI SMC based transport. + + If you want the SCMI SMC based transport to operate in atomic + mode, avoiding any kind of sleeping behaviour for selected + transactions on the TX path, answer Y. + Enabling atomic mode operations allows any SCMI driver using this + transport to optionally ask for atomic SCMI transactions and operate + in atomic context too, at the price of using a number of busy-waiting + primitives all over instead. If unsure say N. + config ARM_SCMI_TRANSPORT_VIRTIO bool "SCMI transport based on VirtIO" depends on VIRTIO=y || VIRTIO=ARM_SCMI_PROTOCOL @@ -77,6 +103,36 @@ config ARM_SCMI_TRANSPORT_VIRTIO If you want the ARM SCMI PROTOCOL stack to include support for a transport based on VirtIO, answer Y. +config ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE + bool "SCMI VirtIO transport Version 1 compliance" + depends on ARM_SCMI_TRANSPORT_VIRTIO + default y + help + This enforces strict compliance with VirtIO Version 1 specification. + + If you want the ARM SCMI VirtIO transport layer to refuse to work + with Legacy VirtIO backends and instead support only VirtIO Version 1 + devices (or above), answer Y. + + If you want instead to support also old Legacy VirtIO backends (like + the ones implemented by kvmtool) and let the core Kernel VirtIO layer + take care of the needed conversions, say N. + +config ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE + bool "Enable atomic mode for SCMI VirtIO transport" + depends on ARM_SCMI_TRANSPORT_VIRTIO + help + Enable support of atomic operation for SCMI VirtIO based transport. + + If you want the SCMI VirtIO based transport to operate in atomic + mode, avoiding any kind of sleeping behaviour for selected + transactions on the TX path, answer Y. + + Enabling atomic mode operations allows any SCMI driver using this + transport to optionally ask for atomic SCMI transactions and operate + in atomic context too, at the price of using a number of busy-waiting + primitives all over instead. If unsure say N. + endif #ARM_SCMI_PROTOCOL config ARM_SCMI_POWER_DOMAIN diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi/Makefile index 1dcf123d64ab..8d4afadda38c 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -6,8 +6,16 @@ scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_MAILBOX) += mailbox.o scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_SMC) += smc.o scmi-transport-$(CONFIG_ARM_SCMI_HAVE_MSG) += msg.o scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_VIRTIO) += virtio.o +scmi-transport-$(CONFIG_ARM_SCMI_TRANSPORT_OPTEE) += optee.o scmi-protocols-y = base.o clock.o perf.o power.o reset.o sensors.o system.o voltage.o scmi-module-objs := $(scmi-bus-y) $(scmi-driver-y) $(scmi-protocols-y) \ $(scmi-transport-y) obj-$(CONFIG_ARM_SCMI_PROTOCOL) += scmi-module.o obj-$(CONFIG_ARM_SCMI_POWER_DOMAIN) += scmi_pm_domain.o + +ifeq ($(CONFIG_THUMB2_KERNEL)$(CONFIG_CC_IS_CLANG),yy) +# The use of R7 in the SMCCC conflicts with the compiler's use of R7 as a frame +# pointer in Thumb2 mode, which is forcibly enabled by Clang when profiling +# hooks are inserted via the -pg switch. +CFLAGS_REMOVE_smc.o += $(CC_FLAGS_FTRACE) +endif diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c index 35b56c8ba0c0..cf6fed6dec77 100644 --- a/drivers/firmware/arm_scmi/clock.c +++ b/drivers/firmware/arm_scmi/clock.c @@ -27,7 +27,8 @@ struct scmi_msg_resp_clock_protocol_attributes { struct scmi_msg_resp_clock_attributes { __le32 attributes; #define CLOCK_ENABLE BIT(0) - u8 name[SCMI_MAX_STR_SIZE]; + u8 name[SCMI_MAX_STR_SIZE]; + __le32 clock_enable_latency; }; struct scmi_clock_set_config { @@ -116,10 +117,15 @@ static int scmi_clock_attributes_get(const struct scmi_protocol_handle *ph, attr = t->rx.buf; ret = ph->xops->do_xfer(ph, t); - if (!ret) + if (!ret) { strlcpy(clk->name, attr->name, SCMI_MAX_STR_SIZE); - else + /* Is optional field clock_enable_latency provided ? */ + if (t->rx.len == sizeof(*attr)) + clk->enable_latency = + le32_to_cpu(attr->clock_enable_latency); + } else { clk->name[0] = '\0'; + } ph->xops->xfer_put(ph, t); return ret; @@ -273,7 +279,7 @@ static int scmi_clock_rate_set(const struct scmi_protocol_handle *ph, static int scmi_clock_config_set(const struct scmi_protocol_handle *ph, u32 clk_id, - u32 config) + u32 config, bool atomic) { int ret; struct scmi_xfer *t; @@ -284,6 +290,8 @@ scmi_clock_config_set(const struct scmi_protocol_handle *ph, u32 clk_id, if (ret) return ret; + t->hdr.poll_completion = atomic; + cfg = t->tx.buf; cfg->id = cpu_to_le32(clk_id); cfg->attributes = cpu_to_le32(config); @@ -296,12 +304,24 @@ scmi_clock_config_set(const struct scmi_protocol_handle *ph, u32 clk_id, static int scmi_clock_enable(const struct scmi_protocol_handle *ph, u32 clk_id) { - return scmi_clock_config_set(ph, clk_id, CLOCK_ENABLE); + return scmi_clock_config_set(ph, clk_id, CLOCK_ENABLE, false); } static int scmi_clock_disable(const struct scmi_protocol_handle *ph, u32 clk_id) { - return scmi_clock_config_set(ph, clk_id, 0); + return scmi_clock_config_set(ph, clk_id, 0, false); +} + +static int scmi_clock_enable_atomic(const struct scmi_protocol_handle *ph, + u32 clk_id) +{ + return scmi_clock_config_set(ph, clk_id, CLOCK_ENABLE, true); +} + +static int scmi_clock_disable_atomic(const struct scmi_protocol_handle *ph, + u32 clk_id) +{ + return scmi_clock_config_set(ph, clk_id, 0, true); } static int scmi_clock_count_get(const struct scmi_protocol_handle *ph) @@ -330,6 +350,8 @@ static const struct scmi_clk_proto_ops clk_proto_ops = { .rate_set = scmi_clock_rate_set, .enable = scmi_clock_enable, .disable = scmi_clock_disable, + .enable_atomic = scmi_clock_enable_atomic, + .disable_atomic = scmi_clock_disable_atomic, }; static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph) diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h index dea1bfbe1052..4fda84bfab42 100644 --- a/drivers/firmware/arm_scmi/common.h +++ b/drivers/firmware/arm_scmi/common.h @@ -339,11 +339,16 @@ void scmi_protocol_release(const struct scmi_handle *handle, u8 protocol_id); * @dev: Reference to device in the SCMI hierarchy corresponding to this * channel * @handle: Pointer to SCMI entity handle + * @no_completion_irq: Flag to indicate that this channel has no completion + * interrupt mechanism for synchronous commands. + * This can be dynamically set by transports at run-time + * inside their provided .chan_setup(). * @transport_info: Transport layer related information */ struct scmi_chan_info { struct device *dev; struct scmi_handle *handle; + bool no_completion_irq; void *transport_info; }; @@ -373,7 +378,8 @@ struct scmi_transport_ops { unsigned int (*get_max_msg)(struct scmi_chan_info *base_cinfo); int (*send_message)(struct scmi_chan_info *cinfo, struct scmi_xfer *xfer); - void (*mark_txdone)(struct scmi_chan_info *cinfo, int ret); + void (*mark_txdone)(struct scmi_chan_info *cinfo, int ret, + struct scmi_xfer *xfer); void (*fetch_response)(struct scmi_chan_info *cinfo, struct scmi_xfer *xfer); void (*fetch_notification)(struct scmi_chan_info *cinfo, @@ -402,6 +408,18 @@ struct scmi_device *scmi_child_dev_find(struct device *parent, * be pending simultaneously in the system. May be overridden by the * get_max_msg op. * @max_msg_size: Maximum size of data per message that can be handled. + * @force_polling: Flag to force this whole transport to use SCMI core polling + * mechanism instead of completion interrupts even if available. + * @sync_cmds_completed_on_ret: Flag to indicate that the transport assures + * synchronous-command messages are atomically + * completed on .send_message: no need to poll + * actively waiting for a response. + * Used by core internally only when polling is + * selected as a waiting for reply method: i.e. + * if a completion irq was found use that anyway. + * @atomic_enabled: Flag to indicate that this transport, which is assured not + * to sleep anywhere on the TX path, can be used in atomic mode + * when requested. */ struct scmi_desc { int (*transport_init)(void); @@ -410,6 +428,9 @@ struct scmi_desc { int max_rx_timeout_ms; int max_msg; int max_msg_size; + const bool force_polling; + const bool sync_cmds_completed_on_ret; + const bool atomic_enabled; }; #ifdef CONFIG_ARM_SCMI_TRANSPORT_MAILBOX @@ -421,6 +442,9 @@ extern const struct scmi_desc scmi_smc_desc; #ifdef CONFIG_ARM_SCMI_TRANSPORT_VIRTIO extern const struct scmi_desc scmi_virtio_desc; #endif +#ifdef CONFIG_ARM_SCMI_TRANSPORT_OPTEE +extern const struct scmi_desc scmi_optee_desc; +#endif void scmi_rx_callback(struct scmi_chan_info *cinfo, u32 msg_hdr, void *priv); void scmi_free_channel(struct scmi_chan_info *cinfo, struct idr *idr, int id); diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index d76bab3aaac4..46118300a4d1 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -131,6 +131,12 @@ struct scmi_protocol_instance { * MAX_PROTOCOLS_IMP elements allocated by the base protocol * @active_protocols: IDR storing device_nodes for protocols actually defined * in the DT and confirmed as implemented by fw. + * @atomic_threshold: Optional system wide DT-configured threshold, expressed + * in microseconds, for atomic operations. + * Only SCMI synchronous commands reported by the platform + * to have an execution latency lesser-equal to the threshold + * should be considered for atomic mode operation: such + * decision is finally left up to the SCMI drivers. * @notify_priv: Pointer to private data structure specific to notifications. * @node: List head * @users: Number of users of this instance @@ -149,6 +155,7 @@ struct scmi_info { struct mutex protocols_mtx; u8 *protocols_imp; struct idr active_protocols; + unsigned int atomic_threshold; void *notify_priv; struct list_head node; int users; @@ -609,6 +616,25 @@ static inline void scmi_clear_channel(struct scmi_info *info, info->desc->ops->clear_channel(cinfo); } +static inline bool is_polling_required(struct scmi_chan_info *cinfo, + struct scmi_info *info) +{ + return cinfo->no_completion_irq || info->desc->force_polling; +} + +static inline bool is_transport_polling_capable(struct scmi_info *info) +{ + return info->desc->ops->poll_done || + info->desc->sync_cmds_completed_on_ret; +} + +static inline bool is_polling_enabled(struct scmi_chan_info *cinfo, + struct scmi_info *info) +{ + return is_polling_required(cinfo, info) && + is_transport_polling_capable(info); +} + static void scmi_handle_notification(struct scmi_chan_info *cinfo, u32 msg_hdr, void *priv) { @@ -629,7 +655,8 @@ static void scmi_handle_notification(struct scmi_chan_info *cinfo, unpack_scmi_header(msg_hdr, &xfer->hdr); if (priv) - xfer->priv = priv; + /* Ensure order between xfer->priv store and following ops */ + smp_store_mb(xfer->priv, priv); info->desc->ops->fetch_notification(cinfo, info->desc->max_msg_size, xfer); scmi_notify(cinfo->handle, xfer->hdr.protocol_id, @@ -661,7 +688,8 @@ static void scmi_handle_response(struct scmi_chan_info *cinfo, xfer->rx.len = info->desc->max_msg_size; if (priv) - xfer->priv = priv; + /* Ensure order between xfer->priv store and following ops */ + smp_store_mb(xfer->priv, priv); info->desc->ops->fetch_response(cinfo, xfer); trace_scmi_rx_done(xfer->transfer_id, xfer->hdr.id, @@ -724,8 +752,6 @@ static void xfer_put(const struct scmi_protocol_handle *ph, __scmi_xfer_put(&info->tx_minfo, xfer); } -#define SCMI_MAX_POLL_TO_NS (100 * NSEC_PER_USEC) - static bool scmi_xfer_done_no_timeout(struct scmi_chan_info *cinfo, struct scmi_xfer *xfer, ktime_t stop) { @@ -740,6 +766,79 @@ static bool scmi_xfer_done_no_timeout(struct scmi_chan_info *cinfo, ktime_after(ktime_get(), stop); } +/** + * scmi_wait_for_message_response - An helper to group all the possible ways of + * waiting for a synchronous message response. + * + * @cinfo: SCMI channel info + * @xfer: Reference to the transfer being waited for. + * + * Chooses waiting strategy (sleep-waiting vs busy-waiting) depending on + * configuration flags like xfer->hdr.poll_completion. + * + * Return: 0 on Success, error otherwise. + */ +static int scmi_wait_for_message_response(struct scmi_chan_info *cinfo, + struct scmi_xfer *xfer) +{ + struct scmi_info *info = handle_to_scmi_info(cinfo->handle); + struct device *dev = info->dev; + int ret = 0, timeout_ms = info->desc->max_rx_timeout_ms; + + trace_scmi_xfer_response_wait(xfer->transfer_id, xfer->hdr.id, + xfer->hdr.protocol_id, xfer->hdr.seq, + timeout_ms, + xfer->hdr.poll_completion); + + if (xfer->hdr.poll_completion) { + /* + * Real polling is needed only if transport has NOT declared + * itself to support synchronous commands replies. + */ + if (!info->desc->sync_cmds_completed_on_ret) { + /* + * Poll on xfer using transport provided .poll_done(); + * assumes no completion interrupt was available. + */ + ktime_t stop = ktime_add_ms(ktime_get(), timeout_ms); + + spin_until_cond(scmi_xfer_done_no_timeout(cinfo, + xfer, stop)); + if (ktime_after(ktime_get(), stop)) { + dev_err(dev, + "timed out in resp(caller: %pS) - polling\n", + (void *)_RET_IP_); + ret = -ETIMEDOUT; + } + } + + if (!ret) { + unsigned long flags; + + /* + * Do not fetch_response if an out-of-order delayed + * response is being processed. + */ + spin_lock_irqsave(&xfer->lock, flags); + if (xfer->state == SCMI_XFER_SENT_OK) { + info->desc->ops->fetch_response(cinfo, xfer); + xfer->state = SCMI_XFER_RESP_OK; + } + spin_unlock_irqrestore(&xfer->lock, flags); + } + } else { + /* And we wait for the response. */ + if (!wait_for_completion_timeout(&xfer->done, + msecs_to_jiffies(timeout_ms))) { + dev_err(dev, "timed out in resp(caller: %pS)\n", + (void *)_RET_IP_); + ret = -ETIMEDOUT; + } + } + + return ret; +} + /** * do_xfer() - Do one transfer * @@ -754,18 +853,26 @@ static int do_xfer(const struct scmi_protocol_handle *ph, struct scmi_xfer *xfer) { int ret; - int timeout; const struct scmi_protocol_instance *pi = ph_to_pi(ph); struct scmi_info *info = handle_to_scmi_info(pi->handle); struct device *dev = info->dev; struct scmi_chan_info *cinfo; - if (xfer->hdr.poll_completion && !info->desc->ops->poll_done) { + /* Check for polling request on custom command xfers at first */ + if (xfer->hdr.poll_completion && !is_transport_polling_capable(info)) { dev_warn_once(dev, "Polling mode is not supported by transport.\n"); return -EINVAL; } + cinfo = idr_find(&info->tx_idr, pi->proto->id); + if (unlikely(!cinfo)) + return -EINVAL; + + /* True ONLY if also supported by transport. */ + if (is_polling_enabled(cinfo, info)) + xfer->hdr.poll_completion = true; + /* * Initialise protocol id now from protocol handle to avoid it being * overridden by mistake (or malice) by the protocol code mangling with @@ -774,10 +881,6 @@ static int do_xfer(const struct scmi_protocol_handle *ph, xfer->hdr.protocol_id = pi->proto->id; reinit_completion(&xfer->done); - cinfo = idr_find(&info->tx_idr, xfer->hdr.protocol_id); - if (unlikely(!cinfo)) - return -EINVAL; - trace_scmi_xfer_begin(xfer->transfer_id, xfer->hdr.id, xfer->hdr.protocol_id, xfer->hdr.seq, xfer->hdr.poll_completion); @@ -798,41 +901,12 @@ static int do_xfer(const struct scmi_protocol_handle *ph, return ret; } - if (xfer->hdr.poll_completion) { - ktime_t stop = ktime_add_ns(ktime_get(), SCMI_MAX_POLL_TO_NS); - - spin_until_cond(scmi_xfer_done_no_timeout(cinfo, xfer, stop)); - if (ktime_before(ktime_get(), stop)) { - unsigned long flags; - - /* - * Do not fetch_response if an out-of-order delayed - * response is being processed. - */ - spin_lock_irqsave(&xfer->lock, flags); - if (xfer->state == SCMI_XFER_SENT_OK) { - info->desc->ops->fetch_response(cinfo, xfer); - xfer->state = SCMI_XFER_RESP_OK; - } - spin_unlock_irqrestore(&xfer->lock, flags); - } else { - ret = -ETIMEDOUT; - } - } else { - /* And we wait for the response. */ - timeout = msecs_to_jiffies(info->desc->max_rx_timeout_ms); - if (!wait_for_completion_timeout(&xfer->done, timeout)) { - dev_err(dev, "timed out in resp(caller: %pS)\n", - (void *)_RET_IP_); - ret = -ETIMEDOUT; - } - } - + ret = scmi_wait_for_message_response(cinfo, xfer); if (!ret && xfer->hdr.status) ret = scmi_to_linux_errno(xfer->hdr.status); if (info->desc->ops->mark_txdone) - info->desc->ops->mark_txdone(cinfo, ret); + info->desc->ops->mark_txdone(cinfo, ret, xfer); trace_scmi_xfer_end(xfer->transfer_id, xfer->hdr.id, xfer->hdr.protocol_id, xfer->hdr.seq, ret); @@ -858,6 +932,20 @@ static void reset_rx_to_maxsz(const struct scmi_protocol_handle *ph, * @ph: Pointer to SCMI protocol handle * @xfer: Transfer to initiate and wait for response * + * Using asynchronous commands in atomic/polling mode should be avoided since + * it could cause long busy-waiting here, so ignore polling for the delayed + * response and WARN if it was requested for this command transaction since + * upper layers should refrain from issuing such kind of requests. + * + * The only other option would have been to refrain from using any asynchronous + * command even if made available, when an atomic transport is detected, and + * instead forcibly use the synchronous version (thing that can be easily + * attained at the protocol layer), but this would also have led to longer + * stalls of the channel for synchronous commands and possibly timeouts. + * (in other words there is usually a good reason if a platform provides an + * asynchronous version of a command and we should prefer to use it...just not + * when using atomic/polling mode) + * * Return: -ETIMEDOUT in case of no delayed response, if transmit error, * return corresponding error, else if all goes well, return 0. */ @@ -869,12 +957,24 @@ static int do_xfer_with_response(const struct scmi_protocol_handle *ph, xfer->async_done = &async_response; + /* + * Delayed responses should not be polled, so an async command should + * not have been used when requiring an atomic/poll context; WARN and + * perform instead a sleeping wait. + * (Note Async + IgnoreDelayedResponses are sent via do_xfer) + */ + WARN_ON_ONCE(xfer->hdr.poll_completion); + ret = do_xfer(ph, xfer); if (!ret) { - if (!wait_for_completion_timeout(xfer->async_done, timeout)) + if (!wait_for_completion_timeout(xfer->async_done, timeout)) { + dev_err(ph->dev, + "timed out in delayed resp(caller: %pS)\n", + (void *)_RET_IP_); ret = -ETIMEDOUT; - else if (xfer->hdr.status) + } else if (xfer->hdr.status) { ret = scmi_to_linux_errno(xfer->hdr.status); + } } xfer->async_done = NULL; @@ -1308,6 +1408,29 @@ static void scmi_devm_protocol_put(struct scmi_device *sdev, u8 protocol_id) WARN_ON(ret); } +/** + * scmi_is_transport_atomic - Method to check if underlying transport for an + * SCMI instance is configured as atomic. + * + * @handle: A reference to the SCMI platform instance. + * @atomic_threshold: An optional return value for the system wide currently + * configured threshold for atomic operations. + * + * Return: True if transport is configured as atomic + */ +static bool scmi_is_transport_atomic(const struct scmi_handle *handle, + unsigned int *atomic_threshold) +{ + bool ret; + struct scmi_info *info = handle_to_scmi_info(handle); + + ret = info->desc->atomic_enabled && is_transport_polling_capable(info); + if (ret && atomic_threshold) + *atomic_threshold = info->atomic_threshold; + + return ret; +} + static inline struct scmi_handle *scmi_handle_get_from_info_unlocked(struct scmi_info *info) { @@ -1499,6 +1622,16 @@ static int scmi_chan_setup(struct scmi_info *info, struct device *dev, if (ret) return ret; + if (tx && is_polling_required(cinfo, info)) { + if (is_transport_polling_capable(info)) + dev_info(dev, + "Enabled polling mode TX channel - prot_id:%d\n", + prot_id); + else + dev_warn(dev, + "Polling mode NOT supported by transport.\n"); + } + idr_alloc: ret = idr_alloc(idr, cinfo, prot_id, prot_id + 1, GFP_KERNEL); if (ret != prot_id) { @@ -1836,6 +1969,14 @@ static int scmi_probe(struct platform_device *pdev) handle->devm_protocol_get = scmi_devm_protocol_get; handle->devm_protocol_put = scmi_devm_protocol_put; + /* System wide atomic threshold for atomic ops .. if any */ + if (!of_property_read_u32(np, "atomic-threshold-us", + &info->atomic_threshold)) + dev_info(dev, + "SCMI System wide atomic threshold set to %d us\n", + info->atomic_threshold); + handle->is_transport_atomic = scmi_is_transport_atomic; + if (desc->ops->link_supplier) { ret = desc->ops->link_supplier(dev); if (ret) @@ -1853,6 +1994,10 @@ static int scmi_probe(struct platform_device *pdev) if (scmi_notification_init(handle)) dev_err(dev, "SCMI Notifications NOT available.\n"); + if (info->desc->atomic_enabled && !is_transport_polling_capable(info)) + dev_err(dev, + "Transport is not polling capable. Atomic mode not supported.\n"); + /* * Trigger SCMI Base protocol initialization. * It's mandatory and won't be ever released/deinit until the @@ -1994,6 +2139,9 @@ static const struct of_device_id scmi_of_match[] = { #ifdef CONFIG_ARM_SCMI_TRANSPORT_MAILBOX { .compatible = "arm,scmi", .data = &scmi_mailbox_desc }, #endif +#ifdef CONFIG_ARM_SCMI_TRANSPORT_OPTEE + { .compatible = "linaro,scmi-optee", .data = &scmi_optee_desc }, +#endif #ifdef CONFIG_ARM_SCMI_TRANSPORT_SMC { .compatible = "arm,scmi-smc", .data = &scmi_smc_desc}, #endif diff --git a/drivers/firmware/arm_scmi/mailbox.c b/drivers/firmware/arm_scmi/mailbox.c index e09eb12bf421..08ff4d110beb 100644 --- a/drivers/firmware/arm_scmi/mailbox.c +++ b/drivers/firmware/arm_scmi/mailbox.c @@ -140,7 +140,8 @@ static int mailbox_send_message(struct scmi_chan_info *cinfo, return ret; } -static void mailbox_mark_txdone(struct scmi_chan_info *cinfo, int ret) +static void mailbox_mark_txdone(struct scmi_chan_info *cinfo, int ret, + struct scmi_xfer *__unused) { struct scmi_mailbox *smbox = cinfo->transport_info; diff --git a/drivers/firmware/arm_scmi/optee.c b/drivers/firmware/arm_scmi/optee.c new file mode 100644 index 000000000000..734f1eeee161 --- /dev/null +++ b/drivers/firmware/arm_scmi/optee.c @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019-2021 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" + +#define SCMI_OPTEE_MAX_MSG_SIZE 128 + +enum scmi_optee_pta_cmd { + /* + * PTA_SCMI_CMD_CAPABILITIES - Get channel capabilities + * + * [out] value[0].a: Capability bit mask (enum pta_scmi_caps) + * [out] value[0].b: Extended capabilities or 0 + */ + PTA_SCMI_CMD_CAPABILITIES = 0, + + /* + * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL - Process SCMI message in SMT buffer + * + * [in] value[0].a: Channel handle + * + * Shared memory used for SCMI message/response exhange is expected + * already identified and bound to channel handle in both SCMI agent + * and SCMI server (OP-TEE) parts. + * The memory uses SMT header to carry SCMI meta-data (protocol ID and + * protocol message ID). + */ + PTA_SCMI_CMD_PROCESS_SMT_CHANNEL = 1, + + /* + * PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE - Process SMT/SCMI message + * + * [in] value[0].a: Channel handle + * [in/out] memref[1]: Message/response buffer (SMT and SCMI payload) + * + * Shared memory used for SCMI message/response is a SMT buffer + * referenced by param[1]. It shall be 128 bytes large to fit response + * payload whatever message playload size. + * The memory uses SMT header to carry SCMI meta-data (protocol ID and + * protocol message ID). + */ + PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE = 2, + + /* + * PTA_SCMI_CMD_GET_CHANNEL - Get channel handle + * + * SCMI shm information are 0 if agent expects to use OP-TEE regular SHM + * + * [in] value[0].a: Channel identifier + * [out] value[0].a: Returned channel handle + * [in] value[0].b: Requested capabilities mask (enum pta_scmi_caps) + */ + PTA_SCMI_CMD_GET_CHANNEL = 3, +}; + +/* + * OP-TEE SCMI service capabilities bit flags (32bit) + * + * PTA_SCMI_CAPS_SMT_HEADER + * When set, OP-TEE supports command using SMT header protocol (SCMI shmem) in + * shared memory buffers to carry SCMI protocol synchronisation information. + */ +#define PTA_SCMI_CAPS_NONE 0 +#define PTA_SCMI_CAPS_SMT_HEADER BIT(0) + +/** + * struct scmi_optee_channel - Description of an OP-TEE SCMI channel + * + * @channel_id: OP-TEE channel ID used for this transport + * @tee_session: TEE session identifier + * @caps: OP-TEE SCMI channel capabilities + * @mu: Mutex protection on channel access + * @cinfo: SCMI channel information + * @shmem: Virtual base address of the shared memory + * @tee_shm: Reference to TEE shared memory or NULL if using static shmem + * @link: Reference in agent's channel list + */ +struct scmi_optee_channel { + u32 channel_id; + u32 tee_session; + u32 caps; + struct mutex mu; + struct scmi_chan_info *cinfo; + struct scmi_shared_mem __iomem *shmem; + struct tee_shm *tee_shm; + struct list_head link; +}; + +/** + * struct scmi_optee_agent - OP-TEE transport private data + * + * @dev: Device used for communication with TEE + * @tee_ctx: TEE context used for communication + * @caps: Supported channel capabilities + * @mu: Mutex for protection of @channel_list + * @channel_list: List of all created channels for the agent + */ +struct scmi_optee_agent { + struct device *dev; + struct tee_context *tee_ctx; + u32 caps; + struct mutex mu; + struct list_head channel_list; +}; + +/* There can be only 1 SCMI service in OP-TEE we connect to */ +static struct scmi_optee_agent *scmi_optee_private; + +/* Forward reference to scmi_optee transport initialization */ +static int scmi_optee_init(void); + +/* Open a session toward SCMI OP-TEE service with REE_KERNEL identity */ +static int open_session(struct scmi_optee_agent *agent, u32 *tee_session) +{ + struct device *dev = agent->dev; + struct tee_client_device *scmi_pta = to_tee_client_device(dev); + struct tee_ioctl_open_session_arg arg = { }; + int ret; + + memcpy(arg.uuid, scmi_pta->id.uuid.b, TEE_IOCTL_UUID_LEN); + arg.clnt_login = TEE_IOCTL_LOGIN_REE_KERNEL; + + ret = tee_client_open_session(agent->tee_ctx, &arg, NULL); + if (ret < 0 || arg.ret) { + dev_err(dev, "Can't open tee session: %d / %#x\n", ret, arg.ret); + return -EOPNOTSUPP; + } + + *tee_session = arg.session; + + return 0; +} + +static void close_session(struct scmi_optee_agent *agent, u32 tee_session) +{ + tee_client_close_session(agent->tee_ctx, tee_session); +} + +static int get_capabilities(struct scmi_optee_agent *agent) +{ + struct tee_ioctl_invoke_arg arg = { }; + struct tee_param param[1] = { }; + u32 caps; + u32 tee_session; + int ret; + + ret = open_session(agent, &tee_session); + if (ret) + return ret; + + arg.func = PTA_SCMI_CMD_CAPABILITIES; + arg.session = tee_session; + arg.num_params = 1; + + param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_OUTPUT; + + ret = tee_client_invoke_func(agent->tee_ctx, &arg, param); + + close_session(agent, tee_session); + + if (ret < 0 || arg.ret) { + dev_err(agent->dev, "Can't get capabilities: %d / %#x\n", ret, arg.ret); + return -EOPNOTSUPP; + } + + caps = param[0].u.value.a; + + if (!(caps & PTA_SCMI_CAPS_SMT_HEADER)) { + dev_err(agent->dev, "OP-TEE SCMI PTA doesn't support SMT\n"); + return -EOPNOTSUPP; + } + + agent->caps = caps; + + return 0; +} + +static int get_channel(struct scmi_optee_channel *channel) +{ + struct device *dev = scmi_optee_private->dev; + struct tee_ioctl_invoke_arg arg = { }; + struct tee_param param[1] = { }; + unsigned int caps = PTA_SCMI_CAPS_SMT_HEADER; + int ret; + + arg.func = PTA_SCMI_CMD_GET_CHANNEL; + arg.session = channel->tee_session; + arg.num_params = 1; + + param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INOUT; + param[0].u.value.a = channel->channel_id; + param[0].u.value.b = caps; + + ret = tee_client_invoke_func(scmi_optee_private->tee_ctx, &arg, param); + + if (ret || arg.ret) { + dev_err(dev, "Can't get channel with caps %#x: %d / %#x\n", caps, ret, arg.ret); + return -EOPNOTSUPP; + } + + /* From now on use channel identifer provided by OP-TEE SCMI service */ + channel->channel_id = param[0].u.value.a; + channel->caps = caps; + + return 0; +} + +static int invoke_process_smt_channel(struct scmi_optee_channel *channel) +{ + struct tee_ioctl_invoke_arg arg = { }; + struct tee_param param[2] = { }; + int ret; + + arg.session = channel->tee_session; + param[0].attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT; + param[0].u.value.a = channel->channel_id; + + if (channel->tee_shm) { + param[1].attr = TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT; + param[1].u.memref.shm = channel->tee_shm; + param[1].u.memref.size = SCMI_OPTEE_MAX_MSG_SIZE; + arg.num_params = 2; + arg.func = PTA_SCMI_CMD_PROCESS_SMT_CHANNEL_MESSAGE; + } else { + arg.num_params = 1; + arg.func = PTA_SCMI_CMD_PROCESS_SMT_CHANNEL; + } + + ret = tee_client_invoke_func(scmi_optee_private->tee_ctx, &arg, param); + if (ret < 0 || arg.ret) { + dev_err(scmi_optee_private->dev, "Can't invoke channel %u: %d / %#x\n", + channel->channel_id, ret, arg.ret); + return -EIO; + } + + return 0; +} + +static int scmi_optee_link_supplier(struct device *dev) +{ + if (!scmi_optee_private) { + if (scmi_optee_init()) + dev_dbg(dev, "Optee bus not yet ready\n"); + + /* Wait for optee bus */ + return -EPROBE_DEFER; + } + + if (!device_link_add(dev, scmi_optee_private->dev, DL_FLAG_AUTOREMOVE_CONSUMER)) { + dev_err(dev, "Adding link to supplier optee device failed\n"); + return -ECANCELED; + } + + return 0; +} + +static bool scmi_optee_chan_available(struct device *dev, int idx) +{ + u32 channel_id; + + return !of_property_read_u32_index(dev->of_node, "linaro,optee-channel-id", + idx, &channel_id); +} + +static void scmi_optee_clear_channel(struct scmi_chan_info *cinfo) +{ + struct scmi_optee_channel *channel = cinfo->transport_info; + + shmem_clear_channel(channel->shmem); +} + +static int setup_static_shmem(struct device *dev, struct scmi_chan_info *cinfo, + struct scmi_optee_channel *channel) +{ + struct device_node *np; + resource_size_t size; + struct resource res; + int ret; + + np = of_parse_phandle(cinfo->dev->of_node, "shmem", 0); + if (!of_device_is_compatible(np, "arm,scmi-shmem")) { + ret = -ENXIO; + goto out; + } + + ret = of_address_to_resource(np, 0, &res); + if (ret) { + dev_err(dev, "Failed to get SCMI Tx shared memory\n"); + goto out; + } + + size = resource_size(&res); + + channel->shmem = devm_ioremap(dev, res.start, size); + if (!channel->shmem) { + dev_err(dev, "Failed to ioremap SCMI Tx shared memory\n"); + ret = -EADDRNOTAVAIL; + goto out; + } + + ret = 0; + +out: + of_node_put(np); + + return ret; +} + +static int setup_shmem(struct device *dev, struct scmi_chan_info *cinfo, + struct scmi_optee_channel *channel) +{ + if (of_find_property(cinfo->dev->of_node, "shmem", NULL)) + return setup_static_shmem(dev, cinfo, channel); + else + return -ENOMEM; +} + +static int scmi_optee_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, bool tx) +{ + struct scmi_optee_channel *channel; + uint32_t channel_id; + int ret; + + if (!tx) + return -ENODEV; + + channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL); + if (!channel) + return -ENOMEM; + + ret = of_property_read_u32_index(cinfo->dev->of_node, "linaro,optee-channel-id", + 0, &channel_id); + if (ret) + return ret; + + cinfo->transport_info = channel; + channel->cinfo = cinfo; + channel->channel_id = channel_id; + mutex_init(&channel->mu); + + ret = setup_shmem(dev, cinfo, channel); + if (ret) + return ret; + + ret = open_session(scmi_optee_private, &channel->tee_session); + if (ret) + goto err_free_shm; + + ret = get_channel(channel); + if (ret) + goto err_close_sess; + + /* Enable polling */ + cinfo->no_completion_irq = true; + + mutex_lock(&scmi_optee_private->mu); + list_add(&channel->link, &scmi_optee_private->channel_list); + mutex_unlock(&scmi_optee_private->mu); + + return 0; + +err_close_sess: + close_session(scmi_optee_private, channel->tee_session); +err_free_shm: + if (channel->tee_shm) + tee_shm_free(channel->tee_shm); + + return ret; +} + +static int scmi_optee_chan_free(int id, void *p, void *data) +{ + struct scmi_chan_info *cinfo = p; + struct scmi_optee_channel *channel = cinfo->transport_info; + + mutex_lock(&scmi_optee_private->mu); + list_del(&channel->link); + mutex_unlock(&scmi_optee_private->mu); + + close_session(scmi_optee_private, channel->tee_session); + + if (channel->tee_shm) { + tee_shm_free(channel->tee_shm); + channel->tee_shm = NULL; + } + + cinfo->transport_info = NULL; + channel->cinfo = NULL; + + scmi_free_channel(cinfo, data, id); + + return 0; +} + +static struct scmi_shared_mem *get_channel_shm(struct scmi_optee_channel *chan, + struct scmi_xfer *xfer) +{ + if (!chan) + return NULL; + + return chan->shmem; +} + + +static int scmi_optee_send_message(struct scmi_chan_info *cinfo, + struct scmi_xfer *xfer) +{ + struct scmi_optee_channel *channel = cinfo->transport_info; + struct scmi_shared_mem *shmem = get_channel_shm(channel, xfer); + int ret; + + mutex_lock(&channel->mu); + shmem_tx_prepare(shmem, xfer); + + ret = invoke_process_smt_channel(channel); + if (ret) + mutex_unlock(&channel->mu); + + return ret; +} + +static void scmi_optee_fetch_response(struct scmi_chan_info *cinfo, + struct scmi_xfer *xfer) +{ + struct scmi_optee_channel *channel = cinfo->transport_info; + struct scmi_shared_mem *shmem = get_channel_shm(channel, xfer); + + shmem_fetch_response(shmem, xfer); +} + +static void scmi_optee_mark_txdone(struct scmi_chan_info *cinfo, int ret, + struct scmi_xfer *__unused) +{ + struct scmi_optee_channel *channel = cinfo->transport_info; + + mutex_unlock(&channel->mu); +} + +static struct scmi_transport_ops scmi_optee_ops = { + .link_supplier = scmi_optee_link_supplier, + .chan_available = scmi_optee_chan_available, + .chan_setup = scmi_optee_chan_setup, + .chan_free = scmi_optee_chan_free, + .send_message = scmi_optee_send_message, + .mark_txdone = scmi_optee_mark_txdone, + .fetch_response = scmi_optee_fetch_response, + .clear_channel = scmi_optee_clear_channel, +}; + +static int scmi_optee_ctx_match(struct tee_ioctl_version_data *ver, const void *data) +{ + return ver->impl_id == TEE_IMPL_ID_OPTEE; +} + +static int scmi_optee_service_probe(struct device *dev) +{ + struct scmi_optee_agent *agent; + struct tee_context *tee_ctx; + int ret; + + /* Only one SCMI OP-TEE device allowed */ + if (scmi_optee_private) { + dev_err(dev, "An SCMI OP-TEE device was already initialized: only one allowed\n"); + return -EBUSY; + } + + tee_ctx = tee_client_open_context(NULL, scmi_optee_ctx_match, NULL, NULL); + if (IS_ERR(tee_ctx)) + return -ENODEV; + + agent = devm_kzalloc(dev, sizeof(*agent), GFP_KERNEL); + if (!agent) { + ret = -ENOMEM; + goto err; + } + + agent->dev = dev; + agent->tee_ctx = tee_ctx; + INIT_LIST_HEAD(&agent->channel_list); + mutex_init(&agent->mu); + + ret = get_capabilities(agent); + if (ret) + goto err; + + /* Ensure agent resources are all visible before scmi_optee_private is */ + smp_mb(); + scmi_optee_private = agent; + + return 0; + +err: + tee_client_close_context(tee_ctx); + + return ret; +} + +static int scmi_optee_service_remove(struct device *dev) +{ + struct scmi_optee_agent *agent = scmi_optee_private; + + if (!scmi_optee_private) + return -EINVAL; + + if (!list_empty(&scmi_optee_private->channel_list)) + return -EBUSY; + + /* Ensure cleared reference is visible before resources are released */ + smp_store_mb(scmi_optee_private, NULL); + + tee_client_close_context(agent->tee_ctx); + + return 0; +} + +static const struct tee_client_device_id scmi_optee_service_id[] = { + { + UUID_INIT(0xa8cfe406, 0xd4f5, 0x4a2e, + 0x9f, 0x8d, 0xa2, 0x5d, 0xc7, 0x54, 0xc0, 0x99) + }, + { } +}; + +MODULE_DEVICE_TABLE(tee, scmi_optee_service_id); + +static struct tee_client_driver scmi_optee_driver = { + .id_table = scmi_optee_service_id, + .driver = { + .name = "scmi-optee", + .bus = &tee_bus_type, + .probe = scmi_optee_service_probe, + .remove = scmi_optee_service_remove, + }, +}; + +static int scmi_optee_init(void) +{ + return driver_register(&scmi_optee_driver.driver); +} + +static void scmi_optee_exit(void) +{ + if (scmi_optee_private) + driver_unregister(&scmi_optee_driver.driver); +} + +const struct scmi_desc scmi_optee_desc = { + .transport_exit = scmi_optee_exit, + .ops = &scmi_optee_ops, + .max_rx_timeout_ms = 30, + .max_msg = 20, + .max_msg_size = SCMI_OPTEE_MAX_MSG_SIZE, + .sync_cmds_completed_on_ret = true, +}; diff --git a/drivers/firmware/arm_scmi/smc.c b/drivers/firmware/arm_scmi/smc.c index 4effecc3bb46..745acfdd0b3d 100644 --- a/drivers/firmware/arm_scmi/smc.c +++ b/drivers/firmware/arm_scmi/smc.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -14,6 +15,7 @@ #include #include #include +#include #include #include "common.h" @@ -23,26 +25,29 @@ * * @cinfo: SCMI channel info * @shmem: Transmit/Receive shared memory area - * @shmem_lock: Lock to protect access to Tx/Rx shared memory area + * @shmem_lock: Lock to protect access to Tx/Rx shared memory area. + * Used when NOT operating in atomic mode. + * @inflight: Atomic flag to protect access to Tx/Rx shared memory area. + * Used when operating in atomic mode. * @func_id: smc/hvc call function id - * @irq: Optional; employed when platforms indicates msg completion by intr. - * @tx_complete: Optional, employed only when irq is valid. */ struct scmi_smc { struct scmi_chan_info *cinfo; struct scmi_shared_mem __iomem *shmem; + /* Protect access to shmem area */ struct mutex shmem_lock; +#define INFLIGHT_NONE MSG_TOKEN_MAX + atomic_t inflight; u32 func_id; - int irq; - struct completion tx_complete; }; static irqreturn_t smc_msg_done_isr(int irq, void *data) { struct scmi_smc *scmi_info = data; - complete(&scmi_info->tx_complete); + scmi_rx_callback(scmi_info->cinfo, + shmem_read_header(scmi_info->shmem), NULL); return IRQ_HANDLED; } @@ -57,6 +62,41 @@ static bool smc_chan_available(struct device *dev, int idx) return true; } +static inline void smc_channel_lock_init(struct scmi_smc *scmi_info) +{ + if (IS_ENABLED(CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE)) + atomic_set(&scmi_info->inflight, INFLIGHT_NONE); + else + mutex_init(&scmi_info->shmem_lock); +} + +static bool smc_xfer_inflight(struct scmi_xfer *xfer, atomic_t *inflight) +{ + int ret; + + ret = atomic_cmpxchg(inflight, INFLIGHT_NONE, xfer->hdr.seq); + + return ret == INFLIGHT_NONE; +} + +static inline void +smc_channel_lock_acquire(struct scmi_smc *scmi_info, + struct scmi_xfer *xfer __maybe_unused) +{ + if (IS_ENABLED(CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE)) + spin_until_cond(smc_xfer_inflight(xfer, &scmi_info->inflight)); + else + mutex_lock(&scmi_info->shmem_lock); +} + +static inline void smc_channel_lock_release(struct scmi_smc *scmi_info) +{ + if (IS_ENABLED(CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE)) + atomic_set(&scmi_info->inflight, INFLIGHT_NONE); + else + mutex_unlock(&scmi_info->shmem_lock); +} + static int smc_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, bool tx) { @@ -111,13 +151,13 @@ static int smc_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, dev_err(dev, "failed to setup SCMI smc irq\n"); return ret; } - init_completion(&scmi_info->tx_complete); - scmi_info->irq = irq; + } else { + cinfo->no_completion_irq = true; } scmi_info->func_id = func_id; scmi_info->cinfo = cinfo; - mutex_init(&scmi_info->shmem_lock); + smc_channel_lock_init(scmi_info); cinfo->transport_info = scmi_info; return 0; @@ -142,26 +182,22 @@ static int smc_send_message(struct scmi_chan_info *cinfo, struct scmi_smc *scmi_info = cinfo->transport_info; struct arm_smccc_res res; - mutex_lock(&scmi_info->shmem_lock); + /* + * Channel will be released only once response has been + * surely fully retrieved, so after .mark_txdone() + */ + smc_channel_lock_acquire(scmi_info, xfer); shmem_tx_prepare(scmi_info->shmem, xfer); - if (scmi_info->irq) - reinit_completion(&scmi_info->tx_complete); - arm_smccc_1_1_invoke(scmi_info->func_id, 0, 0, 0, 0, 0, 0, 0, &res); - if (scmi_info->irq) - wait_for_completion(&scmi_info->tx_complete); - - scmi_rx_callback(scmi_info->cinfo, - shmem_read_header(scmi_info->shmem), NULL); - - mutex_unlock(&scmi_info->shmem_lock); - /* Only SMCCC_RET_NOT_SUPPORTED is valid error code */ - if (res.a0) + if (res.a0) { + smc_channel_lock_release(scmi_info); return -EOPNOTSUPP; + } + return 0; } @@ -173,12 +209,12 @@ static void smc_fetch_response(struct scmi_chan_info *cinfo, shmem_fetch_response(scmi_info->shmem, xfer); } -static bool -smc_poll_done(struct scmi_chan_info *cinfo, struct scmi_xfer *xfer) +static void smc_mark_txdone(struct scmi_chan_info *cinfo, int ret, + struct scmi_xfer *__unused) { struct scmi_smc *scmi_info = cinfo->transport_info; - return shmem_poll_done(scmi_info->shmem, xfer); + smc_channel_lock_release(scmi_info); } static const struct scmi_transport_ops scmi_smc_ops = { @@ -186,8 +222,8 @@ static const struct scmi_transport_ops scmi_smc_ops = { .chan_setup = smc_chan_setup, .chan_free = smc_chan_free, .send_message = smc_send_message, + .mark_txdone = smc_mark_txdone, .fetch_response = smc_fetch_response, - .poll_done = smc_poll_done, }; const struct scmi_desc scmi_smc_desc = { @@ -195,4 +231,14 @@ const struct scmi_desc scmi_smc_desc = { .max_rx_timeout_ms = 30, .max_msg = 20, .max_msg_size = 128, + /* + * Setting .sync_cmds_atomic_replies to true for SMC assumes that, + * once the SMC instruction has completed successfully, the issued + * SCMI command would have been already fully processed by the SCMI + * platform firmware and so any possible response value expected + * for the issued command will be immmediately ready to be fetched + * from the shared memory area. + */ + .sync_cmds_completed_on_ret = true, + .atomic_enabled = IS_ENABLED(CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE), }; diff --git a/drivers/firmware/arm_scmi/virtio.c b/drivers/firmware/arm_scmi/virtio.c index eefcc4146749..14709dbc96a1 100644 --- a/drivers/firmware/arm_scmi/virtio.c +++ b/drivers/firmware/arm_scmi/virtio.c @@ -3,8 +3,8 @@ * Virtio Transport driver for Arm System Control and Management Interface * (SCMI). * - * Copyright (C) 2020-2021 OpenSynergy. - * Copyright (C) 2021 ARM Ltd. + * Copyright (C) 2020-2022 OpenSynergy. + * Copyright (C) 2021-2022 ARM Ltd. */ /** @@ -17,7 +17,9 @@ * virtqueue. Access to each virtqueue is protected by spinlocks. */ +#include #include +#include #include #include #include @@ -27,6 +29,7 @@ #include "common.h" +#define VIRTIO_MAX_RX_TIMEOUT_MS 60000 #define VIRTIO_SCMI_MAX_MSG_SIZE 128 /* Value may be increased. */ #define VIRTIO_SCMI_MAX_PDU_SIZE \ (VIRTIO_SCMI_MAX_MSG_SIZE + SCMI_MSG_MAX_PROT_OVERHEAD) @@ -37,25 +40,46 @@ * * @vqueue: Associated virtqueue * @cinfo: SCMI Tx or Rx channel + * @free_lock: Protects access to the @free_list. * @free_list: List of unused scmi_vio_msg, maintained for Tx channels only + * @deferred_tx_work: Worker for TX deferred replies processing + * @deferred_tx_wq: Workqueue for TX deferred replies + * @pending_lock: Protects access to the @pending_cmds_list. + * @pending_cmds_list: List of pre-fetched commands queueud for later processing * @is_rx: Whether channel is an Rx channel - * @ready: Whether transport user is ready to hear about channel * @max_msg: Maximum number of pending messages for this channel. - * @lock: Protects access to all members except ready. - * @ready_lock: Protects access to ready. If required, it must be taken before - * lock. + * @lock: Protects access to all members except users, free_list and + * pending_cmds_list. + * @shutdown_done: A reference to a completion used when freeing this channel. + * @users: A reference count to currently active users of this channel. */ struct scmi_vio_channel { struct virtqueue *vqueue; struct scmi_chan_info *cinfo; + /* lock to protect access to the free list. */ + spinlock_t free_lock; struct list_head free_list; + /* lock to protect access to the pending list. */ + spinlock_t pending_lock; + struct list_head pending_cmds_list; + struct work_struct deferred_tx_work; + struct workqueue_struct *deferred_tx_wq; bool is_rx; - bool ready; unsigned int max_msg; - /* lock to protect access to all members except ready. */ + /* + * Lock to protect access to all members except users, free_list and + * pending_cmds_list + */ spinlock_t lock; - /* lock to rotects access to ready flag. */ - spinlock_t ready_lock; + struct completion *shutdown_done; + refcount_t users; +}; + +enum poll_states { + VIO_MSG_NOT_POLLED, + VIO_MSG_POLL_TIMEOUT, + VIO_MSG_POLLING, + VIO_MSG_POLL_DONE, }; /** @@ -65,29 +89,154 @@ struct scmi_vio_channel { * @input: SDU used for (delayed) responses and notifications * @list: List which scmi_vio_msg may be part of * @rx_len: Input SDU size in bytes, once input has been received + * @poll_idx: Last used index registered for polling purposes if this message + * transaction reply was configured for polling. + * @poll_status: Polling state for this message. + * @poll_lock: A lock to protect @poll_status + * @users: A reference count to track this message users and avoid premature + * freeing (and reuse) when polling and IRQ execution paths interleave. */ struct scmi_vio_msg { struct scmi_msg_payld *request; struct scmi_msg_payld *input; struct list_head list; unsigned int rx_len; + unsigned int poll_idx; + enum poll_states poll_status; + /* Lock to protect access to poll_status */ + spinlock_t poll_lock; + refcount_t users; }; /* Only one SCMI VirtIO device can possibly exist */ static struct virtio_device *scmi_vdev; +static void scmi_vio_channel_ready(struct scmi_vio_channel *vioch, + struct scmi_chan_info *cinfo) +{ + unsigned long flags; + + spin_lock_irqsave(&vioch->lock, flags); + cinfo->transport_info = vioch; + /* Indirectly setting channel not available any more */ + vioch->cinfo = cinfo; + spin_unlock_irqrestore(&vioch->lock, flags); + + refcount_set(&vioch->users, 1); +} + +static inline bool scmi_vio_channel_acquire(struct scmi_vio_channel *vioch) +{ + return refcount_inc_not_zero(&vioch->users); +} + +static inline void scmi_vio_channel_release(struct scmi_vio_channel *vioch) +{ + if (refcount_dec_and_test(&vioch->users)) { + unsigned long flags; + + spin_lock_irqsave(&vioch->lock, flags); + if (vioch->shutdown_done) { + vioch->cinfo = NULL; + complete(vioch->shutdown_done); + } + spin_unlock_irqrestore(&vioch->lock, flags); + } +} + +static void scmi_vio_channel_cleanup_sync(struct scmi_vio_channel *vioch) +{ + unsigned long flags; + DECLARE_COMPLETION_ONSTACK(vioch_shutdown_done); + void *deferred_wq = NULL; + + /* + * Prepare to wait for the last release if not already released + * or in progress. + */ + spin_lock_irqsave(&vioch->lock, flags); + if (!vioch->cinfo || vioch->shutdown_done) { + spin_unlock_irqrestore(&vioch->lock, flags); + return; + } + + vioch->shutdown_done = &vioch_shutdown_done; + virtio_break_device(vioch->vqueue->vdev); + if (!vioch->is_rx && vioch->deferred_tx_wq) { + deferred_wq = vioch->deferred_tx_wq; + /* Cannot be kicked anymore after this...*/ + vioch->deferred_tx_wq = NULL; + } + spin_unlock_irqrestore(&vioch->lock, flags); + + if (deferred_wq) + destroy_workqueue(deferred_wq); + + scmi_vio_channel_release(vioch); + + /* Let any possibly concurrent RX path release the channel */ + wait_for_completion(vioch->shutdown_done); +} + +/* Assumes to be called with vio channel acquired already */ +static struct scmi_vio_msg * +scmi_virtio_get_free_msg(struct scmi_vio_channel *vioch) +{ + unsigned long flags; + struct scmi_vio_msg *msg; + + spin_lock_irqsave(&vioch->free_lock, flags); + if (list_empty(&vioch->free_list)) { + spin_unlock_irqrestore(&vioch->free_lock, flags); + return NULL; + } + + msg = list_first_entry(&vioch->free_list, typeof(*msg), list); + list_del_init(&msg->list); + spin_unlock_irqrestore(&vioch->free_lock, flags); + + /* Still no users, no need to acquire poll_lock */ + msg->poll_status = VIO_MSG_NOT_POLLED; + refcount_set(&msg->users, 1); + + return msg; +} + +static inline bool scmi_vio_msg_acquire(struct scmi_vio_msg *msg) +{ + return refcount_inc_not_zero(&msg->users); +} + +/* Assumes to be called with vio channel acquired already */ +static inline bool scmi_vio_msg_release(struct scmi_vio_channel *vioch, + struct scmi_vio_msg *msg) +{ + bool ret; + + ret = refcount_dec_and_test(&msg->users); + if (ret) { + unsigned long flags; + + spin_lock_irqsave(&vioch->free_lock, flags); + list_add_tail(&msg->list, &vioch->free_list); + spin_unlock_irqrestore(&vioch->free_lock, flags); + } + + return ret; +} + static bool scmi_vio_have_vq_rx(struct virtio_device *vdev) { return virtio_has_feature(vdev, VIRTIO_SCMI_F_P2A_CHANNELS); } static int scmi_vio_feed_vq_rx(struct scmi_vio_channel *vioch, - struct scmi_vio_msg *msg, - struct device *dev) + struct scmi_vio_msg *msg) { struct scatterlist sg_in; int rc; unsigned long flags; + struct device *dev = &vioch->vqueue->vdev->dev; sg_init_one(&sg_in, msg->input, VIRTIO_SCMI_MAX_PDU_SIZE); @@ -95,7 +244,7 @@ static int scmi_vio_feed_vq_rx(struct scmi_vio_channel *vioch, rc = virtqueue_add_inbuf(vioch->vqueue, &sg_in, 1, msg, GFP_ATOMIC); if (rc) - dev_err_once(dev, "failed to add to virtqueue (%d)\n", rc); + dev_err(dev, "failed to add to RX virtqueue (%d)\n", rc); else virtqueue_kick(vioch->vqueue); @@ -104,22 +253,22 @@ static int scmi_vio_feed_vq_rx(struct scmi_vio_channel *vioch, return rc; } +/* + * Assume to be called with channel already acquired or not ready at all; + * vioch->lock MUST NOT have been already acquired. + */ static void scmi_finalize_message(struct scmi_vio_channel *vioch, struct scmi_vio_msg *msg) { - if (vioch->is_rx) { - scmi_vio_feed_vq_rx(vioch, msg, vioch->cinfo->dev); - } else { - /* Here IRQs are assumed to be already disabled by the caller */ - spin_lock(&vioch->lock); - list_add(&msg->list, &vioch->free_list); - spin_unlock(&vioch->lock); - } + if (vioch->is_rx) + scmi_vio_feed_vq_rx(vioch, msg); + else + scmi_vio_msg_release(vioch, msg); } static void scmi_vio_complete_cb(struct virtqueue *vqueue) { - unsigned long ready_flags; + unsigned long flags; unsigned int length; struct scmi_vio_channel *vioch; struct scmi_vio_msg *msg; @@ -130,27 +279,25 @@ static void scmi_vio_complete_cb(struct virtqueue *vqueue) vioch = &((struct scmi_vio_channel *)vqueue->vdev->priv)[vqueue->index]; for (;;) { - spin_lock_irqsave(&vioch->ready_lock, ready_flags); + if (!scmi_vio_channel_acquire(vioch)) + return; - if (!vioch->ready) { - if (!cb_enabled) - (void)virtqueue_enable_cb(vqueue); - goto unlock_ready_out; - } - - /* IRQs already disabled here no need to irqsave */ - spin_lock(&vioch->lock); + spin_lock_irqsave(&vioch->lock, flags); if (cb_enabled) { virtqueue_disable_cb(vqueue); cb_enabled = false; } + msg = virtqueue_get_buf(vqueue, &length); if (!msg) { - if (virtqueue_enable_cb(vqueue)) - goto unlock_out; + if (virtqueue_enable_cb(vqueue)) { + spin_unlock_irqrestore(&vioch->lock, flags); + scmi_vio_channel_release(vioch); + return; + } cb_enabled = true; } - spin_unlock(&vioch->lock); + spin_unlock_irqrestore(&vioch->lock, flags); if (msg) { msg->rx_len = length; @@ -161,19 +308,57 @@ static void scmi_vio_complete_cb(struct virtqueue *vqueue) } /* - * Release ready_lock and re-enable IRQs between loop iterations - * to allow virtio_chan_free() to possibly kick in and set the - * flag vioch->ready to false even in between processing of - * messages, so as to force outstanding messages to be ignored - * when system is shutting down. + * Release vio channel between loop iterations to allow + * virtio_chan_free() to eventually fully release it when + * shutting down; in such a case, any outstanding message will + * be ignored since this loop will bail out at the next + * iteration. */ - spin_unlock_irqrestore(&vioch->ready_lock, ready_flags); + scmi_vio_channel_release(vioch); + } +} + +static void scmi_vio_deferred_tx_worker(struct work_struct *work) +{ + unsigned long flags; + struct scmi_vio_channel *vioch; + struct scmi_vio_msg *msg, *tmp; + + vioch = container_of(work, struct scmi_vio_channel, deferred_tx_work); + + if (!scmi_vio_channel_acquire(vioch)) + return; + + /* + * Process pre-fetched messages: these could be non-polled messages or + * late timed-out replies to polled messages dequeued by chance while + * polling for some other messages: this worker is in charge to process + * the valid non-expired messages and anyway finally free all of them. + */ + spin_lock_irqsave(&vioch->pending_lock, flags); + + /* Scan the list of possibly pre-fetched messages during polling. */ + list_for_each_entry_safe(msg, tmp, &vioch->pending_cmds_list, list) { + list_del(&msg->list); + + /* + * Channel is acquired here (cannot vanish) and this message + * is no more processed elsewhere so no poll_lock needed. + */ + if (msg->poll_status == VIO_MSG_NOT_POLLED) + scmi_rx_callback(vioch->cinfo, + msg_read_header(msg->input), msg); + + /* Free the processed message once done */ + scmi_vio_msg_release(vioch, msg); } -unlock_out: - spin_unlock(&vioch->lock); -unlock_ready_out: - spin_unlock_irqrestore(&vioch->ready_lock, ready_flags); + spin_unlock_irqrestore(&vioch->pending_lock, flags); + + /* Process possibly still pending messages */ + scmi_vio_complete_cb(vioch->vqueue); + + scmi_vio_channel_release(vioch); } static const char *const scmi_vio_vqueue_names[] = { "tx", "rx" }; @@ -193,8 +378,8 @@ static unsigned int virtio_get_max_msg(struct scmi_chan_info *base_cinfo) static int virtio_link_supplier(struct device *dev) { if (!scmi_vdev) { - dev_notice_once(dev, - "Deferring probe after not finding a bound scmi-virtio device\n"); + dev_notice(dev, + "Deferring probe after not finding a bound scmi-virtio device\n"); return -EPROBE_DEFER; } @@ -234,7 +419,6 @@ static bool virtio_chan_available(struct device *dev, int idx) static int virtio_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, bool tx) { - unsigned long flags; struct scmi_vio_channel *vioch; int index = tx ? VIRTIO_SCMI_VQ_TX : VIRTIO_SCMI_VQ_RX; int i; @@ -244,6 +428,19 @@ static int virtio_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, vioch = &((struct scmi_vio_channel *)scmi_vdev->priv)[index]; + /* Setup a deferred worker for polling. */ + if (tx && !vioch->deferred_tx_wq) { + vioch->deferred_tx_wq = + alloc_workqueue(dev_name(&scmi_vdev->dev), + WQ_UNBOUND | WQ_FREEZABLE | WQ_SYSFS, + 0); + if (!vioch->deferred_tx_wq) + return -ENOMEM; + + INIT_WORK(&vioch->deferred_tx_work, + scmi_vio_deferred_tx_worker); + } + for (i = 0; i < vioch->max_msg; i++) { struct scmi_vio_msg *msg; @@ -257,6 +454,8 @@ static int virtio_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, GFP_KERNEL); if (!msg->request) return -ENOMEM; + spin_lock_init(&msg->poll_lock); + refcount_set(&msg->users, 1); } msg->input = devm_kzalloc(cinfo->dev, VIRTIO_SCMI_MAX_PDU_SIZE, @@ -264,44 +463,23 @@ static int virtio_chan_setup(struct scmi_chan_info *cinfo, struct device *dev, if (!msg->input) return -ENOMEM; - if (tx) { - spin_lock_irqsave(&vioch->lock, flags); - list_add_tail(&msg->list, &vioch->free_list); - spin_unlock_irqrestore(&vioch->lock, flags); - } else { - scmi_vio_feed_vq_rx(vioch, msg, cinfo->dev); - } + scmi_finalize_message(vioch, msg); } - spin_lock_irqsave(&vioch->lock, flags); - cinfo->transport_info = vioch; - /* Indirectly setting channel not available any more */ - vioch->cinfo = cinfo; - spin_unlock_irqrestore(&vioch->lock, flags); - - spin_lock_irqsave(&vioch->ready_lock, flags); - vioch->ready = true; - spin_unlock_irqrestore(&vioch->ready_lock, flags); + scmi_vio_channel_ready(vioch, cinfo); return 0; } static int virtio_chan_free(int id, void *p, void *data) { - unsigned long flags; struct scmi_chan_info *cinfo = p; struct scmi_vio_channel *vioch = cinfo->transport_info; - spin_lock_irqsave(&vioch->ready_lock, flags); - vioch->ready = false; - spin_unlock_irqrestore(&vioch->ready_lock, flags); + scmi_vio_channel_cleanup_sync(vioch); scmi_free_channel(cinfo, data, id); - spin_lock_irqsave(&vioch->lock, flags); - vioch->cinfo = NULL; - spin_unlock_irqrestore(&vioch->lock, flags); - return 0; } @@ -316,33 +494,56 @@ static int virtio_send_message(struct scmi_chan_info *cinfo, int rc; struct scmi_vio_msg *msg; - spin_lock_irqsave(&vioch->lock, flags); + if (!scmi_vio_channel_acquire(vioch)) + return -EINVAL; - if (list_empty(&vioch->free_list)) { - spin_unlock_irqrestore(&vioch->lock, flags); + msg = scmi_virtio_get_free_msg(vioch); + if (!msg) { + scmi_vio_channel_release(vioch); return -EBUSY; } - msg = list_first_entry(&vioch->free_list, typeof(*msg), list); - list_del(&msg->list); - msg_tx_prepare(msg->request, xfer); sg_init_one(&sg_out, msg->request, msg_command_size(xfer)); sg_init_one(&sg_in, msg->input, msg_response_size(xfer)); - rc = virtqueue_add_sgs(vioch->vqueue, sgs, 1, 1, msg, GFP_ATOMIC); - if (rc) { - list_add(&msg->list, &vioch->free_list); - dev_err_once(vioch->cinfo->dev, - "%s() failed to add to virtqueue (%d)\n", __func__, - rc); - } else { - virtqueue_kick(vioch->vqueue); + spin_lock_irqsave(&vioch->lock, flags); + + /* + * If polling was requested for this transaction: + * - retrieve last used index (will be used as polling reference) + * - bind the polled message to the xfer via .priv + * - grab an additional msg refcount for the poll-path + */ + if (xfer->hdr.poll_completion) { + msg->poll_idx = virtqueue_enable_cb_prepare(vioch->vqueue); + /* Still no users, no need to acquire poll_lock */ + msg->poll_status = VIO_MSG_POLLING; + scmi_vio_msg_acquire(msg); + /* Ensure initialized msg is visibly bound to xfer */ + smp_store_mb(xfer->priv, msg); } + rc = virtqueue_add_sgs(vioch->vqueue, sgs, 1, 1, msg, GFP_ATOMIC); + if (rc) + dev_err(vioch->cinfo->dev, + "failed to add to TX virtqueue (%d)\n", rc); + else + virtqueue_kick(vioch->vqueue); + spin_unlock_irqrestore(&vioch->lock, flags); + if (rc) { + /* Ensure order between xfer->priv clear and vq feeding */ + smp_store_mb(xfer->priv, NULL); + if (xfer->hdr.poll_completion) + scmi_vio_msg_release(vioch, msg); + scmi_vio_msg_release(vioch, msg); + } + + scmi_vio_channel_release(vioch); + return rc; } @@ -351,10 +552,8 @@ static void virtio_fetch_response(struct scmi_chan_info *cinfo, { struct scmi_vio_msg *msg = xfer->priv; - if (msg) { + if (msg) msg_fetch_response(msg->input, msg->rx_len, xfer); - xfer->priv = NULL; - } } static void virtio_fetch_notification(struct scmi_chan_info *cinfo, @@ -362,10 +561,225 @@ static void virtio_fetch_notification(struct scmi_chan_info *cinfo, { struct scmi_vio_msg *msg = xfer->priv; - if (msg) { + if (msg) msg_fetch_notification(msg->input, msg->rx_len, max_len, xfer); - xfer->priv = NULL; +} + +/** + * virtio_mark_txdone - Mark transmission done + * + * Free only completed polling transfer messages. + * + * Note that in the SCMI VirtIO transport we never explicitly release still + * outstanding but timed-out messages by forcibly re-adding them to the + * free-list inside the TX code path; we instead let IRQ/RX callbacks, or the + * TX deferred worker, eventually clean up such messages once, finally, a late + * reply is received and discarded (if ever). + * + * This approach was deemed preferable since those pending timed-out buffers are + * still effectively owned by the SCMI platform VirtIO device even after timeout + * expiration: forcibly freeing and reusing them before they had been returned + * explicitly by the SCMI platform could lead to subtle bugs due to message + * corruption. + * An SCMI platform VirtIO device which never returns message buffers is + * anyway broken and it will quickly lead to exhaustion of available messages. + * + * For this same reason, here, we take care to free only the polled messages + * that had been somehow replied (only if not by chance already processed on the + * IRQ path - the initial scmi_vio_msg_release() takes care of this) and also + * any timed-out polled message if that indeed appears to have been at least + * dequeued from the virtqueues (VIO_MSG_POLL_DONE): this is needed since such + * messages won't be freed elsewhere. Any other polled message is marked as + * VIO_MSG_POLL_TIMEOUT. + * + * Possible late replies to timed-out polled messages will be eventually freed + * by RX callbacks if delivered on the IRQ path or by the deferred TX worker if + * dequeued on some other polling path. + * + * @cinfo: SCMI channel info + * @ret: Transmission return code + * @xfer: Transfer descriptor + */ +static void virtio_mark_txdone(struct scmi_chan_info *cinfo, int ret, + struct scmi_xfer *xfer) +{ + unsigned long flags; + struct scmi_vio_channel *vioch = cinfo->transport_info; + struct scmi_vio_msg *msg = xfer->priv; + + if (!msg || !scmi_vio_channel_acquire(vioch)) + return; + + /* Ensure msg is unbound from xfer anyway at this point */ + smp_store_mb(xfer->priv, NULL); + + /* Must be a polled xfer and not already freed on the IRQ path */ + if (!xfer->hdr.poll_completion || scmi_vio_msg_release(vioch, msg)) { + scmi_vio_channel_release(vioch); + return; } + + spin_lock_irqsave(&msg->poll_lock, flags); + /* Do not free timedout polled messages only if still inflight */ + if (ret != -ETIMEDOUT || msg->poll_status == VIO_MSG_POLL_DONE) + scmi_vio_msg_release(vioch, msg); + else if (msg->poll_status == VIO_MSG_POLLING) + msg->poll_status = VIO_MSG_POLL_TIMEOUT; + spin_unlock_irqrestore(&msg->poll_lock, flags); + + scmi_vio_channel_release(vioch); +} + +/** + * virtio_poll_done - Provide polling support for VirtIO transport + * + * @cinfo: SCMI channel info + * @xfer: Reference to the transfer being poll for. + * + * VirtIO core provides a polling mechanism based only on last used indexes: + * this means that it is possible to poll the virtqueues waiting for something + * new to arrive from the host side, but the only way to check if the freshly + * arrived buffer was indeed what we were waiting for is to compare the newly + * arrived message descriptor with the one we are polling on. + * + * As a consequence it can happen to dequeue something different from the buffer + * we were poll-waiting for: if that is the case such early fetched buffers are + * then added to a the @pending_cmds_list list for later processing by a + * dedicated deferred worker. + * + * So, basically, once something new is spotted we proceed to de-queue all the + * freshly received used buffers until we found the one we were polling on, or, + * we have 'seemingly' emptied the virtqueue; if some buffers are still pending + * in the vqueue at the end of the polling loop (possible due to inherent races + * in virtqueues handling mechanisms), we similarly kick the deferred worker + * and let it process those, to avoid indefinitely looping in the .poll_done + * busy-waiting helper. + * + * Finally, we delegate to the deferred worker also the final free of any timed + * out reply to a polled message that we should dequeue. + * + * Note that, since we do NOT have per-message suppress notification mechanism, + * the message we are polling for could be alternatively delivered via usual + * IRQs callbacks on another core which happened to have IRQs enabled while we + * are actively polling for it here: in such a case it will be handled as such + * by scmi_rx_callback() and the polling loop in the SCMI Core TX path will be + * transparently terminated anyway. + * + * Return: True once polling has successfully completed. + */ +static bool virtio_poll_done(struct scmi_chan_info *cinfo, + struct scmi_xfer *xfer) +{ + bool pending, found = false; + unsigned int length, any_prefetched = 0; + unsigned long flags; + struct scmi_vio_msg *next_msg, *msg = xfer->priv; + struct scmi_vio_channel *vioch = cinfo->transport_info; + + if (!msg) + return true; + + /* + * Processed already by other polling loop on another CPU ? + * + * Note that this message is acquired on the poll path so cannot vanish + * while inside this loop iteration even if concurrently processed on + * the IRQ path. + * + * Avoid to acquire poll_lock since polled_status can be changed + * in a relevant manner only later in this same thread of execution: + * any other possible changes made concurrently by other polling loops + * or by a reply delivered on the IRQ path have no meaningful impact on + * this loop iteration: in other words it is harmless to allow this + * possible race but let has avoid spinlocking with irqs off in this + * initial part of the polling loop. + */ + if (msg->poll_status == VIO_MSG_POLL_DONE) + return true; + + if (!scmi_vio_channel_acquire(vioch)) + return true; + + /* Has cmdq index moved at all ? */ + pending = virtqueue_poll(vioch->vqueue, msg->poll_idx); + if (!pending) { + scmi_vio_channel_release(vioch); + return false; + } + + spin_lock_irqsave(&vioch->lock, flags); + virtqueue_disable_cb(vioch->vqueue); + + /* + * Process all new messages till the polled-for message is found OR + * the vqueue is empty. + */ + while ((next_msg = virtqueue_get_buf(vioch->vqueue, &length))) { + bool next_msg_done = false; + + /* + * Mark any dequeued buffer message as VIO_MSG_POLL_DONE so + * that can be properly freed even on timeout in mark_txdone. + */ + spin_lock(&next_msg->poll_lock); + if (next_msg->poll_status == VIO_MSG_POLLING) { + next_msg->poll_status = VIO_MSG_POLL_DONE; + next_msg_done = true; + } + spin_unlock(&next_msg->poll_lock); + + next_msg->rx_len = length; + /* Is the message we were polling for ? */ + if (next_msg == msg) { + found = true; + break; + } else if (next_msg_done) { + /* Skip the rest if this was another polled msg */ + continue; + } + + /* + * Enqueue for later processing any non-polled message and any + * timed-out polled one that we happen to have dequeued. + */ + spin_lock(&next_msg->poll_lock); + if (next_msg->poll_status == VIO_MSG_NOT_POLLED || + next_msg->poll_status == VIO_MSG_POLL_TIMEOUT) { + spin_unlock(&next_msg->poll_lock); + + any_prefetched++; + spin_lock(&vioch->pending_lock); + list_add_tail(&next_msg->list, + &vioch->pending_cmds_list); + spin_unlock(&vioch->pending_lock); + } else { + spin_unlock(&next_msg->poll_lock); + } + } + + /* + * When the polling loop has successfully terminated if something + * else was queued in the meantime, it will be served by a deferred + * worker OR by the normal IRQ/callback OR by other poll loops. + * + * If we are still looking for the polled reply, the polling index has + * to be updated to the current vqueue last used index. + */ + if (found) { + pending = !virtqueue_enable_cb(vioch->vqueue); + } else { + msg->poll_idx = virtqueue_enable_cb_prepare(vioch->vqueue); + pending = virtqueue_poll(vioch->vqueue, msg->poll_idx); + } + + if (vioch->deferred_tx_wq && (any_prefetched || pending)) + queue_work(vioch->deferred_tx_wq, &vioch->deferred_tx_work); + + spin_unlock_irqrestore(&vioch->lock, flags); + + scmi_vio_channel_release(vioch); + + return found; } static const struct scmi_transport_ops scmi_virtio_ops = { @@ -377,6 +791,8 @@ static const struct scmi_transport_ops scmi_virtio_ops = { .send_message = virtio_send_message, .fetch_response = virtio_fetch_response, .fetch_notification = virtio_fetch_notification, + .mark_txdone = virtio_mark_txdone, + .poll_done = virtio_poll_done, }; static int scmi_vio_probe(struct virtio_device *vdev) @@ -417,8 +833,10 @@ static int scmi_vio_probe(struct virtio_device *vdev) unsigned int sz; spin_lock_init(&channels[i].lock); - spin_lock_init(&channels[i].ready_lock); + spin_lock_init(&channels[i].free_lock); INIT_LIST_HEAD(&channels[i].free_list); + spin_lock_init(&channels[i].pending_lock); + INIT_LIST_HEAD(&channels[i].pending_cmds_list); channels[i].vqueue = vqs[i]; sz = virtqueue_get_vring_size(channels[i].vqueue); @@ -427,10 +845,10 @@ static int scmi_vio_probe(struct virtio_device *vdev) sz /= DESCRIPTORS_PER_TX_MSG; if (sz > MSG_TOKEN_MAX) { - dev_info_once(dev, - "%s virtqueue could hold %d messages. Only %ld allowed to be pending.\n", - channels[i].is_rx ? "rx" : "tx", - sz, MSG_TOKEN_MAX); + dev_info(dev, + "%s virtqueue could hold %d messages. Only %ld allowed to be pending.\n", + channels[i].is_rx ? "rx" : "tx", + sz, MSG_TOKEN_MAX); sz = MSG_TOKEN_MAX; } channels[i].max_msg = sz; @@ -460,12 +878,13 @@ static void scmi_vio_remove(struct virtio_device *vdev) static int scmi_vio_validate(struct virtio_device *vdev) { +#ifdef CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_VERSION1_COMPLIANCE if (!virtio_has_feature(vdev, VIRTIO_F_VERSION_1)) { dev_err(&vdev->dev, "device does not comply with spec version 1.x\n"); return -EINVAL; } - +#endif return 0; } @@ -503,7 +922,9 @@ const struct scmi_desc scmi_virtio_desc = { .transport_init = virtio_scmi_init, .transport_exit = virtio_scmi_exit, .ops = &scmi_virtio_ops, - .max_rx_timeout_ms = 60000, /* for non-realtime virtio devices */ + /* for non-realtime virtio devices */ + .max_rx_timeout_ms = VIRTIO_MAX_RX_TIMEOUT_MS, .max_msg = 0, /* overridden by virtio_get_max_msg() */ .max_msg_size = VIRTIO_SCMI_MAX_MSG_SIZE, + .atomic_enabled = IS_ENABLED(CONFIG_ARM_SCMI_TRANSPORT_VIRTIO_ATOMIC_ENABLE), }; diff --git a/drivers/firmware/imx/rm.c b/drivers/firmware/imx/rm.c index a12db6ff323b..d492b99e1c6c 100644 --- a/drivers/firmware/imx/rm.c +++ b/drivers/firmware/imx/rm.c @@ -43,3 +43,48 @@ bool imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource) return hdr->func; } EXPORT_SYMBOL(imx_sc_rm_is_resource_owned); + +struct imx_sc_msg_rm_get_resource_owner { + struct imx_sc_rpc_msg hdr; + union { + struct { + u16 resource; + } req; + struct { + u8 val; + } resp; + } data; +} __packed __aligned(4); + +/* + * This function get @resource partition number + * + * @param[in] ipc IPC handle + * @param[in] resource resource the control is associated with + * @param[out] pt pointer to return the partition number + * + * @return Returns 0 for success and < 0 for errors. + */ +int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt) +{ + struct imx_sc_msg_rm_get_resource_owner msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_RM; + hdr->func = IMX_SC_RM_FUNC_GET_RESOURCE_OWNER; + hdr->size = 2; + + msg.data.req.resource = resource; + + ret = imx_scu_call_rpc(ipc, &msg, true); + if (ret) + return ret; + + if (pt) + *pt = msg.data.resp.val; + + return 0; +} +EXPORT_SYMBOL(imx_sc_rm_get_resource_owner); diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index ff6569c4a53b..af3d057e6421 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -155,6 +155,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 }, /* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 }, diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 7db8066b19fd..491bbf70c94a 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -49,26 +49,12 @@ struct qcom_scm_mem_map_info { __le64 mem_size; }; -#define QCOM_SCM_FLAG_COLDBOOT_CPU0 0x00 -#define QCOM_SCM_FLAG_COLDBOOT_CPU1 0x01 -#define QCOM_SCM_FLAG_COLDBOOT_CPU2 0x08 -#define QCOM_SCM_FLAG_COLDBOOT_CPU3 0x20 - -#define QCOM_SCM_FLAG_WARMBOOT_CPU0 0x04 -#define QCOM_SCM_FLAG_WARMBOOT_CPU1 0x02 -#define QCOM_SCM_FLAG_WARMBOOT_CPU2 0x10 -#define QCOM_SCM_FLAG_WARMBOOT_CPU3 0x40 - -struct qcom_scm_wb_entry { - int flag; - void *entry; +/* Each bit configures cold/warm boot address for one of the 4 CPUs */ +static const u8 qcom_scm_cpu_cold_bits[QCOM_SCM_BOOT_MAX_CPUS] = { + 0, BIT(0), BIT(3), BIT(5) }; - -static struct qcom_scm_wb_entry qcom_scm_wb[] = { - { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 }, - { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 }, - { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 }, - { .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 }, +static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = { + BIT(2), BIT(1), BIT(4), BIT(6) }; static const char * const qcom_scm_convention_names[] = { @@ -179,9 +165,8 @@ found: /** * qcom_scm_call() - Invoke a syscall in the secure world * @dev: device - * @svc_id: service identifier - * @cmd_id: command identifier * @desc: Descriptor structure containing arguments and return values + * @res: Structure containing results from SMC/HVC call * * Sends a command to the SCM and waits for the command to finish processing. * This should *only* be called in pre-emptible context. @@ -205,8 +190,6 @@ static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, /** * qcom_scm_call_atomic() - atomic variation of qcom_scm_call() * @dev: device - * @svc_id: service identifier - * @cmd_id: command identifier * @desc: Descriptor structure containing arguments and return values * @res: Structure containing results from SMC/HVC call * @@ -260,70 +243,10 @@ static bool __qcom_scm_is_call_available(struct device *dev, u32 svc_id, return ret ? false : !!res.result[0]; } -/** - * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus - * @entry: Entry point function for the cpus - * @cpus: The cpumask of cpus that will use the entry point - * - * Set the Linux entry point for the SCM to transfer control to when coming - * out of a power down. CPU power down may be executed on cpuidle or hotplug. - */ -int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus) +static int qcom_scm_set_boot_addr(void *entry, const u8 *cpu_bits) { - int ret; - int flags = 0; int cpu; - struct qcom_scm_desc desc = { - .svc = QCOM_SCM_SVC_BOOT, - .cmd = QCOM_SCM_BOOT_SET_ADDR, - .arginfo = QCOM_SCM_ARGS(2), - }; - - /* - * Reassign only if we are switching from hotplug entry point - * to cpuidle entry point or vice versa. - */ - for_each_cpu(cpu, cpus) { - if (entry == qcom_scm_wb[cpu].entry) - continue; - flags |= qcom_scm_wb[cpu].flag; - } - - /* No change in entry function */ - if (!flags) - return 0; - - desc.args[0] = flags; - desc.args[1] = virt_to_phys(entry); - - ret = qcom_scm_call(__scm->dev, &desc, NULL); - if (!ret) { - for_each_cpu(cpu, cpus) - qcom_scm_wb[cpu].entry = entry; - } - - return ret; -} -EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); - -/** - * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus - * @entry: Entry point function for the cpus - * @cpus: The cpumask of cpus that will use the entry point - * - * Set the cold boot address of the cpus. Any cpu outside the supported - * range would be removed from the cpu present mask. - */ -int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) -{ - int flags = 0; - int cpu; - int scm_cb_flags[] = { - QCOM_SCM_FLAG_COLDBOOT_CPU0, - QCOM_SCM_FLAG_COLDBOOT_CPU1, - QCOM_SCM_FLAG_COLDBOOT_CPU2, - QCOM_SCM_FLAG_COLDBOOT_CPU3, - }; + unsigned int flags = 0; struct qcom_scm_desc desc = { .svc = QCOM_SCM_SVC_BOOT, .cmd = QCOM_SCM_BOOT_SET_ADDR, @@ -331,14 +254,10 @@ int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) .owner = ARM_SMCCC_OWNER_SIP, }; - if (!cpus || cpumask_empty(cpus)) - return -EINVAL; - - for_each_cpu(cpu, cpus) { - if (cpu < ARRAY_SIZE(scm_cb_flags)) - flags |= scm_cb_flags[cpu]; - else - set_cpu_present(cpu, false); + for_each_present_cpu(cpu) { + if (cpu >= QCOM_SCM_BOOT_MAX_CPUS) + return -EINVAL; + flags |= cpu_bits[cpu]; } desc.args[0] = flags; @@ -346,11 +265,61 @@ int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus) return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); } + +static int qcom_scm_set_boot_addr_mc(void *entry, unsigned int flags) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_BOOT, + .cmd = QCOM_SCM_BOOT_SET_ADDR_MC, + .owner = ARM_SMCCC_OWNER_SIP, + .arginfo = QCOM_SCM_ARGS(6), + .args = { + virt_to_phys(entry), + /* Apply to all CPUs in all affinity levels */ + ~0ULL, ~0ULL, ~0ULL, ~0ULL, + flags, + }, + }; + + /* Need a device for DMA of the additional arguments */ + if (!__scm || __get_convention() == SMC_CONVENTION_LEGACY) + return -EOPNOTSUPP; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} + +/** + * qcom_scm_set_warm_boot_addr() - Set the warm boot address for all cpus + * @entry: Entry point function for the cpus + * + * Set the Linux entry point for the SCM to transfer control to when coming + * out of a power down. CPU power down may be executed on cpuidle or hotplug. + */ +int qcom_scm_set_warm_boot_addr(void *entry) +{ + if (qcom_scm_set_boot_addr_mc(entry, QCOM_SCM_BOOT_MC_FLAG_WARMBOOT)) + /* Fallback to old SCM call */ + return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_warm_bits); + return 0; +} +EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); + +/** + * qcom_scm_set_cold_boot_addr() - Set the cold boot address for all cpus + * @entry: Entry point function for the cpus + */ +int qcom_scm_set_cold_boot_addr(void *entry) +{ + if (qcom_scm_set_boot_addr_mc(entry, QCOM_SCM_BOOT_MC_FLAG_COLDBOOT)) + /* Fallback to old SCM call */ + return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_cold_bits); + return 0; +} EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); /** * qcom_scm_cpu_power_down() - Power down the cpu - * @flags - Flags to flush cache + * @flags: Flags to flush cache * * This is an end point to power down cpu. If there was a pending interrupt, * the control would return from this function, otherwise, the cpu jumps to the @@ -435,10 +404,16 @@ static void qcom_scm_set_download_mode(bool enable) * and optional blob of data used for authenticating the metadata * and the rest of the firmware * @size: size of the metadata + * @ctx: optional metadata context * - * Returns 0 on success. + * Return: 0 on success. + * + * Upon successful return, the PAS metadata context (@ctx) will be used to + * track the metadata allocation, this needs to be released by invoking + * qcom_scm_pas_metadata_release() by the caller. */ -int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size) +int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, + struct qcom_scm_pas_metadata *ctx) { dma_addr_t mdata_phys; void *mdata_buf; @@ -467,7 +442,7 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size) ret = qcom_scm_clk_enable(); if (ret) - goto free_metadata; + goto out; desc.args[1] = mdata_phys; @@ -475,13 +450,36 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size) qcom_scm_clk_disable(); -free_metadata: - dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); +out: + if (ret < 0 || !ctx) { + dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); + } else if (ctx) { + ctx->ptr = mdata_buf; + ctx->phys = mdata_phys; + ctx->size = size; + } return ret ? : res.result[0]; } EXPORT_SYMBOL(qcom_scm_pas_init_image); +/** + * qcom_scm_pas_metadata_release() - release metadata context + * @ctx: metadata context + */ +void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx) +{ + if (!ctx->ptr) + return; + + dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys); + + ctx->ptr = NULL; + ctx->phys = 0; + ctx->size = 0; +} +EXPORT_SYMBOL(qcom_scm_pas_metadata_release); + /** * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral * for firmware loading @@ -749,12 +747,6 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) }; int ret; - desc.args[0] = addr; - desc.args[1] = size; - desc.args[2] = spare; - desc.arginfo = QCOM_SCM_ARGS(3, QCOM_SCM_RW, QCOM_SCM_VAL, - QCOM_SCM_VAL); - ret = qcom_scm_call(__scm->dev, &desc, NULL); /* the pg table has been initialized already, ignore the error */ @@ -765,6 +757,21 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) } EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init); +int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_MP, + .cmd = QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE, + .arginfo = QCOM_SCM_ARGS(2), + .args[0] = size, + .args[1] = spare, + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL(qcom_scm_iommu_set_cp_pool_size); + int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, u32 cp_nonpixel_start, u32 cp_nonpixel_size) @@ -1131,6 +1138,22 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) } EXPORT_SYMBOL(qcom_scm_hdcp_req); +int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt) +{ + struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_SMMU_PROGRAM, + .cmd = QCOM_SCM_SMMU_PT_FORMAT, + .arginfo = QCOM_SCM_ARGS(3), + .args[0] = sec_id, + .args[1] = ctx_num, + .args[2] = pt_fmt, /* 0: LPAE AArch32 - 1: AArch64 */ + .owner = ARM_SMCCC_OWNER_SIP, + }; + + return qcom_scm_call(__scm->dev, &desc, NULL); +} +EXPORT_SYMBOL(qcom_scm_iommu_set_pt_format); + int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { struct qcom_scm_desc desc = { diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index d92156ceb3ac..0d51eef2472f 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -78,8 +78,13 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_BOOT_SET_ADDR 0x01 #define QCOM_SCM_BOOT_TERMINATE_PC 0x02 #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 +#define QCOM_SCM_BOOT_SET_ADDR_MC 0x11 #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a #define QCOM_SCM_FLUSH_FLAG_MASK 0x3 +#define QCOM_SCM_BOOT_MAX_CPUS 4 +#define QCOM_SCM_BOOT_MC_FLAG_AARCH64 BIT(0) +#define QCOM_SCM_BOOT_MC_FLAG_COLDBOOT BIT(1) +#define QCOM_SCM_BOOT_MC_FLAG_WARMBOOT BIT(2) #define QCOM_SCM_SVC_PIL 0x02 #define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01 @@ -100,6 +105,7 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02 #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03 #define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04 +#define QCOM_SCM_MP_IOMMU_SET_CP_POOL_SIZE 0x05 #define QCOM_SCM_MP_VIDEO_VAR 0x08 #define QCOM_SCM_MP_ASSIGN 0x16 @@ -119,6 +125,7 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_LMH_LIMIT_DCVSH 0x10 #define QCOM_SCM_SVC_SMMU_PROGRAM 0x15 +#define QCOM_SCM_SMMU_PT_FORMAT 0x01 #define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03 #define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02 diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 5ae2040b8b02..4697edc125b1 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -3412,7 +3412,7 @@ static int ti_sci_probe(struct platform_device *pdev) ret = register_restart_handler(&info->nb); if (ret) { dev_err(dev, "reboot registration fail(%d)\n", ret); - return ret; + goto out; } } diff --git a/drivers/hid/uhid.c b/drivers/hid/uhid.c index 614adb510dbd..2a918aeb0af1 100644 --- a/drivers/hid/uhid.c +++ b/drivers/hid/uhid.c @@ -747,7 +747,7 @@ static ssize_t uhid_char_write(struct file *file, const char __user *buffer, * copied from, so it's unsafe to allow this with elevated * privileges (e.g. from a setuid binary) or via kernel_write(). */ - if (file->f_cred != current_cred() || uaccess_kernel()) { + if (file->f_cred != current_cred()) { pr_err_once("UHID_CREATE from different security context by process %d (%s), this is not allowed.\n", task_tgid_vnr(current), current->comm); ret = -EACCES; diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 1f8990f812f1..160a1d8ceaa9 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -92,7 +92,6 @@ obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o obj-$(CONFIG_ARCH_SYNQUACER) += irq-sni-exiu.o obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o obj-$(CONFIG_GOLDFISH_PIC) += irq-goldfish-pic.o -obj-$(CONFIG_NDS32) += irq-ativic32.o obj-$(CONFIG_QCOM_PDC) += qcom-pdc.o obj-$(CONFIG_QCOM_MPM) += irq-qcom-mpm.o obj-$(CONFIG_CSKY_MPINTC) += irq-csky-mpintc.o diff --git a/drivers/irqchip/irq-ativic32.c b/drivers/irqchip/irq-ativic32.c deleted file mode 100644 index 223dd2f97d28..000000000000 --- a/drivers/irqchip/irq-ativic32.c +++ /dev/null @@ -1,156 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -unsigned long wake_mask; - -static void ativic32_ack_irq(struct irq_data *data) -{ - __nds32__mtsr_dsb(BIT(data->hwirq), NDS32_SR_INT_PEND2); -} - -static void ativic32_mask_irq(struct irq_data *data) -{ - unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2); - __nds32__mtsr_dsb(int_mask2 & (~(BIT(data->hwirq))), NDS32_SR_INT_MASK2); -} - -static void ativic32_unmask_irq(struct irq_data *data) -{ - unsigned long int_mask2 = __nds32__mfsr(NDS32_SR_INT_MASK2); - __nds32__mtsr_dsb(int_mask2 | (BIT(data->hwirq)), NDS32_SR_INT_MASK2); -} - -static int nointc_set_wake(struct irq_data *data, unsigned int on) -{ - unsigned long int_mask = __nds32__mfsr(NDS32_SR_INT_MASK); - static unsigned long irq_orig_bit; - u32 bit = 1 << data->hwirq; - - if (on) { - if (int_mask & bit) - __assign_bit(data->hwirq, &irq_orig_bit, true); - else - __assign_bit(data->hwirq, &irq_orig_bit, false); - - __assign_bit(data->hwirq, &int_mask, true); - __assign_bit(data->hwirq, &wake_mask, true); - - } else { - if (!(irq_orig_bit & bit)) - __assign_bit(data->hwirq, &int_mask, false); - - __assign_bit(data->hwirq, &wake_mask, false); - __assign_bit(data->hwirq, &irq_orig_bit, false); - } - - __nds32__mtsr_dsb(int_mask, NDS32_SR_INT_MASK); - - return 0; -} - -static struct irq_chip ativic32_chip = { - .name = "ativic32", - .irq_ack = ativic32_ack_irq, - .irq_mask = ativic32_mask_irq, - .irq_unmask = ativic32_unmask_irq, - .irq_set_wake = nointc_set_wake, -}; - -static unsigned int __initdata nivic_map[6] = { 6, 2, 10, 16, 24, 32 }; - -static struct irq_domain *root_domain; -static int ativic32_irq_domain_map(struct irq_domain *id, unsigned int virq, - irq_hw_number_t hw) -{ - - unsigned long int_trigger_type; - u32 type; - struct irq_data *irq_data; - int_trigger_type = __nds32__mfsr(NDS32_SR_INT_TRIGGER); - irq_data = irq_get_irq_data(virq); - if (!irq_data) - return -EINVAL; - - if (int_trigger_type & (BIT(hw))) { - irq_set_chip_and_handler(virq, &ativic32_chip, handle_edge_irq); - type = IRQ_TYPE_EDGE_RISING; - } else { - irq_set_chip_and_handler(virq, &ativic32_chip, handle_level_irq); - type = IRQ_TYPE_LEVEL_HIGH; - } - - irqd_set_trigger_type(irq_data, type); - return 0; -} - -static const struct irq_domain_ops ativic32_ops = { - .map = ativic32_irq_domain_map, - .xlate = irq_domain_xlate_onecell -}; - -static irq_hw_number_t get_intr_src(void) -{ - return ((__nds32__mfsr(NDS32_SR_ITYPE) & ITYPE_mskVECTOR) >> ITYPE_offVECTOR) - - NDS32_VECTOR_offINTERRUPT; -} - -static void ativic32_handle_irq(struct pt_regs *regs) -{ - irq_hw_number_t hwirq = get_intr_src(); - generic_handle_domain_irq(root_domain, hwirq); -} - -/* - * TODO: convert nds32 to GENERIC_IRQ_MULTI_HANDLER so that this entry logic - * can live in arch code. - */ -asmlinkage void asm_do_IRQ(struct pt_regs *regs) -{ - struct pt_regs *old_regs; - - irq_enter(); - old_regs = set_irq_regs(regs); - ativic32_handle_irq(regs); - set_irq_regs(old_regs); - irq_exit(); -} - -int __init ativic32_init_irq(struct device_node *node, struct device_node *parent) -{ - unsigned long int_vec_base, nivic, nr_ints; - - if (WARN(parent, "non-root ativic32 are not supported")) - return -EINVAL; - - int_vec_base = __nds32__mfsr(NDS32_SR_IVB); - - if (((int_vec_base & IVB_mskIVIC_VER) >> IVB_offIVIC_VER) == 0) - panic("Unable to use atcivic32 for this cpu.\n"); - - nivic = (int_vec_base & IVB_mskNIVIC) >> IVB_offNIVIC; - if (nivic >= ARRAY_SIZE(nivic_map)) - panic("The number of input for ativic32 is not supported.\n"); - - nr_ints = nivic_map[nivic]; - - root_domain = irq_domain_add_linear(node, nr_ints, - &ativic32_ops, NULL); - - if (!root_domain) - panic("%s: unable to create IRQ domain\n", node->full_name); - - return 0; -} -IRQCHIP_DECLARE(ativic32, "andestech,ativic32", ativic32_init_irq); diff --git a/drivers/irqchip/irq-nvic.c b/drivers/irqchip/irq-nvic.c index 94230306e0ee..ba6332b00a0a 100644 --- a/drivers/irqchip/irq-nvic.c +++ b/drivers/irqchip/irq-nvic.c @@ -37,27 +37,14 @@ static struct irq_domain *nvic_irq_domain; -static void __nvic_handle_irq(irq_hw_number_t hwirq) +static void __irq_entry nvic_handle_irq(struct pt_regs *regs) { + unsigned long icsr = readl_relaxed(BASEADDR_V7M_SCB + V7M_SCB_ICSR); + irq_hw_number_t hwirq = (icsr & V7M_SCB_ICSR_VECTACTIVE) - 16; + generic_handle_domain_irq(nvic_irq_domain, hwirq); } -/* - * TODO: restructure the ARMv7M entry logic so that this entry logic can live - * in arch code. - */ -asmlinkage void __exception_irq_entry -nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs) -{ - struct pt_regs *old_regs; - - irq_enter(); - old_regs = set_irq_regs(regs); - __nvic_handle_irq(hwirq); - set_irq_regs(old_regs); - irq_exit(); -} - static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs, void *arg) { @@ -143,6 +130,7 @@ static int __init nvic_of_init(struct device_node *node, for (i = 0; i < irqs; i += 4) writel_relaxed(0, nvic_base + NVIC_IPR + i); + set_handle_irq(nvic_handle_irq); return 0; } IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init); diff --git a/drivers/memory/brcmstb_dpfe.c b/drivers/memory/brcmstb_dpfe.c index f43ba69fbb3e..14412002775d 100644 --- a/drivers/memory/brcmstb_dpfe.c +++ b/drivers/memory/brcmstb_dpfe.c @@ -424,7 +424,7 @@ static void __finalize_command(struct brcmstb_dpfe_priv *priv) /* * It depends on the API version which MBOX register we have to write to - * to signal we are done. + * signal we are done. */ release_mbox = (priv->dpfe_api->version < 2) ? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX; diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c index 762d0c0f0716..ecc78d6f89ed 100644 --- a/drivers/memory/emif.c +++ b/drivers/memory/emif.c @@ -1025,7 +1025,7 @@ static struct emif_data *__init_or_module get_device_details( temp = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL); dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL); - if (!emif || !pd || !dev_info) { + if (!emif || !temp || !dev_info) { dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__); goto error; } @@ -1117,7 +1117,7 @@ static int __init_or_module emif_probe(struct platform_device *pdev) { struct emif_data *emif; struct resource *res; - int irq; + int irq, ret; if (pdev->dev.of_node) emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev); @@ -1147,7 +1147,9 @@ static int __init_or_module emif_probe(struct platform_device *pdev) emif_onetime_settings(emif); emif_debugfs_init(emif); disable_and_clear_all_interrupts(emif); - setup_interrupts(emif, irq); + ret = setup_interrupts(emif, irq); + if (ret) + goto error; /* One-time actions taken on probing the first device */ if (!emif1) { diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c index 75a8c38df939..2f6939da21cd 100644 --- a/drivers/memory/fsl_ifc.c +++ b/drivers/memory/fsl_ifc.c @@ -88,6 +88,7 @@ static int fsl_ifc_ctrl_remove(struct platform_device *dev) { struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev); + of_platform_depopulate(&dev->dev); free_irq(ctrl->nand_irq, ctrl); free_irq(ctrl->irq, ctrl); @@ -285,8 +286,16 @@ static int fsl_ifc_ctrl_probe(struct platform_device *dev) } } + /* legacy dts may still use "simple-bus" compatible */ + ret = of_platform_populate(dev->dev.of_node, NULL, NULL, + &dev->dev); + if (ret) + goto err_free_nandirq; + return 0; +err_free_nandirq: + free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev); err_free_irq: free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev); err_unmap_nandirq: diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index 40408a88f464..86a3d34f418e 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,10 @@ #define SMI_DUMMY 0x444 /* SMI LARB */ +#define SMI_LARB_SLP_CON 0xc +#define SLP_PROT_EN BIT(0) +#define SLP_PROT_RDY BIT(16) + #define SMI_LARB_CMD_THRT_CON 0x24 #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4) #define SMI_LARB_THRT_RD_NU_LMT (5 << 4) @@ -81,6 +86,7 @@ #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) #define MTK_SMI_FLAG_SW_FLAG BIT(1) +#define MTK_SMI_FLAG_SLEEP_CTL BIT(2) #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) struct mtk_smi_reg_pair { @@ -94,8 +100,6 @@ enum mtk_smi_type { MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ }; -#define MTK_SMI_CLK_NR_MAX 4 - /* larbs: Require apb/smi clocks while gals is optional. */ static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; #define MTK_SMI_LARB_REQ_CLK_NR 2 @@ -106,6 +110,7 @@ static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. */ static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; +#define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks) #define MTK_SMI_COM_REQ_CLK_NR 2 #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 @@ -335,13 +340,19 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { /* IPU0 | IPU1 | CCU */ }; +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = { + .config_port = mtk_smi_larb_config_port_gen2_general, + .flags_general = MTK_SMI_FLAG_SLEEP_CTL, +}; + static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { .config_port = mtk_smi_larb_config_port_gen2_general, }; static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { .config_port = mtk_smi_larb_config_port_gen2_general, - .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG, + .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | + MTK_SMI_FLAG_SLEEP_CTL, .ostd = mtk_smi_larb_mt8195_ostd, }; @@ -352,11 +363,32 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, + {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186}, {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, {} }; +static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) +{ + int ret; + u32 tmp; + + writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON); + ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON, + tmp, !!(tmp & SLP_PROT_RDY), 10, 1000); + if (ret) { + /* TODO: Reset this larb if it fails here. */ + dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp); + } + return ret; +} + +static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb) +{ + writel_relaxed(0, larb->base + SMI_LARB_SLP_CON); +} + static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) { struct platform_device *smi_com_pdev; @@ -466,9 +498,12 @@ static int __maybe_unused mtk_smi_larb_resume(struct device *dev) int ret; ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); - if (ret < 0) + if (ret) return ret; + if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) + mtk_smi_larb_sleep_ctrl_disable(larb); + /* Configure the basic setting for this larb */ larb_gen->config_port(dev); @@ -478,6 +513,13 @@ static int __maybe_unused mtk_smi_larb_resume(struct device *dev) static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) { struct mtk_smi_larb *larb = dev_get_drvdata(dev); + int ret; + + if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) { + ret = mtk_smi_larb_sleep_ctrl_enable(larb); + if (ret) + return ret; + } clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); return 0; @@ -530,6 +572,12 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { F_MMU1_LARB(7), }; +static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = { + .type = MTK_SMI_GEN2, + .has_gals = true, + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7), +}; + static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { .type = MTK_SMI_GEN2, .has_gals = true, @@ -564,6 +612,7 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, + {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c index b94408954d85..dbdf87bc0b78 100644 --- a/drivers/memory/of_memory.c +++ b/drivers/memory/of_memory.c @@ -212,8 +212,10 @@ static int of_lpddr3_do_get_timings(struct device_node *np, { int ret; - /* The 'reg' param required since DT has changed, used as 'max-freq' */ - ret = of_property_read_u32(np, "reg", &tim->max_freq); + ret = of_property_read_u32(np, "max-freq", &tim->max_freq); + if (ret) + /* Deprecated way of passing max-freq as 'reg' */ + ret = of_property_read_u32(np, "reg", &tim->max_freq); ret |= of_property_read_u32(np, "min-freq", &tim->min_freq); ret |= of_property_read_u32(np, "tRFC", &tim->tRFC); ret |= of_property_read_u32(np, "tRRD", &tim->tRRD); @@ -316,14 +318,21 @@ const struct lpddr2_info struct property *prop; const char *cp; int err; + u32 revision_id[2]; - err = of_property_read_u32(np, "revision-id1", &info.revision_id1); - if (err) - info.revision_id1 = -ENOENT; + err = of_property_read_u32_array(np, "revision-id", revision_id, 2); + if (!err) { + info.revision_id1 = revision_id[0]; + info.revision_id2 = revision_id[1]; + } else { + err = of_property_read_u32(np, "revision-id1", &info.revision_id1); + if (err) + info.revision_id1 = -ENOENT; - err = of_property_read_u32(np, "revision-id2", &info.revision_id2); - if (err) - info.revision_id2 = -ENOENT; + err = of_property_read_u32(np, "revision-id2", &info.revision_id2); + if (err) + info.revision_id2 = -ENOENT; + } err = of_property_read_u32(np, "io-width", &info.io_width); if (err) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 7951764b4efe..3fe83d7c2bf8 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -28,6 +28,7 @@ config TEGRA30_EMC default y depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST select PM_OPP + select DDR help This driver is for the External Memory Controller (EMC) found on Tegra30 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 497b6edbf3ca..25ba3c5e4ad6 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -540,7 +540,7 @@ static int emc_read_lpddr_mode_register(struct tegra_emc *emc, unsigned int register_addr, unsigned int *register_data) { - u32 memory_dev = emem_dev + 1; + u32 memory_dev = emem_dev ? 1 : 2; u32 val, mr_mask = 0xff; int err; diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegra/tegra210-emc-core.c index 13584f9317a4..cbe1a7723514 100644 --- a/drivers/memory/tegra/tegra210-emc-core.c +++ b/drivers/memory/tegra/tegra210-emc-core.c @@ -711,7 +711,7 @@ static int tegra210_emc_cd_set_state(struct thermal_cooling_device *cd, return 0; } -static struct thermal_cooling_device_ops tegra210_emc_cd_ops = { +static const struct thermal_cooling_device_ops tegra210_emc_cd_ops = { .get_max_state = tegra210_emc_cd_max_state, .get_cur_state = tegra210_emc_cd_get_state, .set_cur_state = tegra210_emc_cd_set_state, diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 80f98d717e13..9ba2a9e5316b 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -9,6 +9,7 @@ * Copyright (C) 2019 GRATE-DRIVER project */ +#include #include #include #include @@ -31,11 +32,15 @@ #include #include +#include "../jedec_ddr.h" +#include "../of_memory.h" + #include "mc.h" #define EMC_INTSTATUS 0x000 #define EMC_INTMASK 0x004 #define EMC_DBG 0x008 +#define EMC_ADR_CFG 0x010 #define EMC_CFG 0x00c #define EMC_REFCTRL 0x020 #define EMC_TIMING_CONTROL 0x028 @@ -81,6 +86,7 @@ #define EMC_EMRS 0x0d0 #define EMC_SELF_REF 0x0e0 #define EMC_MRW 0x0e8 +#define EMC_MRR 0x0ec #define EMC_XM2DQSPADCTRL3 0x0f8 #define EMC_FBIO_SPARE 0x100 #define EMC_FBIO_CFG5 0x104 @@ -208,6 +214,13 @@ #define EMC_REFRESH_OVERFLOW_INT BIT(3) #define EMC_CLKCHANGE_COMPLETE_INT BIT(4) +#define EMC_MRR_DIVLD_INT BIT(5) + +#define EMC_MRR_DEV_SELECTN GENMASK(31, 30) +#define EMC_MRR_MRR_MA GENMASK(23, 16) +#define EMC_MRR_MRR_DATA GENMASK(15, 0) + +#define EMC_ADR_CFG_EMEM_NUMDEV BIT(0) enum emc_dram_type { DRAM_TYPE_DDR3, @@ -378,6 +391,8 @@ struct tegra_emc { /* protect shared rate-change code path */ struct mutex rate_lock; + + bool mrr_error; }; static int emc_seq_update_timing(struct tegra_emc *emc) @@ -1008,12 +1023,18 @@ static int emc_load_timings_from_dt(struct tegra_emc *emc, return 0; } -static struct device_node *emc_find_node_by_ram_code(struct device *dev) +static struct device_node *emc_find_node_by_ram_code(struct tegra_emc *emc) { + struct device *dev = emc->dev; struct device_node *np; u32 value, ram_code; int err; + if (emc->mrr_error) { + dev_warn(dev, "memory timings skipped due to MRR error\n"); + return NULL; + } + if (of_get_child_count(dev->of_node) == 0) { dev_info_once(dev, "device-tree doesn't have memory timings\n"); return NULL; @@ -1035,11 +1056,73 @@ static struct device_node *emc_find_node_by_ram_code(struct device *dev) return NULL; } +static int emc_read_lpddr_mode_register(struct tegra_emc *emc, + unsigned int emem_dev, + unsigned int register_addr, + unsigned int *register_data) +{ + u32 memory_dev = emem_dev ? 1 : 2; + u32 val, mr_mask = 0xff; + int err; + + /* clear data-valid interrupt status */ + writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS); + + /* issue mode register read request */ + val = FIELD_PREP(EMC_MRR_DEV_SELECTN, memory_dev); + val |= FIELD_PREP(EMC_MRR_MRR_MA, register_addr); + + writel_relaxed(val, emc->regs + EMC_MRR); + + /* wait for the LPDDR2 data-valid interrupt */ + err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val, + val & EMC_MRR_DIVLD_INT, + 1, 100); + if (err) { + dev_err(emc->dev, "mode register %u read failed: %d\n", + register_addr, err); + emc->mrr_error = true; + return err; + } + + /* read out mode register data */ + val = readl_relaxed(emc->regs + EMC_MRR); + *register_data = FIELD_GET(EMC_MRR_MRR_DATA, val) & mr_mask; + + return 0; +} + +static void emc_read_lpddr_sdram_info(struct tegra_emc *emc, + unsigned int emem_dev) +{ + union lpddr2_basic_config4 basic_conf4; + unsigned int manufacturer_id; + unsigned int revision_id1; + unsigned int revision_id2; + + /* these registers are standard for all LPDDR JEDEC memory chips */ + emc_read_lpddr_mode_register(emc, emem_dev, 5, &manufacturer_id); + emc_read_lpddr_mode_register(emc, emem_dev, 6, &revision_id1); + emc_read_lpddr_mode_register(emc, emem_dev, 7, &revision_id2); + emc_read_lpddr_mode_register(emc, emem_dev, 8, &basic_conf4.value); + + dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u density: %uMbit iowidth: %ubit\n", + emem_dev, manufacturer_id, + lpddr2_jedec_manufacturer(manufacturer_id), + revision_id1, revision_id2, + 4 >> basic_conf4.arch_type, + 64 << basic_conf4.density, + 32 >> basic_conf4.io_width); +} + static int emc_setup_hw(struct tegra_emc *emc) { + u32 fbio_cfg5, emc_cfg, emc_dbg, emc_adr_cfg; u32 intmask = EMC_REFRESH_OVERFLOW_INT; - u32 fbio_cfg5, emc_cfg, emc_dbg; + static bool print_sdram_info_once; enum emc_dram_type dram_type; + const char *dram_type_str; + unsigned int emem_numdev; fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK; @@ -1076,6 +1159,34 @@ static int emc_setup_hw(struct tegra_emc *emc) emc_dbg &= ~EMC_DBG_FORCE_UPDATE; writel_relaxed(emc_dbg, emc->regs + EMC_DBG); + switch (dram_type) { + case DRAM_TYPE_DDR1: + dram_type_str = "DDR1"; + break; + case DRAM_TYPE_LPDDR2: + dram_type_str = "LPDDR2"; + break; + case DRAM_TYPE_DDR2: + dram_type_str = "DDR2"; + break; + case DRAM_TYPE_DDR3: + dram_type_str = "DDR3"; + break; + } + + emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG); + emem_numdev = FIELD_GET(EMC_ADR_CFG_EMEM_NUMDEV, emc_adr_cfg) + 1; + + dev_info_once(emc->dev, "%u %s %s attached\n", emem_numdev, + dram_type_str, emem_numdev == 2 ? "devices" : "device"); + + if (dram_type == DRAM_TYPE_LPDDR2 && !print_sdram_info_once) { + while (emem_numdev--) + emc_read_lpddr_sdram_info(emc, emem_numdev); + + print_sdram_info_once = true; + } + return 0; } @@ -1538,14 +1649,6 @@ static int tegra_emc_probe(struct platform_device *pdev) emc->clk_nb.notifier_call = emc_clk_change_notify; emc->dev = &pdev->dev; - np = emc_find_node_by_ram_code(&pdev->dev); - if (np) { - err = emc_load_timings_from_dt(emc, np); - of_node_put(np); - if (err) - return err; - } - emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) return PTR_ERR(emc->regs); @@ -1554,6 +1657,14 @@ static int tegra_emc_probe(struct platform_device *pdev) if (err) return err; + np = emc_find_node_by_ram_code(emc); + if (np) { + err = emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + } + err = platform_get_irq(pdev, 0); if (err < 0) return err; diff --git a/drivers/net/ethernet/faraday/Kconfig b/drivers/net/ethernet/faraday/Kconfig index 3d1e9a302148..c699bd6bcbb9 100644 --- a/drivers/net/ethernet/faraday/Kconfig +++ b/drivers/net/ethernet/faraday/Kconfig @@ -6,7 +6,7 @@ config NET_VENDOR_FARADAY bool "Faraday devices" default y - depends on ARM || NDS32 || COMPILE_TEST + depends on ARM || COMPILE_TEST help If you have a network (Ethernet) card belonging to this class, say Y. @@ -19,24 +19,22 @@ if NET_VENDOR_FARADAY config FTMAC100 tristate "Faraday FTMAC100 10/100 Ethernet support" - depends on ARM || NDS32 || COMPILE_TEST + depends on ARM || COMPILE_TEST depends on !64BIT || BROKEN select MII help This driver supports the FTMAC100 10/100 Ethernet controller - from Faraday. It is used on Faraday A320, Andes AG101 and some - other ARM/NDS32 SoC's. + from Faraday. It is used on Faraday A320 and some other ARM SoC's. config FTGMAC100 tristate "Faraday FTGMAC100 Gigabit Ethernet support" - depends on ARM || NDS32 || COMPILE_TEST + depends on ARM || COMPILE_TEST depends on !64BIT || BROKEN select PHYLIB select MDIO_ASPEED if MACH_ASPEED_G6 select CRC32 help This driver supports the FTGMAC100 Gigabit Ethernet controller - from Faraday. It is used on Faraday A369, Andes AG102 and some - other ARM/NDS32 SoC's. + from Faraday. It is used on Faraday A369 and some other ARM SoC's. endif # NET_VENDOR_FARADAY diff --git a/drivers/net/ethernet/xscale/Kconfig b/drivers/net/ethernet/xscale/Kconfig index 0e878fa6e322..b33f64c54b0e 100644 --- a/drivers/net/ethernet/xscale/Kconfig +++ b/drivers/net/ethernet/xscale/Kconfig @@ -20,9 +20,9 @@ if NET_VENDOR_XSCALE config IXP4XX_ETH tristate "Intel IXP4xx Ethernet support" - depends on ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR + depends on ARM && ARCH_IXP4XX && IXP4XX_NPE && IXP4XX_QMGR && OF select PHYLIB - select OF_MDIO if OF + select OF_MDIO select NET_PTP_CLASSIFY help Say Y here if you want to use built-in Ethernet ports diff --git a/drivers/net/ethernet/xscale/ixp4xx_eth.c b/drivers/net/ethernet/xscale/ixp4xx_eth.c index df77a22d1b81..d947955621ee 100644 --- a/drivers/net/ethernet/xscale/ixp4xx_eth.c +++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -38,6 +37,11 @@ #include #include #include +#include + +#define IXP4XX_ETH_NPEA 0x00 +#define IXP4XX_ETH_NPEB 0x10 +#define IXP4XX_ETH_NPEC 0x20 #include "ixp46x_ts.h" @@ -147,6 +151,16 @@ typedef void buffer_t; #define free_buffer_irq kfree #endif +/* Information about built-in Ethernet MAC interfaces */ +struct eth_plat_info { + u8 phy; /* MII PHY ID, 0 - 31 */ + u8 rxq; /* configurable, currently 0 - 31 only */ + u8 txreadyq; + u8 hwaddr[6]; + u8 npe; /* NPE instance used by this interface */ + bool has_mdio; /* If this instance has an MDIO bus */ +}; + struct eth_regs { u32 tx_control[2], __res1[2]; /* 000 */ u32 rx_control[2], __res2[2]; /* 010 */ @@ -1366,7 +1380,6 @@ static const struct net_device_ops ixp4xx_netdev_ops = { .ndo_validate_addr = eth_validate_addr, }; -#ifdef CONFIG_OF static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev) { struct device_node *np = dev->of_node; @@ -1417,12 +1430,6 @@ static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev) return plat; } -#else -static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev) -{ - return NULL; -} -#endif static int ixp4xx_eth_probe(struct platform_device *pdev) { @@ -1434,49 +1441,9 @@ static int ixp4xx_eth_probe(struct platform_device *pdev) struct port *port; int err; - if (np) { - plat = ixp4xx_of_get_platdata(dev); - if (!plat) - return -ENODEV; - } else { - plat = dev_get_platdata(dev); - if (!plat) - return -ENODEV; - plat->npe = pdev->id; - switch (plat->npe) { - case IXP4XX_ETH_NPEA: - /* If the MDIO bus is not up yet, defer probe */ - break; - case IXP4XX_ETH_NPEB: - /* On all except IXP43x, NPE-B is used for the MDIO bus. - * If there is no NPE-B in the feature set, bail out, - * else we have the MDIO bus here. - */ - if (!cpu_is_ixp43x()) { - if (!(ixp4xx_read_feature_bits() & - IXP4XX_FEATURE_NPEB_ETH0)) - return -ENODEV; - /* Else register the MDIO bus on NPE-B */ - plat->has_mdio = true; - } - break; - case IXP4XX_ETH_NPEC: - /* IXP43x lacks NPE-B and uses NPE-C for the MDIO bus - * access, if there is no NPE-C, no bus, nothing works, - * so bail out. - */ - if (cpu_is_ixp43x()) { - if (!(ixp4xx_read_feature_bits() & - IXP4XX_FEATURE_NPEC_ETH)) - return -ENODEV; - /* Else register the MDIO bus on NPE-B */ - plat->has_mdio = true; - } - break; - default: - return -ENODEV; - } - } + plat = ixp4xx_of_get_platdata(dev); + if (!plat) + return -ENODEV; if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port)))) return -ENOMEM; @@ -1530,21 +1497,7 @@ static int ixp4xx_eth_probe(struct platform_device *pdev) __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control); udelay(50); - if (np) { - phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link); - } else { - phydev = mdiobus_get_phy(mdio_bus, plat->phy); - if (!phydev) { - err = -ENODEV; - dev_err(dev, "could not connect phydev (%d)\n", err); - goto err_free_mem; - } - err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link, - PHY_INTERFACE_MODE_MII); - if (err) - goto err_free_mem; - - } + phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link); if (!phydev) { err = -ENODEV; dev_err(dev, "no phydev\n"); diff --git a/drivers/net/ethernet/xscale/ptp_ixp46x.c b/drivers/net/ethernet/xscale/ptp_ixp46x.c index 39234852e01b..1f382777aa5a 100644 --- a/drivers/net/ethernet/xscale/ptp_ixp46x.c +++ b/drivers/net/ethernet/xscale/ptp_ixp46x.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "ixp46x_ts.h" diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig index 592a8389fc5a..140780ac1745 100644 --- a/drivers/net/wan/Kconfig +++ b/drivers/net/wan/Kconfig @@ -293,7 +293,8 @@ config SLIC_DS26522 config IXP4XX_HSS tristate "Intel IXP4xx HSS (synchronous serial port) support" depends on HDLC && IXP4XX_NPE && IXP4XX_QMGR - depends on ARCH_IXP4XX + depends on ARCH_IXP4XX && OF + select MFD_SYSCON help Say Y here if you want to use built-in HSS ports on IXP4xx processor. diff --git a/drivers/net/wan/ixp4xx_hss.c b/drivers/net/wan/ixp4xx_hss.c index 0b7d9f2f2b8b..863c3e34e136 100644 --- a/drivers/net/wan/ixp4xx_hss.c +++ b/drivers/net/wan/ixp4xx_hss.c @@ -16,8 +16,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -1389,9 +1391,28 @@ static int ixp4xx_hss_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct net_device *ndev; struct device_node *np; + struct regmap *rmap; struct port *port; hdlc_device *hdlc; int err; + u32 val; + + /* + * Go into the syscon and check if we have the HSS and HDLC + * features available, else this will not work. + */ + rmap = syscon_regmap_lookup_by_compatible("syscon"); + if (IS_ERR(rmap)) + return dev_err_probe(dev, PTR_ERR(rmap), + "failed to look up syscon\n"); + + val = cpu_ixp4xx_features(rmap); + + if ((val & (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) != + (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) { + dev_err(dev, "HDLC and HSS feature unavailable in platform\n"); + return -ENODEV; + } np = dev->of_node; @@ -1516,25 +1537,9 @@ static struct platform_driver ixp4xx_hss_driver = { .probe = ixp4xx_hss_probe, .remove = ixp4xx_hss_remove, }; - -static int __init hss_init_module(void) -{ - if ((ixp4xx_read_feature_bits() & - (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) != - (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) - return -ENODEV; - - return platform_driver_register(&ixp4xx_hss_driver); -} - -static void __exit hss_cleanup_module(void) -{ - platform_driver_unregister(&ixp4xx_hss_driver); -} +module_platform_driver(ixp4xx_hss_driver); MODULE_AUTHOR("Krzysztof Halasa"); MODULE_DESCRIPTION("Intel IXP4xx HSS driver"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("platform:ixp4xx_hss"); -module_init(hss_init_module); -module_exit(hss_cleanup_module); diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index ab53eab635f6..2ce261cfff8e 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -210,7 +210,7 @@ config PCMCIA_PXA2XX depends on ARM && ARCH_PXA && PCMCIA depends on (ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL \ || ARCH_PXA_PALM || TRIZEPS_PCMCIA \ - || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2 \ + || ARCOM_PCMCIA || ARCH_PXA_ESERIES \ || MACH_VPAC270 || MACH_BALLOON3 || MACH_COLIBRI \ || MACH_COLIBRI320 || MACH_H4700) select PCMCIA_SOC_COMMON diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 2d5657cfc49c..c43267b18f55 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -56,7 +56,6 @@ pxa2xx-obj-$(CONFIG_MACH_PALMTX) += pxa2xx_palmtx.o pxa2xx-obj-$(CONFIG_MACH_PALMTC) += pxa2xx_palmtc.o pxa2xx-obj-$(CONFIG_MACH_PALMLD) += pxa2xx_palmld.o pxa2xx-obj-$(CONFIG_MACH_E740) += pxa2xx_e740.o -pxa2xx-obj-$(CONFIG_MACH_STARGATE2) += pxa2xx_stargate2.o pxa2xx-obj-$(CONFIG_MACH_VPAC270) += pxa2xx_vpac270.o pxa2xx-obj-$(CONFIG_MACH_BALLOON3) += pxa2xx_balloon3.o pxa2xx-obj-$(CONFIG_MACH_COLIBRI) += pxa2xx_colibri.o diff --git a/drivers/pcmcia/pxa2xx_stargate2.c b/drivers/pcmcia/pxa2xx_stargate2.c deleted file mode 100644 index 6efb7f814b4a..000000000000 --- a/drivers/pcmcia/pxa2xx_stargate2.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/drivers/pcmcia/pxa2xx_stargate2.c - * - * Stargate 2 PCMCIA specific routines. - * - * Created: December 6, 2005 - * Author: Ed C. Epp - * Copyright: Intel Corp 2005 - * Jonathan Cameron 2009 - */ - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include "soc_common.h" - -#define SG2_S0_POWER_CTL 108 -#define SG2_S0_GPIO_RESET 82 -#define SG2_S0_GPIO_DETECT 53 -#define SG2_S0_GPIO_READY 81 - -static struct gpio sg2_pcmcia_gpios[] = { - { SG2_S0_GPIO_RESET, GPIOF_OUT_INIT_HIGH, "PCMCIA Reset" }, - { SG2_S0_POWER_CTL, GPIOF_OUT_INIT_HIGH, "PCMCIA Power Ctrl" }, -}; - -static int sg2_pcmcia_hw_init(struct soc_pcmcia_socket *skt) -{ - skt->stat[SOC_STAT_CD].gpio = SG2_S0_GPIO_DETECT; - skt->stat[SOC_STAT_CD].name = "PCMCIA0 CD"; - skt->stat[SOC_STAT_RDY].gpio = SG2_S0_GPIO_READY; - skt->stat[SOC_STAT_RDY].name = "PCMCIA0 RDY"; - return 0; -} - -static void sg2_pcmcia_socket_state(struct soc_pcmcia_socket *skt, - struct pcmcia_state *state) -{ - state->bvd1 = 0; /* not available - battery detect on card */ - state->bvd2 = 0; /* not available */ - state->vs_3v = 1; /* not available - voltage detect for card */ - state->vs_Xv = 0; /* not available */ -} - -static int sg2_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, - const socket_state_t *state) -{ - /* Enable card power */ - switch (state->Vcc) { - case 0: - /* sets power ctl register high */ - gpio_set_value(SG2_S0_POWER_CTL, 1); - break; - case 33: - case 50: - /* sets power control register low (clear) */ - gpio_set_value(SG2_S0_POWER_CTL, 0); - msleep(100); - break; - default: - pr_err("%s(): bad Vcc %u\n", - __func__, state->Vcc); - return -1; - } - - /* reset */ - gpio_set_value(SG2_S0_GPIO_RESET, !!(state->flags & SS_RESET)); - - return 0; -} - -static struct pcmcia_low_level sg2_pcmcia_ops __initdata = { - .owner = THIS_MODULE, - .hw_init = sg2_pcmcia_hw_init, - .socket_state = sg2_pcmcia_socket_state, - .configure_socket = sg2_pcmcia_configure_socket, - .nr = 1, -}; - -static struct platform_device *sg2_pcmcia_device; - -static int __init sg2_pcmcia_init(void) -{ - int ret; - - if (!machine_is_stargate2()) - return -ENODEV; - - sg2_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1); - if (!sg2_pcmcia_device) - return -ENOMEM; - - ret = gpio_request_array(sg2_pcmcia_gpios, ARRAY_SIZE(sg2_pcmcia_gpios)); - if (ret) - goto error_put_platform_device; - - ret = platform_device_add_data(sg2_pcmcia_device, - &sg2_pcmcia_ops, - sizeof(sg2_pcmcia_ops)); - if (ret) - goto error_free_gpios; - - ret = platform_device_add(sg2_pcmcia_device); - if (ret) - goto error_free_gpios; - - return 0; -error_free_gpios: - gpio_free_array(sg2_pcmcia_gpios, ARRAY_SIZE(sg2_pcmcia_gpios)); -error_put_platform_device: - platform_device_put(sg2_pcmcia_device); - - return ret; -} - -static void __exit sg2_pcmcia_exit(void) -{ - platform_device_unregister(sg2_pcmcia_device); - gpio_free_array(sg2_pcmcia_gpios, ARRAY_SIZE(sg2_pcmcia_gpios)); -} - -fs_initcall(sg2_pcmcia_init); -module_exit(sg2_pcmcia_exit); - -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:pxa2xx-pcmcia"); diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 2e490e7696f4..4102ce955bd7 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -585,13 +585,11 @@ static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { /* pin-controller instance 0 ALIVE data */ .pin_banks = exynos850_pin_banks0, .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, }, { /* pin-controller instance 1 CMGP data */ .pin_banks = exynos850_pin_banks1, .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, .eint_wkup_init = exynos_eint_wkup_init, }, { /* pin-controller instance 2 AUD data */ diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 0489c899b401..a158d587814e 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -465,6 +465,10 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { .data = &exynos4210_wkup_irq_chip }, { .compatible = "samsung,exynos7-wakeup-eint", .data = &exynos7_wkup_irq_chip }, + { .compatible = "samsung,exynos850-wakeup-eint", + .data = &exynos7_wkup_irq_chip }, + { .compatible = "samsung,exynosautov9-wakeup-eint", + .data = &exynos7_wkup_irq_chip }, { } }; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 0f6e9305fec5..568b6e65dfed 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1002,13 +1002,66 @@ samsung_pinctrl_get_soc_data_for_of_alias(struct platform_device *pdev) return &(of_data->ctrl[id]); } +static void samsung_banks_of_node_put(struct samsung_pinctrl_drv_data *d) +{ + struct samsung_pin_bank *bank; + unsigned int i; + + bank = d->pin_banks; + for (i = 0; i < d->nr_banks; ++i, ++bank) + of_node_put(bank->of_node); +} + +/* + * Iterate over all driver pin banks to find one matching the name of node, + * skipping optional "-gpio" node suffix. When found, assign node to the bank. + */ +static void samsung_banks_of_node_get(struct device *dev, + struct samsung_pinctrl_drv_data *d, + struct device_node *node) +{ + const char *suffix = "-gpio-bank"; + struct samsung_pin_bank *bank; + struct device_node *child; + /* Pin bank names are up to 4 characters */ + char node_name[20]; + unsigned int i; + size_t len; + + bank = d->pin_banks; + for (i = 0; i < d->nr_banks; ++i, ++bank) { + strscpy(node_name, bank->name, sizeof(node_name)); + len = strlcat(node_name, suffix, sizeof(node_name)); + if (len >= sizeof(node_name)) { + dev_err(dev, "Too long pin bank name '%s', ignoring\n", + bank->name); + continue; + } + + for_each_child_of_node(node, child) { + if (!of_find_property(child, "gpio-controller", NULL)) + continue; + if (of_node_name_eq(child, node_name)) + break; + else if (of_node_name_eq(child, bank->name)) + break; + } + + if (child) + bank->of_node = child; + else + dev_warn(dev, "Missing node for bank %s - invalid DTB\n", + bank->name); + /* child reference dropped in samsung_drop_banks_of_node() */ + } +} + /* retrieve the soc specific data */ static const struct samsung_pin_ctrl * samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; - struct device_node *np; const struct samsung_pin_bank_data *bdata; const struct samsung_pin_ctrl *ctrl; struct samsung_pin_bank *bank; @@ -1072,17 +1125,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, */ d->virt_base = virt_base[0]; - for_each_child_of_node(node, np) { - if (!of_find_property(np, "gpio-controller", NULL)) - continue; - bank = d->pin_banks; - for (i = 0; i < d->nr_banks; ++i, ++bank) { - if (of_node_name_eq(np, bank->name)) { - bank->of_node = np; - break; - } - } - } + samsung_banks_of_node_get(&pdev->dev, d, node); d->pin_base = pin_base; pin_base += d->nr_pins; @@ -1117,19 +1160,19 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) if (ctrl->retention_data) { drvdata->retention_ctrl = ctrl->retention_data->init(drvdata, ctrl->retention_data); - if (IS_ERR(drvdata->retention_ctrl)) - return PTR_ERR(drvdata->retention_ctrl); + if (IS_ERR(drvdata->retention_ctrl)) { + ret = PTR_ERR(drvdata->retention_ctrl); + goto err_put_banks; + } } ret = samsung_pinctrl_register(pdev, drvdata); if (ret) - return ret; + goto err_put_banks; ret = samsung_gpiolib_register(pdev, drvdata); - if (ret) { - samsung_pinctrl_unregister(pdev, drvdata); - return ret; - } + if (ret) + goto err_unregister; if (ctrl->eint_gpio_init) ctrl->eint_gpio_init(drvdata); @@ -1139,6 +1182,12 @@ static int samsung_pinctrl_probe(struct platform_device *pdev) platform_set_drvdata(pdev, drvdata); return 0; + +err_unregister: + samsung_pinctrl_unregister(pdev, drvdata); +err_put_banks: + samsung_banks_of_node_put(drvdata); + return ret; } /* diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c index 43ea8455546c..a2c231a17b2b 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -928,7 +928,8 @@ static void q6v5proc_halt_axi_port(struct q6v5 *qproc, regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); } -static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw) +static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw, + const char *fw_name) { unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; dma_addr_t phys; @@ -939,7 +940,7 @@ static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw) void *ptr; int ret; - metadata = qcom_mdt_read_metadata(fw, &size); + metadata = qcom_mdt_read_metadata(fw, &size, fw_name, qproc->dev); if (IS_ERR(metadata)) return PTR_ERR(metadata); @@ -1289,7 +1290,7 @@ static int q6v5_mpss_load(struct q6v5 *qproc) /* Initialize the RMB validator */ writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); - ret = q6v5_mpss_init_image(qproc, fw); + ret = q6v5_mpss_init_image(qproc, fw, qproc->hexagon_mdt_image); if (ret) goto release_firmware; diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index 184bb7cdf95a..1ae47cc153e5 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -79,6 +79,8 @@ struct qcom_adsp { struct qcom_rproc_subdev smd_subdev; struct qcom_rproc_ssr ssr_subdev; struct qcom_sysmon *sysmon; + + struct qcom_scm_pas_metadata pas_metadata; }; static void adsp_minidump(struct rproc *rproc) @@ -126,14 +128,34 @@ static void adsp_pds_disable(struct qcom_adsp *adsp, struct device **pds, } } +static int adsp_unprepare(struct rproc *rproc) +{ + struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; + + /* + * adsp_load() did pass pas_metadata to the SCM driver for storing + * metadata context. It might have been released already if + * auth_and_reset() was successful, but in other cases clean it up + * here. + */ + qcom_scm_pas_metadata_release(&adsp->pas_metadata); + + return 0; +} + static int adsp_load(struct rproc *rproc, const struct firmware *fw) { struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv; int ret; - ret = qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id, - adsp->mem_region, adsp->mem_phys, adsp->mem_size, - &adsp->mem_reloc); + ret = qcom_mdt_pas_init(adsp->dev, fw, rproc->firmware, adsp->pas_id, + adsp->mem_phys, &adsp->pas_metadata); + if (ret) + return ret; + + ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, adsp->pas_id, + adsp->mem_region, adsp->mem_phys, adsp->mem_size, + &adsp->mem_reloc); if (ret) return ret; @@ -185,6 +207,8 @@ static int adsp_start(struct rproc *rproc) goto disable_px_supply; } + qcom_scm_pas_metadata_release(&adsp->pas_metadata); + return 0; disable_px_supply: @@ -255,6 +279,7 @@ static unsigned long adsp_panic(struct rproc *rproc) } static const struct rproc_ops adsp_ops = { + .unprepare = adsp_unprepare, .start = adsp_start, .stop = adsp_stop, .da_to_va = adsp_da_to_va, @@ -264,6 +289,7 @@ static const struct rproc_ops adsp_ops = { }; static const struct rproc_ops adsp_minidump_ops = { + .unprepare = adsp_unprepare, .start = adsp_start, .stop = adsp_stop, .da_to_va = adsp_da_to_va, @@ -853,6 +879,10 @@ static const struct of_device_id adsp_of_match[] = { { .compatible = "qcom,sm8350-cdsp-pas", .data = &sm8350_cdsp_resource}, { .compatible = "qcom,sm8350-slpi-pas", .data = &sm8350_slpi_resource}, { .compatible = "qcom,sm8350-mpss-pas", .data = &mpss_resource_init}, + { .compatible = "qcom,sm8450-adsp-pas", .data = &sm8350_adsp_resource}, + { .compatible = "qcom,sm8450-cdsp-pas", .data = &sm8350_cdsp_resource}, + { .compatible = "qcom,sm8450-slpi-pas", .data = &sm8350_slpi_resource}, + { .compatible = "qcom,sm8450-mpss-pas", .data = &mpss_resource_init}, { }, }; MODULE_DEVICE_TABLE(of, adsp_of_match); diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c index 6b43e97bd417..aaa2376b9d34 100644 --- a/drivers/scsi/sg.c +++ b/drivers/scsi/sg.c @@ -224,11 +224,6 @@ static int sg_check_file_access(struct file *filp, const char *caller) caller, task_tgid_vnr(current), current->comm); return -EPERM; } - if (uaccess_kernel()) { - pr_err_once("%s: process %d (%s) called from kernel context, this is not allowed.\n", - caller, task_tgid_vnr(current), current->comm); - return -EACCES; - } return 0; } diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index a8562678c437..c5aae42673d3 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -13,6 +13,7 @@ source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" source "drivers/soc/litex/Kconfig" source "drivers/soc/mediatek/Kconfig" +source "drivers/soc/microchip/Kconfig" source "drivers/soc/qcom/Kconfig" source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index adb30c2d4fea..904eec2a7871 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -18,6 +18,7 @@ obj-y += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/ obj-y += mediatek/ +obj-y += microchip/ obj-y += amlogic/ obj-y += qcom/ obj-y += renesas/ diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c b/drivers/soc/amlogic/meson-secure-pwrc.c index 59bd195fa9c9..a10a417a87db 100644 --- a/drivers/soc/amlogic/meson-secure-pwrc.c +++ b/drivers/soc/amlogic/meson-secure-pwrc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -119,6 +120,18 @@ static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = { SEC_PD(RSA, 0), }; +static struct meson_secure_pwrc_domain_desc s4_pwrc_domains[] = { + SEC_PD(S4_DOS_HEVC, 0), + SEC_PD(S4_DOS_VDEC, 0), + SEC_PD(S4_VPU_HDMI, 0), + SEC_PD(S4_USB_COMB, 0), + SEC_PD(S4_GE2D, 0), + /* ETH is for ethernet online wakeup, and should be always on */ + SEC_PD(S4_ETH, GENPD_FLAG_ALWAYS_ON), + SEC_PD(S4_DEMOD, 0), + SEC_PD(S4_AUDIO, 0), +}; + static int meson_secure_pwrc_probe(struct platform_device *pdev) { int i; @@ -187,11 +200,20 @@ static struct meson_secure_pwrc_domain_data meson_secure_a1_pwrc_data = { .count = ARRAY_SIZE(a1_pwrc_domains), }; +static struct meson_secure_pwrc_domain_data meson_secure_s4_pwrc_data = { + .domains = s4_pwrc_domains, + .count = ARRAY_SIZE(s4_pwrc_domains), +}; + static const struct of_device_id meson_secure_pwrc_match_table[] = { { .compatible = "amlogic,meson-a1-pwrc", .data = &meson_secure_a1_pwrc_data, }, + { + .compatible = "amlogic,meson-s4-pwrc", + .data = &meson_secure_s4_pwrc_data, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, meson_secure_pwrc_match_table); diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index a490ad7e090f..b2d365ae0282 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -156,6 +156,9 @@ static const struct at91_soc socs[] __initconst = { AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH, "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"), + AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK, + AT91_CIDR_VERSION_MASK, SAMA5D29CN_EXID_MATCH, + "sama5d29", "sama5d2"), AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH, "sama5d31", "sama5d3"), diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index c3eb3c8f0834..2ecaa75b00f0 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -95,6 +95,7 @@ at91_soc_init(const struct at91_soc *socs); #define SAMA5D28C_LD2G_EXID_MATCH 0x00000072 #define SAMA5D28CU_EXID_MATCH 0x00000010 #define SAMA5D28CN_EXID_MATCH 0x00000020 +#define SAMA5D29CN_EXID_MATCH 0x00000023 #define SAMA5D3_CIDR_MATCH 0x0a5c07c0 #define SAMA5D31_EXID_MATCH 0x00444300 diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index 511e74f0db8a..122f9c884b38 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -15,6 +15,7 @@ #include #include +#include #define BLK_SFT_RSTN 0x0 #define BLK_CLK_EN 0x4 @@ -589,6 +590,68 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data), }; +static int imx8mq_vpu_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, + power_nb); + + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) + return NOTIFY_OK; + + /* + * The ADB in the VPUMIX domain has no separate reset and clock + * enable bits, but is ungated and reset together with the VPUs. The + * reset and clock enable inputs to the ADB is a logical OR of the + * VPU bits. In order to set the G2 fuse bits, the G2 clock must + * also be enabled. + */ + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1)); + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1)); + + if (action == GENPD_NOTIFY_ON) { + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ + udelay(5); + + /* set "fuse" bits to enable the VPUs */ + regmap_set_bits(bc->regmap, 0x8, 0xffffffff); + regmap_set_bits(bc->regmap, 0xc, 0xffffffff); + regmap_set_bits(bc->regmap, 0x10, 0xffffffff); + } + + return NOTIFY_OK; +} + +static const struct imx8m_blk_ctrl_domain_data imx8mq_vpu_blk_ctl_domain_data[] = { + [IMX8MQ_VPUBLK_PD_G1] = { + .name = "vpublk-g1", + .clk_names = (const char *[]){ "g1", }, + .num_clks = 1, + .gpc_name = "g1", + .rst_mask = BIT(1), + .clk_mask = BIT(1), + }, + [IMX8MQ_VPUBLK_PD_G2] = { + .name = "vpublk-g2", + .clk_names = (const char *[]){ "g2", }, + .num_clks = 1, + .gpc_name = "g2", + .rst_mask = BIT(0), + .clk_mask = BIT(0), + }, +}; + +static const struct imx8m_blk_ctrl_data imx8mq_vpu_blk_ctl_dev_data = { + .max_reg = 0x14, + .power_notifier_fn = imx8mq_vpu_power_notifier, + .domains = imx8mq_vpu_blk_ctl_domain_data, + .num_domains = ARRAY_SIZE(imx8mq_vpu_blk_ctl_domain_data), +}; + static const struct of_device_id imx8m_blk_ctrl_of_match[] = { { .compatible = "fsl,imx8mm-vpu-blk-ctrl", @@ -599,6 +662,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { }, { .compatible = "fsl,imx8mn-disp-blk-ctrl", .data = &imx8mn_disp_blk_ctl_dev_data + }, { + .compatible = "fsl,imx8mq-vpu-blk-ctrl", + .data = &imx8mq_vpu_blk_ctl_dev_data }, { /* Sentinel */ } diff --git a/drivers/soc/imx/soc-imx.c b/drivers/soc/imx/soc-imx.c index 77bc12039c3d..fab668c83f98 100644 --- a/drivers/soc/imx/soc-imx.c +++ b/drivers/soc/imx/soc-imx.c @@ -40,9 +40,6 @@ static int __init imx_soc_device_init(void) if (!__mxc_cpu_type) return 0; - if (of_machine_is_compatible("fsl,ls1021a")) - return 0; - soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); if (!soc_dev_attr) return -ENOMEM; diff --git a/drivers/soc/ixp4xx/Kconfig b/drivers/soc/ixp4xx/Kconfig index e3eb19b85fa4..c55f0c9ae513 100644 --- a/drivers/soc/ixp4xx/Kconfig +++ b/drivers/soc/ixp4xx/Kconfig @@ -12,6 +12,7 @@ config IXP4XX_QMGR config IXP4XX_NPE tristate "IXP4xx Network Processor Engine support" select FW_LOADER + select MFD_SYSCON help This driver supports IXP4xx built-in network coprocessors and is automatically selected by Ethernet and HSS drivers. diff --git a/drivers/soc/ixp4xx/ixp4xx-npe.c b/drivers/soc/ixp4xx/ixp4xx-npe.c index f490c4ca51f5..613935cb6a48 100644 --- a/drivers/soc/ixp4xx/ixp4xx-npe.c +++ b/drivers/soc/ixp4xx/ixp4xx-npe.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -284,6 +285,7 @@ static int __must_check npe_logical_reg_write32(struct npe *npe, u32 addr, static int npe_reset(struct npe *npe) { + u32 reset_bit = (IXP4XX_FEATURE_RESET_NPEA << npe->id); u32 val, ctl, exec_count, ctx_reg2; int i; @@ -380,16 +382,19 @@ static int npe_reset(struct npe *npe) __raw_writel(0, &npe->regs->action_points[3]); __raw_writel(0, &npe->regs->watch_count); - val = ixp4xx_read_feature_bits(); + /* + * We need to work on cached values here because the register + * will read inverted but needs to be written non-inverted. + */ + val = cpu_ixp4xx_features(npe->rmap); /* reset the NPE */ - ixp4xx_write_feature_bits(val & - ~(IXP4XX_FEATURE_RESET_NPEA << npe->id)); + regmap_write(npe->rmap, IXP4XX_EXP_CNFG2, val & ~reset_bit); /* deassert reset */ - ixp4xx_write_feature_bits(val | - (IXP4XX_FEATURE_RESET_NPEA << npe->id)); + regmap_write(npe->rmap, IXP4XX_EXP_CNFG2, val | reset_bit); + for (i = 0; i < MAX_RETRIES; i++) { - if (ixp4xx_read_feature_bits() & - (IXP4XX_FEATURE_RESET_NPEA << npe->id)) + val = cpu_ixp4xx_features(npe->rmap); + if (val & reset_bit) break; /* NPE is back alive */ udelay(1); } @@ -683,6 +688,14 @@ static int ixp4xx_npe_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct resource *res; + struct regmap *rmap; + u32 val; + + /* This system has only one syscon, so fetch it */ + rmap = syscon_regmap_lookup_by_compatible("syscon"); + if (IS_ERR(rmap)) + return dev_err_probe(dev, PTR_ERR(rmap), + "failed to look up syscon\n"); for (i = 0; i < NPE_COUNT; i++) { struct npe *npe = &npe_tab[i]; @@ -691,8 +704,9 @@ static int ixp4xx_npe_probe(struct platform_device *pdev) if (!res) return -ENODEV; - if (!(ixp4xx_read_feature_bits() & - (IXP4XX_FEATURE_RESET_NPEA << i))) { + val = cpu_ixp4xx_features(rmap); + + if (!(val & (IXP4XX_FEATURE_RESET_NPEA << i))) { dev_info(dev, "NPE%d at %pR not available\n", i, res); continue; /* NPE already disabled or not present */ @@ -700,6 +714,7 @@ static int ixp4xx_npe_probe(struct platform_device *pdev) npe->regs = devm_ioremap_resource(dev, res); if (IS_ERR(npe->regs)) return PTR_ERR(npe->regs); + npe->rmap = rmap; if (npe_reset(npe)) { dev_info(dev, "NPE%d at %pR does not reset\n", diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h b/drivers/soc/mediatek/mt8167-pm-domains.h index 15559ddf26e4..4d6c32759606 100644 --- a/drivers/soc/mediatek/mt8167-pm-domains.h +++ b/drivers/soc/mediatek/mt8167-pm-domains.h @@ -18,6 +18,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "mm", .sta_mask = PWR_STATUS_DISP, .ctl_offs = SPM_DIS_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -30,6 +32,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "vdec", .sta_mask = PWR_STATUS_VDEC, .ctl_offs = SPM_VDE_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .caps = MTK_SCPD_ACTIVE_WAKEUP, @@ -38,6 +42,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "isp", .sta_mask = PWR_STATUS_ISP, .ctl_offs = SPM_ISP_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), .caps = MTK_SCPD_ACTIVE_WAKEUP, @@ -46,6 +52,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "mfg_async", .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC, .ctl_offs = SPM_MFG_ASYNC_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, .bp_infracfg = { @@ -57,6 +65,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "mfg_2d", .sta_mask = MT8167_PWR_STATUS_MFG_2D, .ctl_offs = SPM_MFG_2D_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -64,6 +74,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "mfg", .sta_mask = PWR_STATUS_MFG, .ctl_offs = SPM_MFG_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -71,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "conn", .sta_mask = PWR_STATUS_CONN, .ctl_offs = SPM_CONN_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = 0, .caps = MTK_SCPD_ACTIVE_WAKEUP, @@ -85,8 +99,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { static const struct scpsys_soc_data mt8167_scpsys_data = { .domains_data = scpsys_domain_data_mt8167, .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167), - .pwr_sta_offs = SPM_PWR_STATUS, - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, }; #endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h index 714fa92575df..1a5dc63b7357 100644 --- a/drivers/soc/mediatek/mt8173-pm-domains.h +++ b/drivers/soc/mediatek/mt8173-pm-domains.h @@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "vdec", .sta_mask = PWR_STATUS_VDEC, .ctl_offs = SPM_VDE_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -22,6 +24,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "venc", .sta_mask = PWR_STATUS_VENC, .ctl_offs = SPM_VEN_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -29,6 +33,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "isp", .sta_mask = PWR_STATUS_ISP, .ctl_offs = SPM_ISP_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), }, @@ -36,6 +42,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "mm", .sta_mask = PWR_STATUS_DISP, .ctl_offs = SPM_DIS_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -47,6 +55,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "venc_lt", .sta_mask = PWR_STATUS_VENC_LT, .ctl_offs = SPM_VEN2_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -54,6 +64,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "audio", .sta_mask = PWR_STATUS_AUDIO, .ctl_offs = SPM_AUDIO_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -61,6 +73,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "usb", .sta_mask = PWR_STATUS_USB, .ctl_offs = SPM_USB_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), .caps = MTK_SCPD_ACTIVE_WAKEUP, @@ -69,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "mfg_async", .sta_mask = PWR_STATUS_MFG_ASYNC, .ctl_offs = SPM_MFG_ASYNC_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = 0, .caps = MTK_SCPD_DOMAIN_SUPPLY, @@ -77,6 +93,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "mfg_2d", .sta_mask = PWR_STATUS_MFG_2D, .ctl_offs = SPM_MFG_2D_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), }, @@ -84,6 +102,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "mfg", .sta_mask = PWR_STATUS_MFG, .ctl_offs = SPM_MFG_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(13, 8), .sram_pdn_ack_bits = GENMASK(21, 16), .bp_infracfg = { @@ -98,8 +118,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { static const struct scpsys_soc_data mt8173_scpsys_data = { .domains_data = scpsys_domain_data_mt8173, .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173), - .pwr_sta_offs = SPM_PWR_STATUS, - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, }; #endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h index 9dee485807c9..0c021f4b76d2 100644 --- a/drivers/soc/mediatek/mt8183-mmsys.h +++ b/drivers/soc/mediatek/mt8183-mmsys.h @@ -25,6 +25,8 @@ #define MT8183_RDMA0_SOUT_COLOR0 0x1 #define MT8183_RDMA1_SOUT_DSI0 0x1 +#define MT8183_MMSYS_SW0_RST_B 0x140 + static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = { { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, diff --git a/drivers/soc/mediatek/mt8183-pm-domains.h b/drivers/soc/mediatek/mt8183-pm-domains.h index 98a9940d05fb..71b8757e552d 100644 --- a/drivers/soc/mediatek/mt8183-pm-domains.h +++ b/drivers/soc/mediatek/mt8183-pm-domains.h @@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "audio", .sta_mask = PWR_STATUS_AUDIO, .ctl_offs = 0x0314, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -22,6 +24,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "conn", .sta_mask = PWR_STATUS_CONN, .ctl_offs = 0x032c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, .bp_infracfg = { @@ -33,6 +37,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "mfg_async", .sta_mask = PWR_STATUS_MFG_ASYNC, .ctl_offs = 0x0334, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, }, @@ -40,6 +46,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "mfg", .sta_mask = PWR_STATUS_MFG, .ctl_offs = 0x0338, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .caps = MTK_SCPD_DOMAIN_SUPPLY, @@ -48,6 +56,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "mfg_core0", .sta_mask = BIT(7), .ctl_offs = 0x034c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -55,6 +65,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "mfg_core1", .sta_mask = BIT(20), .ctl_offs = 0x0310, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -62,6 +74,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "mfg_2d", .sta_mask = PWR_STATUS_MFG_2D, .ctl_offs = 0x0348, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -75,6 +89,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "disp", .sta_mask = PWR_STATUS_DISP, .ctl_offs = 0x030c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -94,6 +110,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "cam", .sta_mask = BIT(25), .ctl_offs = 0x0344, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(9, 8), .sram_pdn_ack_bits = GENMASK(13, 12), .bp_infracfg = { @@ -117,6 +135,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "isp", .sta_mask = PWR_STATUS_ISP, .ctl_offs = 0x0308, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(9, 8), .sram_pdn_ack_bits = GENMASK(13, 12), .bp_infracfg = { @@ -140,6 +160,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "vdec", .sta_mask = BIT(31), .ctl_offs = 0x0300, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_smi = { @@ -153,6 +175,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "venc", .sta_mask = PWR_STATUS_VENC, .ctl_offs = 0x0304, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), .bp_smi = { @@ -166,6 +190,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "vpu_top", .sta_mask = BIT(26), .ctl_offs = 0x0324, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -193,6 +219,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "vpu_core0", .sta_mask = BIT(27), .ctl_offs = 0x33c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), .bp_infracfg = { @@ -211,6 +239,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "vpu_core1", .sta_mask = BIT(28), .ctl_offs = 0x0340, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), .bp_infracfg = { @@ -230,8 +260,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { static const struct scpsys_soc_data mt8183_scpsys_data = { .domains_data = scpsys_domain_data_mt8183, .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183), - .pwr_sta_offs = 0x0180, - .pwr_sta2nd_offs = 0x0184 }; #endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h new file mode 100644 index 000000000000..c72ccf86ea28 --- /dev/null +++ b/drivers/soc/mediatek/mt8186-mmsys.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H +#define __SOC_MEDIATEK_MT8186_MMSYS_H + +#define MT8186_MMSYS_OVL_CON 0xF04 +#define MT8186_MMSYS_OVL0_CON_MASK 0x3 +#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC +#define MT8186_OVL0_GO_BLEND BIT(0) +#define MT8186_OVL0_GO_BG BIT(1) +#define MT8186_OVL0_2L_GO_BLEND BIT(2) +#define MT8186_OVL0_2L_GO_BG BIT(3) +#define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C +#define MT8186_RDMA0_SOUT_SEL_MASK 0xF +#define MT8186_RDMA0_SOUT_TO_DSI0 (0) +#define MT8186_RDMA0_SOUT_TO_COLOR0 (1) +#define MT8186_RDMA0_SOUT_TO_DPI0 (2) +#define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14 +#define MT8186_OVL0_2L_MOUT_EN_MASK 0xF +#define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0) +#define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3) +#define MT8186_DISP_OVL0_MOUT_EN 0xF18 +#define MT8186_OVL0_MOUT_EN_MASK 0xF +#define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0) +#define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3) +#define MT8186_DISP_DITHER0_MOUT_EN 0xF20 +#define MT8186_DITHER0_MOUT_EN_MASK 0xF +#define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0) +#define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2) +#define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3) +#define MT8186_DISP_RDMA0_SEL_IN 0xF28 +#define MT8186_RDMA0_SEL_IN_MASK 0xF +#define MT8186_RDMA0_FROM_OVL0 0 +#define MT8186_RDMA0_FROM_OVL0_2L 2 +#define MT8186_DISP_DSI0_SEL_IN 0xF30 +#define MT8186_DSI0_SEL_IN_MASK 0xF +#define MT8186_DSI0_FROM_RDMA0 0 +#define MT8186_DSI0_FROM_DITHER0 1 +#define MT8186_DSI0_FROM_RDMA1 2 +#define MT8186_DISP_RDMA1_MOUT_EN 0xF3C +#define MT8186_RDMA1_MOUT_EN_MASK 0xF +#define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0) +#define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2) +#define MT8186_DISP_RDMA1_SEL_IN 0xF40 +#define MT8186_RDMA1_SEL_IN_MASK 0xF +#define MT8186_RDMA1_FROM_OVL0 0 +#define MT8186_RDMA1_FROM_OVL0_2L 2 +#define MT8186_RDMA1_FROM_DITHER0 3 +#define MT8186_DISP_DPI0_SEL_IN 0xF44 +#define MT8186_DPI0_SEL_IN_MASK 0xF +#define MT8186_DPI0_FROM_RDMA1 0 +#define MT8186_DPI0_FROM_DITHER0 1 +#define MT8186_DPI0_FROM_RDMA0 2 + +#define MT8186_MMSYS_SW0_RST_B 0x160 + +static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = { + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK, + MT8186_OVL0_MOUT_TO_RDMA0 + }, + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK, + MT8186_RDMA0_FROM_OVL0 + }, + { + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK, + MT8186_OVL0_GO_BLEND + }, + { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK, + MT8186_RDMA0_SOUT_TO_COLOR0 + }, + { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK, + MT8186_DITHER0_MOUT_TO_DSI0, + }, + { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK, + MT8186_DSI0_FROM_DITHER0 + }, + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, + MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK, + MT8186_OVL0_2L_MOUT_TO_RDMA1 + }, + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, + MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK, + MT8186_RDMA1_FROM_OVL0_2L + }, + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1, + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK, + MT8186_OVL0_2L_GO_BLEND + }, + { + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, + MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK, + MT8186_RDMA1_MOUT_TO_DPI0_SEL + }, + { + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0, + MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK, + MT8186_DPI0_FROM_RDMA1 + }, +}; + +#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */ diff --git a/drivers/soc/mediatek/mt8186-pm-domains.h b/drivers/soc/mediatek/mt8186-pm-domains.h new file mode 100644 index 000000000000..bf2dd0cdc3a8 --- /dev/null +++ b/drivers/soc/mediatek/mt8186-pm-domains.h @@ -0,0 +1,344 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Chun-Jie Chen + */ + +#ifndef __SOC_MEDIATEK_MT8186_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8186_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8186 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8186[] = { + [MT8186_POWER_DOMAIN_MFG0] = { + .name = "mfg0", + .sta_mask = BIT(2), + .ctl_offs = 0x308, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, + }, + [MT8186_POWER_DOMAIN_MFG1] = { + .name = "mfg1", + .sta_mask = BIT(3), + .ctl_offs = 0x30c, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_MFG1_STEP3, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_MFG2] = { + .name = "mfg2", + .sta_mask = BIT(4), + .ctl_offs = 0x310, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_MFG3] = { + .name = "mfg3", + .sta_mask = BIT(5), + .ctl_offs = 0x314, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_SSUSB] = { + .name = "ssusb", + .sta_mask = BIT(20), + .ctl_offs = 0x9F0, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8186_POWER_DOMAIN_SSUSB_P1] = { + .name = "ssusb_p1", + .sta_mask = BIT(19), + .ctl_offs = 0x9F4, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8186_POWER_DOMAIN_DIS] = { + .name = "dis", + .sta_mask = BIT(21), + .ctl_offs = 0x354, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_DIS_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + }, + }, + [MT8186_POWER_DOMAIN_IMG] = { + .name = "img", + .sta_mask = BIT(13), + .ctl_offs = 0x334, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_IMG2] = { + .name = "img2", + .sta_mask = BIT(14), + .ctl_offs = 0x338, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_IPE] = { + .name = "ipe", + .sta_mask = BIT(15), + .ctl_offs = 0x33C, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(23), + .ctl_offs = 0x35C, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_CAM_RAWA] = { + .name = "cam_rawa", + .sta_mask = BIT(24), + .ctl_offs = 0x360, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_CAM_RAWB] = { + .name = "cam_rawb", + .sta_mask = BIT(25), + .ctl_offs = 0x364, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = BIT(18), + .ctl_offs = 0x348, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_VDEC] = { + .name = "vdec", + .sta_mask = BIT(16), + .ctl_offs = 0x340, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_WPE] = { + .name = "wpe", + .sta_mask = BIT(0), + .ctl_offs = 0x3F8, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1, + MT8186_TOP_AXI_PROT_EN_2_SET, + MT8186_TOP_AXI_PROT_EN_2_CLR, + MT8186_TOP_AXI_PROT_EN_2_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2, + MT8186_TOP_AXI_PROT_EN_2_SET, + MT8186_TOP_AXI_PROT_EN_2_CLR, + MT8186_TOP_AXI_PROT_EN_2_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_CONN_ON] = { + .name = "conn_on", + .sta_mask = BIT(1), + .ctl_offs = 0x304, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1, + MT8186_TOP_AXI_PROT_EN_1_SET, + MT8186_TOP_AXI_PROT_EN_1_CLR, + MT8186_TOP_AXI_PROT_EN_1_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4, + MT8186_TOP_AXI_PROT_EN_SET, + MT8186_TOP_AXI_PROT_EN_CLR, + MT8186_TOP_AXI_PROT_EN_STA), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8186_POWER_DOMAIN_CSIRX_TOP] = { + .name = "csirx_top", + .sta_mask = BIT(6), + .ctl_offs = 0x318, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_ADSP_AO] = { + .name = "adsp_ao", + .sta_mask = BIT(17), + .ctl_offs = 0x9FC, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_ADSP_INFRA] = { + .name = "adsp_infra", + .sta_mask = BIT(10), + .ctl_offs = 0x9F8, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8186_POWER_DOMAIN_ADSP_TOP] = { + .name = "adsp_top", + .sta_mask = BIT(31), + .ctl_offs = 0x3E4, + .pwr_sta_offs = 0x16C, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1, + MT8186_TOP_AXI_PROT_EN_3_SET, + MT8186_TOP_AXI_PROT_EN_3_CLR, + MT8186_TOP_AXI_PROT_EN_3_STA), + BUS_PROT_WR_IGN(MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2, + MT8186_TOP_AXI_PROT_EN_3_SET, + MT8186_TOP_AXI_PROT_EN_3_CLR, + MT8186_TOP_AXI_PROT_EN_3_STA), + }, + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, + }, +}; + +static const struct scpsys_soc_data mt8186_scpsys_data = { + .domains_data = scpsys_domain_data_mt8186, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8186), +}; + +#endif /* __SOC_MEDIATEK_MT8186_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h index 543dda70de01..558c4ee4784a 100644 --- a/drivers/soc/mediatek/mt8192-pm-domains.h +++ b/drivers/soc/mediatek/mt8192-pm-domains.h @@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "audio", .sta_mask = BIT(21), .ctl_offs = 0x0354, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -28,6 +30,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "conn", .sta_mask = PWR_STATUS_CONN, .ctl_offs = 0x0304, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, .bp_infracfg = { @@ -50,6 +54,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg0", .sta_mask = BIT(2), .ctl_offs = 0x0308, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -57,6 +63,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg1", .sta_mask = BIT(3), .ctl_offs = 0x030c, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -82,6 +90,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg2", .sta_mask = BIT(4), .ctl_offs = 0x0310, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -89,6 +99,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg3", .sta_mask = BIT(5), .ctl_offs = 0x0314, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -96,6 +108,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg4", .sta_mask = BIT(6), .ctl_offs = 0x0318, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -103,6 +117,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg5", .sta_mask = BIT(7), .ctl_offs = 0x031c, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -110,6 +126,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg6", .sta_mask = BIT(8), .ctl_offs = 0x0320, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -117,6 +135,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "disp", .sta_mask = BIT(20), .ctl_offs = 0x0350, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -146,6 +166,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "ipe", .sta_mask = BIT(14), .ctl_offs = 0x0338, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -163,6 +185,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "isp", .sta_mask = BIT(12), .ctl_offs = 0x0330, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -180,6 +204,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "isp2", .sta_mask = BIT(13), .ctl_offs = 0x0334, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -197,6 +223,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mdp", .sta_mask = BIT(19), .ctl_offs = 0x034c, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -214,6 +242,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "venc", .sta_mask = BIT(17), .ctl_offs = 0x0344, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -231,6 +261,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "vdec", .sta_mask = BIT(15), .ctl_offs = 0x033c, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -248,6 +280,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "vdec2", .sta_mask = BIT(16), .ctl_offs = 0x0340, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -255,6 +289,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "cam", .sta_mask = BIT(23), .ctl_offs = 0x035c, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -284,6 +320,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "cam_rawa", .sta_mask = BIT(24), .ctl_offs = 0x0360, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -291,6 +329,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "cam_rawb", .sta_mask = BIT(25), .ctl_offs = 0x0364, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -298,6 +338,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "cam_rawc", .sta_mask = BIT(26), .ctl_offs = 0x0368, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -306,8 +348,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { static const struct scpsys_soc_data mt8192_scpsys_data = { .domains_data = scpsys_domain_data_mt8192, .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192), - .pwr_sta_offs = 0x016c, - .pwr_sta2nd_offs = 0x0170, }; #endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mt8195-pm-domains.h b/drivers/soc/mediatek/mt8195-pm-domains.h new file mode 100644 index 000000000000..938f4d51f5ae --- /dev/null +++ b/drivers/soc/mediatek/mt8195-pm-domains.h @@ -0,0 +1,613 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Chun-Jie Chen + */ + +#ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8195 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { + [MT8195_POWER_DOMAIN_PCIE_MAC_P0] = { + .name = "pcie_mac_p0", + .sta_mask = BIT(11), + .ctl_offs = 0x328, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, + MT8195_TOP_AXI_PROT_EN_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + }, + }, + [MT8195_POWER_DOMAIN_PCIE_MAC_P1] = { + .name = "pcie_mac_p1", + .sta_mask = BIT(12), + .ctl_offs = 0x32C, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, + MT8195_TOP_AXI_PROT_EN_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + }, + }, + [MT8195_POWER_DOMAIN_PCIE_PHY] = { + .name = "pcie_phy", + .sta_mask = BIT(13), + .ctl_offs = 0x330, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = { + .name = "ssusb_pcie_phy", + .sta_mask = BIT(14), + .ctl_offs = 0x334, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8195_POWER_DOMAIN_CSI_RX_TOP] = { + .name = "csi_rx_top", + .sta_mask = BIT(18), + .ctl_offs = 0x3C4, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_ETHER] = { + .name = "ether", + .sta_mask = BIT(3), + .ctl_offs = 0x344, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8195_POWER_DOMAIN_ADSP] = { + .name = "adsp", + .sta_mask = BIT(10), + .ctl_offs = 0x360, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + }, + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8195_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = BIT(8), + .ctl_offs = 0x358, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + }, + }, + [MT8195_POWER_DOMAIN_MFG0] = { + .name = "mfg0", + .sta_mask = BIT(1), + .ctl_offs = 0x300, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY, + }, + [MT8195_POWER_DOMAIN_MFG1] = { + .name = "mfg1", + .sta_mask = BIT(2), + .ctl_offs = 0x304, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1, + MT8195_TOP_AXI_PROT_EN_1_SET, + MT8195_TOP_AXI_PROT_EN_1_CLR, + MT8195_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG2] = { + .name = "mfg2", + .sta_mask = BIT(3), + .ctl_offs = 0x308, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG3] = { + .name = "mfg3", + .sta_mask = BIT(4), + .ctl_offs = 0x30C, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG4] = { + .name = "mfg4", + .sta_mask = BIT(5), + .ctl_offs = 0x310, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG5] = { + .name = "mfg5", + .sta_mask = BIT(6), + .ctl_offs = 0x314, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG6] = { + .name = "mfg6", + .sta_mask = BIT(7), + .ctl_offs = 0x318, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_VPPSYS0] = { + .name = "vppsys0", + .sta_mask = BIT(11), + .ctl_offs = 0x364, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + }, + }, + [MT8195_POWER_DOMAIN_VDOSYS0] = { + .name = "vdosys0", + .sta_mask = BIT(13), + .ctl_offs = 0x36C, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + }, + }, + [MT8195_POWER_DOMAIN_VPPSYS1] = { + .name = "vppsys1", + .sta_mask = BIT(12), + .ctl_offs = 0x368, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + }, + [MT8195_POWER_DOMAIN_VDOSYS1] = { + .name = "vdosys1", + .sta_mask = BIT(14), + .ctl_offs = 0x370, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + }, + [MT8195_POWER_DOMAIN_DP_TX] = { + .name = "dp_tx", + .sta_mask = BIT(16), + .ctl_offs = 0x378, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_EPD_TX] = { + .name = "epd_tx", + .sta_mask = BIT(17), + .ctl_offs = 0x37C, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_HDMI_TX] = { + .name = "hdmi_tx", + .sta_mask = BIT(18), + .ctl_offs = 0x380, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8195_POWER_DOMAIN_WPESYS] = { + .name = "wpesys", + .sta_mask = BIT(15), + .ctl_offs = 0x374, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + }, + [MT8195_POWER_DOMAIN_VDEC0] = { + .name = "vdec0", + .sta_mask = BIT(20), + .ctl_offs = 0x388, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_VDEC1] = { + .name = "vdec1", + .sta_mask = BIT(21), + .ctl_offs = 0x38C, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_VDEC2] = { + .name = "vdec2", + .sta_mask = BIT(22), + .ctl_offs = 0x390, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = BIT(23), + .ctl_offs = 0x394, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_VENC_CORE1] = { + .name = "venc_core1", + .sta_mask = BIT(24), + .ctl_offs = 0x398, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_IMG] = { + .name = "img", + .sta_mask = BIT(29), + .ctl_offs = 0x3AC, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_DIP] = { + .name = "dip", + .sta_mask = BIT(30), + .ctl_offs = 0x3B0, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_IPE] = { + .name = "ipe", + .sta_mask = BIT(31), + .ctl_offs = 0x3B4, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x39C, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM, + MT8195_TOP_AXI_PROT_EN_1_SET, + MT8195_TOP_AXI_PROT_EN_1_CLR, + MT8195_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_CAM_RAWA] = { + .name = "cam_rawa", + .sta_mask = BIT(26), + .ctl_offs = 0x3A0, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_CAM_RAWB] = { + .name = "cam_rawb", + .sta_mask = BIT(27), + .ctl_offs = 0x3A4, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_CAM_MRAW] = { + .name = "cam_mraw", + .sta_mask = BIT(28), + .ctl_offs = 0x3A8, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, +}; + +static const struct scpsys_soc_data mt8195_scpsys_data = { + .domains_data = scpsys_domain_data_mt8195, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195), +}; + +#endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c index 0590b68e0d78..2acf19676af2 100644 --- a/drivers/soc/mediatek/mtk-infracfg.c +++ b/drivers/soc/mediatek/mtk-infracfg.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -72,3 +73,21 @@ int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, return ret; } + +static int __init mtk_infracfg_init(void) +{ + struct regmap *infracfg; + + /* + * MT8192 has an experimental path to route GPU traffic to the DSU's + * Accelerator Coherency Port, which is inadvertently enabled by + * default. It turns out not to work, so disable it to prevent spurious + * GPU faults. + */ + infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg"); + if (!IS_ERR(infracfg)) + regmap_set_bits(infracfg, MT8192_INFRA_CTRL, + MT8192_INFRA_CTRL_DISABLE_MFG2ACP); + return 0; +} +postcore_initcall(mtk_infracfg_init); diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 1e448f1ffefb..4fc4c2c9ea20 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -15,6 +15,7 @@ #include "mtk-mmsys.h" #include "mt8167-mmsys.h" #include "mt8183-mmsys.h" +#include "mt8186-mmsys.h" #include "mt8192-mmsys.h" #include "mt8365-mmsys.h" @@ -48,12 +49,21 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { .clk_driver = "clk-mt8173-mm", .routes = mmsys_default_routing_table, .num_routes = ARRAY_SIZE(mmsys_default_routing_table), + .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, }; static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .clk_driver = "clk-mt8183-mm", .routes = mmsys_mt8183_routing_table, .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), + .sw0_rst_offset = MT8183_MMSYS_SW0_RST_B, +}; + +static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = { + .clk_driver = "clk-mt8186-mm", + .routes = mmsys_mt8186_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table), + .sw0_rst_offset = MT8186_MMSYS_SW0_RST_B, }; static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { @@ -121,14 +131,14 @@ static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned l spin_lock_irqsave(&mmsys->lock, flags); - reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B); + reg = readl_relaxed(mmsys->regs + mmsys->data->sw0_rst_offset); if (assert) reg &= ~BIT(id); else reg |= BIT(id); - writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B); + writel_relaxed(reg, mmsys->regs + mmsys->data->sw0_rst_offset); spin_unlock_irqrestore(&mmsys->lock, flags); @@ -242,6 +252,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8186-mmsys", + .data = &mt8186_mmsys_driver_data, + }, { .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data, diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 8b0ed05117ea..77f37f8c715b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -78,8 +78,6 @@ #define DSI_SEL_IN_RDMA 0x1 #define DSI_SEL_IN_MASK 0x1 -#define MMSYS_SW0_RST_B 0x140 - struct mtk_mmsys_routes { u32 from_comp; u32 to_comp; @@ -92,6 +90,7 @@ struct mtk_mmsys_driver_data { const char *clk_driver; const struct mtk_mmsys_routes *routes; const unsigned int num_routes; + const u16 sw0_rst_offset; }; /* diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 2ca55bb5a8be..aaf8fc1abb43 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -26,6 +26,23 @@ #define INT_MUTEX BIT(1) +#define MT8186_MUTEX_MOD_DISP_OVL0 0 +#define MT8186_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT8186_MUTEX_MOD_DISP_RDMA0 2 +#define MT8186_MUTEX_MOD_DISP_COLOR0 4 +#define MT8186_MUTEX_MOD_DISP_CCORR0 5 +#define MT8186_MUTEX_MOD_DISP_AAL0 7 +#define MT8186_MUTEX_MOD_DISP_GAMMA0 8 +#define MT8186_MUTEX_MOD_DISP_POSTMASK0 9 +#define MT8186_MUTEX_MOD_DISP_DITHER0 10 +#define MT8186_MUTEX_MOD_DISP_RDMA1 17 + +#define MT8186_MUTEX_SOF_SINGLE_MODE 0 +#define MT8186_MUTEX_SOF_DSI0 1 +#define MT8186_MUTEX_SOF_DPI0 2 +#define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6) +#define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6) + #define MT8167_MUTEX_MOD_DISP_PWM 1 #define MT8167_MUTEX_MOD_DISP_OVL0 6 #define MT8167_MUTEX_MOD_DISP_OVL1 7 @@ -226,6 +243,19 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; +static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0, + [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1, +}; + static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, @@ -264,6 +294,12 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, }; +static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = { + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0, + [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0, +}; + static const struct mtk_mutex_data mt2701_mutex_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -301,6 +337,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .no_clk = true, }; +static const struct mtk_mutex_data mt8186_mutex_driver_data = { + .mutex_mod = mt8186_mutex_mod, + .mutex_sof = mt8186_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, +}; + static const struct mtk_mutex_data mt8192_mutex_driver_data = { .mutex_mod = mt8192_mutex_mod, .mutex_sof = mt8183_mutex_sof, @@ -540,6 +583,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8173_mutex_driver_data}, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data}, + { .compatible = "mediatek,mt8186-disp-mutex", + .data = &mt8186_mutex_driver_data}, { .compatible = "mediatek,mt8192-disp-mutex", .data = &mt8192_mutex_driver_data}, {}, diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index b762bc40f56b..5ced254b082b 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -19,7 +19,9 @@ #include "mt8167-pm-domains.h" #include "mt8173-pm-domains.h" #include "mt8183-pm-domains.h" +#include "mt8186-pm-domains.h" #include "mt8192-pm-domains.h" +#include "mt8195-pm-domains.h" #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -60,10 +62,10 @@ static bool scpsys_domain_is_on(struct scpsys_domain *pd) struct scpsys *scpsys = pd->scpsys; u32 status, status2; - regmap_read(scpsys->base, scpsys->soc_data->pwr_sta_offs, &status); + regmap_read(scpsys->base, pd->data->pwr_sta_offs, &status); status &= pd->data->sta_mask; - regmap_read(scpsys->base, scpsys->soc_data->pwr_sta2nd_offs, &status2); + regmap_read(scpsys->base, pd->data->pwr_sta2nd_offs, &status2); status2 &= pd->data->sta_mask; /* A domain is on when both status bits are set. */ @@ -443,6 +445,9 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no pd->genpd.power_off = scpsys_power_off; pd->genpd.power_on = scpsys_power_on; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_ACTIVE_WAKEUP)) + pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF)) pm_genpd_init(&pd->genpd, NULL, true); else @@ -562,10 +567,18 @@ static const struct of_device_id scpsys_of_match[] = { .compatible = "mediatek,mt8183-power-controller", .data = &mt8183_scpsys_data, }, + { + .compatible = "mediatek,mt8186-power-controller", + .data = &mt8186_scpsys_data, + }, { .compatible = "mediatek,mt8192-power-controller", .data = &mt8192_scpsys_data, }, + { + .compatible = "mediatek,mt8195-power-controller", + .data = &mt8195_scpsys_data, + }, { } }; diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index c5ac649ae51b..daa24e890dd4 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -37,7 +37,7 @@ #define PWR_STATUS_AUDIO BIT(24) #define PWR_STATUS_USB BIT(25) -#define SPM_MAX_BUS_PROT_DATA 5 +#define SPM_MAX_BUS_PROT_DATA 6 #define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ .bus_prot_mask = (_mask), \ @@ -72,8 +72,6 @@ struct scpsys_bus_prot_data { bool ignore_clr_ack; }; -#define MAX_SUBSYS_CLKS 10 - /** * struct scpsys_domain_data - scp domain data for power on/off flow * @name: The name of the power domain. @@ -94,13 +92,13 @@ struct scpsys_domain_data { u8 caps; const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA]; + int pwr_sta_offs; + int pwr_sta2nd_offs; }; struct scpsys_soc_data { const struct scpsys_domain_data *domains_data; int num_domains; - int pwr_sta_offs; - int pwr_sta2nd_offs; }; #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 952bc554f443..bf39a64f3ecc 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -30,6 +30,7 @@ #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001) #define PWRAP_STATE_SYNC_IDLE0 BIT(20) #define PWRAP_STATE_INIT_DONE0 BIT(21) +#define PWRAP_STATE_INIT_DONE0_MT8186 BIT(22) #define PWRAP_STATE_INIT_DONE1 BIT(15) /* macro for WACS FSM */ @@ -77,6 +78,7 @@ #define PWRAP_CAP_INT1_EN BIT(3) #define PWRAP_CAP_WDT_SRC1 BIT(4) #define PWRAP_CAP_ARB BIT(5) +#define PWRAP_CAP_ARB_MT8186 BIT(8) /* defines for slave device wrapper registers */ enum dew_regs { @@ -1063,6 +1065,55 @@ static int mt8516_regs[] = { [PWRAP_MSB_FIRST] = 0x170, }; +static int mt8186_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_RDDMY] = 0x20, + [PWRAP_CSHEXT_WRITE] = 0x24, + [PWRAP_CSHEXT_READ] = 0x28, + [PWRAP_CSLEXT_WRITE] = 0x2C, + [PWRAP_CSLEXT_READ] = 0x30, + [PWRAP_EXT_CK_WRITE] = 0x34, + [PWRAP_STAUPD_CTRL] = 0x3C, + [PWRAP_STAUPD_GRPEN] = 0x40, + [PWRAP_EINT_STA0_ADR] = 0x44, + [PWRAP_EINT_STA1_ADR] = 0x48, + [PWRAP_INT_CLR] = 0xC8, + [PWRAP_INT_FLG] = 0xC4, + [PWRAP_MAN_EN] = 0x7C, + [PWRAP_MAN_CMD] = 0x80, + [PWRAP_WACS0_EN] = 0x8C, + [PWRAP_WACS1_EN] = 0x94, + [PWRAP_WACS2_EN] = 0x9C, + [PWRAP_INIT_DONE0] = 0x90, + [PWRAP_INIT_DONE1] = 0x98, + [PWRAP_INIT_DONE2] = 0xA0, + [PWRAP_INT_EN] = 0xBC, + [PWRAP_INT1_EN] = 0xCC, + [PWRAP_INT1_FLG] = 0xD4, + [PWRAP_INT1_CLR] = 0xD8, + [PWRAP_TIMER_EN] = 0xF0, + [PWRAP_WDT_UNIT] = 0xF8, + [PWRAP_WDT_SRC_EN] = 0xFC, + [PWRAP_WDT_SRC_EN_1] = 0x100, + [PWRAP_WDT_FLG] = 0x104, + [PWRAP_SPMINF_STA] = 0x1B4, + [PWRAP_DCM_EN] = 0x1EC, + [PWRAP_DCM_DBC_PRD] = 0x1F0, + [PWRAP_GPSINF_0_STA] = 0x204, + [PWRAP_GPSINF_1_STA] = 0x208, + [PWRAP_WACS0_CMD] = 0xC00, + [PWRAP_WACS0_RDATA] = 0xC04, + [PWRAP_WACS0_VLDCLR] = 0xC08, + [PWRAP_WACS1_CMD] = 0xC10, + [PWRAP_WACS1_RDATA] = 0xC14, + [PWRAP_WACS1_VLDCLR] = 0xC18, + [PWRAP_WACS2_CMD] = 0xC20, + [PWRAP_WACS2_RDATA] = 0xC24, + [PWRAP_WACS2_VLDCLR] = 0xC28, +}; + enum pmic_type { PMIC_MT6323, PMIC_MT6351, @@ -1083,6 +1134,7 @@ enum pwrap_type { PWRAP_MT8135, PWRAP_MT8173, PWRAP_MT8183, + PWRAP_MT8186, PWRAP_MT8195, PWRAP_MT8516, }; @@ -1535,6 +1587,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) case PWRAP_MT6779: case PWRAP_MT6797: case PWRAP_MT8173: + case PWRAP_MT8186: case PWRAP_MT8516: pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); break; @@ -2069,6 +2122,19 @@ static struct pmic_wrapper_type pwrap_mt8516 = { .init_soc_specific = NULL, }; +static struct pmic_wrapper_type pwrap_mt8186 = { + .regs = mt8186_regs, + .type = PWRAP_MT8186, + .arb_en_all = 0xfb27f, + .int_en_all = 0xfffffffe, /* disable WatchDog Timeout for bit 1 */ + .int1_en_all = 0x000017ff, /* disable Matching interrupt for bit 13 */ + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB_MT8186, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = NULL, +}; + static const struct of_device_id of_pwrap_match_tbl[] = { { .compatible = "mediatek,mt2701-pwrap", @@ -2097,6 +2163,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = { }, { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183, + }, { + .compatible = "mediatek,mt8186-pwrap", + .data = &pwrap_mt8186, }, { .compatible = "mediatek,mt8195-pwrap", .data = &pwrap_mt8195, @@ -2209,6 +2278,8 @@ static int pwrap_probe(struct platform_device *pdev) if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) mask_done = PWRAP_STATE_INIT_DONE1; + else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186)) + mask_done = PWRAP_STATE_INIT_DONE0_MT8186; else mask_done = PWRAP_STATE_INIT_DONE0; diff --git a/drivers/soc/microchip/Kconfig b/drivers/soc/microchip/Kconfig new file mode 100644 index 000000000000..eb656b33156b --- /dev/null +++ b/drivers/soc/microchip/Kconfig @@ -0,0 +1,10 @@ +config POLARFIRE_SOC_SYS_CTRL + tristate "POLARFIRE_SOC_SYS_CTRL" + depends on POLARFIRE_SOC_MAILBOX + help + This driver adds support for the PolarFire SoC (MPFS) system controller. + + To compile this driver as a module, choose M here. the + module will be called mpfs_system_controller. + + If unsure, say N. diff --git a/drivers/soc/microchip/Makefile b/drivers/soc/microchip/Makefile new file mode 100644 index 000000000000..14489919fe4b --- /dev/null +++ b/drivers/soc/microchip/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) += mpfs-sys-controller.o diff --git a/drivers/soc/microchip/mpfs-sys-controller.c b/drivers/soc/microchip/mpfs-sys-controller.c new file mode 100644 index 000000000000..6e20207b5756 --- /dev/null +++ b/drivers/soc/microchip/mpfs-sys-controller.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip PolarFire SoC (MPFS) system controller driver + * + * Copyright (c) 2020-2021 Microchip Corporation. All rights reserved. + * + * Author: Conor Dooley + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_MUTEX(transaction_lock); + +struct mpfs_sys_controller { + struct mbox_client client; + struct mbox_chan *chan; + struct completion c; + struct kref consumers; +}; + +int mpfs_blocking_transaction(struct mpfs_sys_controller *sys_controller, struct mpfs_mss_msg *msg) +{ + int ret, err; + + err = mutex_lock_interruptible(&transaction_lock); + if (err) + return err; + + reinit_completion(&sys_controller->c); + + ret = mbox_send_message(sys_controller->chan, msg); + if (ret >= 0) { + if (wait_for_completion_timeout(&sys_controller->c, HZ)) { + ret = 0; + } else { + ret = -ETIMEDOUT; + dev_warn(sys_controller->client.dev, + "MPFS sys controller transaction timeout\n"); + } + } else { + dev_err(sys_controller->client.dev, + "mpfs sys controller transaction returned %d\n", ret); + } + + mutex_unlock(&transaction_lock); + + return ret; +} +EXPORT_SYMBOL(mpfs_blocking_transaction); + +static void rx_callback(struct mbox_client *client, void *msg) +{ + struct mpfs_sys_controller *sys_controller = + container_of(client, struct mpfs_sys_controller, client); + + complete(&sys_controller->c); +} + +static void mpfs_sys_controller_delete(struct kref *kref) +{ + struct mpfs_sys_controller *sys_controller = container_of(kref, struct mpfs_sys_controller, + consumers); + + mbox_free_channel(sys_controller->chan); + kfree(sys_controller); +} + +static void mpfs_sys_controller_put(void *data) +{ + struct mpfs_sys_controller *sys_controller = data; + + kref_put(&sys_controller->consumers, mpfs_sys_controller_delete); +} + +static struct platform_device subdevs[] = { + { + .name = "mpfs-rng", + .id = -1, + }, + { + .name = "mpfs-generic-service", + .id = -1, + } +}; + +static int mpfs_sys_controller_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mpfs_sys_controller *sys_controller; + int i, ret; + + sys_controller = kzalloc(sizeof(*sys_controller), GFP_KERNEL); + if (!sys_controller) + return -ENOMEM; + + sys_controller->client.dev = dev; + sys_controller->client.rx_callback = rx_callback; + sys_controller->client.tx_block = 1U; + + sys_controller->chan = mbox_request_channel(&sys_controller->client, 0); + if (IS_ERR(sys_controller->chan)) { + ret = dev_err_probe(dev, PTR_ERR(sys_controller->chan), + "Failed to get mbox channel\n"); + kfree(sys_controller); + return ret; + } + + init_completion(&sys_controller->c); + kref_init(&sys_controller->consumers); + + platform_set_drvdata(pdev, sys_controller); + + dev_info(&pdev->dev, "Registered MPFS system controller\n"); + + for (i = 0; i < ARRAY_SIZE(subdevs); i++) { + subdevs[i].dev.parent = dev; + if (platform_device_register(&subdevs[i])) + dev_warn(dev, "Error registering sub device %s\n", subdevs[i].name); + } + + return 0; +} + +static int mpfs_sys_controller_remove(struct platform_device *pdev) +{ + struct mpfs_sys_controller *sys_controller = platform_get_drvdata(pdev); + + mpfs_sys_controller_put(sys_controller); + + return 0; +} + +static const struct of_device_id mpfs_sys_controller_of_match[] = { + {.compatible = "microchip,mpfs-sys-controller", }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpfs_sys_controller_of_match); + +struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev) +{ + const struct of_device_id *match; + struct mpfs_sys_controller *sys_controller; + int ret; + + if (!dev->parent) + goto err_no_device; + + match = of_match_node(mpfs_sys_controller_of_match, dev->parent->of_node); + of_node_put(dev->parent->of_node); + if (!match) + goto err_no_device; + + sys_controller = dev_get_drvdata(dev->parent); + if (!sys_controller) + goto err_bad_device; + + if (!kref_get_unless_zero(&sys_controller->consumers)) + goto err_bad_device; + + ret = devm_add_action_or_reset(dev, mpfs_sys_controller_put, sys_controller); + if (ret) + return ERR_PTR(ret); + + return sys_controller; + +err_no_device: + dev_dbg(dev, "Parent device was not an MPFS system controller\n"); + return ERR_PTR(-ENODEV); + +err_bad_device: + dev_dbg(dev, "MPFS system controller found but could not register as a sub device\n"); + return ERR_PTR(-EPROBE_DEFER); +} +EXPORT_SYMBOL(mpfs_sys_controller_get); + +static struct platform_driver mpfs_sys_controller_driver = { + .driver = { + .name = "mpfs-sys-controller", + .of_match_table = mpfs_sys_controller_of_match, + }, + .probe = mpfs_sys_controller_probe, + .remove = mpfs_sys_controller_remove, +}; +module_platform_driver(mpfs_sys_controller_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Conor Dooley "); +MODULE_DESCRIPTION("MPFS system controller driver"); diff --git a/drivers/soc/qcom/apr.c b/drivers/soc/qcom/apr.c index 82ca12c9328a..3caabd873322 100644 --- a/drivers/soc/qcom/apr.c +++ b/drivers/soc/qcom/apr.c @@ -653,7 +653,6 @@ static void apr_remove(struct rpmsg_device *rpdev) pdr_handle_release(apr->pdr); device_for_each_child(&rpdev->dev, NULL, apr_remove_device); - flush_workqueue(apr->rxwq); destroy_workqueue(apr->rxwq); } diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index ec52f29c8867..eecafeded56f 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -29,17 +29,13 @@ #define ATTR1_FIXED_SIZE_SHIFT 0x03 #define ATTR1_PRIORITY_SHIFT 0x04 #define ATTR1_MAX_CAP_SHIFT 0x10 -#define ATTR0_RES_WAYS_MASK GENMASK(11, 0) -#define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16) +#define ATTR0_RES_WAYS_MASK GENMASK(15, 0) +#define ATTR0_BONUS_WAYS_MASK GENMASK(31, 16) #define ATTR0_BONUS_WAYS_SHIFT 0x10 #define LLCC_STATUS_READ_DELAY 100 #define CACHE_LINE_SIZE_SHIFT 6 -#define LLCC_COMMON_HW_INFO 0x00030000 -#define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24) - -#define LLCC_COMMON_STATUS0 0x0003000c #define LLCC_LB_CNT_MASK GENMASK(31, 28) #define LLCC_LB_CNT_SHIFT 28 @@ -52,9 +48,13 @@ #define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 #define LLCC_TRP_PCB_ACT 0x21f04 #define LLCC_TRP_WRSC_EN 0x21f20 +#define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define BANK_OFFSET_STRIDE 0x80000 +#define LLCC_VERSION_2_0_0_0 0x02000000 +#define LLCC_VERSION_2_1_0_0 0x02010000 + /** * struct llcc_slice_config - Data associated with the llcc slice * @usecase_id: Unique id for the client's use case @@ -79,6 +79,8 @@ * collapse. * @activate_on_init: Activate the slice immediately after it is programmed * @write_scid_en: Bit enables write cache support for a given scid. + * @write_scid_cacheable_en: Enables write cache cacheable support for a + * given scid (not supported on v2 or older hardware). */ struct llcc_slice_config { u32 usecase_id; @@ -94,12 +96,19 @@ struct llcc_slice_config { bool retain_on_pc; bool activate_on_init; bool write_scid_en; + bool write_scid_cacheable_en; }; struct qcom_llcc_config { const struct llcc_slice_config *sct_data; int size; bool need_llcc_cfg; + const u32 *reg_offset; +}; + +enum llcc_reg_offset { + LLCC_COMMON_HW_INFO, + LLCC_COMMON_STATUS0, }; static const struct llcc_slice_config sc7180_data[] = { @@ -217,42 +226,96 @@ static const struct llcc_slice_config sm8350_data[] = { { LLCC_CPUHWT, 5, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 1 }, }; +static const struct llcc_slice_config sm8450_data[] = { + {LLCC_CPUSS, 1, 3072, 1, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, + {LLCC_VIDSC0, 2, 512, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_AUDIO, 6, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, + {LLCC_MDMHPGRW, 7, 1024, 3, 0, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_CMPT, 10, 4096, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_GPUHTW, 11, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_GPU, 12, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 1, 0 }, + {LLCC_MMUHWT, 13, 768, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_DISP, 16, 4096, 2, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 1024, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_AUDHW, 22, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, + {LLCC_CVP, 28, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODPE, 29, 64, 1, 1, 0xF000, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xF0, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_CVPFW, 17, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_CPUSS1, 3, 1024, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_CAMEXP0, 4, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_CPUMTE, 23, 256, 1, 1, 0x0FFF, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_CPUHWT, 5, 512, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 1, 0, 0 }, + {LLCC_CAMEXP1, 27, 256, 3, 1, 0xFFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_AENPU, 8, 2048, 1, 1, 0xFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0 }, +}; + +static const u32 llcc_v1_2_reg_offset[] = { + [LLCC_COMMON_HW_INFO] = 0x00030000, + [LLCC_COMMON_STATUS0] = 0x0003000c, +}; + +static const u32 llcc_v21_reg_offset[] = { + [LLCC_COMMON_HW_INFO] = 0x00034000, + [LLCC_COMMON_STATUS0] = 0x0003400c, +}; + static const struct qcom_llcc_config sc7180_cfg = { .sct_data = sc7180_data, .size = ARRAY_SIZE(sc7180_data), .need_llcc_cfg = true, + .reg_offset = llcc_v1_2_reg_offset, }; static const struct qcom_llcc_config sc7280_cfg = { .sct_data = sc7280_data, .size = ARRAY_SIZE(sc7280_data), .need_llcc_cfg = true, + .reg_offset = llcc_v1_2_reg_offset, }; static const struct qcom_llcc_config sdm845_cfg = { .sct_data = sdm845_data, .size = ARRAY_SIZE(sdm845_data), .need_llcc_cfg = false, + .reg_offset = llcc_v1_2_reg_offset, }; static const struct qcom_llcc_config sm6350_cfg = { .sct_data = sm6350_data, .size = ARRAY_SIZE(sm6350_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_2_reg_offset, }; static const struct qcom_llcc_config sm8150_cfg = { .sct_data = sm8150_data, .size = ARRAY_SIZE(sm8150_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_2_reg_offset, }; static const struct qcom_llcc_config sm8250_cfg = { .sct_data = sm8250_data, .size = ARRAY_SIZE(sm8250_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_2_reg_offset, }; static const struct qcom_llcc_config sm8350_cfg = { .sct_data = sm8350_data, .size = ARRAY_SIZE(sm8350_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_2_reg_offset, +}; + +static const struct qcom_llcc_config sm8450_cfg = { + .sct_data = sm8450_data, + .size = ARRAY_SIZE(sm8450_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v21_reg_offset, }; static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; @@ -504,7 +567,7 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, return ret; } - if (drv_data->major_version == 2) { + if (drv_data->version >= LLCC_VERSION_2_0_0_0) { u32 wren; wren = config->write_scid_en << config->slice_id; @@ -514,6 +577,16 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, return ret; } + if (drv_data->version >= LLCC_VERSION_2_1_0_0) { + u32 wr_cache_en; + + wr_cache_en = config->write_scid_cacheable_en << config->slice_id; + ret = regmap_update_bits(drv_data->bcast_regmap, LLCC_TRP_WRSC_CACHEABLE_EN, + BIT(config->slice_id), wr_cache_en); + if (ret) + return ret; + } + if (config->activate_on_init) { desc.slice_id = config->slice_id; ret = llcc_slice_activate(&desc); @@ -598,15 +671,18 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } - /* Extract major version of the IP */ - ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version); + cfg = of_device_get_match_data(&pdev->dev); + + /* Extract version of the IP */ + ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], + &version); if (ret) goto err; - drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version); + drv_data->version = version; - ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0, - &num_banks); + ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], + &num_banks); if (ret) goto err; @@ -614,7 +690,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) num_banks >>= LLCC_LB_CNT_SHIFT; drv_data->num_banks = num_banks; - cfg = of_device_get_match_data(&pdev->dev); llcc_cfg = cfg->sct_data; sz = cfg->size; @@ -632,9 +707,8 @@ static int qcom_llcc_probe(struct platform_device *pdev) for (i = 0; i < num_banks; i++) drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; - drv_data->bitmap = devm_kcalloc(dev, - BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long), - GFP_KERNEL); + drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, + GFP_KERNEL); if (!drv_data->bitmap) { ret = -ENOMEM; goto err; @@ -672,6 +746,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, + { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg }, { } }; diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index 72fc2b539213..366db493579b 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -31,6 +31,44 @@ static bool mdt_phdr_valid(const struct elf32_phdr *phdr) return true; } +static ssize_t mdt_load_split_segment(void *ptr, const struct elf32_phdr *phdrs, + unsigned int segment, const char *fw_name, + struct device *dev) +{ + const struct elf32_phdr *phdr = &phdrs[segment]; + const struct firmware *seg_fw; + char *seg_name; + ssize_t ret; + + if (strlen(fw_name) < 4) + return -EINVAL; + + seg_name = kstrdup(fw_name, GFP_KERNEL); + if (!seg_name) + return -ENOMEM; + + sprintf(seg_name + strlen(fw_name) - 3, "b%02d", segment); + ret = request_firmware_into_buf(&seg_fw, seg_name, dev, + ptr, phdr->p_filesz); + if (ret) { + dev_err(dev, "error %zd loading %s\n", ret, seg_name); + kfree(seg_name); + return ret; + } + + if (seg_fw->size != phdr->p_filesz) { + dev_err(dev, + "failed to load segment %d from truncated file %s\n", + segment, seg_name); + ret = -EINVAL; + } + + release_firmware(seg_fw); + kfree(seg_name); + + return ret; +} + /** * qcom_mdt_get_size() - acquire size of the memory region needed to load mdt * @fw: firmware object for the mdt file @@ -83,13 +121,17 @@ EXPORT_SYMBOL_GPL(qcom_mdt_get_size); * * Return: pointer to data, or ERR_PTR() */ -void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len) +void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len, + const char *fw_name, struct device *dev) { const struct elf32_phdr *phdrs; const struct elf32_hdr *ehdr; + unsigned int hash_segment = 0; size_t hash_offset; size_t hash_size; size_t ehdr_size; + unsigned int i; + ssize_t ret; void *data; ehdr = (struct elf32_hdr *)fw->data; @@ -101,24 +143,44 @@ void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len) if (phdrs[0].p_type == PT_LOAD) return ERR_PTR(-EINVAL); - if ((phdrs[1].p_flags & QCOM_MDT_TYPE_MASK) != QCOM_MDT_TYPE_HASH) + for (i = 1; i < ehdr->e_phnum; i++) { + if ((phdrs[i].p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH) { + hash_segment = i; + break; + } + } + + if (!hash_segment) { + dev_err(dev, "no hash segment found in %s\n", fw_name); return ERR_PTR(-EINVAL); + } ehdr_size = phdrs[0].p_filesz; - hash_size = phdrs[1].p_filesz; + hash_size = phdrs[hash_segment].p_filesz; data = kmalloc(ehdr_size + hash_size, GFP_KERNEL); if (!data) return ERR_PTR(-ENOMEM); - /* Is the header and hash already packed */ - if (ehdr_size + hash_size == fw->size) - hash_offset = phdrs[0].p_filesz; - else - hash_offset = phdrs[1].p_offset; - + /* Copy ELF header */ memcpy(data, fw->data, ehdr_size); - memcpy(data + ehdr_size, fw->data + hash_offset, hash_size); + + if (ehdr_size + hash_size == fw->size) { + /* Firmware is split and hash is packed following the ELF header */ + hash_offset = phdrs[0].p_filesz; + memcpy(data + ehdr_size, fw->data + hash_offset, hash_size); + } else if (phdrs[hash_segment].p_offset + hash_size <= fw->size) { + /* Hash is in its own segment, but within the loaded file */ + hash_offset = phdrs[hash_segment].p_offset; + memcpy(data + ehdr_size, fw->data + hash_offset, hash_size); + } else { + /* Hash is in its own segment, beyond the loaded file */ + ret = mdt_load_split_segment(data + ehdr_size, phdrs, hash_segment, fw_name, dev); + if (ret) { + kfree(data); + return ERR_PTR(ret); + } + } *data_len = ehdr_size + hash_size; @@ -126,23 +188,85 @@ void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len) } EXPORT_SYMBOL_GPL(qcom_mdt_read_metadata); +/** + * qcom_mdt_pas_init() - initialize PAS region for firmware loading + * @dev: device handle to associate resources with + * @fw: firmware object for the mdt file + * @firmware: name of the firmware, for construction of segment file names + * @pas_id: PAS identifier + * @mem_phys: physical address of allocated memory region + * @ctx: PAS metadata context, to be released by caller + * + * Returns 0 on success, negative errno otherwise. + */ +int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, + const char *fw_name, int pas_id, phys_addr_t mem_phys, + struct qcom_scm_pas_metadata *ctx) +{ + const struct elf32_phdr *phdrs; + const struct elf32_phdr *phdr; + const struct elf32_hdr *ehdr; + phys_addr_t min_addr = PHYS_ADDR_MAX; + phys_addr_t max_addr = 0; + size_t metadata_len; + void *metadata; + int ret; + int i; + + ehdr = (struct elf32_hdr *)fw->data; + phdrs = (struct elf32_phdr *)(ehdr + 1); + + for (i = 0; i < ehdr->e_phnum; i++) { + phdr = &phdrs[i]; + + if (!mdt_phdr_valid(phdr)) + continue; + + if (phdr->p_paddr < min_addr) + min_addr = phdr->p_paddr; + + if (phdr->p_paddr + phdr->p_memsz > max_addr) + max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); + } + + metadata = qcom_mdt_read_metadata(fw, &metadata_len, fw_name, dev); + if (IS_ERR(metadata)) { + ret = PTR_ERR(metadata); + dev_err(dev, "error %d reading firmware %s metadata\n", ret, fw_name); + goto out; + } + + ret = qcom_scm_pas_init_image(pas_id, metadata, metadata_len, ctx); + kfree(metadata); + if (ret) { + /* Invalid firmware metadata */ + dev_err(dev, "error %d initializing firmware %s\n", ret, fw_name); + goto out; + } + + ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); + if (ret) { + /* Unable to set up relocation */ + dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name); + goto out; + } + +out: + return ret; +} +EXPORT_SYMBOL_GPL(qcom_mdt_pas_init); + static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, - const char *firmware, int pas_id, void *mem_region, + const char *fw_name, int pas_id, void *mem_region, phys_addr_t mem_phys, size_t mem_size, phys_addr_t *reloc_base, bool pas_init) { const struct elf32_phdr *phdrs; const struct elf32_phdr *phdr; const struct elf32_hdr *ehdr; - const struct firmware *seg_fw; phys_addr_t mem_reloc; phys_addr_t min_addr = PHYS_ADDR_MAX; - phys_addr_t max_addr = 0; - size_t metadata_len; - size_t fw_name_len; ssize_t offset; - void *metadata; - char *fw_name; bool relocate = false; void *ptr; int ret = 0; @@ -154,34 +278,6 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, ehdr = (struct elf32_hdr *)fw->data; phdrs = (struct elf32_phdr *)(ehdr + 1); - fw_name_len = strlen(firmware); - if (fw_name_len <= 4) - return -EINVAL; - - fw_name = kstrdup(firmware, GFP_KERNEL); - if (!fw_name) - return -ENOMEM; - - if (pas_init) { - metadata = qcom_mdt_read_metadata(fw, &metadata_len); - if (IS_ERR(metadata)) { - ret = PTR_ERR(metadata); - dev_err(dev, "error %d reading firmware %s metadata\n", - ret, fw_name); - goto out; - } - - ret = qcom_scm_pas_init_image(pas_id, metadata, metadata_len); - - kfree(metadata); - if (ret) { - /* Invalid firmware metadata */ - dev_err(dev, "error %d initializing firmware %s\n", - ret, fw_name); - goto out; - } - } - for (i = 0; i < ehdr->e_phnum; i++) { phdr = &phdrs[i]; @@ -193,23 +289,9 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, if (phdr->p_paddr < min_addr) min_addr = phdr->p_paddr; - - if (phdr->p_paddr + phdr->p_memsz > max_addr) - max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); } if (relocate) { - if (pas_init) { - ret = qcom_scm_pas_mem_setup(pas_id, mem_phys, - max_addr - min_addr); - if (ret) { - /* Unable to set up relocation */ - dev_err(dev, "error %d setting up firmware %s\n", - ret, fw_name); - goto out; - } - } - /* * The image is relocatable, so offset each segment based on * the lowest segment address. @@ -246,7 +328,8 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, ptr = mem_region + offset; - if (phdr->p_filesz && phdr->p_offset < fw->size) { + if (phdr->p_filesz && phdr->p_offset < fw->size && + phdr->p_offset + phdr->p_filesz <= fw->size) { /* Firmware is large enough to be non-split */ if (phdr->p_offset + phdr->p_filesz > fw->size) { dev_err(dev, "file %s segment %d would be truncated\n", @@ -258,25 +341,9 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz); } else if (phdr->p_filesz) { /* Firmware not large enough, load split-out segments */ - sprintf(fw_name + fw_name_len - 3, "b%02d", i); - ret = request_firmware_into_buf(&seg_fw, fw_name, dev, - ptr, phdr->p_filesz); - if (ret) { - dev_err(dev, "error %d loading %s\n", - ret, fw_name); + ret = mdt_load_split_segment(ptr, phdrs, i, fw_name, dev); + if (ret) break; - } - - if (seg_fw->size != phdr->p_filesz) { - dev_err(dev, - "failed to load segment %d from truncated file %s\n", - i, fw_name); - release_firmware(seg_fw); - ret = -EINVAL; - break; - } - - release_firmware(seg_fw); } if (phdr->p_memsz > phdr->p_filesz) @@ -286,9 +353,6 @@ static int __qcom_mdt_load(struct device *dev, const struct firmware *fw, if (reloc_base) *reloc_base = mem_reloc; -out: - kfree(fw_name); - return ret; } @@ -310,6 +374,12 @@ int qcom_mdt_load(struct device *dev, const struct firmware *fw, phys_addr_t mem_phys, size_t mem_size, phys_addr_t *reloc_base) { + int ret; + + ret = qcom_mdt_pas_init(dev, fw, firmware, pas_id, mem_phys, NULL); + if (ret) + return ret; + return __qcom_mdt_load(dev, fw, firmware, pas_id, mem_region, mem_phys, mem_size, reloc_base, true); } diff --git a/drivers/soc/qcom/ocmem.c b/drivers/soc/qcom/ocmem.c index d2dacbbaafbd..97fd24c178f8 100644 --- a/drivers/soc/qcom/ocmem.c +++ b/drivers/soc/qcom/ocmem.c @@ -206,6 +206,7 @@ struct ocmem *of_get_ocmem(struct device *dev) ocmem = platform_get_drvdata(pdev); if (!ocmem) { dev_err(dev, "Cannot get ocmem\n"); + put_device(&pdev->dev); return ERR_PTR(-ENODEV); } return ocmem; diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index cbe5e39fdaeb..a59bb34e5eba 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -451,7 +451,11 @@ struct qmp *qmp_get(struct device *dev) qmp = platform_get_drvdata(pdev); - return qmp ? qmp : ERR_PTR(-EPROBE_DEFER); + if (!qmp) { + put_device(&pdev->dev); + return ERR_PTR(-EPROBE_DEFER); + } + return qmp; } EXPORT_SYMBOL(qmp_get); @@ -497,7 +501,7 @@ static int qmp_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - ret = devm_request_irq(&pdev->dev, irq, qmp_intr, IRQF_ONESHOT, + ret = devm_request_irq(&pdev->dev, irq, qmp_intr, 0, "aoss-qmp", qmp); if (ret < 0) { dev_err(&pdev->dev, "failed to request interrupt\n"); diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 0a8d8d24bfb7..3b5b91621532 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -138,6 +138,22 @@ static const struct rpmpd_desc mdm9607_desc = { .max_state = RPM_SMD_LEVEL_TURBO, }; +/* msm8226 RPM Power Domains */ +DEFINE_RPMPD_PAIR(msm8226, vddcx, vddcx_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_VFC(msm8226, vddcx_vfc, SMPA, 1); + +static struct rpmpd *msm8226_rpmpds[] = { + [MSM8226_VDDCX] = &msm8226_vddcx, + [MSM8226_VDDCX_AO] = &msm8226_vddcx_ao, + [MSM8226_VDDCX_VFC] = &msm8226_vddcx_vfc, +}; + +static const struct rpmpd_desc msm8226_desc = { + .rpmpds = msm8226_rpmpds, + .num_pds = ARRAY_SIZE(msm8226_rpmpds), + .max_state = MAX_CORNER_RPMPD_STATE, +}; + /* msm8939 RPM Power Domains */ DEFINE_RPMPD_PAIR(msm8939, vddmd, vddmd_ao, SMPA, CORNER, 1); DEFINE_RPMPD_VFC(msm8939, vddmd_vfc, SMPA, 1); @@ -436,6 +452,7 @@ static const struct rpmpd_desc qcm2290_desc = { static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc }, + { .compatible = "qcom,msm8226-rpmpd", .data = &msm8226_desc }, { .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc }, { .compatible = "qcom,msm8939-rpmpd", .data = &msm8939_desc }, { .compatible = "qcom,msm8953-rpmpd", .data = &msm8953_desc }, @@ -610,6 +627,9 @@ static int rpmpd_probe(struct platform_device *pdev) data->domains = devm_kcalloc(&pdev->dev, num, sizeof(*data->domains), GFP_KERNEL); + if (!data->domains) + return -ENOMEM; + data->num_domains = num; for (i = 0; i < num; i++) { diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 6dc0f39c0ec3..8b38d134720a 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -104,6 +104,14 @@ static const char *const pmic_models[] = { [36] = "PM8009", [38] = "PM8150C", [41] = "SMB2351", + [47] = "PMK8350", + [48] = "PM8350", + [49] = "PM8350C", + [50] = "PM8350B", + [51] = "PMR735A", + [52] = "PMR735B", + [58] = "PM8450", + [65] = "PM8010", }; #endif /* CONFIG_DEBUG_FS */ @@ -314,10 +322,14 @@ static const struct soc_id soc_id[] = { { 422, "IPQ6010" }, { 425, "SC7180" }, { 434, "SM6350" }, + { 439, "SM8350" }, + { 449, "SC8280XP" }, { 453, "IPQ6005" }, { 455, "QRB5165" }, { 457, "SM8450" }, { 459, "SM7225" }, + { 460, "SA8540P" }, + { 480, "SM8450" }, }; static const char *socinfo_machine(struct device *dev, unsigned int id) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 2cbd03db2cc7..fdc99a05a7e0 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -40,6 +40,11 @@ config ARCH_RMOBILE select SYS_SUPPORTS_SH_TMU select SYSC_RMOBILE +config ARCH_RZG2L + bool + select PM + select PM_GENERIC_DOMAINS + config ARCH_RZN1 bool select ARM_AMBA @@ -293,9 +298,16 @@ config ARCH_R8A774B1 config ARCH_R9A07G044 bool "ARM64 Platform support for RZ/G2L" + select ARCH_RZG2L help This enables support for the Renesas RZ/G2L SoC variants. +config ARCH_R9A07G054 + bool "ARM64 Platform support for RZ/V2L" + select ARCH_RZG2L + help + This enables support for the Renesas RZ/V2L SoC variants. + endif # ARM64 config RST_RCAR diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index 62540ffc581a..92c7b42250ee 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -64,6 +64,10 @@ static const struct renesas_family fam_rzg2l __initconst __maybe_unused = { .name = "RZ/G2L", }; +static const struct renesas_family fam_rzv2l __initconst __maybe_unused = { + .name = "RZ/V2L", +}; + static const struct renesas_family fam_shmobile __initconst __maybe_unused = { .name = "SH-Mobile", .reg = 0xe600101c, /* CCCR (Common Chip Code Register) */ @@ -144,6 +148,11 @@ static const struct renesas_soc soc_rz_g2l __initconst __maybe_unused = { .id = 0x841c447, }; +static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = { + .family = &fam_rzv2l, + .id = 0x8447447, +}; + static const struct renesas_soc soc_rcar_m1a __initconst __maybe_unused = { .family = &fam_rcar_gen1, }; @@ -334,6 +343,9 @@ static const struct of_device_id renesas_socs[] __initconst = { #if defined(CONFIG_ARCH_R9A07G044) { .compatible = "renesas,r9a07g044", .data = &soc_rz_g2l }, #endif +#if defined(CONFIG_ARCH_R9A07G054) + { .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l }, +#endif #ifdef CONFIG_ARCH_SH73A0 { .compatible = "renesas,sh73a0", .data = &soc_shmobile_ag5 }, #endif @@ -367,6 +379,7 @@ static const struct renesas_id id_prr __initconst = { static const struct of_device_id renesas_ids[] __initconst = { { .compatible = "renesas,bsid", .data = &id_bsid }, { .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l }, + { .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l }, { .compatible = "renesas,prr", .data = &id_prr }, { /* sentinel */ } }; @@ -380,9 +393,11 @@ static int __init renesas_soc_init(void) const struct renesas_soc *soc; const struct renesas_id *id; void __iomem *chipid = NULL; + const char *rev_prefix = ""; struct soc_device *soc_dev; struct device_node *np; const char *soc_id; + int ret; match = of_match_node(renesas_socs, of_root); if (!match) @@ -403,6 +418,17 @@ static int __init renesas_soc_init(void) chipid = ioremap(family->reg, 4); } + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + np = of_find_node_by_path("/"); + of_property_read_string(np, "model", &soc_dev_attr->machine); + of_node_put(np); + + soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL); + soc_dev_attr->soc_id = kstrdup_const(soc_id, GFP_KERNEL); + if (chipid) { product = readl(chipid + id->offset); iounmap(chipid); @@ -417,41 +443,39 @@ static int __init renesas_soc_init(void) eshi = ((product >> 4) & 0x0f) + 1; eslo = product & 0xf; + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u", + eshi, eslo); + } else if (id == &id_rzg2l) { + eshi = ((product >> 28) & 0x0f); + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%u", + eshi); + rev_prefix = "Rev "; } if (soc->id && ((product & id->mask) >> __ffs(id->mask)) != soc->id) { pr_warn("SoC mismatch (product = 0x%x)\n", product); - return -ENODEV; + ret = -ENODEV; + goto free_soc_dev_attr; } } - soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); - if (!soc_dev_attr) - return -ENOMEM; - - np = of_find_node_by_path("/"); - of_property_read_string(np, "model", &soc_dev_attr->machine); - of_node_put(np); - - soc_dev_attr->family = kstrdup_const(family->name, GFP_KERNEL); - soc_dev_attr->soc_id = kstrdup_const(soc_id, GFP_KERNEL); - if (eshi) - soc_dev_attr->revision = kasprintf(GFP_KERNEL, "ES%u.%u", eshi, - eslo); - - pr_info("Detected Renesas %s %s %s\n", soc_dev_attr->family, - soc_dev_attr->soc_id, soc_dev_attr->revision ?: ""); + pr_info("Detected Renesas %s %s %s%s\n", soc_dev_attr->family, + soc_dev_attr->soc_id, rev_prefix, soc_dev_attr->revision ?: ""); soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { - kfree(soc_dev_attr->revision); - kfree_const(soc_dev_attr->soc_id); - kfree_const(soc_dev_attr->family); - kfree(soc_dev_attr); - return PTR_ERR(soc_dev); + ret = PTR_ERR(soc_dev); + goto free_soc_dev_attr; } return 0; + +free_soc_dev_attr: + kfree(soc_dev_attr->revision); + kfree_const(soc_dev_attr->soc_id); + kfree_const(soc_dev_attr->family); + kfree(soc_dev_attr); + return ret; } early_initcall(renesas_soc_init); diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 913103ee5432..aa94fda282f4 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2021, NVIDIA CORPORATION. All rights reserved. */ #include @@ -161,6 +161,12 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { .bytes = 4, .bit_offset = 0, .nbits = 32, + }, { + .name = "gcplex-config-fuse", + .offset = 0x1c8, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, }, { .name = "tsensor-realignment", .offset = 0x1fc, @@ -179,13 +185,25 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = { .bytes = 4, .bit_offset = 0, .nbits = 32, + }, { + .name = "pdi0", + .offset = 0x300, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, + }, { + .name = "pdi1", + .offset = 0x304, + .bytes = 4, + .bit_offset = 0, + .nbits = 32, }, }; static void tegra_fuse_restore(void *base) { + fuse->base = (void __iomem *)base; fuse->clk = NULL; - fuse->base = base; } static int tegra_fuse_probe(struct platform_device *pdev) @@ -195,7 +213,7 @@ static int tegra_fuse_probe(struct platform_device *pdev) struct resource *res; int err; - err = devm_add_action(&pdev->dev, tegra_fuse_restore, base); + err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base); if (err) return err; diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 5aceacbd8ce0..fdf508e03400 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -3,7 +3,7 @@ * drivers/soc/tegra/pmc.c * * Copyright (c) 2010 Google, Inc - * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. * * Author: * Colin Cross @@ -54,6 +54,7 @@ #include #include #include +#include #include #define PMC_CNTRL 0x0 @@ -3066,7 +3067,7 @@ static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, } static const struct tegra_pmc_soc tegra20_pmc_soc = { - .supports_core_domain = false, + .supports_core_domain = true, .num_powergates = ARRAY_SIZE(tegra20_powergates), .powergates = tegra20_powergates, .num_cpu_powergates = 0, @@ -3127,7 +3128,7 @@ static const char * const tegra30_reset_sources[] = { }; static const struct tegra_pmc_soc tegra30_pmc_soc = { - .supports_core_domain = false, + .supports_core_domain = true, .num_powergates = ARRAY_SIZE(tegra30_powergates), .powergates = tegra30_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), @@ -3788,6 +3789,11 @@ static const char * const tegra234_reset_sources[] = { "FUSECRC", }; +static const struct tegra_wake_event tegra234_wake_events[] = { + TEGRA_WAKE_GPIO("power", 29, 1, TEGRA234_AON_GPIO(EE, 4)), + TEGRA_WAKE_IRQ("rtc", 73, 10), +}; + static const struct tegra_pmc_soc tegra234_pmc_soc = { .supports_core_domain = false, .num_powergates = 0, @@ -3812,8 +3818,8 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = { .num_reset_sources = ARRAY_SIZE(tegra234_reset_sources), .reset_levels = tegra186_reset_levels, .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), - .num_wake_events = 0, - .wake_events = NULL, + .num_wake_events = ARRAY_SIZE(tegra234_wake_events), + .wake_events = tegra234_wake_events, .pmc_clks_data = NULL, .num_pmc_clks = 0, .has_blink_output = false, diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 31ab6c657fec..f7bf18b8229a 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -1402,12 +1402,10 @@ static int k3_ringacc_init(struct platform_device *pdev, sizeof(*ringacc->rings) * ringacc->num_rings, GFP_KERNEL); - ringacc->rings_inuse = devm_kcalloc(dev, - BITS_TO_LONGS(ringacc->num_rings), - sizeof(unsigned long), GFP_KERNEL); - ringacc->proxy_inuse = devm_kcalloc(dev, - BITS_TO_LONGS(ringacc->num_proxies), - sizeof(unsigned long), GFP_KERNEL); + ringacc->rings_inuse = devm_bitmap_zalloc(dev, ringacc->num_rings, + GFP_KERNEL); + ringacc->proxy_inuse = devm_bitmap_zalloc(dev, ringacc->num_proxies, + GFP_KERNEL); if (!ringacc->rings || !ringacc->rings_inuse || !ringacc->proxy_inuse) return -ENOMEM; @@ -1483,9 +1481,8 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev, sizeof(*ringacc->rings) * ringacc->num_rings * 2, GFP_KERNEL); - ringacc->rings_inuse = devm_kcalloc(dev, - BITS_TO_LONGS(ringacc->num_rings), - sizeof(unsigned long), GFP_KERNEL); + ringacc->rings_inuse = devm_bitmap_zalloc(dev, ringacc->num_rings, + GFP_KERNEL); if (!ringacc->rings || !ringacc->rings_inuse) return ERR_PTR(-ENOMEM); diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index b6b2150aca4e..91f441ee6175 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -42,6 +42,7 @@ static const struct k3_soc_id { { 0xBB6D, "J7200" }, { 0xBB38, "AM64X" }, { 0xBB75, "J721S2"}, + { 0xBB7E, "AM62X" }, }; static int diff --git a/drivers/soc/ti/smartreflex.c b/drivers/soc/ti/smartreflex.c index b5b2fa538d5c..ad2bb72e640c 100644 --- a/drivers/soc/ti/smartreflex.c +++ b/drivers/soc/ti/smartreflex.c @@ -819,7 +819,7 @@ static int omap_sr_probe(struct platform_device *pdev) { struct omap_sr *sr_info; struct omap_sr_data *pdata = pdev->dev.platform_data; - struct resource *mem, *irq; + struct resource *mem; struct dentry *nvalue_dir; int i, ret = 0; @@ -844,7 +844,11 @@ static int omap_sr_probe(struct platform_device *pdev) if (IS_ERR(sr_info->base)) return PTR_ERR(sr_info->base); - irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + ret = platform_get_irq_optional(pdev, 0); + if (ret < 0 && ret != -ENXIO) + return dev_err_probe(&pdev->dev, ret, "failed to get IRQ resource\n"); + if (ret > 0) + sr_info->irq = ret; sr_info->fck = devm_clk_get(pdev->dev.parent, "fck"); if (IS_ERR(sr_info->fck)) @@ -870,9 +874,6 @@ static int omap_sr_probe(struct platform_device *pdev) sr_info->autocomp_active = false; sr_info->ip_type = pdata->ip_type; - if (irq) - sr_info->irq = irq->start; - sr_set_clk_length(sr_info); list_add(&sr_info->node, &sr_list); @@ -926,7 +927,7 @@ static int omap_sr_probe(struct platform_device *pdev) } - return ret; + return 0; err_debugfs: debugfs_remove_recursive(sr_info->dbg_dir); diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index 72386bd393fe..2f03ced0f411 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -450,9 +450,9 @@ static int wkup_m3_ipc_probe(struct platform_device *pdev) return PTR_ERR(m3_ipc->ipc_mem_base); irq = platform_get_irq(pdev, 0); - if (!irq) { + if (irq < 0) { dev_err(&pdev->dev, "no irq resource\n"); - return -ENXIO; + return irq; } ret = devm_request_irq(dev, irq, wkup_m3_txev_handler, diff --git a/drivers/tee/amdtee/call.c b/drivers/tee/amdtee/call.c index 07f36ac834c8..cec6e70f0ac9 100644 --- a/drivers/tee/amdtee/call.c +++ b/drivers/tee/amdtee/call.c @@ -122,7 +122,7 @@ static int amd_params_to_tee_params(struct tee_param *tee, u32 count, } static DEFINE_MUTEX(ta_refcount_mutex); -static struct list_head ta_list = LIST_HEAD_INIT(ta_list); +static LIST_HEAD(ta_list); static u32 get_ta_refcount(u32 ta_handle) { diff --git a/drivers/tee/amdtee/shm_pool.c b/drivers/tee/amdtee/shm_pool.c index 065854e2db18..f87f96a291c9 100644 --- a/drivers/tee/amdtee/shm_pool.c +++ b/drivers/tee/amdtee/shm_pool.c @@ -8,13 +8,17 @@ #include #include "amdtee_private.h" -static int pool_op_alloc(struct tee_shm_pool_mgr *poolm, struct tee_shm *shm, - size_t size) +static int pool_op_alloc(struct tee_shm_pool *pool, struct tee_shm *shm, + size_t size, size_t align) { unsigned int order = get_order(size); unsigned long va; int rc; + /* + * Ignore alignment since this is already going to be page aligned + * and there's no need for any larger alignment. + */ va = __get_free_pages(GFP_KERNEL | __GFP_ZERO, order); if (!va) return -ENOMEM; @@ -34,7 +38,7 @@ static int pool_op_alloc(struct tee_shm_pool_mgr *poolm, struct tee_shm *shm, return 0; } -static void pool_op_free(struct tee_shm_pool_mgr *poolm, struct tee_shm *shm) +static void pool_op_free(struct tee_shm_pool *pool, struct tee_shm *shm) { /* Unmap the shared memory from TEE */ amdtee_unmap_shmem(shm); @@ -42,52 +46,25 @@ static void pool_op_free(struct tee_shm_pool_mgr *poolm, struct tee_shm *shm) shm->kaddr = NULL; } -static void pool_op_destroy_poolmgr(struct tee_shm_pool_mgr *poolm) +static void pool_op_destroy_pool(struct tee_shm_pool *pool) { - kfree(poolm); + kfree(pool); } -static const struct tee_shm_pool_mgr_ops pool_ops = { +static const struct tee_shm_pool_ops pool_ops = { .alloc = pool_op_alloc, .free = pool_op_free, - .destroy_poolmgr = pool_op_destroy_poolmgr, + .destroy_pool = pool_op_destroy_pool, }; -static struct tee_shm_pool_mgr *pool_mem_mgr_alloc(void) -{ - struct tee_shm_pool_mgr *mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); - - if (!mgr) - return ERR_PTR(-ENOMEM); - - mgr->ops = &pool_ops; - - return mgr; -} - struct tee_shm_pool *amdtee_config_shm(void) { - struct tee_shm_pool_mgr *priv_mgr; - struct tee_shm_pool_mgr *dmabuf_mgr; - void *rc; + struct tee_shm_pool *pool = kzalloc(sizeof(*pool), GFP_KERNEL); - rc = pool_mem_mgr_alloc(); - if (IS_ERR(rc)) - return rc; - priv_mgr = rc; + if (!pool) + return ERR_PTR(-ENOMEM); - rc = pool_mem_mgr_alloc(); - if (IS_ERR(rc)) { - tee_shm_pool_mgr_destroy(priv_mgr); - return rc; - } - dmabuf_mgr = rc; + pool->ops = &pool_ops; - rc = tee_shm_pool_alloc(priv_mgr, dmabuf_mgr); - if (IS_ERR(rc)) { - tee_shm_pool_mgr_destroy(priv_mgr); - tee_shm_pool_mgr_destroy(dmabuf_mgr); - } - - return rc; + return pool; } diff --git a/drivers/tee/optee/Kconfig b/drivers/tee/optee/Kconfig index 3ca71e3812ed..f121c224e682 100644 --- a/drivers/tee/optee/Kconfig +++ b/drivers/tee/optee/Kconfig @@ -7,11 +7,3 @@ config OPTEE help This implements the OP-TEE Trusted Execution Environment (TEE) driver. - -config OPTEE_SHM_NUM_PRIV_PAGES - int "Private Shared Memory Pages" - default 1 - depends on OPTEE - help - This sets the number of private shared memory pages to be - used by OP-TEE TEE driver. diff --git a/drivers/tee/optee/call.c b/drivers/tee/optee/call.c index b25cc1fac945..bd49ec934060 100644 --- a/drivers/tee/optee/call.c +++ b/drivers/tee/optee/call.c @@ -120,7 +120,7 @@ struct tee_shm *optee_get_msg_arg(struct tee_context *ctx, size_t num_params, if (optee->rpc_arg_count) sz += OPTEE_MSG_GET_ARG_SIZE(optee->rpc_arg_count); - shm = tee_shm_alloc(ctx, sz, TEE_SHM_MAPPED | TEE_SHM_PRIV); + shm = tee_shm_alloc_priv_buf(ctx, sz); if (IS_ERR(shm)) return shm; diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index 17a6f51d3089..daf947e98d14 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -18,8 +18,8 @@ #include #include "optee_private.h" -int optee_pool_op_alloc_helper(struct tee_shm_pool_mgr *poolm, - struct tee_shm *shm, size_t size, +int optee_pool_op_alloc_helper(struct tee_shm_pool *pool, struct tee_shm *shm, + size_t size, size_t align, int (*shm_register)(struct tee_context *ctx, struct tee_shm *shm, struct page **pages, @@ -30,6 +30,10 @@ int optee_pool_op_alloc_helper(struct tee_shm_pool_mgr *poolm, struct page *page; int rc = 0; + /* + * Ignore alignment since this is already going to be page aligned + * and there's no need for any larger alignment. + */ page = alloc_pages(GFP_KERNEL | __GFP_ZERO, order); if (!page) return -ENOMEM; @@ -51,7 +55,6 @@ int optee_pool_op_alloc_helper(struct tee_shm_pool_mgr *poolm, for (i = 0; i < nr_pages; i++) pages[i] = page + i; - shm->flags |= TEE_SHM_REGISTER; rc = shm_register(shm->ctx, shm, pages, nr_pages, (unsigned long)shm->kaddr); kfree(pages); @@ -62,10 +65,20 @@ int optee_pool_op_alloc_helper(struct tee_shm_pool_mgr *poolm, return 0; err: - __free_pages(page, order); + free_pages((unsigned long)shm->kaddr, order); return rc; } +void optee_pool_op_free_helper(struct tee_shm_pool *pool, struct tee_shm *shm, + int (*shm_unregister)(struct tee_context *ctx, + struct tee_shm *shm)) +{ + if (shm_unregister) + shm_unregister(shm->ctx, shm); + free_pages((unsigned long)shm->kaddr, get_order(shm->size)); + shm->kaddr = NULL; +} + static void optee_bus_scan(struct work_struct *work) { WARN_ON(optee_enumerate_devices(PTA_CMD_GET_DEVICES_SUPP)); diff --git a/drivers/tee/optee/device.c b/drivers/tee/optee/device.c index 128a2d2a50a1..f3947be13e2e 100644 --- a/drivers/tee/optee/device.c +++ b/drivers/tee/optee/device.c @@ -121,10 +121,9 @@ static int __optee_enumerate_devices(u32 func) if (rc < 0 || !shm_size) goto out_sess; - device_shm = tee_shm_alloc(ctx, shm_size, - TEE_SHM_MAPPED | TEE_SHM_DMA_BUF); + device_shm = tee_shm_alloc_kernel_buf(ctx, shm_size); if (IS_ERR(device_shm)) { - pr_err("tee_shm_alloc failed\n"); + pr_err("tee_shm_alloc_kernel_buf failed\n"); rc = PTR_ERR(device_shm); goto out_sess; } diff --git a/drivers/tee/optee/ffa_abi.c b/drivers/tee/optee/ffa_abi.c index f744ab15bf2c..a5eb4ef46971 100644 --- a/drivers/tee/optee/ffa_abi.c +++ b/drivers/tee/optee/ffa_abi.c @@ -369,30 +369,28 @@ static int optee_ffa_shm_unregister_supp(struct tee_context *ctx, * The main function is optee_ffa_shm_pool_alloc_pages(). */ -static int pool_ffa_op_alloc(struct tee_shm_pool_mgr *poolm, - struct tee_shm *shm, size_t size) +static int pool_ffa_op_alloc(struct tee_shm_pool *pool, + struct tee_shm *shm, size_t size, size_t align) { - return optee_pool_op_alloc_helper(poolm, shm, size, + return optee_pool_op_alloc_helper(pool, shm, size, align, optee_ffa_shm_register); } -static void pool_ffa_op_free(struct tee_shm_pool_mgr *poolm, +static void pool_ffa_op_free(struct tee_shm_pool *pool, struct tee_shm *shm) { - optee_ffa_shm_unregister(shm->ctx, shm); - free_pages((unsigned long)shm->kaddr, get_order(shm->size)); - shm->kaddr = NULL; + optee_pool_op_free_helper(pool, shm, optee_ffa_shm_unregister); } -static void pool_ffa_op_destroy_poolmgr(struct tee_shm_pool_mgr *poolm) +static void pool_ffa_op_destroy_pool(struct tee_shm_pool *pool) { - kfree(poolm); + kfree(pool); } -static const struct tee_shm_pool_mgr_ops pool_ffa_ops = { +static const struct tee_shm_pool_ops pool_ffa_ops = { .alloc = pool_ffa_op_alloc, .free = pool_ffa_op_free, - .destroy_poolmgr = pool_ffa_op_destroy_poolmgr, + .destroy_pool = pool_ffa_op_destroy_pool, }; /** @@ -401,16 +399,16 @@ static const struct tee_shm_pool_mgr_ops pool_ffa_ops = { * This pool is used with OP-TEE over FF-A. In this case command buffers * and such are allocated from kernel's own memory. */ -static struct tee_shm_pool_mgr *optee_ffa_shm_pool_alloc_pages(void) +static struct tee_shm_pool *optee_ffa_shm_pool_alloc_pages(void) { - struct tee_shm_pool_mgr *mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); + struct tee_shm_pool *pool = kzalloc(sizeof(*pool), GFP_KERNEL); - if (!mgr) + if (!pool) return ERR_PTR(-ENOMEM); - mgr->ops = &pool_ffa_ops; + pool->ops = &pool_ffa_ops; - return mgr; + return pool; } /* @@ -440,8 +438,8 @@ static void handle_ffa_rpc_func_cmd_shm_alloc(struct tee_context *ctx, shm = optee_rpc_cmd_alloc_suppl(ctx, arg->params[0].u.value.b); break; case OPTEE_RPC_SHM_TYPE_KERNEL: - shm = tee_shm_alloc(optee->ctx, arg->params[0].u.value.b, - TEE_SHM_MAPPED | TEE_SHM_PRIV); + shm = tee_shm_alloc_priv_buf(optee->ctx, + arg->params[0].u.value.b); break; default: arg->ret = TEEC_ERROR_BAD_PARAMETERS; @@ -700,33 +698,6 @@ static bool optee_ffa_exchange_caps(struct ffa_device *ffa_dev, return true; } -static struct tee_shm_pool *optee_ffa_config_dyn_shm(void) -{ - struct tee_shm_pool_mgr *priv_mgr; - struct tee_shm_pool_mgr *dmabuf_mgr; - void *rc; - - rc = optee_ffa_shm_pool_alloc_pages(); - if (IS_ERR(rc)) - return rc; - priv_mgr = rc; - - rc = optee_ffa_shm_pool_alloc_pages(); - if (IS_ERR(rc)) { - tee_shm_pool_mgr_destroy(priv_mgr); - return rc; - } - dmabuf_mgr = rc; - - rc = tee_shm_pool_alloc(priv_mgr, dmabuf_mgr); - if (IS_ERR(rc)) { - tee_shm_pool_mgr_destroy(priv_mgr); - tee_shm_pool_mgr_destroy(dmabuf_mgr); - } - - return rc; -} - static void optee_ffa_get_version(struct tee_device *teedev, struct tee_ioctl_version_data *vers) { @@ -824,7 +795,7 @@ static int optee_ffa_probe(struct ffa_device *ffa_dev) if (!optee) return -ENOMEM; - pool = optee_ffa_config_dyn_shm(); + pool = optee_ffa_shm_pool_alloc_pages(); if (IS_ERR(pool)) { rc = PTR_ERR(pool); goto err_free_optee; diff --git a/drivers/tee/optee/optee_private.h b/drivers/tee/optee/optee_private.h index 92bc47bef95f..e77765c78878 100644 --- a/drivers/tee/optee/optee_private.h +++ b/drivers/tee/optee/optee_private.h @@ -229,13 +229,16 @@ int optee_cancel_req(struct tee_context *ctx, u32 cancel_id, u32 session); int optee_enumerate_devices(u32 func); void optee_unregister_devices(void); -int optee_pool_op_alloc_helper(struct tee_shm_pool_mgr *poolm, - struct tee_shm *shm, size_t size, +int optee_pool_op_alloc_helper(struct tee_shm_pool *pool, struct tee_shm *shm, + size_t size, size_t align, int (*shm_register)(struct tee_context *ctx, struct tee_shm *shm, struct page **pages, size_t num_pages, unsigned long start)); +void optee_pool_op_free_helper(struct tee_shm_pool *pool, struct tee_shm *shm, + int (*shm_unregister)(struct tee_context *ctx, + struct tee_shm *shm)); void optee_remove_common(struct optee *optee); diff --git a/drivers/tee/optee/smc_abi.c b/drivers/tee/optee/smc_abi.c index c517d310249f..67b7f7d2ff27 100644 --- a/drivers/tee/optee/smc_abi.c +++ b/drivers/tee/optee/smc_abi.c @@ -42,7 +42,15 @@ * 6. Driver initialization. */ -#define OPTEE_SHM_NUM_PRIV_PAGES CONFIG_OPTEE_SHM_NUM_PRIV_PAGES +/* + * A typical OP-TEE private shm allocation is 224 bytes (argument struct + * with 6 parameters, needed for open session). So with an alignment of 512 + * we'll waste a bit more than 50%. However, it's only expected that we'll + * have a handful of these structs allocated at a time. Most memory will + * be allocated aligned to the page size, So all in all this should scale + * up and down quite well. + */ +#define OPTEE_MIN_STATIC_POOL_ALIGN 9 /* 512 bytes aligned */ /* * 1. Convert between struct tee_param and struct optee_msg_param @@ -220,7 +228,7 @@ static int optee_to_msg_param(struct optee *optee, case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT: case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT: case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT: - if (tee_shm_is_registered(p->u.memref.shm)) + if (tee_shm_is_dynamic(p->u.memref.shm)) rc = to_msg_param_reg_mem(mp, p); else rc = to_msg_param_tmp_mem(mp, p); @@ -522,38 +530,38 @@ static int optee_shm_unregister_supp(struct tee_context *ctx, * The main function is optee_shm_pool_alloc_pages(). */ -static int pool_op_alloc(struct tee_shm_pool_mgr *poolm, - struct tee_shm *shm, size_t size) +static int pool_op_alloc(struct tee_shm_pool *pool, + struct tee_shm *shm, size_t size, size_t align) { /* * Shared memory private to the OP-TEE driver doesn't need * to be registered with OP-TEE. */ if (shm->flags & TEE_SHM_PRIV) - return optee_pool_op_alloc_helper(poolm, shm, size, NULL); + return optee_pool_op_alloc_helper(pool, shm, size, align, NULL); - return optee_pool_op_alloc_helper(poolm, shm, size, optee_shm_register); + return optee_pool_op_alloc_helper(pool, shm, size, align, + optee_shm_register); } -static void pool_op_free(struct tee_shm_pool_mgr *poolm, +static void pool_op_free(struct tee_shm_pool *pool, struct tee_shm *shm) { if (!(shm->flags & TEE_SHM_PRIV)) - optee_shm_unregister(shm->ctx, shm); - - free_pages((unsigned long)shm->kaddr, get_order(shm->size)); - shm->kaddr = NULL; + optee_pool_op_free_helper(pool, shm, optee_shm_unregister); + else + optee_pool_op_free_helper(pool, shm, NULL); } -static void pool_op_destroy_poolmgr(struct tee_shm_pool_mgr *poolm) +static void pool_op_destroy_pool(struct tee_shm_pool *pool) { - kfree(poolm); + kfree(pool); } -static const struct tee_shm_pool_mgr_ops pool_ops = { +static const struct tee_shm_pool_ops pool_ops = { .alloc = pool_op_alloc, .free = pool_op_free, - .destroy_poolmgr = pool_op_destroy_poolmgr, + .destroy_pool = pool_op_destroy_pool, }; /** @@ -562,16 +570,16 @@ static const struct tee_shm_pool_mgr_ops pool_ops = { * This pool is used when OP-TEE supports dymanic SHM. In this case * command buffers and such are allocated from kernel's own memory. */ -static struct tee_shm_pool_mgr *optee_shm_pool_alloc_pages(void) +static struct tee_shm_pool *optee_shm_pool_alloc_pages(void) { - struct tee_shm_pool_mgr *mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); + struct tee_shm_pool *pool = kzalloc(sizeof(*pool), GFP_KERNEL); - if (!mgr) + if (!pool) return ERR_PTR(-ENOMEM); - mgr->ops = &pool_ops; + pool->ops = &pool_ops; - return mgr; + return pool; } /* @@ -642,8 +650,7 @@ static void handle_rpc_func_cmd_shm_alloc(struct tee_context *ctx, shm = optee_rpc_cmd_alloc_suppl(ctx, sz); break; case OPTEE_RPC_SHM_TYPE_KERNEL: - shm = tee_shm_alloc(optee->ctx, sz, - TEE_SHM_MAPPED | TEE_SHM_PRIV); + shm = tee_shm_alloc_priv_buf(optee->ctx, sz); break; default: arg->ret = TEEC_ERROR_BAD_PARAMETERS; @@ -662,7 +669,7 @@ static void handle_rpc_func_cmd_shm_alloc(struct tee_context *ctx, sz = tee_shm_get_size(shm); - if (tee_shm_is_registered(shm)) { + if (tee_shm_is_dynamic(shm)) { struct page **pages; u64 *pages_list; size_t page_num; @@ -768,8 +775,7 @@ static void optee_handle_rpc(struct tee_context *ctx, switch (OPTEE_SMC_RETURN_GET_RPC_FUNC(param->a0)) { case OPTEE_SMC_RPC_FUNC_ALLOC: - shm = tee_shm_alloc(optee->ctx, param->a1, - TEE_SHM_MAPPED | TEE_SHM_PRIV); + shm = tee_shm_alloc_priv_buf(optee->ctx, param->a1); if (!IS_ERR(shm) && !tee_shm_get_pa(shm, 0, &pa)) { reg_pair_from_64(¶m->a1, ¶m->a2, pa); reg_pair_from_64(¶m->a4, ¶m->a5, @@ -1143,33 +1149,6 @@ static bool optee_msg_exchange_capabilities(optee_invoke_fn *invoke_fn, return true; } -static struct tee_shm_pool *optee_config_dyn_shm(void) -{ - struct tee_shm_pool_mgr *priv_mgr; - struct tee_shm_pool_mgr *dmabuf_mgr; - void *rc; - - rc = optee_shm_pool_alloc_pages(); - if (IS_ERR(rc)) - return rc; - priv_mgr = rc; - - rc = optee_shm_pool_alloc_pages(); - if (IS_ERR(rc)) { - tee_shm_pool_mgr_destroy(priv_mgr); - return rc; - } - dmabuf_mgr = rc; - - rc = tee_shm_pool_alloc(priv_mgr, dmabuf_mgr); - if (IS_ERR(rc)) { - tee_shm_pool_mgr_destroy(priv_mgr); - tee_shm_pool_mgr_destroy(dmabuf_mgr); - } - - return rc; -} - static struct tee_shm_pool * optee_config_shm_memremap(optee_invoke_fn *invoke_fn, void **memremaped_shm) { @@ -1183,10 +1162,7 @@ optee_config_shm_memremap(optee_invoke_fn *invoke_fn, void **memremaped_shm) phys_addr_t begin; phys_addr_t end; void *va; - struct tee_shm_pool_mgr *priv_mgr; - struct tee_shm_pool_mgr *dmabuf_mgr; void *rc; - const int sz = OPTEE_SHM_NUM_PRIV_PAGES * PAGE_SIZE; invoke_fn(OPTEE_SMC_GET_SHM_CONFIG, 0, 0, 0, 0, 0, 0, 0, &res.smccc); if (res.result.status != OPTEE_SMC_RETURN_OK) { @@ -1204,11 +1180,6 @@ optee_config_shm_memremap(optee_invoke_fn *invoke_fn, void **memremaped_shm) paddr = begin; size = end - begin; - if (size < 2 * OPTEE_SHM_NUM_PRIV_PAGES * PAGE_SIZE) { - pr_err("too small shared memory area\n"); - return ERR_PTR(-EINVAL); - } - va = memremap(paddr, size, MEMREMAP_WB); if (!va) { pr_err("shared memory ioremap failed\n"); @@ -1216,35 +1187,13 @@ optee_config_shm_memremap(optee_invoke_fn *invoke_fn, void **memremaped_shm) } vaddr = (unsigned long)va; - rc = tee_shm_pool_mgr_alloc_res_mem(vaddr, paddr, sz, - 3 /* 8 bytes aligned */); + rc = tee_shm_pool_alloc_res_mem(vaddr, paddr, size, + OPTEE_MIN_STATIC_POOL_ALIGN); if (IS_ERR(rc)) - goto err_memunmap; - priv_mgr = rc; + memunmap(va); + else + *memremaped_shm = va; - vaddr += sz; - paddr += sz; - size -= sz; - - rc = tee_shm_pool_mgr_alloc_res_mem(vaddr, paddr, size, PAGE_SHIFT); - if (IS_ERR(rc)) - goto err_free_priv_mgr; - dmabuf_mgr = rc; - - rc = tee_shm_pool_alloc(priv_mgr, dmabuf_mgr); - if (IS_ERR(rc)) - goto err_free_dmabuf_mgr; - - *memremaped_shm = va; - - return rc; - -err_free_dmabuf_mgr: - tee_shm_pool_mgr_destroy(dmabuf_mgr); -err_free_priv_mgr: - tee_shm_pool_mgr_destroy(priv_mgr); -err_memunmap: - memunmap(va); return rc; } @@ -1366,7 +1315,7 @@ static int optee_probe(struct platform_device *pdev) * Try to use dynamic shared memory if possible */ if (sec_caps & OPTEE_SMC_SEC_CAP_DYNAMIC_SHM) - pool = optee_config_dyn_shm(); + pool = optee_shm_pool_alloc_pages(); /* * If dynamic shared memory is not available or failed - try static one diff --git a/drivers/tee/tee_core.c b/drivers/tee/tee_core.c index 3fc426dad2df..8aa1a4836b92 100644 --- a/drivers/tee/tee_core.c +++ b/drivers/tee/tee_core.c @@ -297,7 +297,7 @@ static int tee_ioctl_shm_alloc(struct tee_context *ctx, if (data.flags) return -EINVAL; - shm = tee_shm_alloc(ctx, data.size, TEE_SHM_MAPPED | TEE_SHM_DMA_BUF); + shm = tee_shm_alloc_user_buf(ctx, data.size); if (IS_ERR(shm)) return PTR_ERR(shm); @@ -334,8 +334,7 @@ tee_ioctl_shm_register(struct tee_context *ctx, if (data.flags) return -EINVAL; - shm = tee_shm_register(ctx, data.addr, data.length, - TEE_SHM_DMA_BUF | TEE_SHM_USER_MAPPED); + shm = tee_shm_register_user_buf(ctx, data.addr, data.length); if (IS_ERR(shm)) return PTR_ERR(shm); diff --git a/drivers/tee/tee_private.h b/drivers/tee/tee_private.h index e55204df31ce..409cadcc1cff 100644 --- a/drivers/tee/tee_private.h +++ b/drivers/tee/tee_private.h @@ -12,17 +12,6 @@ #include #include -/** - * struct tee_shm_pool - shared memory pool - * @private_mgr: pool manager for shared memory only between kernel - * and secure world - * @dma_buf_mgr: pool manager for shared memory exported to user space - */ -struct tee_shm_pool { - struct tee_shm_pool_mgr *private_mgr; - struct tee_shm_pool_mgr *dma_buf_mgr; -}; - #define TEE_DEVICE_FLAG_REGISTERED 0x1 #define TEE_MAX_DEV_NAME_LEN 32 @@ -68,4 +57,8 @@ void tee_device_put(struct tee_device *teedev); void teedev_ctx_get(struct tee_context *ctx); void teedev_ctx_put(struct tee_context *ctx); +struct tee_shm *tee_shm_alloc_user_buf(struct tee_context *ctx, size_t size); +struct tee_shm *tee_shm_register_user_buf(struct tee_context *ctx, + unsigned long addr, size_t length); + #endif /*TEE_PRIVATE_H*/ diff --git a/drivers/tee/tee_shm.c b/drivers/tee/tee_shm.c index 499fccba3d74..f31e29e8f1ca 100644 --- a/drivers/tee/tee_shm.c +++ b/drivers/tee/tee_shm.c @@ -12,17 +12,43 @@ #include #include "tee_private.h" +static void shm_put_kernel_pages(struct page **pages, size_t page_count) +{ + size_t n; + + for (n = 0; n < page_count; n++) + put_page(pages[n]); +} + +static int shm_get_kernel_pages(unsigned long start, size_t page_count, + struct page **pages) +{ + struct kvec *kiov; + size_t n; + int rc; + + kiov = kcalloc(page_count, sizeof(*kiov), GFP_KERNEL); + if (!kiov) + return -ENOMEM; + + for (n = 0; n < page_count; n++) { + kiov[n].iov_base = (void *)(start + n * PAGE_SIZE); + kiov[n].iov_len = PAGE_SIZE; + } + + rc = get_kernel_pages(kiov, page_count, 0, pages); + kfree(kiov); + + return rc; +} + static void release_registered_pages(struct tee_shm *shm) { if (shm->pages) { - if (shm->flags & TEE_SHM_USER_MAPPED) { + if (shm->flags & TEE_SHM_USER_MAPPED) unpin_user_pages(shm->pages, shm->num_pages); - } else { - size_t n; - - for (n = 0; n < shm->num_pages; n++) - put_page(shm->pages[n]); - } + else + shm_put_kernel_pages(shm->pages, shm->num_pages); kfree(shm->pages); } @@ -31,15 +57,8 @@ static void release_registered_pages(struct tee_shm *shm) static void tee_shm_release(struct tee_device *teedev, struct tee_shm *shm) { if (shm->flags & TEE_SHM_POOL) { - struct tee_shm_pool_mgr *poolm; - - if (shm->flags & TEE_SHM_DMA_BUF) - poolm = teedev->pool->dma_buf_mgr; - else - poolm = teedev->pool->private_mgr; - - poolm->ops->free(poolm, shm); - } else if (shm->flags & TEE_SHM_REGISTER) { + teedev->pool->ops->free(teedev->pool, shm); + } else if (shm->flags & TEE_SHM_DYNAMIC) { int rc = teedev->desc->ops->shm_unregister(shm->ctx, shm); if (rc) @@ -56,25 +75,14 @@ static void tee_shm_release(struct tee_device *teedev, struct tee_shm *shm) tee_device_put(teedev); } -struct tee_shm *tee_shm_alloc(struct tee_context *ctx, size_t size, u32 flags) +static struct tee_shm *shm_alloc_helper(struct tee_context *ctx, size_t size, + size_t align, u32 flags, int id) { struct tee_device *teedev = ctx->teedev; - struct tee_shm_pool_mgr *poolm = NULL; struct tee_shm *shm; void *ret; int rc; - if (!(flags & TEE_SHM_MAPPED)) { - dev_err(teedev->dev.parent, - "only mapped allocations supported\n"); - return ERR_PTR(-EINVAL); - } - - if ((flags & ~(TEE_SHM_MAPPED | TEE_SHM_DMA_BUF | TEE_SHM_PRIV))) { - dev_err(teedev->dev.parent, "invalid shm flags 0x%x", flags); - return ERR_PTR(-EINVAL); - } - if (!tee_device_get(teedev)) return ERR_PTR(-EINVAL); @@ -91,41 +99,76 @@ struct tee_shm *tee_shm_alloc(struct tee_context *ctx, size_t size, u32 flags) } refcount_set(&shm->refcount, 1); - shm->flags = flags | TEE_SHM_POOL; - shm->ctx = ctx; - if (flags & TEE_SHM_DMA_BUF) - poolm = teedev->pool->dma_buf_mgr; - else - poolm = teedev->pool->private_mgr; + shm->flags = flags; + shm->id = id; - rc = poolm->ops->alloc(poolm, shm, size); + /* + * We're assigning this as it is needed if the shm is to be + * registered. If this function returns OK then the caller expected + * to call teedev_ctx_get() or clear shm->ctx in case it's not + * needed any longer. + */ + shm->ctx = ctx; + + rc = teedev->pool->ops->alloc(teedev->pool, shm, size, align); if (rc) { ret = ERR_PTR(rc); goto err_kfree; } - if (flags & TEE_SHM_DMA_BUF) { - mutex_lock(&teedev->mutex); - shm->id = idr_alloc(&teedev->idr, shm, 1, 0, GFP_KERNEL); - mutex_unlock(&teedev->mutex); - if (shm->id < 0) { - ret = ERR_PTR(shm->id); - goto err_pool_free; - } - } - teedev_ctx_get(ctx); - return shm; -err_pool_free: - poolm->ops->free(poolm, shm); err_kfree: kfree(shm); err_dev_put: tee_device_put(teedev); return ret; } -EXPORT_SYMBOL_GPL(tee_shm_alloc); + +/** + * tee_shm_alloc_user_buf() - Allocate shared memory for user space + * @ctx: Context that allocates the shared memory + * @size: Requested size of shared memory + * + * Memory allocated as user space shared memory is automatically freed when + * the TEE file pointer is closed. The primary usage of this function is + * when the TEE driver doesn't support registering ordinary user space + * memory. + * + * @returns a pointer to 'struct tee_shm' + */ +struct tee_shm *tee_shm_alloc_user_buf(struct tee_context *ctx, size_t size) +{ + u32 flags = TEE_SHM_DYNAMIC | TEE_SHM_POOL; + struct tee_device *teedev = ctx->teedev; + struct tee_shm *shm; + void *ret; + int id; + + mutex_lock(&teedev->mutex); + id = idr_alloc(&teedev->idr, NULL, 1, 0, GFP_KERNEL); + mutex_unlock(&teedev->mutex); + if (id < 0) + return ERR_PTR(id); + + shm = shm_alloc_helper(ctx, size, PAGE_SIZE, flags, id); + if (IS_ERR(shm)) { + mutex_lock(&teedev->mutex); + idr_remove(&teedev->idr, id); + mutex_unlock(&teedev->mutex); + return shm; + } + + mutex_lock(&teedev->mutex); + ret = idr_replace(&teedev->idr, shm, id); + mutex_unlock(&teedev->mutex); + if (IS_ERR(ret)) { + tee_shm_free(shm); + return ret; + } + + return shm; +} /** * tee_shm_alloc_kernel_buf() - Allocate shared memory for kernel buffer @@ -141,32 +184,54 @@ EXPORT_SYMBOL_GPL(tee_shm_alloc); */ struct tee_shm *tee_shm_alloc_kernel_buf(struct tee_context *ctx, size_t size) { - return tee_shm_alloc(ctx, size, TEE_SHM_MAPPED); + u32 flags = TEE_SHM_DYNAMIC | TEE_SHM_POOL; + + return shm_alloc_helper(ctx, size, PAGE_SIZE, flags, -1); } EXPORT_SYMBOL_GPL(tee_shm_alloc_kernel_buf); -struct tee_shm *tee_shm_register(struct tee_context *ctx, unsigned long addr, - size_t length, u32 flags) +/** + * tee_shm_alloc_priv_buf() - Allocate shared memory for a privately shared + * kernel buffer + * @ctx: Context that allocates the shared memory + * @size: Requested size of shared memory + * + * This function returns similar shared memory as + * tee_shm_alloc_kernel_buf(), but with the difference that the memory + * might not be registered in secure world in case the driver supports + * passing memory not registered in advance. + * + * This function should normally only be used internally in the TEE + * drivers. + * + * @returns a pointer to 'struct tee_shm' + */ +struct tee_shm *tee_shm_alloc_priv_buf(struct tee_context *ctx, size_t size) +{ + u32 flags = TEE_SHM_PRIV | TEE_SHM_POOL; + + return shm_alloc_helper(ctx, size, sizeof(long) * 2, flags, -1); +} +EXPORT_SYMBOL_GPL(tee_shm_alloc_priv_buf); + +static struct tee_shm * +register_shm_helper(struct tee_context *ctx, unsigned long addr, + size_t length, u32 flags, int id) { struct tee_device *teedev = ctx->teedev; - const u32 req_user_flags = TEE_SHM_DMA_BUF | TEE_SHM_USER_MAPPED; - const u32 req_kernel_flags = TEE_SHM_DMA_BUF | TEE_SHM_KERNEL_MAPPED; struct tee_shm *shm; + unsigned long start; + size_t num_pages; void *ret; int rc; - int num_pages; - unsigned long start; - - if (flags != req_user_flags && flags != req_kernel_flags) - return ERR_PTR(-ENOTSUPP); if (!tee_device_get(teedev)) return ERR_PTR(-EINVAL); if (!teedev->desc->ops->shm_register || !teedev->desc->ops->shm_unregister) { - tee_device_put(teedev); - return ERR_PTR(-ENOTSUPP); + ret = ERR_PTR(-ENOTSUPP); + goto err_dev_put; } teedev_ctx_get(ctx); @@ -174,13 +239,13 @@ struct tee_shm *tee_shm_register(struct tee_context *ctx, unsigned long addr, shm = kzalloc(sizeof(*shm), GFP_KERNEL); if (!shm) { ret = ERR_PTR(-ENOMEM); - goto err; + goto err_ctx_put; } refcount_set(&shm->refcount, 1); - shm->flags = flags | TEE_SHM_REGISTER; + shm->flags = flags; shm->ctx = ctx; - shm->id = -1; + shm->id = id; addr = untagged_addr(addr); start = rounddown(addr, PAGE_SIZE); shm->offset = addr - start; @@ -189,71 +254,106 @@ struct tee_shm *tee_shm_register(struct tee_context *ctx, unsigned long addr, shm->pages = kcalloc(num_pages, sizeof(*shm->pages), GFP_KERNEL); if (!shm->pages) { ret = ERR_PTR(-ENOMEM); - goto err; + goto err_free_shm; } - if (flags & TEE_SHM_USER_MAPPED) { + if (flags & TEE_SHM_USER_MAPPED) rc = pin_user_pages_fast(start, num_pages, FOLL_WRITE, shm->pages); - } else { - struct kvec *kiov; - int i; - - kiov = kcalloc(num_pages, sizeof(*kiov), GFP_KERNEL); - if (!kiov) { - ret = ERR_PTR(-ENOMEM); - goto err; - } - - for (i = 0; i < num_pages; i++) { - kiov[i].iov_base = (void *)(start + i * PAGE_SIZE); - kiov[i].iov_len = PAGE_SIZE; - } - - rc = get_kernel_pages(kiov, num_pages, 0, shm->pages); - kfree(kiov); - } + else + rc = shm_get_kernel_pages(start, num_pages, shm->pages); if (rc > 0) shm->num_pages = rc; if (rc != num_pages) { if (rc >= 0) rc = -ENOMEM; ret = ERR_PTR(rc); - goto err; - } - - mutex_lock(&teedev->mutex); - shm->id = idr_alloc(&teedev->idr, shm, 1, 0, GFP_KERNEL); - mutex_unlock(&teedev->mutex); - - if (shm->id < 0) { - ret = ERR_PTR(shm->id); - goto err; + goto err_put_shm_pages; } rc = teedev->desc->ops->shm_register(ctx, shm, shm->pages, shm->num_pages, start); if (rc) { ret = ERR_PTR(rc); - goto err; + goto err_put_shm_pages; } return shm; -err: - if (shm) { - if (shm->id >= 0) { - mutex_lock(&teedev->mutex); - idr_remove(&teedev->idr, shm->id); - mutex_unlock(&teedev->mutex); - } - release_registered_pages(shm); - } +err_put_shm_pages: + if (flags & TEE_SHM_USER_MAPPED) + unpin_user_pages(shm->pages, shm->num_pages); + else + shm_put_kernel_pages(shm->pages, shm->num_pages); + kfree(shm->pages); +err_free_shm: kfree(shm); +err_ctx_put: teedev_ctx_put(ctx); +err_dev_put: tee_device_put(teedev); return ret; } -EXPORT_SYMBOL_GPL(tee_shm_register); + +/** + * tee_shm_register_user_buf() - Register a userspace shared memory buffer + * @ctx: Context that registers the shared memory + * @addr: The userspace address of the shared buffer + * @length: Length of the shared buffer + * + * @returns a pointer to 'struct tee_shm' + */ +struct tee_shm *tee_shm_register_user_buf(struct tee_context *ctx, + unsigned long addr, size_t length) +{ + u32 flags = TEE_SHM_USER_MAPPED | TEE_SHM_DYNAMIC; + struct tee_device *teedev = ctx->teedev; + struct tee_shm *shm; + void *ret; + int id; + + mutex_lock(&teedev->mutex); + id = idr_alloc(&teedev->idr, NULL, 1, 0, GFP_KERNEL); + mutex_unlock(&teedev->mutex); + if (id < 0) + return ERR_PTR(id); + + shm = register_shm_helper(ctx, addr, length, flags, id); + if (IS_ERR(shm)) { + mutex_lock(&teedev->mutex); + idr_remove(&teedev->idr, id); + mutex_unlock(&teedev->mutex); + return shm; + } + + mutex_lock(&teedev->mutex); + ret = idr_replace(&teedev->idr, shm, id); + mutex_unlock(&teedev->mutex); + if (IS_ERR(ret)) { + tee_shm_free(shm); + return ret; + } + + return shm; +} + +/** + * tee_shm_register_kernel_buf() - Register kernel memory to be shared with + * secure world + * @ctx: Context that registers the shared memory + * @addr: The buffer + * @length: Length of the buffer + * + * @returns a pointer to 'struct tee_shm' + */ + +struct tee_shm *tee_shm_register_kernel_buf(struct tee_context *ctx, + void *addr, size_t length) +{ + u32 flags = TEE_SHM_DYNAMIC; + + return register_shm_helper(ctx, (unsigned long)addr, length, flags, -1); +} +EXPORT_SYMBOL_GPL(tee_shm_register_kernel_buf); static int tee_shm_fop_release(struct inode *inode, struct file *filp) { @@ -293,7 +393,7 @@ int tee_shm_get_fd(struct tee_shm *shm) { int fd; - if (!(shm->flags & TEE_SHM_DMA_BUF)) + if (shm->id < 0) return -EINVAL; /* matched by tee_shm_put() in tee_shm_op_release() */ @@ -323,7 +423,7 @@ EXPORT_SYMBOL_GPL(tee_shm_free); */ int tee_shm_va2pa(struct tee_shm *shm, void *va, phys_addr_t *pa) { - if (!(shm->flags & TEE_SHM_MAPPED)) + if (!shm->kaddr) return -EINVAL; /* Check that we're in the range of the shm */ if ((char *)va < (char *)shm->kaddr) @@ -345,7 +445,7 @@ EXPORT_SYMBOL_GPL(tee_shm_va2pa); */ int tee_shm_pa2va(struct tee_shm *shm, phys_addr_t pa, void **va) { - if (!(shm->flags & TEE_SHM_MAPPED)) + if (!shm->kaddr) return -EINVAL; /* Check that we're in the range of the shm */ if (pa < shm->paddr) @@ -373,7 +473,7 @@ EXPORT_SYMBOL_GPL(tee_shm_pa2va); */ void *tee_shm_get_va(struct tee_shm *shm, size_t offs) { - if (!(shm->flags & TEE_SHM_MAPPED)) + if (!shm->kaddr) return ERR_PTR(-EINVAL); if (offs >= shm->size) return ERR_PTR(-EINVAL); @@ -448,7 +548,7 @@ void tee_shm_put(struct tee_shm *shm) * the refcount_inc() in tee_shm_get_from_id() never starts * from 0. */ - if (shm->flags & TEE_SHM_DMA_BUF) + if (shm->id >= 0) idr_remove(&teedev->idr, shm->id); do_release = true; } diff --git a/drivers/tee/tee_shm_pool.c b/drivers/tee/tee_shm_pool.c index fcbb461fc59c..058bfbac657a 100644 --- a/drivers/tee/tee_shm_pool.c +++ b/drivers/tee/tee_shm_pool.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015, Linaro Limited + * Copyright (c) 2015, 2017, 2022 Linaro Limited */ #include #include @@ -9,14 +9,16 @@ #include #include "tee_private.h" -static int pool_op_gen_alloc(struct tee_shm_pool_mgr *poolm, - struct tee_shm *shm, size_t size) +static int pool_op_gen_alloc(struct tee_shm_pool *pool, struct tee_shm *shm, + size_t size, size_t align) { unsigned long va; - struct gen_pool *genpool = poolm->private_data; - size_t s = roundup(size, 1 << genpool->min_alloc_order); + struct gen_pool *genpool = pool->private_data; + size_t a = max_t(size_t, align, BIT(genpool->min_alloc_order)); + struct genpool_data_align data = { .align = a }; + size_t s = roundup(size, a); - va = gen_pool_alloc(genpool, s); + va = gen_pool_alloc_algo(genpool, s, gen_pool_first_fit_align, &data); if (!va) return -ENOMEM; @@ -24,163 +26,67 @@ static int pool_op_gen_alloc(struct tee_shm_pool_mgr *poolm, shm->kaddr = (void *)va; shm->paddr = gen_pool_virt_to_phys(genpool, va); shm->size = s; + /* + * This is from a static shared memory pool so no need to register + * each chunk, and no need to unregister later either. + */ + shm->flags &= ~TEE_SHM_DYNAMIC; return 0; } -static void pool_op_gen_free(struct tee_shm_pool_mgr *poolm, - struct tee_shm *shm) +static void pool_op_gen_free(struct tee_shm_pool *pool, struct tee_shm *shm) { - gen_pool_free(poolm->private_data, (unsigned long)shm->kaddr, + gen_pool_free(pool->private_data, (unsigned long)shm->kaddr, shm->size); shm->kaddr = NULL; } -static void pool_op_gen_destroy_poolmgr(struct tee_shm_pool_mgr *poolm) +static void pool_op_gen_destroy_pool(struct tee_shm_pool *pool) { - gen_pool_destroy(poolm->private_data); - kfree(poolm); + gen_pool_destroy(pool->private_data); + kfree(pool); } -static const struct tee_shm_pool_mgr_ops pool_ops_generic = { +static const struct tee_shm_pool_ops pool_ops_generic = { .alloc = pool_op_gen_alloc, .free = pool_op_gen_free, - .destroy_poolmgr = pool_op_gen_destroy_poolmgr, + .destroy_pool = pool_op_gen_destroy_pool, }; -/** - * tee_shm_pool_alloc_res_mem() - Create a shared memory pool from reserved - * memory range - * @priv_info: Information for driver private shared memory pool - * @dmabuf_info: Information for dma-buf shared memory pool - * - * Start and end of pools will must be page aligned. - * - * Allocation with the flag TEE_SHM_DMA_BUF set will use the range supplied - * in @dmabuf, others will use the range provided by @priv. - * - * @returns pointer to a 'struct tee_shm_pool' or an ERR_PTR on failure. - */ -struct tee_shm_pool * -tee_shm_pool_alloc_res_mem(struct tee_shm_pool_mem_info *priv_info, - struct tee_shm_pool_mem_info *dmabuf_info) -{ - struct tee_shm_pool_mgr *priv_mgr; - struct tee_shm_pool_mgr *dmabuf_mgr; - void *rc; - - /* - * Create the pool for driver private shared memory - */ - rc = tee_shm_pool_mgr_alloc_res_mem(priv_info->vaddr, priv_info->paddr, - priv_info->size, - 3 /* 8 byte aligned */); - if (IS_ERR(rc)) - return rc; - priv_mgr = rc; - - /* - * Create the pool for dma_buf shared memory - */ - rc = tee_shm_pool_mgr_alloc_res_mem(dmabuf_info->vaddr, - dmabuf_info->paddr, - dmabuf_info->size, PAGE_SHIFT); - if (IS_ERR(rc)) - goto err_free_priv_mgr; - dmabuf_mgr = rc; - - rc = tee_shm_pool_alloc(priv_mgr, dmabuf_mgr); - if (IS_ERR(rc)) - goto err_free_dmabuf_mgr; - - return rc; - -err_free_dmabuf_mgr: - tee_shm_pool_mgr_destroy(dmabuf_mgr); -err_free_priv_mgr: - tee_shm_pool_mgr_destroy(priv_mgr); - - return rc; -} -EXPORT_SYMBOL_GPL(tee_shm_pool_alloc_res_mem); - -struct tee_shm_pool_mgr *tee_shm_pool_mgr_alloc_res_mem(unsigned long vaddr, - phys_addr_t paddr, - size_t size, - int min_alloc_order) +struct tee_shm_pool *tee_shm_pool_alloc_res_mem(unsigned long vaddr, + phys_addr_t paddr, size_t size, + int min_alloc_order) { const size_t page_mask = PAGE_SIZE - 1; - struct tee_shm_pool_mgr *mgr; + struct tee_shm_pool *pool; int rc; /* Start and end must be page aligned */ if (vaddr & page_mask || paddr & page_mask || size & page_mask) return ERR_PTR(-EINVAL); - mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); - if (!mgr) - return ERR_PTR(-ENOMEM); - - mgr->private_data = gen_pool_create(min_alloc_order, -1); - if (!mgr->private_data) { - rc = -ENOMEM; - goto err; - } - - gen_pool_set_algo(mgr->private_data, gen_pool_best_fit, NULL); - rc = gen_pool_add_virt(mgr->private_data, vaddr, paddr, size, -1); - if (rc) { - gen_pool_destroy(mgr->private_data); - goto err; - } - - mgr->ops = &pool_ops_generic; - - return mgr; -err: - kfree(mgr); - - return ERR_PTR(rc); -} -EXPORT_SYMBOL_GPL(tee_shm_pool_mgr_alloc_res_mem); - -static bool check_mgr_ops(struct tee_shm_pool_mgr *mgr) -{ - return mgr && mgr->ops && mgr->ops->alloc && mgr->ops->free && - mgr->ops->destroy_poolmgr; -} - -struct tee_shm_pool *tee_shm_pool_alloc(struct tee_shm_pool_mgr *priv_mgr, - struct tee_shm_pool_mgr *dmabuf_mgr) -{ - struct tee_shm_pool *pool; - - if (!check_mgr_ops(priv_mgr) || !check_mgr_ops(dmabuf_mgr)) - return ERR_PTR(-EINVAL); - pool = kzalloc(sizeof(*pool), GFP_KERNEL); if (!pool) return ERR_PTR(-ENOMEM); - pool->private_mgr = priv_mgr; - pool->dma_buf_mgr = dmabuf_mgr; + pool->private_data = gen_pool_create(min_alloc_order, -1); + if (!pool->private_data) { + rc = -ENOMEM; + goto err; + } + + rc = gen_pool_add_virt(pool->private_data, vaddr, paddr, size, -1); + if (rc) { + gen_pool_destroy(pool->private_data); + goto err; + } + + pool->ops = &pool_ops_generic; return pool; -} -EXPORT_SYMBOL_GPL(tee_shm_pool_alloc); - -/** - * tee_shm_pool_free() - Free a shared memory pool - * @pool: The shared memory pool to free - * - * There must be no remaining shared memory allocated from this pool when - * this function is called. - */ -void tee_shm_pool_free(struct tee_shm_pool *pool) -{ - if (pool->private_mgr) - tee_shm_pool_mgr_destroy(pool->private_mgr); - if (pool->dma_buf_mgr) - tee_shm_pool_mgr_destroy(pool->dma_buf_mgr); +err: kfree(pool); + + return ERR_PTR(rc); } -EXPORT_SYMBOL_GPL(tee_shm_pool_free); +EXPORT_SYMBOL_GPL(tee_shm_pool_alloc_res_mem); diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig index fcc46380e7c9..40c50fa2dd70 100644 --- a/drivers/video/console/Kconfig +++ b/drivers/video/console/Kconfig @@ -9,7 +9,7 @@ config VGA_CONSOLE bool "VGA text console" if EXPERT || !X86 depends on !4xx && !PPC_8xx && !SPARC && !M68K && !PARISC && !SUPERH && \ (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) && \ - !ARM64 && !ARC && !MICROBLAZE && !OPENRISC && !NDS32 && !S390 && !UML + !ARM64 && !ARC && !MICROBLAZE && !OPENRISC && !S390 && !UML default y help Saying Y here will allow you to use Linux in text mode through a diff --git a/fs/exec.c b/fs/exec.c index 8256e8bb9ad3..a39108c1190a 100644 --- a/fs/exec.c +++ b/fs/exec.c @@ -1309,12 +1309,6 @@ int begin_new_exec(struct linux_binprm * bprm) if (retval) goto out_unlock; - /* - * Ensure that the uaccess routines can actually operate on userspace - * pointers: - */ - force_uaccess_begin(); - if (me->flags & PF_KTHREAD) free_kthread_struct(me); me->flags &= ~(PF_RANDOMIZE | PF_FORKNOEXEC | PF_KTHREAD | diff --git a/include/asm-generic/access_ok.h b/include/asm-generic/access_ok.h new file mode 100644 index 000000000000..2866ae61b1cd --- /dev/null +++ b/include/asm-generic/access_ok.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_GENERIC_ACCESS_OK_H__ +#define __ASM_GENERIC_ACCESS_OK_H__ + +/* + * Checking whether a pointer is valid for user space access. + * These definitions work on most architectures, but overrides can + * be used where necessary. + */ + +/* + * architectures with compat tasks have a variable TASK_SIZE and should + * override this to a constant. + */ +#ifndef TASK_SIZE_MAX +#define TASK_SIZE_MAX TASK_SIZE +#endif + +#ifndef __access_ok +/* + * 'size' is a compile-time constant for most callers, so optimize for + * this case to turn the check into a single comparison against a constant + * limit and catch all possible overflows. + * On architectures with separate user address space (m68k, s390, parisc, + * sparc64) or those without an MMU, this should always return true. + * + * This version was originally contributed by Jonas Bonn for the + * OpenRISC architecture, and was found to be the most efficient + * for constant 'size' and 'limit' values. + */ +static inline int __access_ok(const void __user *ptr, unsigned long size) +{ + unsigned long limit = TASK_SIZE_MAX; + unsigned long addr = (unsigned long)ptr; + + if (IS_ENABLED(CONFIG_ALTERNATE_USER_ADDRESS_SPACE) || + !IS_ENABLED(CONFIG_MMU)) + return true; + + return (size <= limit) && (addr <= (limit - size)); +} +#endif + +#ifndef access_ok +#define access_ok(addr, size) likely(__access_ok(addr, size)) +#endif + +#endif diff --git a/include/asm-generic/uaccess.h b/include/asm-generic/uaccess.h index 10ffa8b5c117..a5be9e61a2a2 100644 --- a/include/asm-generic/uaccess.h +++ b/include/asm-generic/uaccess.h @@ -8,6 +8,7 @@ * address space, e.g. all NOMMU machines. */ #include +#include #ifdef CONFIG_UACCESS_MEMCPY #include @@ -77,8 +78,6 @@ do { \ goto err_label; \ } while (0) -#define HAVE_GET_KERNEL_NOFAULT 1 - static inline __must_check unsigned long raw_copy_from_user(void *to, const void __user * from, unsigned long n) { @@ -96,49 +95,6 @@ raw_copy_to_user(void __user *to, const void *from, unsigned long n) #define INLINE_COPY_TO_USER #endif /* CONFIG_UACCESS_MEMCPY */ -#ifdef CONFIG_SET_FS -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) - -#ifndef KERNEL_DS -#define KERNEL_DS MAKE_MM_SEG(~0UL) -#endif - -#ifndef USER_DS -#define USER_DS MAKE_MM_SEG(TASK_SIZE - 1) -#endif - -#ifndef get_fs -#define get_fs() (current_thread_info()->addr_limit) - -static inline void set_fs(mm_segment_t fs) -{ - current_thread_info()->addr_limit = fs; -} -#endif - -#ifndef uaccess_kernel -#define uaccess_kernel() (get_fs().seg == KERNEL_DS.seg) -#endif - -#ifndef user_addr_max -#define user_addr_max() (uaccess_kernel() ? ~0UL : TASK_SIZE) -#endif - -#endif /* CONFIG_SET_FS */ - -#define access_ok(addr, size) __access_ok((unsigned long)(addr),(size)) - -/* - * The architecture should really override this if possible, at least - * doing a check on the get_fs() - */ -#ifndef __access_ok -static inline int __access_ok(unsigned long addr, unsigned long size) -{ - return 1; -} -#endif - /* * These are the main single-value transfer routines. They automatically * use the right size if we just have the right pointer type. diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h index 98e1b2ab6403..8498c0cd95fe 100644 --- a/include/dt-bindings/clock/at91.h +++ b/include/dt-bindings/clock/at91.h @@ -35,6 +35,7 @@ #define PMC_AUDIOIOPLL (PMC_MAIN + 7) #define PMC_ETHPLL (PMC_MAIN + 8) #define PMC_CPU (PMC_MAIN + 9) +#define PMC_MCK1 (PMC_MAIN + 10) #ifndef AT91_PMC_MOSCS #define AT91_PMC_MOSCS 0 /* MOSCS Flag */ diff --git a/include/dt-bindings/clock/fsd-clk.h b/include/dt-bindings/clock/fsd-clk.h new file mode 100644 index 000000000000..c8a2af1dd1ad --- /dev/null +++ b/include/dt-bindings/clock/fsd-clk.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2017-2022 Tesla, Inc. + * https://www.tesla.com + * + * The constants defined in this header are being used in dts + * and fsd platform driver. + */ + +#ifndef _DT_BINDINGS_CLOCK_FSD_H +#define _DT_BINDINGS_CLOCK_FSD_H + +/* CMU */ +#define DOUT_CMU_PLL_SHARED0_DIV4 1 +#define DOUT_CMU_PERIC_SHARED1DIV36 2 +#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3 +#define DOUT_CMU_PERIC_SHARED0DIV20 4 +#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5 +#define DOUT_CMU_PLL_SHARED0_DIV6 6 +#define DOUT_CMU_FSYS0_SHARED1DIV4 7 +#define DOUT_CMU_FSYS0_SHARED0DIV4 8 +#define DOUT_CMU_FSYS1_SHARED0DIV8 9 +#define DOUT_CMU_FSYS1_SHARED0DIV4 10 +#define CMU_CPUCL_SWITCH_GATE 11 +#define DOUT_CMU_IMEM_TCUCLK 12 +#define DOUT_CMU_IMEM_ACLK 13 +#define DOUT_CMU_IMEM_DMACLK 14 +#define GAT_CMU_FSYS0_SHARED0DIV4 15 +#define CMU_NR_CLK 16 + +/* PERIC */ +#define PERIC_SCLK_UART0 1 +#define PERIC_PCLK_UART0 2 +#define PERIC_SCLK_UART1 3 +#define PERIC_PCLK_UART1 4 +#define PERIC_DMA0_IPCLKPORT_ACLK 5 +#define PERIC_DMA1_IPCLKPORT_ACLK 6 +#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7 +#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8 +#define PERIC_PCLK_SPI0 9 +#define PERIC_SCLK_SPI0 10 +#define PERIC_PCLK_SPI1 11 +#define PERIC_SCLK_SPI1 12 +#define PERIC_PCLK_SPI2 13 +#define PERIC_SCLK_SPI2 14 +#define PERIC_PCLK_TDM0 15 +#define PERIC_PCLK_HSI2C0 16 +#define PERIC_PCLK_HSI2C1 17 +#define PERIC_PCLK_HSI2C2 18 +#define PERIC_PCLK_HSI2C3 19 +#define PERIC_PCLK_HSI2C4 20 +#define PERIC_PCLK_HSI2C5 21 +#define PERIC_PCLK_HSI2C6 22 +#define PERIC_PCLK_HSI2C7 23 +#define PERIC_MCAN0_IPCLKPORT_CCLK 24 +#define PERIC_MCAN0_IPCLKPORT_PCLK 25 +#define PERIC_MCAN1_IPCLKPORT_CCLK 26 +#define PERIC_MCAN1_IPCLKPORT_PCLK 27 +#define PERIC_MCAN2_IPCLKPORT_CCLK 28 +#define PERIC_MCAN2_IPCLKPORT_PCLK 29 +#define PERIC_MCAN3_IPCLKPORT_CCLK 30 +#define PERIC_MCAN3_IPCLKPORT_PCLK 31 +#define PERIC_PCLK_ADCIF 32 +#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33 +#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34 +#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35 +#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36 +#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37 +#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38 +#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39 +#define PERIC_HCLK_TDM0 40 +#define PERIC_PCLK_TDM1 41 +#define PERIC_HCLK_TDM1 42 +#define PERIC_EQOS_PHYRXCLK_MUX 43 +#define PERIC_EQOS_PHYRXCLK 44 +#define PERIC_DOUT_RGMII_CLK 45 +#define PERIC_NR_CLK 46 + +/* FSYS0 */ +#define UFS0_MPHY_REFCLK_IXTAL24 1 +#define UFS0_MPHY_REFCLK_IXTAL26 2 +#define UFS1_MPHY_REFCLK_IXTAL24 3 +#define UFS1_MPHY_REFCLK_IXTAL26 4 +#define UFS0_TOP0_HCLK_BUS 5 +#define UFS0_TOP0_ACLK 6 +#define UFS0_TOP0_CLK_UNIPRO 7 +#define UFS0_TOP0_FMP_CLK 8 +#define UFS1_TOP1_HCLK_BUS 9 +#define UFS1_TOP1_ACLK 10 +#define UFS1_TOP1_CLK_UNIPRO 11 +#define UFS1_TOP1_FMP_CLK 12 +#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13 +#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14 +#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15 +#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16 +#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17 +#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18 +#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19 +#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20 +#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21 +#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22 +#define FSYS0_NR_CLK 23 + +/* FSYS1 */ +#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1 +#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2 +#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3 +#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4 +#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5 +#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6 +#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7 +#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8 +#define FSYS1_NR_CLK 9 + +/* IMEM */ +#define IMEM_DMA0_IPCLKPORT_ACLK 1 +#define IMEM_DMA1_IPCLKPORT_ACLK 2 +#define IMEM_WDT0_IPCLKPORT_PCLK 3 +#define IMEM_WDT1_IPCLKPORT_PCLK 4 +#define IMEM_WDT2_IPCLKPORT_PCLK 5 +#define IMEM_MCT_PCLK 6 +#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7 +#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8 +#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9 +#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10 +#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11 +#define IMEM_NR_CLK 12 + +/* MFC */ +#define MFC_MFC_IPCLKPORT_ACLK 1 +#define MFC_NR_CLK 2 + +/* CAM_CSI */ +#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1 +#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2 +#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3 +#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4 +#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5 +#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6 +#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7 +#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8 +#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9 +#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10 +#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11 +#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12 +#define CAM_CSI_NR_CLK 13 + +#endif /*_DT_BINDINGS_CLOCK_FSD_H */ diff --git a/include/dt-bindings/clock/r9a06g032-sysctrl.h b/include/dt-bindings/clock/r9a06g032-sysctrl.h index 90c0f3dc1ba1..d9d7b8b4f426 100644 --- a/include/dt-bindings/clock/r9a06g032-sysctrl.h +++ b/include/dt-bindings/clock/r9a06g032-sysctrl.h @@ -74,6 +74,7 @@ #define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ #define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ #define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */ #define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ #define R9A06G032_HCLK_CAN0 85 #define R9A06G032_HCLK_CAN1 86 diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h new file mode 100644 index 000000000000..43f4dbda872c --- /dev/null +++ b/include/dt-bindings/clock/r9a07g054-cpg.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ +#define __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ + +#include + +/* R9A07G054 CPG Core Clocks */ +#define R9A07G054_CLK_I 0 +#define R9A07G054_CLK_I2 1 +#define R9A07G054_CLK_G 2 +#define R9A07G054_CLK_S0 3 +#define R9A07G054_CLK_S1 4 +#define R9A07G054_CLK_SPI0 5 +#define R9A07G054_CLK_SPI1 6 +#define R9A07G054_CLK_SD0 7 +#define R9A07G054_CLK_SD1 8 +#define R9A07G054_CLK_M0 9 +#define R9A07G054_CLK_M1 10 +#define R9A07G054_CLK_M2 11 +#define R9A07G054_CLK_M3 12 +#define R9A07G054_CLK_M4 13 +#define R9A07G054_CLK_HP 14 +#define R9A07G054_CLK_TSU 15 +#define R9A07G054_CLK_ZT 16 +#define R9A07G054_CLK_P0 17 +#define R9A07G054_CLK_P1 18 +#define R9A07G054_CLK_P2 19 +#define R9A07G054_CLK_AT 20 +#define R9A07G054_OSCCLK 21 +#define R9A07G054_CLK_P0_DIV2 22 +#define R9A07G054_CLK_DRP_M 23 +#define R9A07G054_CLK_DRP_D 24 +#define R9A07G054_CLK_DRP_A 25 + +/* R9A07G054 Module Clocks */ +#define R9A07G054_CA55_SCLK 0 +#define R9A07G054_CA55_PCLK 1 +#define R9A07G054_CA55_ATCLK 2 +#define R9A07G054_CA55_GICCLK 3 +#define R9A07G054_CA55_PERICLK 4 +#define R9A07G054_CA55_ACLK 5 +#define R9A07G054_CA55_TSCLK 6 +#define R9A07G054_GIC600_GICCLK 7 +#define R9A07G054_IA55_CLK 8 +#define R9A07G054_IA55_PCLK 9 +#define R9A07G054_MHU_PCLK 10 +#define R9A07G054_SYC_CNT_CLK 11 +#define R9A07G054_DMAC_ACLK 12 +#define R9A07G054_DMAC_PCLK 13 +#define R9A07G054_OSTM0_PCLK 14 +#define R9A07G054_OSTM1_PCLK 15 +#define R9A07G054_OSTM2_PCLK 16 +#define R9A07G054_MTU_X_MCK_MTU3 17 +#define R9A07G054_POE3_CLKM_POE 18 +#define R9A07G054_GPT_PCLK 19 +#define R9A07G054_POEG_A_CLKP 20 +#define R9A07G054_POEG_B_CLKP 21 +#define R9A07G054_POEG_C_CLKP 22 +#define R9A07G054_POEG_D_CLKP 23 +#define R9A07G054_WDT0_PCLK 24 +#define R9A07G054_WDT0_CLK 25 +#define R9A07G054_WDT1_PCLK 26 +#define R9A07G054_WDT1_CLK 27 +#define R9A07G054_WDT2_PCLK 28 +#define R9A07G054_WDT2_CLK 29 +#define R9A07G054_SPI_CLK2 30 +#define R9A07G054_SPI_CLK 31 +#define R9A07G054_SDHI0_IMCLK 32 +#define R9A07G054_SDHI0_IMCLK2 33 +#define R9A07G054_SDHI0_CLK_HS 34 +#define R9A07G054_SDHI0_ACLK 35 +#define R9A07G054_SDHI1_IMCLK 36 +#define R9A07G054_SDHI1_IMCLK2 37 +#define R9A07G054_SDHI1_CLK_HS 38 +#define R9A07G054_SDHI1_ACLK 39 +#define R9A07G054_GPU_CLK 40 +#define R9A07G054_GPU_AXI_CLK 41 +#define R9A07G054_GPU_ACE_CLK 42 +#define R9A07G054_ISU_ACLK 43 +#define R9A07G054_ISU_PCLK 44 +#define R9A07G054_H264_CLK_A 45 +#define R9A07G054_H264_CLK_P 46 +#define R9A07G054_CRU_SYSCLK 47 +#define R9A07G054_CRU_VCLK 48 +#define R9A07G054_CRU_PCLK 49 +#define R9A07G054_CRU_ACLK 50 +#define R9A07G054_MIPI_DSI_PLLCLK 51 +#define R9A07G054_MIPI_DSI_SYSCLK 52 +#define R9A07G054_MIPI_DSI_ACLK 53 +#define R9A07G054_MIPI_DSI_PCLK 54 +#define R9A07G054_MIPI_DSI_VCLK 55 +#define R9A07G054_MIPI_DSI_LPCLK 56 +#define R9A07G054_LCDC_CLK_A 57 +#define R9A07G054_LCDC_CLK_P 58 +#define R9A07G054_LCDC_CLK_D 59 +#define R9A07G054_SSI0_PCLK2 60 +#define R9A07G054_SSI0_PCLK_SFR 61 +#define R9A07G054_SSI1_PCLK2 62 +#define R9A07G054_SSI1_PCLK_SFR 63 +#define R9A07G054_SSI2_PCLK2 64 +#define R9A07G054_SSI2_PCLK_SFR 65 +#define R9A07G054_SSI3_PCLK2 66 +#define R9A07G054_SSI3_PCLK_SFR 67 +#define R9A07G054_SRC_CLKP 68 +#define R9A07G054_USB_U2H0_HCLK 69 +#define R9A07G054_USB_U2H1_HCLK 70 +#define R9A07G054_USB_U2P_EXR_CPUCLK 71 +#define R9A07G054_USB_PCLK 72 +#define R9A07G054_ETH0_CLK_AXI 73 +#define R9A07G054_ETH0_CLK_CHI 74 +#define R9A07G054_ETH1_CLK_AXI 75 +#define R9A07G054_ETH1_CLK_CHI 76 +#define R9A07G054_I2C0_PCLK 77 +#define R9A07G054_I2C1_PCLK 78 +#define R9A07G054_I2C2_PCLK 79 +#define R9A07G054_I2C3_PCLK 80 +#define R9A07G054_SCIF0_CLK_PCK 81 +#define R9A07G054_SCIF1_CLK_PCK 82 +#define R9A07G054_SCIF2_CLK_PCK 83 +#define R9A07G054_SCIF3_CLK_PCK 84 +#define R9A07G054_SCIF4_CLK_PCK 85 +#define R9A07G054_SCI0_CLKP 86 +#define R9A07G054_SCI1_CLKP 87 +#define R9A07G054_IRDA_CLKP 88 +#define R9A07G054_RSPI0_CLKB 89 +#define R9A07G054_RSPI1_CLKB 90 +#define R9A07G054_RSPI2_CLKB 91 +#define R9A07G054_CANFD_PCLK 92 +#define R9A07G054_GPIO_HCLK 93 +#define R9A07G054_ADC_ADCLK 94 +#define R9A07G054_ADC_PCLK 95 +#define R9A07G054_TSU_PCLK 96 +#define R9A07G054_STPAI_INITCLK 97 +#define R9A07G054_STPAI_ACLK 98 +#define R9A07G054_STPAI_MCLK 99 +#define R9A07G054_STPAI_DCLKIN 100 +#define R9A07G054_STPAI_ACLK_DRP 101 + +/* R9A07G054 Resets */ +#define R9A07G054_CA55_RST_1_0 0 +#define R9A07G054_CA55_RST_1_1 1 +#define R9A07G054_CA55_RST_3_0 2 +#define R9A07G054_CA55_RST_3_1 3 +#define R9A07G054_CA55_RST_4 4 +#define R9A07G054_CA55_RST_5 5 +#define R9A07G054_CA55_RST_6 6 +#define R9A07G054_CA55_RST_7 7 +#define R9A07G054_CA55_RST_8 8 +#define R9A07G054_CA55_RST_9 9 +#define R9A07G054_CA55_RST_10 10 +#define R9A07G054_CA55_RST_11 11 +#define R9A07G054_CA55_RST_12 12 +#define R9A07G054_GIC600_GICRESET_N 13 +#define R9A07G054_GIC600_DBG_GICRESET_N 14 +#define R9A07G054_IA55_RESETN 15 +#define R9A07G054_MHU_RESETN 16 +#define R9A07G054_DMAC_ARESETN 17 +#define R9A07G054_DMAC_RST_ASYNC 18 +#define R9A07G054_SYC_RESETN 19 +#define R9A07G054_OSTM0_PRESETZ 20 +#define R9A07G054_OSTM1_PRESETZ 21 +#define R9A07G054_OSTM2_PRESETZ 22 +#define R9A07G054_MTU_X_PRESET_MTU3 23 +#define R9A07G054_POE3_RST_M_REG 24 +#define R9A07G054_GPT_RST_C 25 +#define R9A07G054_POEG_A_RST 26 +#define R9A07G054_POEG_B_RST 27 +#define R9A07G054_POEG_C_RST 28 +#define R9A07G054_POEG_D_RST 29 +#define R9A07G054_WDT0_PRESETN 30 +#define R9A07G054_WDT1_PRESETN 31 +#define R9A07G054_WDT2_PRESETN 32 +#define R9A07G054_SPI_RST 33 +#define R9A07G054_SDHI0_IXRST 34 +#define R9A07G054_SDHI1_IXRST 35 +#define R9A07G054_GPU_RESETN 36 +#define R9A07G054_GPU_AXI_RESETN 37 +#define R9A07G054_GPU_ACE_RESETN 38 +#define R9A07G054_ISU_ARESETN 39 +#define R9A07G054_ISU_PRESETN 40 +#define R9A07G054_H264_X_RESET_VCP 41 +#define R9A07G054_H264_CP_PRESET_P 42 +#define R9A07G054_CRU_CMN_RSTB 43 +#define R9A07G054_CRU_PRESETN 44 +#define R9A07G054_CRU_ARESETN 45 +#define R9A07G054_MIPI_DSI_CMN_RSTB 46 +#define R9A07G054_MIPI_DSI_ARESET_N 47 +#define R9A07G054_MIPI_DSI_PRESET_N 48 +#define R9A07G054_LCDC_RESET_N 49 +#define R9A07G054_SSI0_RST_M2_REG 50 +#define R9A07G054_SSI1_RST_M2_REG 51 +#define R9A07G054_SSI2_RST_M2_REG 52 +#define R9A07G054_SSI3_RST_M2_REG 53 +#define R9A07G054_SRC_RST 54 +#define R9A07G054_USB_U2H0_HRESETN 55 +#define R9A07G054_USB_U2H1_HRESETN 56 +#define R9A07G054_USB_U2P_EXL_SYSRST 57 +#define R9A07G054_USB_PRESETN 58 +#define R9A07G054_ETH0_RST_HW_N 59 +#define R9A07G054_ETH1_RST_HW_N 60 +#define R9A07G054_I2C0_MRST 61 +#define R9A07G054_I2C1_MRST 62 +#define R9A07G054_I2C2_MRST 63 +#define R9A07G054_I2C3_MRST 64 +#define R9A07G054_SCIF0_RST_SYSTEM_N 65 +#define R9A07G054_SCIF1_RST_SYSTEM_N 66 +#define R9A07G054_SCIF2_RST_SYSTEM_N 67 +#define R9A07G054_SCIF3_RST_SYSTEM_N 68 +#define R9A07G054_SCIF4_RST_SYSTEM_N 69 +#define R9A07G054_SCI0_RST 70 +#define R9A07G054_SCI1_RST 71 +#define R9A07G054_IRDA_RST 72 +#define R9A07G054_RSPI0_RST 73 +#define R9A07G054_RSPI1_RST 74 +#define R9A07G054_RSPI2_RST 75 +#define R9A07G054_CANFD_RSTP_N 76 +#define R9A07G054_CANFD_RSTC_N 77 +#define R9A07G054_GPIO_RSTN 78 +#define R9A07G054_GPIO_PORT_RESETN 79 +#define R9A07G054_GPIO_SPARE_RESETN 80 +#define R9A07G054_ADC_PRESETN 81 +#define R9A07G054_ADC_ADRST_N 82 +#define R9A07G054_TSU_PRESETN 83 +#define R9A07G054_STPAI_ARESETN 84 + +#endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */ diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8d7e66e1b6ef..8cae969e8cba 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ +/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H @@ -9,6 +9,26 @@ * @defgroup bpmp_clock_ids Clock ID's * @{ */ +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ +#define TEGRA234_CLK_AHUB 4U +/** @brief output of gate CLK_ENB_APB2APE */ +#define TEGRA234_CLK_APB2APE 5U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ +#define TEGRA234_CLK_APE 6U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ +#define TEGRA234_CLK_AUD_MCLK 7U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ +#define TEGRA234_CLK_DMIC1 15U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ +#define TEGRA234_CLK_DMIC2 16U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ +#define TEGRA234_CLK_DMIC3 17U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ +#define TEGRA234_CLK_DMIC4 18U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ +#define TEGRA234_CLK_DSPK1 29U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ +#define TEGRA234_CLK_DSPK2 30U /** * @brief controls the EMC clock frequency. * @details Doing a clk_set_rate on this clock will select the @@ -20,15 +40,126 @@ #define TEGRA234_CLK_EMC 31U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ +#define TEGRA234_CLK_I2C1 48U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ +#define TEGRA234_CLK_I2C2 49U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ +#define TEGRA234_CLK_I2C3 50U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ +#define TEGRA234_CLK_I2C4 51U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ +#define TEGRA234_CLK_I2C6 52U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ +#define TEGRA234_CLK_I2C7 53U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ +#define TEGRA234_CLK_I2C8 54U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ +#define TEGRA234_CLK_I2C9 55U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ +#define TEGRA234_CLK_I2S1 56U +/** @brief clock recovered from I2S1 input */ +#define TEGRA234_CLK_I2S1_SYNC_INPUT 57U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ +#define TEGRA234_CLK_I2S2 58U +/** @brief clock recovered from I2S2 input */ +#define TEGRA234_CLK_I2S2_SYNC_INPUT 59U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ +#define TEGRA234_CLK_I2S3 60U +/** @brief clock recovered from I2S3 input */ +#define TEGRA234_CLK_I2S3_SYNC_INPUT 61U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ +#define TEGRA234_CLK_I2S4 62U +/** @brief clock recovered from I2S4 input */ +#define TEGRA234_CLK_I2S4_SYNC_INPUT 63U +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ +#define TEGRA234_CLK_I2S5 64U +/** @brief clock recovered from I2S5 input */ +#define TEGRA234_CLK_I2S5_SYNC_INPUT 65U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */ +#define TEGRA234_CLK_I2S6 66U +/** @brief clock recovered from I2S6 input */ +#define TEGRA234_CLK_I2S6_SYNC_INPUT 67U +/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ +#define TEGRA234_CLK_PLLA 93U +/** @brief PLLP clk output */ +#define TEGRA234_CLK_PLLP_OUT0 102U +/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ +#define TEGRA234_CLK_PLLA_OUT0 104U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ +#define TEGRA234_CLK_PWM1 105U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ +#define TEGRA234_CLK_PWM2 106U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ +#define TEGRA234_CLK_PWM3 107U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ +#define TEGRA234_CLK_PWM4 108U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ +#define TEGRA234_CLK_PWM5 109U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ +#define TEGRA234_CLK_PWM6 110U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ +#define TEGRA234_CLK_PWM7 111U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ +#define TEGRA234_CLK_PWM8 112U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ #define TEGRA234_CLK_SDMMC4 123U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ +#define TEGRA234_CLK_SYNC_DMIC1 139U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ +#define TEGRA234_CLK_SYNC_DMIC2 140U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ +#define TEGRA234_CLK_SYNC_DMIC3 141U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ +#define TEGRA234_CLK_SYNC_DMIC4 142U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ +#define TEGRA234_CLK_SYNC_DSPK1 143U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ +#define TEGRA234_CLK_SYNC_DSPK2 144U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ +#define TEGRA234_CLK_SYNC_I2S1 145U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ +#define TEGRA234_CLK_SYNC_I2S2 146U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ +#define TEGRA234_CLK_SYNC_I2S3 147U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ +#define TEGRA234_CLK_SYNC_I2S4 148U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ +#define TEGRA234_CLK_SYNC_I2S5 149U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ +#define TEGRA234_CLK_SYNC_I2S6 150U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ #define TEGRA234_CLK_UARTA 155U +/** @brief output of gate CLK_ENB_PEX1_CORE_6 */ +#define TEGRA234_CLK_PEX1_C6_CORE 161U +/** @brief output of gate CLK_ENB_PEX2_CORE_7 */ +#define TEGRA234_CLK_PEX2_C7_CORE 171U +/** @brief output of gate CLK_ENB_PEX2_CORE_8 */ +#define TEGRA234_CLK_PEX2_C8_CORE 172U +/** @brief output of gate CLK_ENB_PEX2_CORE_9 */ +#define TEGRA234_CLK_PEX2_C9_CORE 173U +/** @brief output of gate CLK_ENB_PEX2_CORE_10 */ +#define TEGRA234_CLK_PEX2_C10_CORE 187U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U +/** @brief output of gate CLK_ENB_PEX0_CORE_0 */ +#define TEGRA234_CLK_PEX0_C0_CORE 220U +/** @brief output of gate CLK_ENB_PEX0_CORE_1 */ +#define TEGRA234_CLK_PEX0_C1_CORE 221U +/** @brief output of gate CLK_ENB_PEX0_CORE_2 */ +#define TEGRA234_CLK_PEX0_C2_CORE 222U +/** @brief output of gate CLK_ENB_PEX0_CORE_3 */ +#define TEGRA234_CLK_PEX0_C3_CORE 223U +/** @brief output of gate CLK_ENB_PEX0_CORE_4 */ +#define TEGRA234_CLK_PEX0_C4_CORE 224U +/** @brief output of gate CLK_ENB_PEX1_CORE_5 */ +#define TEGRA234_CLK_PEX1_C5_CORE 225U /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ #define TEGRA234_CLK_PLLC4 237U /** @brief 32K input clock provided by PMIC */ #define TEGRA234_CLK_CLK_32K 289U - +/** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ +#define TEGRA234_CLK_AZA_2XBIT 457U +/** @brief aza_2xbitclk / 2 (aza_bitclk) */ +#define TEGRA234_CLK_AZA_BIT 458U #endif diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 2662f70c15c6..e3b0e9da295d 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef DT_BINDINGS_MEMORY_TEGRA234_MC_H #define DT_BINDINGS_MEMORY_TEGRA234_MC_H @@ -7,15 +8,59 @@ #define TEGRA234_SID_INVALID 0x00 #define TEGRA234_SID_PASSTHROUGH 0x7f +/* NISO0 stream IDs */ +#define TEGRA234_SID_APE 0x02 +#define TEGRA234_SID_HDA 0x03 +#define TEGRA234_SID_PCIE0 0x12 +#define TEGRA234_SID_PCIE4 0x13 +#define TEGRA234_SID_PCIE5 0x14 +#define TEGRA234_SID_PCIE6 0x15 +#define TEGRA234_SID_PCIE9 0x1f /* NISO1 stream IDs */ #define TEGRA234_SID_SDMMC4 0x02 +#define TEGRA234_SID_PCIE1 0x05 +#define TEGRA234_SID_PCIE2 0x06 +#define TEGRA234_SID_PCIE3 0x07 +#define TEGRA234_SID_PCIE7 0x08 +#define TEGRA234_SID_PCIE8 0x09 +#define TEGRA234_SID_PCIE10 0x0b #define TEGRA234_SID_BPMP 0x10 /* * memory client IDs */ +/* High-definition audio (HDA) read clients */ +#define TEGRA234_MEMORY_CLIENT_HDAR 0x15 +/* PCIE6 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 +/* PCIE6 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE6AW 0x29 +/* PCIE7 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE7AR 0x2a +/* PCIE7 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE7AW 0x30 +/* PCIE8 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE8AR 0x32 +/* High-definition audio (HDA) write clients */ +#define TEGRA234_MEMORY_CLIENT_HDAW 0x35 +/* PCIE8 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE8AW 0x3b +/* PCIE9 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE9AR 0x3c +/* PCIE6r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE6AR1 0x3d +/* PCIE9 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE9AW 0x3e +/* PCIE10 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE10AR 0x3f +/* PCIE10 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE10AW 0x40 +/* PCIE10r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE10AR1 0x48 +/* PCIE7r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE7AR1 0x49 /* sdmmcd memory read client */ #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63 /* sdmmcd memory write client */ @@ -28,5 +73,35 @@ #define TEGRA234_MEMORY_CLIENT_BPMPDMAR 0x95 /* BPMPDMA write client */ #define TEGRA234_MEMORY_CLIENT_BPMPDMAW 0x96 +/* APEDMA read client */ +#define TEGRA234_MEMORY_CLIENT_APEDMAR 0x9f +/* APEDMA write client */ +#define TEGRA234_MEMORY_CLIENT_APEDMAW 0xa0 +/* PCIE0 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE0R 0xd8 +/* PCIE0 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE0W 0xd9 +/* PCIE1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE1R 0xda +/* PCIE1 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE1W 0xdb +/* PCIE2 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE2AR 0xdc +/* PCIE2 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE2AW 0xdd +/* PCIE3 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE3R 0xde +/* PCIE3 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE3W 0xdf +/* PCIE4 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE4R 0xe0 +/* PCIE4 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE4W 0xe1 +/* PCIE5 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE5R 0xe2 +/* PCIE5 write clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE5W 0xe3 +/* PCIE5r1 read clients */ +#define TEGRA234_MEMORY_CLIENT_PCIE5R1 0xef #endif diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index 63e038e36ca3..a5204ab91d3e 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -41,4 +41,7 @@ #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #endif diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h new file mode 100644 index 000000000000..9f90c40a2c6c --- /dev/null +++ b/include/dt-bindings/power/imx8mp-power.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (C) 2020 Pengutronix, Sascha Hauer + */ + +#ifndef __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ +#define __DT_BINDINGS_IMX8MP_POWER_DOMAIN_POWER_H__ + +#define IMX8MP_POWER_DOMAIN_MIPI_PHY1 0 +#define IMX8MP_POWER_DOMAIN_PCIE_PHY 1 +#define IMX8MP_POWER_DOMAIN_USB1_PHY 2 +#define IMX8MP_POWER_DOMAIN_USB2_PHY 3 +#define IMX8MP_POWER_DOMAIN_MLMIX 4 +#define IMX8MP_POWER_DOMAIN_AUDIOMIX 5 +#define IMX8MP_POWER_DOMAIN_GPU2D 6 +#define IMX8MP_POWER_DOMAIN_GPUMIX 7 +#define IMX8MP_POWER_DOMAIN_VPUMIX 8 +#define IMX8MP_POWER_DOMAIN_GPU3D 9 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX 10 +#define IMX8MP_POWER_DOMAIN_VPU_G1 11 +#define IMX8MP_POWER_DOMAIN_VPU_G2 12 +#define IMX8MP_POWER_DOMAIN_VPU_VC8000E 13 +#define IMX8MP_POWER_DOMAIN_HDMIMIX 14 +#define IMX8MP_POWER_DOMAIN_HDMI_PHY 15 +#define IMX8MP_POWER_DOMAIN_MIPI_PHY2 16 +#define IMX8MP_POWER_DOMAIN_HSIOMIX 17 +#define IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP 18 + +#define IMX8MP_HSIOBLK_PD_USB 0 +#define IMX8MP_HSIOBLK_PD_USB_PHY1 1 +#define IMX8MP_HSIOBLK_PD_USB_PHY2 2 +#define IMX8MP_HSIOBLK_PD_PCIE 3 +#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4 + +#endif diff --git a/include/dt-bindings/power/imx8mq-power.h b/include/dt-bindings/power/imx8mq-power.h index 8a513bd9166e..9f7d0f1e7c32 100644 --- a/include/dt-bindings/power/imx8mq-power.h +++ b/include/dt-bindings/power/imx8mq-power.h @@ -18,4 +18,7 @@ #define IMX8M_POWER_DOMAIN_MIPI_CSI2 9 #define IMX8M_POWER_DOMAIN_PCIE2 10 +#define IMX8MQ_VPUBLK_PD_G1 0 +#define IMX8MQ_VPUBLK_PD_G2 1 + #endif diff --git a/include/dt-bindings/power/meson-s4-power.h b/include/dt-bindings/power/meson-s4-power.h new file mode 100644 index 000000000000..462dd2cb938b --- /dev/null +++ b/include/dt-bindings/power/meson-s4-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. + * Author: Shunzhou Jiang + */ + +#ifndef _DT_BINDINGS_MESON_S4_POWER_H +#define _DT_BINDINGS_MESON_S4_POWER_H + +#define PWRC_S4_DOS_HEVC_ID 0 +#define PWRC_S4_DOS_VDEC_ID 1 +#define PWRC_S4_VPU_HDMI_ID 2 +#define PWRC_S4_USB_COMB_ID 3 +#define PWRC_S4_GE2D_ID 4 +#define PWRC_S4_ETH_ID 5 +#define PWRC_S4_DEMOD_ID 6 +#define PWRC_S4_AUDIO_ID 7 + +#endif diff --git a/include/dt-bindings/power/mt8186-power.h b/include/dt-bindings/power/mt8186-power.h new file mode 100644 index 000000000000..429f7197f6b6 --- /dev/null +++ b/include/dt-bindings/power/mt8186-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Chun-Jie Chen + */ + +#ifndef _DT_BINDINGS_POWER_MT8186_POWER_H +#define _DT_BINDINGS_POWER_MT8186_POWER_H + +#define MT8186_POWER_DOMAIN_MFG0 0 +#define MT8186_POWER_DOMAIN_MFG1 1 +#define MT8186_POWER_DOMAIN_MFG2 2 +#define MT8186_POWER_DOMAIN_MFG3 3 +#define MT8186_POWER_DOMAIN_SSUSB 4 +#define MT8186_POWER_DOMAIN_SSUSB_P1 5 +#define MT8186_POWER_DOMAIN_DIS 6 +#define MT8186_POWER_DOMAIN_IMG 7 +#define MT8186_POWER_DOMAIN_IMG2 8 +#define MT8186_POWER_DOMAIN_IPE 9 +#define MT8186_POWER_DOMAIN_CAM 10 +#define MT8186_POWER_DOMAIN_CAM_RAWA 11 +#define MT8186_POWER_DOMAIN_CAM_RAWB 12 +#define MT8186_POWER_DOMAIN_VENC 13 +#define MT8186_POWER_DOMAIN_VDEC 14 +#define MT8186_POWER_DOMAIN_WPE 15 +#define MT8186_POWER_DOMAIN_CONN_ON 16 +#define MT8186_POWER_DOMAIN_CSIRX_TOP 17 +#define MT8186_POWER_DOMAIN_ADSP_AO 18 +#define MT8186_POWER_DOMAIN_ADSP_INFRA 19 +#define MT8186_POWER_DOMAIN_ADSP_TOP 20 + +#endif /* _DT_BINDINGS_POWER_MT8186_POWER_H */ diff --git a/include/dt-bindings/power/mt8195-power.h b/include/dt-bindings/power/mt8195-power.h new file mode 100644 index 000000000000..b20ca4b3e3a8 --- /dev/null +++ b/include/dt-bindings/power/mt8195-power.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Chun-Jie Chen + */ + +#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H +#define _DT_BINDINGS_POWER_MT8195_POWER_H + +#define MT8195_POWER_DOMAIN_PCIE_MAC_P0 0 +#define MT8195_POWER_DOMAIN_PCIE_MAC_P1 1 +#define MT8195_POWER_DOMAIN_PCIE_PHY 2 +#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 3 +#define MT8195_POWER_DOMAIN_CSI_RX_TOP 4 +#define MT8195_POWER_DOMAIN_ETHER 5 +#define MT8195_POWER_DOMAIN_ADSP 6 +#define MT8195_POWER_DOMAIN_AUDIO 7 +#define MT8195_POWER_DOMAIN_MFG0 8 +#define MT8195_POWER_DOMAIN_MFG1 9 +#define MT8195_POWER_DOMAIN_MFG2 10 +#define MT8195_POWER_DOMAIN_MFG3 11 +#define MT8195_POWER_DOMAIN_MFG4 12 +#define MT8195_POWER_DOMAIN_MFG5 13 +#define MT8195_POWER_DOMAIN_MFG6 14 +#define MT8195_POWER_DOMAIN_VPPSYS0 15 +#define MT8195_POWER_DOMAIN_VDOSYS0 16 +#define MT8195_POWER_DOMAIN_VPPSYS1 17 +#define MT8195_POWER_DOMAIN_VDOSYS1 18 +#define MT8195_POWER_DOMAIN_DP_TX 19 +#define MT8195_POWER_DOMAIN_EPD_TX 20 +#define MT8195_POWER_DOMAIN_HDMI_TX 21 +#define MT8195_POWER_DOMAIN_WPESYS 22 +#define MT8195_POWER_DOMAIN_VDEC0 23 +#define MT8195_POWER_DOMAIN_VDEC1 24 +#define MT8195_POWER_DOMAIN_VDEC2 25 +#define MT8195_POWER_DOMAIN_VENC 26 +#define MT8195_POWER_DOMAIN_VENC_CORE1 27 +#define MT8195_POWER_DOMAIN_IMG 28 +#define MT8195_POWER_DOMAIN_DIP 29 +#define MT8195_POWER_DOMAIN_IPE 30 +#define MT8195_POWER_DOMAIN_CAM 31 +#define MT8195_POWER_DOMAIN_CAM_RAWA 32 +#define MT8195_POWER_DOMAIN_CAM_RAWB 33 +#define MT8195_POWER_DOMAIN_CAM_MRAW 34 + +#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */ diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index edfc1ff2acb3..c002cc6ddf55 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -139,6 +139,11 @@ #define MDM9607_VDDMX_AO 4 #define MDM9607_VDDMX_VFL 5 +/* MSM8226 Power Domain Indexes */ +#define MSM8226_VDDCX 0 +#define MSM8226_VDDCX_AO 1 +#define MSM8226_VDDCX_VFC 2 + /* MSM8939 Power Domains */ #define MSM8939_VDDMDCX 0 #define MSM8939_VDDMDCX_AO 1 diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h new file mode 100644 index 000000000000..f610eee9bce8 --- /dev/null +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef __ABI_MACH_T234_POWERGATE_T234_H_ +#define __ABI_MACH_T234_POWERGATE_T234_H_ + +#define TEGRA234_POWER_DOMAIN_AUD 2U +#define TEGRA234_POWER_DOMAIN_DISP 3U +#define TEGRA234_POWER_DOMAIN_PCIEX8A 5U +#define TEGRA234_POWER_DOMAIN_PCIEX4A 6U +#define TEGRA234_POWER_DOMAIN_PCIEX4BA 7U +#define TEGRA234_POWER_DOMAIN_PCIEX4BB 8U +#define TEGRA234_POWER_DOMAIN_PCIEX1A 9U +#define TEGRA234_POWER_DOMAIN_PCIEX4CA 13U +#define TEGRA234_POWER_DOMAIN_PCIEX4CB 14U +#define TEGRA234_POWER_DOMAIN_PCIEX4CC 15U +#define TEGRA234_POWER_DOMAIN_PCIEX8B 16U +#define TEGRA234_POWER_DOMAIN_MGBEA 17U +#define TEGRA234_POWER_DOMAIN_MGBEB 18U +#define TEGRA234_POWER_DOMAIN_MGBEC 19U + +#endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 50e13bced642..1362cd5e03f0 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */ +/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H #define DT_BINDINGS_RESET_TEGRA234_RESET_H @@ -10,8 +10,51 @@ * @brief Identifiers for Resets controllable by firmware * @{ */ +#define TEGRA234_RESET_PEX1_CORE_6 11U +#define TEGRA234_RESET_PEX1_CORE_6_APB 12U +#define TEGRA234_RESET_PEX1_COMMON_APB 13U +#define TEGRA234_RESET_PEX2_CORE_7 14U +#define TEGRA234_RESET_PEX2_CORE_7_APB 15U +#define TEGRA234_RESET_HDA 20U +#define TEGRA234_RESET_HDACODEC 21U +#define TEGRA234_RESET_I2C1 24U +#define TEGRA234_RESET_PEX2_CORE_8 25U +#define TEGRA234_RESET_PEX2_CORE_8_APB 26U +#define TEGRA234_RESET_PEX2_CORE_9 27U +#define TEGRA234_RESET_PEX2_CORE_9_APB 28U +#define TEGRA234_RESET_I2C2 29U +#define TEGRA234_RESET_I2C3 30U +#define TEGRA234_RESET_I2C4 31U +#define TEGRA234_RESET_I2C6 32U +#define TEGRA234_RESET_I2C7 33U +#define TEGRA234_RESET_I2C8 34U +#define TEGRA234_RESET_I2C9 35U +#define TEGRA234_RESET_PEX2_CORE_10 56U +#define TEGRA234_RESET_PEX2_CORE_10_APB 57U +#define TEGRA234_RESET_PEX2_COMMON_APB 58U +#define TEGRA234_RESET_PWM1 68U +#define TEGRA234_RESET_PWM2 69U +#define TEGRA234_RESET_PWM3 70U +#define TEGRA234_RESET_PWM4 71U +#define TEGRA234_RESET_PWM5 72U +#define TEGRA234_RESET_PWM6 73U +#define TEGRA234_RESET_PWM7 74U +#define TEGRA234_RESET_PWM8 75U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U +#define TEGRA234_RESET_PEX0_CORE_0 116U +#define TEGRA234_RESET_PEX0_CORE_1 117U +#define TEGRA234_RESET_PEX0_CORE_2 118U +#define TEGRA234_RESET_PEX0_CORE_3 119U +#define TEGRA234_RESET_PEX0_CORE_4 120U +#define TEGRA234_RESET_PEX0_CORE_0_APB 121U +#define TEGRA234_RESET_PEX0_CORE_1_APB 122U +#define TEGRA234_RESET_PEX0_CORE_2_APB 123U +#define TEGRA234_RESET_PEX0_CORE_3_APB 124U +#define TEGRA234_RESET_PEX0_CORE_4_APB 125U +#define TEGRA234_RESET_PEX0_COMMON_APB 126U +#define TEGRA234_RESET_PEX1_CORE_5 129U +#define TEGRA234_RESET_PEX1_CORE_5_APB 130U /** @} */ diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h index ccb3f034bfa9..3484309b59bf 100644 --- a/include/linux/clk/at91_pmc.h +++ b/include/linux/clk/at91_pmc.h @@ -78,6 +78,10 @@ #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ + +#define AT91_PMC_RATIO 0x2c /* Processor clock ratio register [SAMA7G5 only] */ +#define AT91_PMC_RATIO_RATIO (0xf) /* CPU clock ratio. */ + #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ #define AT91_PMC_DIV (0xff << 0) /* Divider */ #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ diff --git a/include/linux/firmware/imx/svc/rm.h b/include/linux/firmware/imx/svc/rm.h index 456b6a59d29b..31456f897aa9 100644 --- a/include/linux/firmware/imx/svc/rm.h +++ b/include/linux/firmware/imx/svc/rm.h @@ -59,11 +59,16 @@ enum imx_sc_rm_func { #if IS_ENABLED(CONFIG_IMX_SCU) bool imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource); +int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt); #else static inline bool imx_sc_rm_is_resource_owned(struct imx_sc_ipc *ipc, u16 resource) { return true; } +static inline int imx_sc_rm_get_resource_owner(struct imx_sc_ipc *ipc, u16 resource, u8 *pt) +{ + return -EOPNOTSUPP; +} #endif #endif diff --git a/include/linux/platform_data/eth_ixp4xx.h b/include/linux/platform_data/eth_ixp4xx.h deleted file mode 100644 index 114b0940729f..000000000000 --- a/include/linux/platform_data/eth_ixp4xx.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __PLATFORM_DATA_ETH_IXP4XX -#define __PLATFORM_DATA_ETH_IXP4XX - -#include - -#define IXP4XX_ETH_NPEA 0x00 -#define IXP4XX_ETH_NPEB 0x10 -#define IXP4XX_ETH_NPEC 0x20 - -/* Information about built-in Ethernet MAC interfaces */ -struct eth_plat_info { - u8 phy; /* MII PHY ID, 0 - 31 */ - u8 rxq; /* configurable, currently 0 - 31 only */ - u8 txreadyq; - u8 hwaddr[6]; - u8 npe; /* NPE instance used by this interface */ - bool has_mdio; /* If this instance has an MDIO bus */ -}; - -#endif diff --git a/include/linux/platform_data/wan_ixp4xx_hss.h b/include/linux/platform_data/wan_ixp4xx_hss.h deleted file mode 100644 index d525a0feb9e1..000000000000 --- a/include/linux/platform_data/wan_ixp4xx_hss.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __PLATFORM_DATA_WAN_IXP4XX_HSS_H -#define __PLATFORM_DATA_WAN_IXP4XX_HSS_H - -#include - -/* Information about built-in HSS (synchronous serial) interfaces */ -struct hss_plat_info { - int (*set_clock)(int port, unsigned int clock_type); - int (*open)(int port, void *pdev, - void (*set_carrier_cb)(void *pdev, int carrier)); - void (*close)(int port, void *pdev); - u8 txreadyq; - u32 timer_freq; -}; - -#endif diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index 81cad9e1e412..f8335644a01a 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -63,13 +63,21 @@ enum qcom_scm_ice_cipher { extern bool qcom_scm_is_available(void); -extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus); -extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus); +extern int qcom_scm_set_cold_boot_addr(void *entry); +extern int qcom_scm_set_warm_boot_addr(void *entry); extern void qcom_scm_cpu_power_down(u32 flags); extern int qcom_scm_set_remote_state(u32 state, u32 id); +struct qcom_scm_pas_metadata { + void *ptr; + dma_addr_t phys; + ssize_t size; +}; + extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, - size_t size); + size_t size, + struct qcom_scm_pas_metadata *ctx); +void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx); extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size); extern int qcom_scm_pas_auth_and_reset(u32 peripheral); @@ -83,6 +91,7 @@ extern bool qcom_scm_restore_sec_cfg_available(void); extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare); extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size); extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare); +extern int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size); extern int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, u32 cp_nonpixel_start, u32 cp_nonpixel_size); @@ -107,6 +116,7 @@ extern bool qcom_scm_hdcp_available(void); extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); +extern int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt); extern int qcom_scm_qsmmu500_wait_safe_toggle(bool en); extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 80e781c51ddc..b87551f41f9f 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -42,6 +42,7 @@ struct scmi_revision_info { struct scmi_clock_info { char name[SCMI_MAX_STR_SIZE]; + unsigned int enable_latency; bool rate_discrete; union { struct { @@ -82,6 +83,9 @@ struct scmi_clk_proto_ops { u64 rate); int (*enable)(const struct scmi_protocol_handle *ph, u32 clk_id); int (*disable)(const struct scmi_protocol_handle *ph, u32 clk_id); + int (*enable_atomic)(const struct scmi_protocol_handle *ph, u32 clk_id); + int (*disable_atomic)(const struct scmi_protocol_handle *ph, + u32 clk_id); }; /** @@ -612,6 +616,15 @@ struct scmi_notify_ops { * @devm_protocol_get: devres managed method to acquire a protocol and get specific * operations and a dedicated protocol handler * @devm_protocol_put: devres managed method to release a protocol + * @is_transport_atomic: method to check if the underlying transport for this + * instance handle is configured to support atomic + * transactions for commands. + * Some users of the SCMI stack in the upper layers could + * be interested to know if they can assume SCMI + * command transactions associated to this handle will + * never sleep and act accordingly. + * An optional atomic threshold value could be returned + * where configured. * @notify_ops: pointer to set of notifications related operations */ struct scmi_handle { @@ -622,6 +635,8 @@ struct scmi_handle { (*devm_protocol_get)(struct scmi_device *sdev, u8 proto, struct scmi_protocol_handle **ph); void (*devm_protocol_put)(struct scmi_device *sdev, u8 proto); + bool (*is_transport_atomic)(const struct scmi_handle *handle, + unsigned int *atomic_threshold); const struct scmi_notify_ops *notify_ops; }; diff --git a/include/linux/soc/ixp4xx/cpu.h b/include/linux/soc/ixp4xx/cpu.h index 88bd8de0e803..f526ac33afea 100644 --- a/include/linux/soc/ixp4xx/cpu.h +++ b/include/linux/soc/ixp4xx/cpu.h @@ -9,6 +9,7 @@ #define __SOC_IXP4XX_CPU_H__ #include +#include #ifdef CONFIG_ARM #include #endif @@ -23,6 +24,9 @@ #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */ #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0 +/* Feature register in the expansion bus controller */ +#define IXP4XX_EXP_CNFG2 0x2c + /* "fuse" bits of IXP_EXP_CFG2 */ /* All IXP4xx CPUs */ #define IXP4XX_FEATURE_RCOMP (1 << 0) @@ -86,21 +90,31 @@ IXP43X_PROCESSOR_ID_VALUE) #define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \ IXP46X_PROCESSOR_ID_VALUE) +static inline u32 cpu_ixp4xx_features(struct regmap *rmap) +{ + u32 val; -u32 ixp4xx_read_feature_bits(void); -void ixp4xx_write_feature_bits(u32 value); + regmap_read(rmap, IXP4XX_EXP_CNFG2, &val); + /* For some reason this register is inverted */ + val = ~val; + if (cpu_is_ixp42x_rev_a0()) + return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | + IXP4XX_FEATURE_AES); + if (cpu_is_ixp42x()) + return val & IXP42X_FEATURE_MASK; + if (cpu_is_ixp43x()) + return val & IXP43X_FEATURE_MASK; + return val & IXP46X_FEATURE_MASK; +} #else #define cpu_is_ixp42x_rev_a0() 0 #define cpu_is_ixp42x() 0 #define cpu_is_ixp43x() 0 #define cpu_is_ixp46x() 0 -static inline u32 ixp4xx_read_feature_bits(void) +static inline u32 cpu_ixp4xx_features(struct regmap *rmap) { return 0; } -static inline void ixp4xx_write_feature_bits(u32 value) -{ -} #endif #endif /* _ASM_ARCH_CPU_H */ diff --git a/include/linux/soc/ixp4xx/npe.h b/include/linux/soc/ixp4xx/npe.h index 2a91f465d456..9efeac777da1 100644 --- a/include/linux/soc/ixp4xx/npe.h +++ b/include/linux/soc/ixp4xx/npe.h @@ -3,6 +3,7 @@ #define __IXP4XX_NPE_H #include +#include extern const char *npe_names[]; @@ -17,6 +18,7 @@ struct npe_regs { struct npe { struct npe_regs __iomem *regs; + struct regmap *rmap; int id; int valid; }; diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index 4615a228da51..50804ac748bd 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -2,6 +2,88 @@ #ifndef __SOC_MEDIATEK_INFRACFG_H #define __SOC_MEDIATEK_INFRACFG_H +#define MT8195_TOP_AXI_PROT_EN_STA1 0x228 +#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258 +#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0 +#define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4 +#define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8 +#define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac +#define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4 +#define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8 +#define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec +#define MT8195_TOP_AXI_PROT_EN_2_SET 0x714 +#define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718 +#define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724 +#define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84 +#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88 +#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90 +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4 +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8 +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0 +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8 +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4 +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0 +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8 +#define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc +#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0 +#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8 + +#define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6) +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10) +#define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11) +#define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, 21) +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23) +#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, 19) +#define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22) +#define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0) +#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5) +#define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7) +#define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11)) +#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14)) +#define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2) | BIT(4)) +#define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1) +#define MT8195_TOP_AXI_PROT_EN_MM_IMG BIT(3) +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 GENMASK(21, 17) +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5) +#define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) | BIT(11)) +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10) | BIT(12)) +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13) +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14) +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22) +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23) +#define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24) +#define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25) +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26) +#define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27) +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28) +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29) +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, 30) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(1, 0) | BIT(4) | BIT(11)) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) | BIT(15)) +#define MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) | BIT(17)) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, 6) | BIT(18)) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 GENMASK(9, 8) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13) +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14) +#define MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22) +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, 23) +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1) +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2) +#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11) | BIT(28)) +#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12) | BIT(29)) +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13) +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14) +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | BIT(19)) +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20) +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21) + #define MT8192_TOP_AXI_PROT_EN_STA1 0x228 #define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258 #define MT8192_TOP_AXI_PROT_EN_SET 0x2a0 @@ -58,6 +140,54 @@ #define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13) #define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21) +#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0) +#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4) +#define MT8186_TOP_AXI_PROT_EN_STA (0x228) +#define MT8186_TOP_AXI_PROT_EN_1_SET (0x2A8) +#define MT8186_TOP_AXI_PROT_EN_1_CLR (0x2AC) +#define MT8186_TOP_AXI_PROT_EN_1_STA (0x258) +#define MT8186_TOP_AXI_PROT_EN_2_SET (0x2B0) +#define MT8186_TOP_AXI_PROT_EN_2_CLR (0x2B4) +#define MT8186_TOP_AXI_PROT_EN_2_STA (0x26C) +#define MT8186_TOP_AXI_PROT_EN_3_SET (0x2B8) +#define MT8186_TOP_AXI_PROT_EN_3_CLR (0x2BC) +#define MT8186_TOP_AXI_PROT_EN_3_STA (0x2C8) + +/* MFG1 */ +#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP1 (GENMASK(28, 27)) +#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP2 (GENMASK(22, 21)) +#define MT8186_TOP_AXI_PROT_EN_MFG1_STEP3 (BIT(25)) +#define MT8186_TOP_AXI_PROT_EN_1_MFG1_STEP4 (BIT(29)) +/* DIS */ +#define MT8186_TOP_AXI_PROT_EN_1_DIS_STEP1 (GENMASK(12, 11)) +#define MT8186_TOP_AXI_PROT_EN_DIS_STEP2 (GENMASK(2, 1) | GENMASK(11, 10)) +/* IMG */ +#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP1 (BIT(23)) +#define MT8186_TOP_AXI_PROT_EN_1_IMG_STEP2 (BIT(15)) +/* IPE */ +#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP1 (BIT(24)) +#define MT8186_TOP_AXI_PROT_EN_1_IPE_STEP2 (BIT(16)) +/* CAM */ +#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP1 (GENMASK(22, 21)) +#define MT8186_TOP_AXI_PROT_EN_1_CAM_STEP2 (GENMASK(14, 13)) +/* VENC */ +#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP1 (BIT(31)) +#define MT8186_TOP_AXI_PROT_EN_1_VENC_STEP2 (BIT(19)) +/* VDEC */ +#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP1 (BIT(30)) +#define MT8186_TOP_AXI_PROT_EN_1_VDEC_STEP2 (BIT(17)) +/* WPE */ +#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP1 (BIT(17)) +#define MT8186_TOP_AXI_PROT_EN_2_WPE_STEP2 (BIT(16)) +/* CONN_ON */ +#define MT8186_TOP_AXI_PROT_EN_1_CONN_ON_STEP1 (BIT(18)) +#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP2 (BIT(14)) +#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP3 (BIT(13)) +#define MT8186_TOP_AXI_PROT_EN_CONN_ON_STEP4 (BIT(16)) +/* ADSP_TOP */ +#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP1 (GENMASK(12, 11)) +#define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2 (GENMASK(1, 0)) + #define MT8183_TOP_AXI_PROT_EN_STA1 0x228 #define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258 #define MT8183_TOP_AXI_PROT_EN_SET 0x2a0 @@ -147,6 +277,9 @@ #define INFRA_TOPAXI_PROTECTEN_SET 0x0260 #define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 +#define MT8192_INFRA_CTRL 0x290 +#define MT8192_INFRA_CTRL_DISABLE_MFG2ACP BIT(9) + #define REG_INFRA_MISC 0xf00 #define F_DDR_4GB_SUPPORT_EN BIT(13) diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 9e8fd92c96b7..0bc21ee58fac 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -35,7 +35,12 @@ #define LLCC_WRCACHE 31 #define LLCC_CVPFW 32 #define LLCC_CPUSS1 33 +#define LLCC_CAMEXP0 34 +#define LLCC_CPUMTE 35 #define LLCC_CPUHWT 36 +#define LLCC_MDMCLAD2 37 +#define LLCC_CAMEXP1 38 +#define LLCC_AENPU 45 /** * struct llcc_slice_desc - Cache slice descriptor @@ -83,7 +88,7 @@ struct llcc_edac_reg_data { * @bitmap: Bit map to track the active slice ids * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting - * @major_version: Indicates the LLCC major version + * @version: Indicates the LLCC version */ struct llcc_drv_data { struct regmap *regmap; @@ -96,7 +101,7 @@ struct llcc_drv_data { unsigned long *bitmap; u32 *offsets; int ecc_irq; - u32 major_version; + u32 version; }; #if IS_ENABLED(CONFIG_QCOM_LLCC) diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/mdt_loader.h index afd47217996b..9e8e60421192 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -10,10 +10,14 @@ struct device; struct firmware; +struct qcom_scm_pas_metadata; #if IS_ENABLED(CONFIG_QCOM_MDT_LOADER) ssize_t qcom_mdt_get_size(const struct firmware *fw); +int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, + const char *fw_name, int pas_id, phys_addr_t mem_phys, + struct qcom_scm_pas_metadata *pas_metadata_ctx); int qcom_mdt_load(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, void *mem_region, phys_addr_t mem_phys, size_t mem_size, @@ -23,7 +27,8 @@ int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, void *mem_region, phys_addr_t mem_phys, size_t mem_size, phys_addr_t *reloc_base); -void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len); +void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len, + const char *fw_name, struct device *dev); #else /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */ @@ -32,6 +37,13 @@ static inline ssize_t qcom_mdt_get_size(const struct firmware *fw) return -ENODEV; } +static inline int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, + const char *fw_name, int pas_id, phys_addr_t mem_phys, + struct qcom_scm_pas_metadata *pas_metadata_ctx) +{ + return -ENODEV; +} + static inline int qcom_mdt_load(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, void *mem_region, phys_addr_t mem_phys, @@ -51,7 +63,8 @@ static inline int qcom_mdt_load_no_init(struct device *dev, } static inline void *qcom_mdt_read_metadata(const struct firmware *fw, - size_t *data_len) + size_t *data_len, const char *fw_name, + struct device *dev) { return ERR_PTR(-ENODEV); } diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index 0aad7009b50e..bd0d11af76c5 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -645,7 +645,7 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle, static inline struct ti_sci_resource * devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev, - u32 dev_id, u32 sub_type); + u32 dev_id, u32 sub_type) { return ERR_PTR(-EINVAL); } diff --git a/include/linux/syscalls.h b/include/linux/syscalls.h index 819c0cb00b6d..a34b0f9a9972 100644 --- a/include/linux/syscalls.h +++ b/include/linux/syscalls.h @@ -290,10 +290,6 @@ static inline void addr_limit_user_check(void) return; #endif - if (CHECK_DATA_CORRUPTION(uaccess_kernel(), - "Invalid address limit on user-mode return")) - force_sig(SIGKILL); - #ifdef TIF_FSCHECK clear_thread_flag(TIF_FSCHECK); #endif diff --git a/include/linux/tee_drv.h b/include/linux/tee_drv.h index 5e1533ee3785..911cad324acc 100644 --- a/include/linux/tee_drv.h +++ b/include/linux/tee_drv.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2015-2016, Linaro Limited + * Copyright (c) 2015-2022 Linaro Limited */ #ifndef __TEE_DRV_H @@ -20,14 +20,11 @@ * specific TEE driver. */ -#define TEE_SHM_MAPPED BIT(0) /* Memory mapped by the kernel */ -#define TEE_SHM_DMA_BUF BIT(1) /* Memory with dma-buf handle */ -#define TEE_SHM_EXT_DMA_BUF BIT(2) /* Memory with dma-buf handle */ -#define TEE_SHM_REGISTER BIT(3) /* Memory registered in secure world */ -#define TEE_SHM_USER_MAPPED BIT(4) /* Memory mapped in user space */ -#define TEE_SHM_POOL BIT(5) /* Memory allocated from pool */ -#define TEE_SHM_KERNEL_MAPPED BIT(6) /* Memory mapped in kernel space */ -#define TEE_SHM_PRIV BIT(7) /* Memory private to TEE driver */ +#define TEE_SHM_DYNAMIC BIT(0) /* Dynamic shared memory registered */ + /* in secure world */ +#define TEE_SHM_USER_MAPPED BIT(1) /* Memory mapped in user space */ +#define TEE_SHM_POOL BIT(2) /* Memory allocated from pool */ +#define TEE_SHM_PRIV BIT(3) /* Memory private to TEE driver */ struct device; struct tee_device; @@ -221,92 +218,39 @@ struct tee_shm { }; /** - * struct tee_shm_pool_mgr - shared memory manager + * struct tee_shm_pool - shared memory pool * @ops: operations * @private_data: private data for the shared memory manager */ -struct tee_shm_pool_mgr { - const struct tee_shm_pool_mgr_ops *ops; +struct tee_shm_pool { + const struct tee_shm_pool_ops *ops; void *private_data; }; /** - * struct tee_shm_pool_mgr_ops - shared memory pool manager operations + * struct tee_shm_pool_ops - shared memory pool operations * @alloc: called when allocating shared memory * @free: called when freeing shared memory - * @destroy_poolmgr: called when destroying the pool manager + * @destroy_pool: called when destroying the pool */ -struct tee_shm_pool_mgr_ops { - int (*alloc)(struct tee_shm_pool_mgr *poolmgr, struct tee_shm *shm, - size_t size); - void (*free)(struct tee_shm_pool_mgr *poolmgr, struct tee_shm *shm); - void (*destroy_poolmgr)(struct tee_shm_pool_mgr *poolmgr); +struct tee_shm_pool_ops { + int (*alloc)(struct tee_shm_pool *pool, struct tee_shm *shm, + size_t size, size_t align); + void (*free)(struct tee_shm_pool *pool, struct tee_shm *shm); + void (*destroy_pool)(struct tee_shm_pool *pool); }; -/** - * tee_shm_pool_alloc() - Create a shared memory pool from shm managers - * @priv_mgr: manager for driver private shared memory allocations - * @dmabuf_mgr: manager for dma-buf shared memory allocations - * - * Allocation with the flag TEE_SHM_DMA_BUF set will use the range supplied - * in @dmabuf, others will use the range provided by @priv. - * - * @returns pointer to a 'struct tee_shm_pool' or an ERR_PTR on failure. - */ -struct tee_shm_pool *tee_shm_pool_alloc(struct tee_shm_pool_mgr *priv_mgr, - struct tee_shm_pool_mgr *dmabuf_mgr); - /* - * tee_shm_pool_mgr_alloc_res_mem() - Create a shm manager for reserved - * memory + * tee_shm_pool_alloc_res_mem() - Create a shm manager for reserved memory * @vaddr: Virtual address of start of pool * @paddr: Physical address of start of pool * @size: Size in bytes of the pool * - * @returns pointer to a 'struct tee_shm_pool_mgr' or an ERR_PTR on failure. - */ -struct tee_shm_pool_mgr *tee_shm_pool_mgr_alloc_res_mem(unsigned long vaddr, - phys_addr_t paddr, - size_t size, - int min_alloc_order); - -/** - * tee_shm_pool_mgr_destroy() - Free a shared memory manager - */ -static inline void tee_shm_pool_mgr_destroy(struct tee_shm_pool_mgr *poolm) -{ - poolm->ops->destroy_poolmgr(poolm); -} - -/** - * struct tee_shm_pool_mem_info - holds information needed to create a shared - * memory pool - * @vaddr: Virtual address of start of pool - * @paddr: Physical address of start of pool - * @size: Size in bytes of the pool - */ -struct tee_shm_pool_mem_info { - unsigned long vaddr; - phys_addr_t paddr; - size_t size; -}; - -/** - * tee_shm_pool_alloc_res_mem() - Create a shared memory pool from reserved - * memory range - * @priv_info: Information for driver private shared memory pool - * @dmabuf_info: Information for dma-buf shared memory pool - * - * Start and end of pools will must be page aligned. - * - * Allocation with the flag TEE_SHM_DMA_BUF set will use the range supplied - * in @dmabuf, others will use the range provided by @priv. - * * @returns pointer to a 'struct tee_shm_pool' or an ERR_PTR on failure. */ -struct tee_shm_pool * -tee_shm_pool_alloc_res_mem(struct tee_shm_pool_mem_info *priv_info, - struct tee_shm_pool_mem_info *dmabuf_info); +struct tee_shm_pool *tee_shm_pool_alloc_res_mem(unsigned long vaddr, + phys_addr_t paddr, size_t size, + int min_alloc_order); /** * tee_shm_pool_free() - Free a shared memory pool @@ -315,7 +259,10 @@ tee_shm_pool_alloc_res_mem(struct tee_shm_pool_mem_info *priv_info, * The must be no remaining shared memory allocated from this pool when * this function is called. */ -void tee_shm_pool_free(struct tee_shm_pool *pool); +static inline void tee_shm_pool_free(struct tee_shm_pool *pool) +{ + pool->ops->destroy_pool(pool); +} /** * tee_get_drvdata() - Return driver_data pointer @@ -323,43 +270,20 @@ void tee_shm_pool_free(struct tee_shm_pool *pool); */ void *tee_get_drvdata(struct tee_device *teedev); -/** - * tee_shm_alloc() - Allocate shared memory - * @ctx: Context that allocates the shared memory - * @size: Requested size of shared memory - * @flags: Flags setting properties for the requested shared memory. - * - * Memory allocated as global shared memory is automatically freed when the - * TEE file pointer is closed. The @flags field uses the bits defined by - * TEE_SHM_* above. TEE_SHM_MAPPED must currently always be set. If - * TEE_SHM_DMA_BUF global shared memory will be allocated and associated - * with a dma-buf handle, else driver private memory. - * - * @returns a pointer to 'struct tee_shm' - */ -struct tee_shm *tee_shm_alloc(struct tee_context *ctx, size_t size, u32 flags); +struct tee_shm *tee_shm_alloc_priv_buf(struct tee_context *ctx, size_t size); struct tee_shm *tee_shm_alloc_kernel_buf(struct tee_context *ctx, size_t size); -/** - * tee_shm_register() - Register shared memory buffer - * @ctx: Context that registers the shared memory - * @addr: Address is userspace of the shared buffer - * @length: Length of the shared buffer - * @flags: Flags setting properties for the requested shared memory. - * - * @returns a pointer to 'struct tee_shm' - */ -struct tee_shm *tee_shm_register(struct tee_context *ctx, unsigned long addr, - size_t length, u32 flags); +struct tee_shm *tee_shm_register_kernel_buf(struct tee_context *ctx, + void *addr, size_t length); /** - * tee_shm_is_registered() - Check if shared memory object in registered in TEE + * tee_shm_is_dynamic() - Check if shared memory object is of the dynamic kind * @shm: Shared memory handle - * @returns true if object is registered in TEE + * @returns true if object is dynamic shared memory */ -static inline bool tee_shm_is_registered(struct tee_shm *shm) +static inline bool tee_shm_is_dynamic(struct tee_shm *shm) { - return shm && (shm->flags & TEE_SHM_REGISTER); + return shm && (shm->flags & TEE_SHM_DYNAMIC); } /** diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h index bca27b4e5eb2..546179418ffa 100644 --- a/include/linux/uaccess.h +++ b/include/linux/uaccess.h @@ -10,46 +10,6 @@ #include -#ifdef CONFIG_SET_FS -/* - * Force the uaccess routines to be wired up for actual userspace access, - * overriding any possible set_fs(KERNEL_DS) still lingering around. Undone - * using force_uaccess_end below. - */ -static inline mm_segment_t force_uaccess_begin(void) -{ - mm_segment_t fs = get_fs(); - - set_fs(USER_DS); - return fs; -} - -static inline void force_uaccess_end(mm_segment_t oldfs) -{ - set_fs(oldfs); -} -#else /* CONFIG_SET_FS */ -typedef struct { - /* empty dummy */ -} mm_segment_t; - -#ifndef TASK_SIZE_MAX -#define TASK_SIZE_MAX TASK_SIZE -#endif - -#define uaccess_kernel() (false) -#define user_addr_max() (TASK_SIZE_MAX) - -static inline mm_segment_t force_uaccess_begin(void) -{ - return (mm_segment_t) { }; -} - -static inline void force_uaccess_end(mm_segment_t oldfs) -{ -} -#endif /* CONFIG_SET_FS */ - /* * Architectures should provide two primitives (raw_copy_{to,from}_user()) * and get rid of their private instances of copy_{to,from}_user() and @@ -368,6 +328,25 @@ long strncpy_from_user_nofault(char *dst, const void __user *unsafe_addr, long count); long strnlen_user_nofault(const void __user *unsafe_addr, long count); +#ifndef __get_kernel_nofault +#define __get_kernel_nofault(dst, src, type, label) \ +do { \ + type __user *p = (type __force __user *)(src); \ + type data; \ + if (__get_user(data, p)) \ + goto label; \ + *(type *)dst = data; \ +} while (0) + +#define __put_kernel_nofault(dst, src, type, label) \ +do { \ + type __user *p = (type __force __user *)(dst); \ + type data = *(type *)src; \ + if (__put_user(data, p)) \ + goto label; \ +} while (0) +#endif + /** * get_kernel_nofault(): safely attempt to read from a location * @val: read into this variable diff --git a/include/rdma/ib.h b/include/rdma/ib.h index 83139b9ce409..f7c185ff7a11 100644 --- a/include/rdma/ib.h +++ b/include/rdma/ib.h @@ -75,7 +75,7 @@ struct sockaddr_ib { */ static inline bool ib_safe_file_access(struct file *filp) { - return filp->f_cred == current_cred() && !uaccess_kernel(); + return filp->f_cred == current_cred(); } #endif /* _RDMA_IB_H */ diff --git a/include/soc/at91/sama7-ddr.h b/include/soc/at91/sama7-ddr.h index f6542584ca13..9e17247474fa 100644 --- a/include/soc/at91/sama7-ddr.h +++ b/include/soc/at91/sama7-ddr.h @@ -11,15 +11,13 @@ #ifndef __SAMA7_DDR_H__ #define __SAMA7_DDR_H__ -#ifdef CONFIG_SOC_SAMA7 - /* DDR3PHY */ #define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */ -#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ +#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */ #define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */ -#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */ +#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */ #define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */ -#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */ +#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */ #define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */ #define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */ @@ -55,7 +53,8 @@ #define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */ #define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */ -#define UDDRC_PWRCTRL_SELFREF_SW (1 << 5) /* Software self-refresh */ +#define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */ +#define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */ #define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */ #define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */ @@ -67,7 +66,7 @@ #define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */ #define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */ -#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */ +#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */ #define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */ #define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */ @@ -75,6 +74,4 @@ #define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */ #define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */ -#endif /* CONFIG_SOC_SAMA7 */ - #endif /* __SAMA7_DDR_H__ */ diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h index 2b64c95f3be5..6466515262bd 100644 --- a/include/soc/microchip/mpfs.h +++ b/include/soc/microchip/mpfs.h @@ -34,9 +34,9 @@ struct mpfs_mss_response { #if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) -int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg); +int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, struct mpfs_mss_msg *msg); -struct mpfs_sys_controller *mpfs_sys_controller_get(struct device_node *mailbox_node); +struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev); #endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */ diff --git a/include/soc/tegra/bpmp-abi.h b/include/soc/tegra/bpmp-abi.h index bff99f23860c..53171e324d1c 100644 --- a/include/soc/tegra/bpmp-abi.h +++ b/include/soc/tegra/bpmp-abi.h @@ -931,7 +931,7 @@ enum mrq_reset_commands { * @brief Request with MRQ_RESET * * Used by the sender of an #MRQ_RESET message to request BPMP to - * assert or or deassert a given reset line. + * assert or deassert a given reset line. */ struct mrq_reset_request { /** @brief Reset action to perform (@ref mrq_reset_commands) */ diff --git a/include/trace/events/scmi.h b/include/trace/events/scmi.h index f3a4b4d60714..cee4b2b64ae4 100644 --- a/include/trace/events/scmi.h +++ b/include/trace/events/scmi.h @@ -33,6 +33,34 @@ TRACE_EVENT(scmi_xfer_begin, __entry->seq, __entry->poll) ); +TRACE_EVENT(scmi_xfer_response_wait, + TP_PROTO(int transfer_id, u8 msg_id, u8 protocol_id, u16 seq, + u32 timeout, bool poll), + TP_ARGS(transfer_id, msg_id, protocol_id, seq, timeout, poll), + + TP_STRUCT__entry( + __field(int, transfer_id) + __field(u8, msg_id) + __field(u8, protocol_id) + __field(u16, seq) + __field(u32, timeout) + __field(bool, poll) + ), + + TP_fast_assign( + __entry->transfer_id = transfer_id; + __entry->msg_id = msg_id; + __entry->protocol_id = protocol_id; + __entry->seq = seq; + __entry->timeout = timeout; + __entry->poll = poll; + ), + + TP_printk("transfer_id=%d msg_id=%u protocol_id=%u seq=%u tmo_ms=%u poll=%u", + __entry->transfer_id, __entry->msg_id, __entry->protocol_id, + __entry->seq, __entry->timeout, __entry->poll) +); + TRACE_EVENT(scmi_xfer_end, TP_PROTO(int transfer_id, u8 msg_id, u8 protocol_id, u16 seq, int status), diff --git a/include/uapi/asm-generic/shmbuf.h b/include/uapi/asm-generic/shmbuf.h index 2bab955e0fed..2979b6dd2c56 100644 --- a/include/uapi/asm-generic/shmbuf.h +++ b/include/uapi/asm-generic/shmbuf.h @@ -3,6 +3,8 @@ #define __ASM_GENERIC_SHMBUF_H #include +#include +#include /* * The shmid64_ds structure for x86 architecture. @@ -24,7 +26,7 @@ struct shmid64_ds { struct ipc64_perm shm_perm; /* operation perms */ - size_t shm_segsz; /* size of segment (bytes) */ + __kernel_size_t shm_segsz; /* size of segment (bytes) */ #if __BITS_PER_LONG == 64 long shm_atime; /* last attach time */ long shm_dtime; /* last detach time */ diff --git a/include/uapi/asm-generic/signal.h b/include/uapi/asm-generic/signal.h index f634822906e4..0eb69dc8e572 100644 --- a/include/uapi/asm-generic/signal.h +++ b/include/uapi/asm-generic/signal.h @@ -85,7 +85,7 @@ struct sigaction { typedef struct sigaltstack { void __user *ss_sp; int ss_flags; - size_t ss_size; + __kernel_size_t ss_size; } stack_t; #endif /* __ASSEMBLY__ */ diff --git a/include/uapi/linux/android/binder.h b/include/uapi/linux/android/binder.h index 2d3f015e2ae3..5f4eb7a04a5d 100644 --- a/include/uapi/linux/android/binder.h +++ b/include/uapi/linux/android/binder.h @@ -336,8 +336,8 @@ struct binder_transaction_data { /* General information about the transaction. */ __u32 flags; - pid_t sender_pid; - uid_t sender_euid; + __kernel_pid_t sender_pid; + __kernel_uid_t sender_euid; binder_size_t data_size; /* number of bytes of data */ binder_size_t offsets_size; /* number of bytes of offsets */ diff --git a/include/uapi/linux/fsmap.h b/include/uapi/linux/fsmap.h index 91fd519a3f7d..c690d17f1d07 100644 --- a/include/uapi/linux/fsmap.h +++ b/include/uapi/linux/fsmap.h @@ -69,7 +69,7 @@ struct fsmap_head { }; /* Size of an fsmap_head with room for nr records. */ -static inline size_t +static inline __kernel_size_t fsmap_sizeof( unsigned int nr) { diff --git a/include/uapi/linux/kexec.h b/include/uapi/linux/kexec.h index 778dc191c265..fb7e2ef60825 100644 --- a/include/uapi/linux/kexec.h +++ b/include/uapi/linux/kexec.h @@ -54,9 +54,9 @@ */ struct kexec_segment { const void *buf; - size_t bufsz; + __kernel_size_t bufsz; const void *mem; - size_t memsz; + __kernel_size_t memsz; }; #endif /* __KERNEL__ */ diff --git a/include/uapi/linux/reiserfs_xattr.h b/include/uapi/linux/reiserfs_xattr.h index 28f10842f047..503ad018ce5b 100644 --- a/include/uapi/linux/reiserfs_xattr.h +++ b/include/uapi/linux/reiserfs_xattr.h @@ -19,7 +19,7 @@ struct reiserfs_xattr_header { struct reiserfs_security_handle { const char *name; void *value; - size_t length; + __kernel_size_t length; }; #endif /* _LINUX_REISERFS_XATTR_H */ diff --git a/kernel/dma/mapping.c b/kernel/dma/mapping.c index 9478eccd1c8e..559461a826ba 100644 --- a/kernel/dma/mapping.c +++ b/kernel/dma/mapping.c @@ -745,7 +745,6 @@ int dma_set_mask(struct device *dev, u64 mask) } EXPORT_SYMBOL(dma_set_mask); -#ifndef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK int dma_set_coherent_mask(struct device *dev, u64 mask) { /* @@ -761,7 +760,6 @@ int dma_set_coherent_mask(struct device *dev, u64 mask) return 0; } EXPORT_SYMBOL(dma_set_coherent_mask); -#endif size_t dma_max_mapping_size(struct device *dev) { diff --git a/kernel/events/callchain.c b/kernel/events/callchain.c index 58cbe357fb2b..1273be84392c 100644 --- a/kernel/events/callchain.c +++ b/kernel/events/callchain.c @@ -209,17 +209,13 @@ get_perf_callchain(struct pt_regs *regs, u32 init_nr, bool kernel, bool user, } if (regs) { - mm_segment_t fs; - if (crosstask) goto exit_put; if (add_mark) perf_callchain_store_context(&ctx, PERF_CONTEXT_USER); - fs = force_uaccess_begin(); perf_callchain_user(&ctx, regs); - force_uaccess_end(fs); } } diff --git a/kernel/events/core.c b/kernel/events/core.c index 39ab0009558c..dc820323cd64 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -6732,7 +6732,6 @@ perf_output_sample_ustack(struct perf_output_handle *handle, u64 dump_size, unsigned long sp; unsigned int rem; u64 dyn_size; - mm_segment_t fs; /* * We dump: @@ -6750,9 +6749,7 @@ perf_output_sample_ustack(struct perf_output_handle *handle, u64 dump_size, /* Data. */ sp = perf_user_stack_pointer(regs); - fs = force_uaccess_begin(); rem = __output_copy_user(handle, (void *) sp, dump_size); - force_uaccess_end(fs); dyn_size = dump_size - rem; perf_output_skip(handle, rem); diff --git a/kernel/exit.c b/kernel/exit.c index 192b90a9ce16..f5459e28b861 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -737,20 +737,6 @@ void __noreturn do_exit(long code) WARN_ON(tsk->plug); - /* - * If do_dead is called because this processes oopsed, it's possible - * that get_fs() was left as KERNEL_DS, so reset it to USER_DS before - * continuing. Amongst other possible reasons, this is to prevent - * mm_release()->clear_child_tid() from writing to a user-controlled - * kernel address. - * - * On uptodate architectures force_uaccess_begin is a noop. On - * architectures that still have set_fs/get_fs in addition to handling - * oopses handles kernel threads that run as set_fs(KERNEL_DS) by - * default. - */ - force_uaccess_begin(); - kcov_task_exit(tsk); coredump_task_exit(tsk); diff --git a/kernel/kthread.c b/kernel/kthread.c index c2a19996effc..8dfab1e825c2 100644 --- a/kernel/kthread.c +++ b/kernel/kthread.c @@ -55,7 +55,6 @@ struct kthread { int result; int (*threadfn)(void *); void *data; - mm_segment_t oldfs; struct completion parked; struct completion exited; #ifdef CONFIG_BLK_CGROUP @@ -1442,8 +1441,6 @@ void kthread_use_mm(struct mm_struct *mm) mmdrop(active_mm); else smp_mb(); - - to_kthread(tsk)->oldfs = force_uaccess_begin(); } EXPORT_SYMBOL_GPL(kthread_use_mm); @@ -1458,8 +1455,6 @@ void kthread_unuse_mm(struct mm_struct *mm) WARN_ON_ONCE(!(tsk->flags & PF_KTHREAD)); WARN_ON_ONCE(!tsk->mm); - force_uaccess_end(to_kthread(tsk)->oldfs); - task_lock(tsk); /* * When a kthread stops operating on an address space, the loop diff --git a/kernel/stacktrace.c b/kernel/stacktrace.c index 6a2fe3490931..af3465071d74 100644 --- a/kernel/stacktrace.c +++ b/kernel/stacktrace.c @@ -228,15 +228,12 @@ unsigned int stack_trace_save_user(unsigned long *store, unsigned int size) .store = store, .size = size, }; - mm_segment_t fs; /* Trace user stack if not a kernel thread */ if (current->flags & PF_KTHREAD) return 0; - fs = force_uaccess_begin(); arch_stack_walk_user(consume_entry, &c, task_pt_regs(current)); - force_uaccess_end(fs); return c.len; } diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index 21aa30644219..8115fff17018 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -332,8 +332,6 @@ BPF_CALL_3(bpf_probe_write_user, void __user *, unsafe_ptr, const void *, src, if (unlikely(in_interrupt() || current->flags & (PF_KTHREAD | PF_EXITING))) return -EPERM; - if (unlikely(uaccess_kernel())) - return -EPERM; if (unlikely(!nmi_uaccess_okay())) return -EPERM; @@ -835,8 +833,6 @@ static int bpf_send_signal_common(u32 sig, enum pid_type type) */ if (unlikely(current->flags & (PF_KTHREAD | PF_EXITING))) return -EPERM; - if (unlikely(uaccess_kernel())) - return -EPERM; if (unlikely(!nmi_uaccess_okay())) return -EPERM; diff --git a/lib/strncpy_from_user.c b/lib/strncpy_from_user.c index 122d8d0e253c..08fc72d3ed16 100644 --- a/lib/strncpy_from_user.c +++ b/lib/strncpy_from_user.c @@ -120,7 +120,7 @@ long strncpy_from_user(char *dst, const char __user *src, long count) if (unlikely(count <= 0)) return 0; - max_addr = user_addr_max(); + max_addr = TASK_SIZE_MAX; src_addr = (unsigned long)untagged_addr(src); if (likely(src_addr < max_addr)) { unsigned long max = max_addr - src_addr; diff --git a/lib/strnlen_user.c b/lib/strnlen_user.c index 1616710b8a82..bffa0ebf9f8b 100644 --- a/lib/strnlen_user.c +++ b/lib/strnlen_user.c @@ -96,7 +96,7 @@ long strnlen_user(const char __user *str, long count) if (unlikely(count <= 0)) return 0; - max_addr = user_addr_max(); + max_addr = TASK_SIZE_MAX; src_addr = (unsigned long)untagged_addr(str); if (likely(src_addr < max_addr)) { unsigned long max = max_addr - src_addr; diff --git a/lib/test_lockup.c b/lib/test_lockup.c index 906b598740a7..c3fd87d6c2dd 100644 --- a/lib/test_lockup.c +++ b/lib/test_lockup.c @@ -417,9 +417,14 @@ static bool test_kernel_ptr(unsigned long addr, int size) return false; /* should be at least readable kernel address */ - if (access_ok(ptr, 1) || - access_ok(ptr + size - 1, 1) || - get_kernel_nofault(buf, ptr) || + if (!IS_ENABLED(CONFIG_ALTERNATE_USER_ADDRESS_SPACE) && + (access_ok((void __user *)ptr, 1) || + access_ok((void __user *)ptr + size - 1, 1))) { + pr_err("user space ptr invalid in kernel: %#lx\n", addr); + return true; + } + + if (get_kernel_nofault(buf, ptr) || get_kernel_nofault(buf, ptr + size - 1)) { pr_err("invalid kernel ptr: %#lx\n", addr); return true; diff --git a/mm/maccess.c b/mm/maccess.c index 3fed2b876539..5f4d240f67ec 100644 --- a/mm/maccess.c +++ b/mm/maccess.c @@ -12,8 +12,6 @@ bool __weak copy_from_kernel_nofault_allowed(const void *unsafe_src, return true; } -#ifdef HAVE_GET_KERNEL_NOFAULT - #define copy_from_kernel_nofault_loop(dst, src, len, type, err_label) \ while (len >= sizeof(type)) { \ __get_kernel_nofault(dst, src, type, err_label); \ @@ -102,112 +100,6 @@ Efault: dst[-1] = '\0'; return -EFAULT; } -#else /* HAVE_GET_KERNEL_NOFAULT */ -/** - * copy_from_kernel_nofault(): safely attempt to read from kernel-space - * @dst: pointer to the buffer that shall take the data - * @src: address to read from - * @size: size of the data chunk - * - * Safely read from kernel address @src to the buffer at @dst. If a kernel - * fault happens, handle that and return -EFAULT. If @src is not a valid kernel - * address, return -ERANGE. - * - * We ensure that the copy_from_user is executed in atomic context so that - * do_page_fault() doesn't attempt to take mmap_lock. This makes - * copy_from_kernel_nofault() suitable for use within regions where the caller - * already holds mmap_lock, or other locks which nest inside mmap_lock. - */ -long copy_from_kernel_nofault(void *dst, const void *src, size_t size) -{ - long ret; - mm_segment_t old_fs = get_fs(); - - if (!copy_from_kernel_nofault_allowed(src, size)) - return -ERANGE; - - set_fs(KERNEL_DS); - pagefault_disable(); - ret = __copy_from_user_inatomic(dst, (__force const void __user *)src, - size); - pagefault_enable(); - set_fs(old_fs); - - if (ret) - return -EFAULT; - return 0; -} -EXPORT_SYMBOL_GPL(copy_from_kernel_nofault); - -/** - * copy_to_kernel_nofault(): safely attempt to write to a location - * @dst: address to write to - * @src: pointer to the data that shall be written - * @size: size of the data chunk - * - * Safely write to address @dst from the buffer at @src. If a kernel fault - * happens, handle that and return -EFAULT. - */ -long copy_to_kernel_nofault(void *dst, const void *src, size_t size) -{ - long ret; - mm_segment_t old_fs = get_fs(); - - set_fs(KERNEL_DS); - pagefault_disable(); - ret = __copy_to_user_inatomic((__force void __user *)dst, src, size); - pagefault_enable(); - set_fs(old_fs); - - if (ret) - return -EFAULT; - return 0; -} - -/** - * strncpy_from_kernel_nofault: - Copy a NUL terminated string from unsafe - * address. - * @dst: Destination address, in kernel space. This buffer must be at - * least @count bytes long. - * @unsafe_addr: Unsafe address. - * @count: Maximum number of bytes to copy, including the trailing NUL. - * - * Copies a NUL-terminated string from unsafe address to kernel buffer. - * - * On success, returns the length of the string INCLUDING the trailing NUL. - * - * If access fails, returns -EFAULT (some data may have been copied and the - * trailing NUL added). If @unsafe_addr is not a valid kernel address, return - * -ERANGE. - * - * If @count is smaller than the length of the string, copies @count-1 bytes, - * sets the last byte of @dst buffer to NUL and returns @count. - */ -long strncpy_from_kernel_nofault(char *dst, const void *unsafe_addr, long count) -{ - mm_segment_t old_fs = get_fs(); - const void *src = unsafe_addr; - long ret; - - if (unlikely(count <= 0)) - return 0; - if (!copy_from_kernel_nofault_allowed(unsafe_addr, count)) - return -ERANGE; - - set_fs(KERNEL_DS); - pagefault_disable(); - - do { - ret = __get_user(*dst++, (const char __user __force *)src++); - } while (dst[-1] && ret == 0 && src - unsafe_addr < count); - - dst[-1] = '\0'; - pagefault_enable(); - set_fs(old_fs); - - return ret ? -EFAULT : src - unsafe_addr; -} -#endif /* HAVE_GET_KERNEL_NOFAULT */ /** * copy_from_user_nofault(): safely attempt to read from a user-space location @@ -221,14 +113,11 @@ long strncpy_from_kernel_nofault(char *dst, const void *unsafe_addr, long count) long copy_from_user_nofault(void *dst, const void __user *src, size_t size) { long ret = -EFAULT; - mm_segment_t old_fs = force_uaccess_begin(); - if (access_ok(src, size)) { pagefault_disable(); ret = __copy_from_user_inatomic(dst, src, size); pagefault_enable(); } - force_uaccess_end(old_fs); if (ret) return -EFAULT; @@ -248,14 +137,12 @@ EXPORT_SYMBOL_GPL(copy_from_user_nofault); long copy_to_user_nofault(void __user *dst, const void *src, size_t size) { long ret = -EFAULT; - mm_segment_t old_fs = force_uaccess_begin(); if (access_ok(dst, size)) { pagefault_disable(); ret = __copy_to_user_inatomic(dst, src, size); pagefault_enable(); } - force_uaccess_end(old_fs); if (ret) return -EFAULT; @@ -284,17 +171,14 @@ EXPORT_SYMBOL_GPL(copy_to_user_nofault); long strncpy_from_user_nofault(char *dst, const void __user *unsafe_addr, long count) { - mm_segment_t old_fs; long ret; if (unlikely(count <= 0)) return 0; - old_fs = force_uaccess_begin(); pagefault_disable(); ret = strncpy_from_user(dst, unsafe_addr, count); pagefault_enable(); - force_uaccess_end(old_fs); if (ret >= count) { ret = count; @@ -324,14 +208,11 @@ long strncpy_from_user_nofault(char *dst, const void __user *unsafe_addr, */ long strnlen_user_nofault(const void __user *unsafe_addr, long count) { - mm_segment_t old_fs; int ret; - old_fs = force_uaccess_begin(); pagefault_disable(); ret = strnlen_user(unsafe_addr, count); pagefault_enable(); - force_uaccess_end(old_fs); return ret; } diff --git a/mm/memory.c b/mm/memory.c index 8a254a4b130e..5d991f71708d 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -5259,14 +5259,6 @@ void print_vma_addr(char *prefix, unsigned long ip) #if defined(CONFIG_PROVE_LOCKING) || defined(CONFIG_DEBUG_ATOMIC_SLEEP) void __might_fault(const char *file, int line) { - /* - * Some code (nfs/sunrpc) uses socket ops on kernel memory while - * holding the mmap_lock, this is safe because kernel memory doesn't - * get paged out, therefore we'll never actually fault, and the - * below annotations will generate false positives. - */ - if (uaccess_kernel()) - return; if (pagefault_disabled()) return; __might_sleep(file, line); diff --git a/net/bpfilter/bpfilter_kern.c b/net/bpfilter/bpfilter_kern.c index 51a941b56ec3..422ec6e7ccff 100644 --- a/net/bpfilter/bpfilter_kern.c +++ b/net/bpfilter/bpfilter_kern.c @@ -70,7 +70,7 @@ static int bpfilter_process_sockopt(struct sock *sk, int optname, .addr = (uintptr_t)optval.user, .len = optlen, }; - if (uaccess_kernel() || sockptr_is_kernel(optval)) { + if (sockptr_is_kernel(optval)) { pr_err("kernel access not supported\n"); return -EFAULT; } diff --git a/scripts/recordmcount.pl b/scripts/recordmcount.pl index 3ccb2c70add4..6a4645a57976 100755 --- a/scripts/recordmcount.pl +++ b/scripts/recordmcount.pl @@ -362,9 +362,6 @@ if ($arch eq "x86_64") { $mcount_regex = "^\\s*([0-9a-fA-F]+):\\sR_RISCV_CALL(_PLT)?\\s_?mcount\$"; $type = ".quad"; $alignment = 2; -} elsif ($arch eq "nds32") { - $mcount_regex = "^\\s*([0-9a-fA-F]+):\\s*R_NDS32_HI20_RELA\\s+_mcount\$"; - $alignment = 2; } elsif ($arch eq "csky") { $mcount_regex = "^\\s*([0-9a-fA-F]+):\\s*R_CKCORE_PCREL_JSR_IMM26BY2\\s+_mcount\$"; $alignment = 2; diff --git a/security/keys/trusted-keys/trusted_tee.c b/security/keys/trusted-keys/trusted_tee.c index 2ce66c199e1d..c8626686ee1b 100644 --- a/security/keys/trusted-keys/trusted_tee.c +++ b/security/keys/trusted-keys/trusted_tee.c @@ -70,17 +70,15 @@ static int trusted_tee_seal(struct trusted_key_payload *p, char *datablob) memset(&inv_arg, 0, sizeof(inv_arg)); memset(¶m, 0, sizeof(param)); - reg_shm_in = tee_shm_register(pvt_data.ctx, (unsigned long)p->key, - p->key_len, TEE_SHM_DMA_BUF | - TEE_SHM_KERNEL_MAPPED); + reg_shm_in = tee_shm_register_kernel_buf(pvt_data.ctx, p->key, + p->key_len); if (IS_ERR(reg_shm_in)) { dev_err(pvt_data.dev, "key shm register failed\n"); return PTR_ERR(reg_shm_in); } - reg_shm_out = tee_shm_register(pvt_data.ctx, (unsigned long)p->blob, - sizeof(p->blob), TEE_SHM_DMA_BUF | - TEE_SHM_KERNEL_MAPPED); + reg_shm_out = tee_shm_register_kernel_buf(pvt_data.ctx, p->blob, + sizeof(p->blob)); if (IS_ERR(reg_shm_out)) { dev_err(pvt_data.dev, "blob shm register failed\n"); ret = PTR_ERR(reg_shm_out); @@ -131,17 +129,15 @@ static int trusted_tee_unseal(struct trusted_key_payload *p, char *datablob) memset(&inv_arg, 0, sizeof(inv_arg)); memset(¶m, 0, sizeof(param)); - reg_shm_in = tee_shm_register(pvt_data.ctx, (unsigned long)p->blob, - p->blob_len, TEE_SHM_DMA_BUF | - TEE_SHM_KERNEL_MAPPED); + reg_shm_in = tee_shm_register_kernel_buf(pvt_data.ctx, p->blob, + p->blob_len); if (IS_ERR(reg_shm_in)) { dev_err(pvt_data.dev, "blob shm register failed\n"); return PTR_ERR(reg_shm_in); } - reg_shm_out = tee_shm_register(pvt_data.ctx, (unsigned long)p->key, - sizeof(p->key), TEE_SHM_DMA_BUF | - TEE_SHM_KERNEL_MAPPED); + reg_shm_out = tee_shm_register_kernel_buf(pvt_data.ctx, p->key, + sizeof(p->key)); if (IS_ERR(reg_shm_out)) { dev_err(pvt_data.dev, "key shm register failed\n"); ret = PTR_ERR(reg_shm_out); @@ -192,8 +188,7 @@ static int trusted_tee_get_random(unsigned char *key, size_t key_len) memset(&inv_arg, 0, sizeof(inv_arg)); memset(¶m, 0, sizeof(param)); - reg_shm = tee_shm_register(pvt_data.ctx, (unsigned long)key, key_len, - TEE_SHM_DMA_BUF | TEE_SHM_KERNEL_MAPPED); + reg_shm = tee_shm_register_kernel_buf(pvt_data.ctx, key, key_len); if (IS_ERR(reg_shm)) { dev_err(pvt_data.dev, "key shm register failed\n"); return PTR_ERR(reg_shm); diff --git a/sound/soc/pxa/Kconfig b/sound/soc/pxa/Kconfig index 9d40e8a206d1..cecbec2a09d7 100644 --- a/sound/soc/pxa/Kconfig +++ b/sound/soc/pxa/Kconfig @@ -220,15 +220,6 @@ config SND_PXA2XX_SOC_MIOA701 Say Y if you want to add support for SoC audio on the MIO A701. -config SND_PXA2XX_SOC_IMOTE2 - tristate "SoC Audio support for IMote 2" - depends on SND_PXA2XX_SOC && MACH_INTELMOTE2 && I2C - select SND_PXA2XX_SOC_I2S - select SND_SOC_WM8940 - help - Say Y if you want to add support for SoC audio on the - IMote 2. - config SND_MMP_SOC_BROWNSTONE tristate "SoC Audio support for Marvell Brownstone" depends on SND_MMP_SOC_SSPA && MACH_BROWNSTONE && I2C diff --git a/sound/soc/pxa/Makefile b/sound/soc/pxa/Makefile index ea4929d73318..b712eb894a61 100644 --- a/sound/soc/pxa/Makefile +++ b/sound/soc/pxa/Makefile @@ -29,7 +29,6 @@ snd-soc-hx4700-objs := hx4700.o snd-soc-magician-objs := magician.o snd-soc-mioa701-objs := mioa701_wm9713.o snd-soc-z2-objs := z2.o -snd-soc-imote2-objs := imote2.o snd-soc-brownstone-objs := brownstone.o snd-soc-ttc-dkb-objs := ttc-dkb.o @@ -47,6 +46,5 @@ obj-$(CONFIG_SND_PXA2XX_SOC_MAGICIAN) += snd-soc-magician.o obj-$(CONFIG_SND_PXA2XX_SOC_MIOA701) += snd-soc-mioa701.o obj-$(CONFIG_SND_PXA2XX_SOC_Z2) += snd-soc-z2.o obj-$(CONFIG_SND_SOC_ZYLONITE) += snd-soc-zylonite.o -obj-$(CONFIG_SND_PXA2XX_SOC_IMOTE2) += snd-soc-imote2.o obj-$(CONFIG_SND_MMP_SOC_BROWNSTONE) += snd-soc-brownstone.o obj-$(CONFIG_SND_SOC_TTC_DKB) += snd-soc-ttc-dkb.o diff --git a/sound/soc/pxa/imote2.c b/sound/soc/pxa/imote2.c deleted file mode 100644 index a575676508b3..000000000000 --- a/sound/soc/pxa/imote2.c +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include -#include - -#include - -#include "../codecs/wm8940.h" -#include "pxa2xx-i2s.h" - -static int imote2_asoc_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); - struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); - struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); - unsigned int clk = 0; - int ret; - - switch (params_rate(params)) { - case 8000: - case 16000: - case 48000: - case 96000: - clk = 12288000; - break; - case 11025: - case 22050: - case 44100: - clk = 11289600; - break; - } - - ret = snd_soc_dai_set_sysclk(codec_dai, 0, clk, - SND_SOC_CLOCK_IN); - if (ret < 0) - return ret; - - /* set the I2S system clock as input (unused) */ - ret = snd_soc_dai_set_sysclk(cpu_dai, PXA2XX_I2S_SYSCLK, clk, - SND_SOC_CLOCK_OUT); - - return ret; -} - -static const struct snd_soc_ops imote2_asoc_ops = { - .hw_params = imote2_asoc_hw_params, -}; - -SND_SOC_DAILINK_DEFS(wm8940, - DAILINK_COMP_ARRAY(COMP_CPU("pxa2xx-i2s")), - DAILINK_COMP_ARRAY(COMP_CODEC("wm8940-codec.0-0034", - "wm8940-hifi")), - DAILINK_COMP_ARRAY(COMP_PLATFORM("pxa-pcm-audio"))); - -static struct snd_soc_dai_link imote2_dai = { - .name = "WM8940", - .stream_name = "WM8940", - .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | - SND_SOC_DAIFMT_CBS_CFS, - .ops = &imote2_asoc_ops, - SND_SOC_DAILINK_REG(wm8940), -}; - -static struct snd_soc_card imote2 = { - .name = "Imote2", - .owner = THIS_MODULE, - .dai_link = &imote2_dai, - .num_links = 1, -}; - -static int imote2_probe(struct platform_device *pdev) -{ - struct snd_soc_card *card = &imote2; - int ret; - - card->dev = &pdev->dev; - - ret = devm_snd_soc_register_card(&pdev->dev, card); - if (ret) - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", - ret); - return ret; -} - -static struct platform_driver imote2_driver = { - .driver = { - .name = "imote2-audio", - .pm = &snd_soc_pm_ops, - }, - .probe = imote2_probe, -}; - -module_platform_driver(imote2_driver); - -MODULE_AUTHOR("Jonathan Cameron"); -MODULE_DESCRIPTION("ALSA SoC Imote 2"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:imote2-audio"); diff --git a/tools/include/asm/barrier.h b/tools/include/asm/barrier.h index dc696c151e1c..8d378c57cb01 100644 --- a/tools/include/asm/barrier.h +++ b/tools/include/asm/barrier.h @@ -24,8 +24,6 @@ #include "../../arch/ia64/include/asm/barrier.h" #elif defined(__xtensa__) #include "../../arch/xtensa/include/asm/barrier.h" -#elif defined(__nds32__) -#include "../../arch/nds32/include/asm/barrier.h" #else #include #endif diff --git a/tools/perf/arch/nds32/Build b/tools/perf/arch/nds32/Build deleted file mode 100644 index e4e5f33c84d8..000000000000 --- a/tools/perf/arch/nds32/Build +++ /dev/null @@ -1 +0,0 @@ -perf-y += util/ diff --git a/tools/perf/arch/nds32/util/Build b/tools/perf/arch/nds32/util/Build deleted file mode 100644 index d0bc205fe49a..000000000000 --- a/tools/perf/arch/nds32/util/Build +++ /dev/null @@ -1 +0,0 @@ -perf-y += header.o diff --git a/tools/perf/arch/nds32/util/header.c b/tools/perf/arch/nds32/util/header.c deleted file mode 100644 index ef9dbdbe7968..000000000000 --- a/tools/perf/arch/nds32/util/header.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2005-2017 Andes Technology Corporation - -#include -#include -#include -#include "header.h" - -#define STR_LEN 1024 - -char *get_cpuid_str(struct perf_pmu *pmu) -{ - /* In nds32, we only have one cpu */ - char *buf = NULL; - struct cpu_map *cpus; - const char *sysfs = sysfs__mountpoint(); - - if (!sysfs || !pmu || !pmu->cpus) - return NULL; - - buf = malloc(STR_LEN); - if (!buf) - return NULL; - - cpus = cpu_map__get(pmu->cpus); - sprintf(buf, "0x%x", cpus->nr - 1); - cpu_map__put(cpus); - return buf; -} diff --git a/tools/testing/selftests/vDSO/vdso_config.h b/tools/testing/selftests/vDSO/vdso_config.h index 6188b16827d1..cdfed403ba13 100644 --- a/tools/testing/selftests/vDSO/vdso_config.h +++ b/tools/testing/selftests/vDSO/vdso_config.h @@ -53,10 +53,6 @@ #if __riscv_xlen == 32 #define VDSO_32BIT 1 #endif -#else /* nds32 */ -#define VDSO_VERSION 4 -#define VDSO_NAMES 1 -#define VDSO_32BIT 1 #endif static const char *versions[6] = { diff --git a/usr/include/Makefile b/usr/include/Makefile index 83822c33e9e7..7b283d43f00d 100644 --- a/usr/include/Makefile +++ b/usr/include/Makefile @@ -20,28 +20,20 @@ override c_flags = $(UAPI_CFLAGS) -Wp,-MMD,$(depfile) -I$(objtree)/usr/include # Please consider to fix the header first. # # Sorted alphabetically. -no-header-test += asm/shmbuf.h -no-header-test += asm/signal.h no-header-test += asm/ucontext.h no-header-test += drm/vmwgfx_drm.h no-header-test += linux/am437x-vpfe.h -no-header-test += linux/android/binder.h -no-header-test += linux/android/binderfs.h no-header-test += linux/coda.h no-header-test += linux/cyclades.h no-header-test += linux/errqueue.h -no-header-test += linux/fsmap.h no-header-test += linux/hdlc/ioctl.h no-header-test += linux/ivtv.h -no-header-test += linux/kexec.h no-header-test += linux/matroxfb.h no-header-test += linux/omap3isp.h no-header-test += linux/omapfb.h no-header-test += linux/patchkey.h no-header-test += linux/phonet.h -no-header-test += linux/reiserfs_xattr.h no-header-test += linux/sctp.h -no-header-test += linux/signal.h no-header-test += linux/sysctl.h no-header-test += linux/usb/audio.h no-header-test += linux/v4l2-mediabus.h