Shay Drory 563476ae0c net/mlx5: Synchronize correct IRQ when destroying CQ ... The CQ destroy is performed based on the IRQ number that is stored in cq->irqn. That number wasn't set explicitly during CQ creation and as expected some of the API users of mlx5_core_create_cq() forgot to update it. This caused to wrong synchronization call of the wrong IRQ with a number 0 instead of the real one. As a fix, set the IRQ number directly in the mlx5_core_create_cq() and update all users accordingly. Fixes: 1a86b377aa ("vdpa/mlx5: Add VDPA driver for supported mlx5 devices") Fixes: ef1659ade3 ("IB/mlx5: Add DEVX support for CQ events") Signed-off-by: Shay Drory <shayd@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>		2021-08-09 20:57:00 -07:00
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accel.h
cq.h
device.h	net/mlx5: mlx5_ifc support for header insert/remove	2021-06-09 18:36:06 -07:00
doorbell.h
driver.h	net/mlx5: Synchronize correct IRQ when destroying CQ	2021-08-09 20:57:00 -07:00
eq.h	net/mlx5: Provide cpumask at EQ creation phase	2021-06-14 20:57:57 -07:00
eswitch.h	net/mlx5e: TC: Reserved bit 31 of REG_C1 for IPsec offload	2021-05-27 11:54:36 -07:00
fs.h	net/mlx5: Bridge, add offload infrastructure	2021-06-09 18:36:09 -07:00
fs_helpers.h
mlx5_ifc.h	vdpa/mlx5: Support creating resources with uid == 0	2021-07-03 04:50:56 -04:00
mlx5_ifc_fpga.h
mlx5_ifc_vdpa.h	vdpa/mlx5: Make hardware definitions visible to all mlx5 devices	2020-12-04 14:46:56 +02:00
mpfs.h	{net,vdpa}/mlx5: Configure interface MAC into mpfs L2 table	2021-05-18 23:01:48 -07:00
port.h	net/mlx5: Add support for DSFP module EEPROM dumps	2021-04-11 16:34:56 -07:00
qp.h	RDMA/mlx5: Refactor get_ts_format functions to simplify code	2021-06-22 09:35:16 +03:00
rsc_dump.h
transobj.h	net/mlx5e: Fix page reclaim for dead peer hairpin	2021-06-09 17:20:03 -07:00
vport.h	net/mlx5: E-Switch, Prepare to return total vports from eswitch struct	2021-04-24 00:58:43 -07:00