3ea465d02a
Add support for CESTA-controlled clocks. CESTA controls clocks in HW using various CRM (CESTA Resource Manager) engines. Instead of SW directly writing to clock registers, SW votes the desired performance levels to CRM. CRM HW aggregates the performance levels across multiple SW and HW voters and configures the clocks and their dependencies entirely in HW. CESTA VCDs (Virtual Clock Domains) control one RCG and multiple clock branches. Clock branches on a VCD cannot be independently enabled/disabled. They all turn on/off at the same time when exiting/entering performance level zero. The standard clock framework interfaces vote using the default SW client. Voting on behalf of additional HW clients is supported through the new qcom_clk_crm_set_rate() API. Change-Id: Ie67c6e3b95cef840ba54a7681a6333c3ad4e5e5f Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com> |
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| .. | ||
| analogbits-wrpll-cln28hpc.h | ||
| at91_pmc.h | ||
| clk-conf.h | ||
| davinci.h | ||
| imx.h | ||
| mmp.h | ||
| mxs.h | ||
| pxa.h | ||
| qcom.h | ||
| renesas.h | ||
| samsung.h | ||
| spear.h | ||
| sunxi-ng.h | ||
| tegra.h | ||
| ti.h | ||
| zynq.h | ||