Andrew Bresticker 3358d2d9f4 clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs ... On Tegra210, hardware control of the SATA and XUSB pad PLLs must be done during the UPHY enable sequence rather than the PLLE enable sequence. Export functions to do this so that hardware control can be enabled from the XUSB padctl driver. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>		2016-04-28 12:41:44 +02:00
..
at91_pmc.h	clk: at91: pmc: drop at91_pmc_base	2016-02-17 17:53:03 +01:00
bcm2835.h
clk-conf.h	clk: Add missing header for 'bool' definition to clk-conf.h	2015-08-25 10:54:06 -07:00
mmp.h	clk: mmp: stop using platform headers	2015-12-01 21:44:22 +01:00
mxs.h	ARM: mxs: remove custom .init_time hook	2013-09-29 21:09:34 +02:00
renesas.h	clk: renesas: Rename header file renesas.h	2016-03-15 18:12:14 -07:00
tegra.h	clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs	2016-04-28 12:41:44 +02:00
ti.h	clk: ti: dpll: convert DPLL support code to use clk_hw instead of clk ptrs	2016-02-22 14:16:49 -08:00
zynq.h	ARM: zynq: Map I/O memory on clkc init	2014-02-10 11:21:13 +01:00