Vivek Aknurwar 3ea465d02a clk: qcom: Add support for CESTA-controlled clocks ... Add support for CESTA-controlled clocks. CESTA controls clocks in HW using various CRM (CESTA Resource Manager) engines. Instead of SW directly writing to clock registers, SW votes the desired performance levels to CRM. CRM HW aggregates the performance levels across multiple SW and HW voters and configures the clocks and their dependencies entirely in HW. CESTA VCDs (Virtual Clock Domains) control one RCG and multiple clock branches. Clock branches on a VCD cannot be independently enabled/disabled. They all turn on/off at the same time when exiting/entering performance level zero. The standard clock framework interfaces vote using the default SW client. Voting on behalf of additional HW clients is supported through the new qcom_clk_crm_set_rate() API. Change-Id: Ie67c6e3b95cef840ba54a7681a6333c3ad4e5e5f Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>		2023-01-11 10:57:43 -08:00
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analogbits-wrpll-cln28hpc.h
at91_pmc.h	clk: at91: fix the build with binutils 2.27	2022-10-14 13:39:23 -07:00
clk-conf.h
davinci.h	clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646x	2022-08-31 18:07:56 -07:00
imx.h	clk: imx: Move 'imx6sl_set_wait_clk()'s prototype out to accessible header	2021-01-30 22:13:23 +08:00
mmp.h
mxs.h
pxa.h	ARM: pxa: move clk register definitions to driver	2022-05-07 22:55:49 +02:00
qcom.h	clk: qcom: Add support for CESTA-controlled clocks	2023-01-11 10:57:43 -08:00
renesas.h
samsung.h	clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210	2020-11-23 10:25:45 +01:00
spear.h	clk: spear: Move prototype to accessible header	2022-10-10 10:37:58 +02:00
sunxi-ng.h	clk: sunxi-ng: Add support for the sun6i RTC clocks	2022-03-23 19:58:38 +01:00
tegra.h	clk: tegra: Add stubs needed for compile testing	2021-10-05 19:08:11 +02:00
ti.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE	2022-06-10 14:51:36 +02:00
zynq.h