Marc Zyngier fb182cf845 KVM: arm/arm64: vgic: Allow HW irq to be encoded in LR ... Now that struct vgic_lr supports the LR_HW bit and carries a hwirq field, we can encode that information into the list registers. This patch provides implementations for both GICv2 and GICv3. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>		2015-08-12 11:28:24 +01:00
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arm-gic-acpi.h	irqchip: Add GICv2 specific ACPI boot support	2015-03-26 15:13:07 +00:00
arm-gic-v3.h	KVM: arm/arm64: vgic: Allow HW irq to be encoded in LR	2015-08-12 11:28:24 +01:00
arm-gic.h	KVM: arm/arm64: vgic: Allow HW irq to be encoded in LR	2015-08-12 11:28:24 +01:00
arm-vic.h	irqchip: support cascaded VICs	2014-02-13 11:21:21 +01:00
chained_irq.h
ingenic.h	MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip	2015-06-21 21:53:10 +02:00
irq-omap-intc.h	irqchip: omap-intc: Remove unused legacy interface for omap2	2015-01-26 11:38:23 +01:00
irq-sa11x0.h	ARM: 8367/1: sa1100: prepare for moving irq driver to drivers/irqchip	2015-05-28 14:40:03 +01:00
metag-ext.h
metag.h
mips-gic.h	IRQCHIP: irq-mips-gic: Add new functions to start/stop the GIC counter	2015-03-31 12:04:13 +02:00
mmp.h
mxs.h
versatile-fpga.h
xtensa-mx.h
xtensa-pic.h