36db10b1ad
The current kernel DMA with PASID support is based on the SVA with a flag SVM_FLAG_SUPERVISOR_MODE. The IOMMU driver binds the kernel memory address space to a PASID of the device. The device driver programs the device with kernel virtual address (KVA) for DMA access. There have been security and functional issues with this approach: - The lack of IOTLB synchronization upon kernel page table updates. (vmalloc, module/BPF loading, CONFIG_DEBUG_PAGEALLOC etc.) - Other than slight more protection, using kernel virtual address (KVA) has little advantage over physical address. There are also no use cases yet where DMA engines need kernel virtual addresses for in-kernel DMA. This removes SVM_FLAG_SUPERVISOR_MODE support from the IOMMU interface. The device drivers are suggested to handle kernel DMA with PASID through the kernel DMA APIs. The drvdata parameter in iommu_sva_bind_device() and all callbacks is not needed anymore. Cleanup them as well. Link: https://lore.kernel.org/linux-iommu/20210511194726.GP1002214@nvidia.com/ Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Reviewed-by: Fenghua Yu <fenghua.yu@intel.com> Tested-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Tony Zhu <tony.zhu@intel.com> Link: https://lore.kernel.org/r/20221031005917.45690-4-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel <jroedel@suse.de> (cherry picked from commit 942fd5435dccb273f90176b046ae6bbba60cfbd8) Bug: 271394577 Change-Id: I568663921ccb4af3898806d576e3d7b605157d32 Signed-off-by: Michael Shavit <mshavit@google.com>
16 lines
381 B
C
16 lines
381 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright © 2015 Intel Corporation.
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*
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* Authors: David Woodhouse <David.Woodhouse@intel.com>
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*/
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#ifndef __INTEL_SVM_H__
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#define __INTEL_SVM_H__
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/* Page Request Queue depth */
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#define PRQ_ORDER 4
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#define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x20)
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#define PRQ_DEPTH ((0x1000 << PRQ_ORDER) >> 5)
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#endif /* __INTEL_SVM_H__ */
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