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Paulo Zanoni 4e4d3814a9 drm/i915/gen9: fix the WaWmMemoryReadLatency implementation 
Bspec says:
  "The mailbox response data may not account for memory read latency.
   If the mailbox response data for level 0 is 0us, add 2 microseconds
   to the result for each valid level."

This means we should only do the +2 in case wm[0] == 0, not always.

So split the sanitizing implementation from the WA implementation and
fix the WA implementation.

v2: Add Fixes tag (Maarten).

Fixes: 367294be7c ("drm/i915/gen9: Add 2us read latency to WM level")
Cc: stable@vger.kernel.org
Cc: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1474578035-424-5-git-send-email-paulo.r.zanoni@intel.com
(cherry picked from commit 0727e40a48)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2016-10-10 16:06:38 +03:00
..
drm drm/i915/gen9: fix the WaWmMemoryReadLatency implementation 2016-10-10 16:06:38 +03:00
host1x drm/tegra: dsi: Enhance runtime power management 2016-08-24 15:58:57 +02:00
ipu-v3 gpu: ipu-v3: Add queued image conversion support 2016-09-19 08:30:27 +02:00
vga vgaarbiter: rst-ifiy and polish kerneldoc 2016-08-16 18:49:56 +02:00
Makefile