548cd3ab54
This patch adds code which enables Quad I/O mode on Micron SPI NOR flashes. For Micron SPI NOR flash, enabling or disabling quad I/O protocol can be done By two methods, which are to use EVCR (Enhanced Volatile Configuration Register) and the ENTER QUAD I/O MODE command. There is no difference between these two methods. Unfortunately, for some Micron SPI NOR flashes, there no ENTER Quad I/O command (35h), such as n25q064. But for all current Micron SPI NOR, if it support quad I/O mode, using EVCR definitely be supported. It is a recommended method to enable Quad I/O mode by EVCR, Quad I/O protocol bit 7. When EVCR bit 7 is reset to 0, the SPI NOR flash will operate in quad I/O mode. This patch has been tested on N25Q512A and MT25TL256BAA1ESF. Micron SPI NOR of spi_nor_ids[] table all support this method. Signed-off-by: Bean Huo <beanhuo@micron.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Brian Norris <computersforpeace@gmail.com> |
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| .. | ||
| acpi | ||
| asm-generic | ||
| clocksource | ||
| crypto | ||
| drm | ||
| dt-bindings | ||
| keys | ||
| kvm | ||
| linux | ||
| math-emu | ||
| media | ||
| memory | ||
| misc | ||
| net | ||
| pcmcia | ||
| ras | ||
| rdma | ||
| rxrpc | ||
| scsi | ||
| soc | ||
| sound | ||
| target | ||
| trace | ||
| uapi | ||
| video | ||
| xen | ||
| Kbuild | ||