Update the firmware header to support uninitialization of UPHY PLL when the PCIe controller is operating in endpoint mode and host cuts the PCIe reference clock. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thierry Reding <treding@nvidia.com> |
||
|---|---|---|
| .. | ||
| arc | ||
| at91 | ||
| bcm2835 | ||
| brcmstb | ||
| fsl | ||
| imx | ||
| mediatek | ||
| mscc | ||
| nps | ||
| qcom | ||
| rockchip | ||
| sa1100 | ||
| sifive | ||
| tegra | ||