Mikko Perttunen 6ea2609ab3 soc/tegra: fuse: Add RAM code reader helper ... Needed for the EMC and MC drivers to know what timings from the DT to use. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>		2015-05-04 14:21:21 +02:00
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at91	pm: at91: Workaround DDRSDRC self-refresh bug with LPDDR1 memories.	2015-03-03 19:43:59 +01:00
tegra	soc/tegra: fuse: Add RAM code reader helper	2015-05-04 14:21:21 +02:00