Ville Syrjälä 91dbe5fb77 drm/i915: Change N divider minimum from 3 to 2 for gen2 ... Bruno Prémont has a 855 machine with a 1400x1050 LVDS screen. The VBT mode is as follows: 0:"1400x1050" 0 108000 1400 1416 1528 1688 1050 1051 1054 1066 0x8 0xa The BIOS uses the following DPLL settings: DPLL = 0x90020000 FP0 = 0x2140e FP1 = 0x21207 We can't generate that pixel clock currently as we're limiting the N divider to at least 3, whereas the BIOS uses a value of 2. Let's reduce the N minimum to 2 and see what happens. Cc: Bruno Prémont <bonbons@linux-vserver.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Bruno Prémont <bonbons@linux-vserver.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2013-12-11 23:52:14 +01:00
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drm	drm/i915: Change N divider minimum from 3 to 2 for gen2	2013-12-11 23:52:14 +01:00
host1x	gpu: host1x: Add syncpoint base support	2013-10-31 09:55:48 +01:00
vga	vgaarb: Fix VGA decodes changes	2013-09-03 19:17:59 +02:00
Makefile	gpu: host1x: Add host1x driver	2013-04-22 12:32:40 +02:00