d7a773e881
Most timings related to the bus timings are different between SDR and NV-DDR. However, we identified 9 individual timings which are more related to the NAND chip internals. These are common between the two interface types. Fortunately, only these common timings are being shared through the NAND core and its ->exec_op() interface, which allows the writing of a simple macro checking the interface type and depending on it, returning either the relevant SDR timing or the NV-DDR timing. This is the purpose of the NAND_COMMON_TIMING_PS() macro. As all this is evaluated at build time, one will immediately be notified in case a non common timing is being accessed through this macro. Two handy macros are also inserted at the same time, which use PSEC_TO_NSEC or PSEC_TO_MSEC so that it is very easy to return timings in milli-, nano- or pico-seconds, as usually requested by the internal API. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20210505213750.257417-14-miquel.raynal@bootlin.com |
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