Ville Syrjälä f72df8dbe2 drm/i915/chv: Don't do group access reads from TX lanes either ... Like PCS, TX group reads return 0xffffffff. So we need to target each lane separately if we want to use RMW cycles to update the registers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2014-05-20 15:52:38 +02:00
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drm	drm/i915/chv: Don't do group access reads from TX lanes either	2014-05-20 15:52:38 +02:00
host1x	gpu: host1x: handle the correct # of syncpt regs	2014-04-16 17:11:04 +02:00
vga	vgaarb: Fix VGA decodes changes	2013-09-03 19:17:59 +02:00
Makefile	gpu: host1x: Add host1x driver	2013-04-22 12:32:40 +02:00