fa4d0ca104
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.) Add a driver for it. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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| .. | ||
| bindings | ||
| 00-INDEX | ||
| booting-without-of.txt | ||
| changesets.txt | ||
| dynamic-resolution-notes.txt | ||
| of_unittest.txt | ||
| overlay-notes.txt | ||
| todo.txt | ||
| usage-model.txt | ||