Change <caadbd1051> ("pci: msm: Update the icc bw voting based
up on link speed and width") is setting AVG and PEAK votes to 0 without
checking whether PCIe CESTA is enabled or not in msm_pcie_drv_suspend.
In case of CESTA, we need to vote for AVG and PEAK BW votes to 500 and
800 in msm_pcie_drv_suspend.
Change-Id: I078f5f935889b5ec7babef175cfc3548a035202f
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Currently the phy-probe requires ref_clk, but if usb2 is
connected directly to the CXO PAD, in that case
ref_clk does not need to be added to the DT.
If devm_clk_get is marked as optional, it means
instead of return - ENOENT, function returns NULL.
In this change devm_clk_get change to devm_clk_get_optional
for ref_clk.
Change-Id: I943a146ebee47e21af9763cab5e21a15aa866497
Signed-off-by: Uttkarsh Aggarwal <quic_uaggarwa@quicinc.com>
Some tlmm pin-control drivers do not define tiles, add support
to restore pin control states for such chips by enhancing the
freeze and restore callbacks.
Change-Id: I868073cac0ed5b9ef4d0f5058aeefcb636df9a09
Signed-off-by: Vivek Kumar <vivekuma@codeaurora.org>
Signed-off-by: Darshankumar Jagdishchandra Thakkar <quic_djagdish@quicinc.com>
After quick boot, the doorbell interrupts need to
be re-enabled. Add support for the same by registering
the resume callback with PM framework.
Change-Id: I3df7a94db4c5acf4fe0462271fac2afe6f9a3b7e
Signed-off-by: Amit Nischal <quic_anischal@quicinc.com>
Add new SCM call to program secure camera qos settings.
For each NIU camera driver can call this scm API which need each NIU's
register offsets, value and number of registers offset that need to be
programed.
CRs-Fixed: 3781697
Change-Id: I35fbb433cceb032762246f526c5b28cb0f3d5d19
Signed-off-by: Dharmender Sharma <quic_dharshar@quicinc.com>
Signed-off-by: Alok Chauhan <quic_alokc@quicinc.com>
Add support for the DeepSleep mode for the RTC driver that
can be enabled based on a DT property.
Change-Id: Id7aab2a1affe26a71194aee0de78e116f1d803a0
Signed-off-by: LADI RAM SAI <quic_lramsai@quicinc.com>
Introduce restart handler to handle "echo b > /proc/sysrq-trigger".
One special thing with 'b' kind of reboot is, it does not call reboot
notifiers and call restart handler right a way and that does not seems
to work for blair SoC and it goes to dump mode.
Keep this restart handler priority to 201 greater than 200 which is the
priority for msm-poweroff to make reboot work cleaner.
Change-Id: I42f8c0fde29af402096d760c37ec2d8b3a85439a
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
The pcieX_i2c_ctrl property string will be different for each pcie
instance. So, using i2c client "of_node" instead of parsing using
"pcieX_i2c_ctrl". This way it does not need extra logic of parsing
different "pcieX_i2c_ctrl" property to read the pcie i2c properties.
Change-Id: I166d08bffff8b286b12f215c9e3b74074a8d4eb4
Signed-off-by: Yogesh Jadav <quic_yjadav@quicinc.com>
Signed-off-by: Joco Zhang <quic_pingshen@quicinc.com>
This patch is:
1) to use the rc_index from the i2c device tree.
2) eliminates need of hardcoded rc_index from structure
define for each PCIe I2C instance.
This will allow to use common compatible string for all instances
of pcie switch i2c device.
Change-Id: I759caa856a0058808ca072c75297a57ad76754b7
Signed-off-by: Yogesh Jadav <quic_yjadav@quicinc.com>
Signed-off-by: Joco Zhang <quic_pingshen@quicinc.com>
For HSP link down issue on CPE platform, because CPE NTN3 pcie switch
separates pcie link between RC and EP into two pcie buses,
RC0<->USP and DSP<->EP, so we should take care of this case on pcie
link training, make code change as following:
1. do link training RC0<->USP first and then do link training for
DSP<->EP
2. link training of DSP<->EP need more time to complete.
From test result, 100ms is not enough, 200ms is ok.
Change-Id: I0f36fc19ab1c6b90132596359c7b158fde7d3e22
Signed-off-by: Harrison Meng <quic_hmeng@quicinc.com>
Signed-off-by: Yogesh Jadav <quic_yjadav@quicinc.com>
Signed-off-by: Joco Zhang <quic_pingshen@quicinc.com>
On CPE platform, there is ntn3 pcie switch locates between RC and
Wlan, so the wlan pcie link is separated two parts, RC<->USP and
DSP<->WLAN, when pcie link suspend/resume, the link status of these
two buses is different, when link suspend the RC<->USP is not powered
off due to the existence of Ethernet device under same pcie switch.
For the case of cnss driver to power on/off wlan soc when pcie link
is still turned on, to avoid AER issue, before power on wlan soc cnss
driver needs to disable DSP<->WLAN link and then enable the link and
wait for link training completion Before powering off wlan soc cnss
driver also needs to disable DSP<->WLAN link at first. Function
msm_pcie_ntn3_dsp_link_control() is called by cnss driver to
enable(with link train)/disable DSP<->WLAN link when RC<->USP is on.
Change-Id: I8236b0786a14d6fb6c11805f24407edaa24e9836
Signed-off-by: Harrison Meng <quic_hmeng@quicinc.com>
Signed-off-by: Yogesh Jadav <quic_yjadav@quicinc.com>
Signed-off-by: Joco Zhang <quic_pingshen@quicinc.com>
Currently, the pmic-pon-log driver will trigger a kernel panic for
all PMIC fault reasons except RESTART_PON.
However, it is possible to encounter a FAULT_N fault reason during
boot-up if the Vph voltage doesn't perform ideally. This could
happen if for example: Vph doesn't drain far enough during a power
cycle/battery pull, Vph voltage is very low, or Vph voltage ramps
up very slowly. In such cases, the FAULT_N condition is transient
and doesn't indicate any particular issue taking place.
When fault reason FAULT_N occurs for a true PMIC issue, a further
root cause fault reason will also be specified. Therefore, it is
safe to ignore PMIC PON log events that specify FAULT_N as the
only fault reason.
Modify the pmic-pon-log driver PMIC fault panic logic to ignore
FAULT_REASON2=FAULT_N events.
Change-Id: Iab23ca43e44035a98ba5815203f4b44e9d98f29d
Signed-off-by: Kamal Wadhwa <quic_kamalw@quicinc.com>
In case if a cluster goes to LPM at higher frequency there is a
possibility of frequency relation choosing a wrong relation based on
frequency at which target cluster went down.
Fix this, by only considering frequency if cluster is running at least
one task.
Change-Id: I8601abc1c3941c91c69d944c56434efb619929f5
Signed-off-by: Ashay Jaiswal <quic_ashayj@quicinc.com>
This change is to bring pine EP out of reset post link-up.
Change-Id: Ied7533258496e8c08f619997626d70bcd6f0f8de
Signed-off-by: Ramya SR <quic_rsr@quicinc.com>
Signed-off-by: Yogesh Jadav <quic_yjadav@quicinc.com>
Signed-off-by: Joco Zhang <quic_pingshen@quicinc.com>
In msm_pcie_enable,EP is brought out of reset
after the link up.This will cause the enumeration
issues with HSP as NTN3 GPIO is connected to WLAN reset.
So moving the part of bringing the EP out of reset
prior link training and after de-emphasis setting.
The reason for moving it after de-emphasis setting is
to ensure WLAN is brought out of reset after all the switch
settings gets applied.
change-Id: I523000fd2475d8a1767423469f3bab0b7bc97ac0
Signed-off-by: Ramya SR <quic_rsr@quicinc.com>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Yogesh Jadav <quic_yjadav@quicinc.com>
Signed-off-by: Joco Zhang <quic_pingshen@quicinc.com>
Enable the emmc config which enables
data encryption (FBE) using wrapped keys.
CONFIG_MMC_CRYPTO_QTI.
Signed-off-by: kundan kumar <quic_kunkum@quicinc.com>
Disable MHI_SATELLITE driver for niobe as there is no use case for now.
Change-Id: I5f203bc9706cdbe957287f5e2cf8f9d2a0503dda
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
The CONFIG_ARM64_PMEM selects CONFIG_ARCH_HAS_PMEM_API for audiolite
module to use arch_invalidate_pmem.
Change-Id: I62cece37ec0ae8adc5485eb8333700b7cb52a6b9
Signed-off-by: Yimin Peng <quic_yiminp@quicinc.com>
In NTN3 switch there are i2c writes performed
in order to update some of the settings prior linkup.
These settings are taken care in upcoming versions of ntn3 chips
i.e, above V1 chips.There are some settings still required for NTN3v2
to solve the gen3 AER's. So added a separate switch reg update
sequence for it.
This change is to support update of de_emphasis settings of ntn3 switch
depending on the chip version.Also added a condition to check the
force update of these settings irrespective of the chip version
if force update flag is set by the client in the dtsi.
Change-Id: Id4828533f3f6f6f309b1c9c844a99a183c2950e1
Signed-off-by: Ramya SR <quic_rsr@quicinc.com>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Yogesh Jadav <quic_yjadav@quicinc.com>
Signed-off-by: Joco Zhang <quic_pingshen@quicinc.com>
